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USRE48879E1 - Spinram - Google Patents

Spinram Download PDF

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USRE48879E1
USRE48879E1 US16/447,777 US201916447777A USRE48879E US RE48879 E1 USRE48879 E1 US RE48879E1 US 201916447777 A US201916447777 A US 201916447777A US RE48879 E USRE48879 E US RE48879E
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film structure
film
structures
memory cell
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E. James Torok
Edward Wuori
Richard Spitzer
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Integrated Magnetoelectronics Corp
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Integrated Magnetoelectronics Corp
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    • H01L43/02
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B61/00Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/10Magnetoresistive devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/80Constructional details
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/80Constructional details
    • H10N50/85Magnetic active materials
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1659Cell access
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1673Reading or sensing circuits or methods
    • H01L27/222
    • H01L43/08
    • H01L43/10

Definitions

  • TMR tunnel magnetoresistance
  • GMR giant magnetoresistance
  • challenges at the basic cell design need to be addressed.
  • Such challenges include (1) scalability (e.g., decreasing drive currents and stable error rates with decreasing feature size); (2) endurance (e.g., the number of read/write cycles before cell breakdown); and (3) thermal stability of stored information (e.g., stability against errors due to thermally-induced transitions between two states that represent different bit values, an effect that increases with decreasing element volume and comes into play at deep nanoscale feature sizes).
  • Cell design features that we have conceived to enable scalability, increased endurance, and thermal stability include (1) a closed-flux cell structure, (2) parallel drive lines at the memory cell, and (3) increased film thickness. Each of these design features is described in more detail below.
  • H d demagnetizing field
  • H d also causes “shearing,” a decrease in the slope of the intrinsic hysteresis loop of a cell, that produces skewed minor loop operation and a resulting decrease in the signal strength of the cell's read signal. Moreover, in a cell without fully-closed flux, H d increases strongly as feature size decreases into nanoscale.
  • Capacity is linked to the signal strength provided by the film (GMR or TMR) used in the memory cell.
  • GMR films for our cell design, despite the smaller signal of presently available GMR structures than that of TMR, for three reasons: (i) simplicity of cell design—the GMR cell size is about one-half that of the TMR cell size, and requires fewer than one-half the number of masking steps; (ii) the method for addressing thermal stability at deep nanoscale lends itself much more readily to GMR than to TMR structures; (iii) the functional memory components of our magnetic RAM—the memory array without support electronics—may be constructed with metals and insulators alone (no semiconductors). This provides the potential for monolithic 3D structures (vertically replicated 2D arrays).
  • a memory includes a plurality of first signal lines, a plurality of second signal lines, and a plurality of first thin-film structures exhibiting magnetoresistance.
  • the first signal lines, the second signal lines, and the first thin-film structures form an array of memory cells.
  • Each memory cell includes (i) a portion of a corresponding one of the first thin-film structures; (ii) a portion of a corresponding one of the first signal lines coinciding with the portion of the corresponding first thin-film structure and electrically isolated therefrom; (iii) a portion of a corresponding one of the second signal lines coinciding with the portion of the corresponding first signal line and the portion of the corresponding first thin-film structure, the portion of the corresponding second signal line being electrically isolated from the corresponding first signal line and the corresponding first thin-film structure; and (iv) one or more keeper elements in direct contact with the portion of the corresponding first thin-film structure such that the portion of the corresponding first thin-film structure and the one or more keeper elements form at least part of a fully-closed-flux structure of the memory cell.
  • the portion of the corresponding first thin-film structure has an easy axis of magnetization perpendicular to a longitudinal axis of the portion of the corresponding first thin-film structure.
  • the first and second signal lines are configured to generate magnetizing fields at each memory cell that are perpendicular to the longitudinal axis of the portion of the corresponding first thin-film structure.
  • the memory includes a plurality of second thin-film structures exhibiting magnetoresistance, and each memory cell includes a portion of a corresponding one of the second thin-film structures.
  • the portion of the corresponding second thin-film structure for each memory cell coincides with and is electrically isolated from the corresponding first signal line, the corresponding second signal line, and the corresponding first thin-film structure.
  • the portion of the corresponding second thin-film structure forms part of the fully-closed flux structure.
  • the first and second signal lines are configured such that, for each memory cell, a primary direction of current flow in the portion of the corresponding first signal line is parallel to a primary direction of current flow in the portion of the corresponding second signal line.
  • each of the first thin-film structures includes sections of non-magnetic conductors between adjacent memory cells.
  • the first thin-film structure includes at least one high-coercivity magnetic layer and at least one low-coercivity magnetic layer. According to a more specific implementation, the first thin-film structure includes a pair of low-coercivity magnetic layers. According to another more specific implementation, the first thin-film structure comprises a ferromagnetically-coupled superlattice having multiple periods of the high and low-coercivity layers.
  • each memory cell is characterized by an aspect ratio of approximately 1 to 1.2.
  • a memory cell includes (i) a portion of a first thin-film structure; (ii) a first signal line coinciding with the portion of the first thin-film structure and electrically isolated therefrom; (iii) a second signal line coinciding with the first signal line and the portion of the first thin-film structure, the second signal line being electrically isolated from the first signal line and the first thin-film structure; and (iv) one or more keeper elements in direct contact with the portion of the first thin-film structure such that the portion of the first thin-film structure and the one or more keeper elements form at least part of a fully-closed-flux structure of the memory cell.
  • the portion of the first thin-film structure has an easy axis of magnetization perpendicular to a longitudinal axis of the first thin-film structure.
  • the first and second signal lines are configured to generate magnetizing fields that are perpendicular to the longitudinal axis of the first thin-film structure.
  • the memory cell includes a portion of a second thin-film structure coinciding with and electrically isolated from the first signal line, the second signal line, and the first thin-film structure.
  • the portion of the second thin-film structure forms part of the fully-closed flux structure.
  • the first and second signal lines are configured such that a primary direction of current flow in the first signal line at the memory cells is parallel to a primary direction of current flow in the second signal line at the memory cell.
  • the portion of the first thin-film structure and the first and second signals lines are co-linear at the memory cell.
  • the first thin-film structure includes sections of non-magnetic conductors on either side of the memory cell.
  • the portion of the first thin-film structure includes at least one high-coercivity magnetic layer and at least one low-coercivity magnetic layer. According to a more specific implementation, the portion of the first thin-film structure includes a pair of low-coercivity magnetic layers. According to another more specific implementation, the portion of the first thin-film structure comprises a ferromagnetically-coupled superlattice having multiple periods of the high and low-coercivity layers.
  • a memory cell includes (i) a portion of a first thin-film structure exhibiting giant magnetoresistance, the first thin film structure including a high-coercivity magnetic layer and a corresponding pair of low-coercivity magnetic layers; (ii) a first signal line coinciding with the portion of the first thin-film structure and electrically isolated therefrom; (iii) a second signal line coinciding with the first signal line and the portion of the first thin-film structure, the second signal line being electrically isolated from the first signal line and the first thin-film structure; (iv) a portion of a second thin-film structure coinciding with and electrically isolated from the first signal line, the second signal line, and the first thin-film structure, the second thin-film structure exhibiting giant magnetoresistance and including a high-coercivity magnetic layer and a corresponding pair of low-coercivity magnetic layers; and (v) one or more keeper elements in direct contact with the portion of the first thin-film structure and the portion
  • the portion of the first thin-film structure has an easy axis of magnetization perpendicular to a longitudinal axis of the first thin-film structure.
  • the portion of the second thin-film structure has an easy axis of magnetization perpendicular to a longitudinal axis of the second thin-film structure.
  • the first and second signal lines are configured to generate magnetizing fields that are perpendicular to the longitudinal axes of both the first and second thin-film structures.
  • FIG. 1 shows a simplified representation of the layout of a SpinRAM array.
  • FIG. 2 shows a simplified representation of the layout of another SpinRAM array.
  • FIG. 3 shows an example of a structure of a GMR film for use with SpinRAM arrays.
  • FIG. 4 shows a cross-section of a SpinRAM memory cell.
  • FIG. 5 shows a cross-section of another SpinRAM memory cell.
  • FIG. 6 shows the physical organization of 3D SpinRAM array.
  • FIG. 7 illustrates chip-scale interconnectivity for a 3D SpinRAM array.
  • FIG. 8 shows the R-H curve of a bulk GMR material.
  • FIGS. 9-12 show the R-H curves for patterned GMR films having different characteristics.
  • FIG. 13 shows a simplified representation of the layout of another SpinRAM array.
  • FIG. 14 shows a cross-section of another SpinRAM memory cell.
  • FIG. 15 includes Table 1 which provides a summary of results for GMR-film and drive-line characteristics in FIGS. 9-12 , with no keepers.
  • the present application describes various implementations of memory cells and memory architectures collectively referred to as SpinRAM. As will be discussed, particular implementations are projected to enable SpinRAM arrays with feature sizes decreasing into deep nanoscale.
  • SpinRAM is implemented as a coincident-current architecture.
  • An example of the physical layout of a SpinRAM array is shown in the plan view of FIG. 1 . The dimensions shown are not to scale.
  • the memory cells include portions of the GMR sense lines 102 .
  • the cells are thus in series, though they are not necessarily structurally distinct entities in the GMR film. That is, the GMR film portions of the cells may be part of one continuous structure.
  • the co-linearity of the drive lines ensures that the drive fields at the cell location are co-linear.
  • Each keeper is constructed from one or more magnetic materials used to help close the flux of the corresponding cell. Magnetization creep is described in Magnetization Creep in Nickel-Iron Films via the Lever Mechanism, A. L. Olson and E. J. Torok, J. Appl. Phys. 37, 1297 (1966), and Magnetization Creep of Cross-Tie Walls, E. J. Torok et al., J. Appl. Phys. 40, 1222 (1969), the entire disclosures of both of which are incorporated herein by reference for all purposes.
  • the bit value of each cell is stored in the hard layer of the GMR film (a higher coercivity layer that switches at relatively higher field strengths; e.g. cobalt) as a magnetization direction of the cell.
  • the soft layer (a lower coercivity layer that switches at relatively lower field strengths; e.g. permalloy) is used for readout. See further discussion of the operation below.
  • the size of the cell in the example array of FIG. 1 is 8F 2 , where F is the feature size.
  • Cell size can be reduced to 4F 2 , the theoretical limit for a single-bit cell in a crosspoint memory, by fabricating alternating digit lines in two separate deposition and patterning steps and introducing additional GMR lines in between the GMR lines in the layout of FIG. 1 .
  • the two sets of serpentine digit lines are insulated from, and partly overlap, each other.
  • there is no GMR film under the overlap of the digit lines so no memory cell that could be affected by the field they produce.
  • a simplified schematic of such a 4F 2 structure is shown in FIG. 2 .
  • FIG. 2 shows a 4F 2 cell structure with two separately deposited and patterned sets of serpentine digit lines 202 and 204 .
  • the two sets of digit lines are insulated from—and partly overlap—each other.
  • GMR sense line 206 does not coincide with the overlap of sense lines 202 and 204 , so no memory cell are affected by the field they produce.
  • the keeper layers are not shown. Again, the dimensions shown are not to scale.
  • CMOS complementary metal-oxide-semiconductor
  • 3D monolithic memories by incorporating replicated 2D arrays into a vertically integrated process in the same production line as the 2D structures.
  • the combination of scalable SpinRAM with 3D capability enables a nonvolatile memory with a density greater than that of hard disk. And because of its all-metal construction, SpinRAM is inherently radiation hard.
  • SpinRAM operation involves a dynamic role for both the hard layer(s) and the soft layer(s) of the multilayer thin-film structure.
  • the bit value is stored as a magnetization direction in the hard layer which may be constructed from, for example, cobalt.
  • a write operation is achieved by coincident half-select currents in word and digit lines that combine into the full-select current required to impress a specific magnetization on the memory cell where the two lines coincide.
  • the soft layer (which may be constructed from, for example, permalloy) is used to effect a read operation by applying a current pulse that switches the soft layer of all cells in the selected word line.
  • the resistance of the GMR element is relatively low for parallel orientations of the magnetization directions in the soft and hard layers, and relatively high for antiparallel orientations. This difference in resistance is used to determine the direction of the hard-layer magnetization, and therefore the bit value of the cell.
  • One method is to apply a full-select bipolar word-current pulse.
  • the cell to be read is selected by the sense line that intersects the word line at this cell.
  • a sample-and-hold circuit stores the sense signal for one magnetization orientation of the soft layer; this signal is then compared to that for the opposite soft-layer magnetization. The comparison yields the orientation of the hard layer.
  • the sense line is connected to the input of an amplifier with autonull capability. The amplifier is then autonulled (i.e., an automatic bias current causes the amplifier output to be adjusted to zero during the time the sense line is connected).
  • the data bit is next written to ‘0’ using the write-current circuit.
  • bit value was already ‘0’, no change in amplifier output occurs and a ‘0’ is stored in the output latch. If the bit value was a ‘1’, the state of the sense line changes, the amplifier produces a nonzero output, and a ‘1 is stored in the output latch. The original datum is then rewritten from value stored by the latch.
  • An alternative method is to store one bit in two cells located on neighboring sense lines, configured so that the soft and hard layers are parallel in one cell and antiparallel in the other.
  • a differential amplifier will see a signed signal that will establish the magnetization of the hard layer. This is a nondestructive readout and is expected to be faster than using a bipolar pulse, but it halves the storage density.
  • a readout-related issue in this architecture is that the number of cells that can be placed on a line is limited by noise and the GMR value.
  • the signal-to-noise ratio of the sense-line output in this architecture is proportional to GMR and inversely proportional to the square root of both the bandwidth and the number of cells/line. It therefore affects both the read speed and memory capacity.
  • GMR values in conventional films are too low to meet the capacity requirements of commercial memories.
  • we have developed a GMR film structure that raises the useful GMR value so as to enable high-capacity memories. Examples of this type of structure are described in U.S. Pat. No. 8,619,467 incorporated herein by reference above.
  • the GMR films in the SpinRAM cells are double pseudo spin valve structures with one or more periods including layers permalloy/copper/cobalt/copper/permalloy as shown in FIG. 3 .
  • the permalloy is dusted with cobalt to inhibit diffusion, and the cobalt contains 10% iron to minimize magnetostriction.
  • the cobalt switches at a field of about 10 Oe; the permalloy, at about 2 Oe.
  • Magnetic RAM e.g., magnetic tunneling junction (MTJ) MRAM
  • MTJ magnetic tunneling junction
  • each of the two adjacent cells includes sections of two GMR films 502 and 504 (i.e., “paired” GMR films) as opposed to the single GMR film 404 (i.e., an “unpaired” GMR film) shown in FIG. 4 .
  • the cell cross sections in FIG. 5 are perpendicular to the plane of the array in FIG. 1 with the horizontal direction of the GMR films 502 and 504 corresponding to the horizontal direction of the GMR film strips 102 in the plane of FIG. 1 .
  • the drive line currents are perpendicular to the plane of the cell cross sections (i.e., into and out of the page).
  • each cell preferably has fully-closed flux (e.g., as shown in FIG. 5 ); (2) the GMR films preferably have paired magnetic layers (e.g., the two permalloy layers in FIG. 3 ); and (3) the cell preferably has paired GMR films (e.g., films 502 and 504 of FIG. 5 ).
  • the cells depicted in FIG. 5 may incorporate ferromagnetically coupled GMR superlattices as operating elements in the cell structure.
  • such cells may be implemented without semiconductor elements, thereby enabling 3D monolithic capability.
  • implementing a SpinRAM cell without semiconductors obviates a major obstacle that characterizes the fabrication of 3D semiconductor circuits. It allows SpinRAM structures to be stacked vertically and electrically connected, as needed, by interconnecting layers. The vertical disposition of SpinRAM structures modifies the physical deployment of the system building blocks without affecting the logical and electronic functionality of the system.
  • 3D SpinRAM creates the potential for 3D SpinRAM to exceed the density of mechanical-magnetic storage (hard disk drives).
  • SpinRAM consumes little power because only accessed lines and associated support electronics are powered, so that, unlike hard-disk storage in data centers, power density remains substantially constant with increasing capacity.
  • a 3D structure may significantly reduce the cost of electronic components as the cost of an IC is more nearly proportional to its area rather than its volume. A simplified schematic of such a structure is shown in FIG. 6 .
  • the basic module referred to herein as a “tile” 602
  • a “tile” 602 is a self-contained memory block, i.e., a memory cell array and associated circuitry. Multiple tiles are physically organized into a 2D construction referred to herein as a “floor” 604 . Multiple floors are stacked to form the 3D “die” 606 .
  • Each tile 602 has a three-level structure: 1) the memory cell array; 2) connections to support electronics (address logic, sense amplifiers) at the periphery; and 3) connection stratum (for intra-die connectivity).
  • the advantage of such a three-level tile structure is that the overhead and connections do not increase the footprint appreciably (i.e., nearly 100% cell-array efficiency).
  • a simplified schematic of intra-die interconnectivity is shown in FIG. 7 .
  • the 3D structure appears linear as the tiles are contiguously connected in a linear address space.
  • Floors are transparent to the selection logic.
  • Intra-tile and inter-tile (horizontal) connectivity is achieved via a dedicated connection stratum 702 .
  • Inter-floor (vertical) connectivity 704 is achieved via a dedicated area at the floor edges which increases floor area by about 2%-5%.
  • the tiles are connected to an internal bus.
  • the number of data and control lines does not increase with component capacity.
  • the number of address lines increases slightly.
  • Such a 3D structure differs fundamentally from the packaging of multiple wafers in a single module. Additional information and examples are provided in U.S. Pat. No. 6,992,919 incorporated herein by reference above.
  • the thin strips are cut perpendicular to the easy axis defined by the direction of the magnetic field present during film deposition (EAM).
  • EAM film deposition
  • the EAM is perpendicular to the strip, but the shape-anisotropy easy axis is in the direction of the strip.
  • Theoretical analysis indicates that narrow strips of either unpaired films or paired films of very wide separation have large demagnetizing fields, and that permalloy and cobalt switch together rather than separately because the differences in anisotropy and coercivity of permalloy and cobalt are overwhelmed by the shape anisotropy and stray field of the strips in an unpaired GMR film.
  • Each of the R-H curve loops has the shape and low resistance change typical of anisotropic magnetoresistance (AMR) rather that of GMR.
  • the orientation of the GMR strip (co-linear with the word line) allows for a similar increase in density as described above with reference to the array of FIG. 2 without the need for adding GMR strips relative to the array shown in FIG. 1 . This is because the overlapping, serpentine digit lines now intersect with the vertical GMR strips at more locations to create memory cells.
  • the resulting area of the memory element is now 1F ⁇ 3F, i.e., three squares in a vertical line with one another; where a square can be thought of as the area of the intersection of a horizontal and vertical line.
  • This aspect ratio may be undesirably far from unity. Therefore, according to some implementations, configurations are contemplated that reduce this area closer to 1F ⁇ 1F.
  • the parts of the GMR line that correspond to the two outer squares in the overlap region of the GMR line are replaced by non-magnetic conductors.
  • SpinRAM feature size can be decreased into deep nanoscale, provided the cell geometry and parameters are designed appropriately. These may include, for example, that (1) the GMR films have paired magnetic layers (e.g., as shown in FIG. 3 ); (2) the GMR films in the memory cell are paired (e.g., as shown in FIG. 5 ); (3) magnetic flux is closed in the memory cell (e.g., as in the cell of FIG. 5 ); (4) the easy axis defined by the direction of the magnetic field present during film deposition (EAM) is perpendicular to the strip length; and/or (5) the cell aspect ratio is approximately 1.
  • the design with fully-closed flux has decisive advantages in power consumption, error rates, and memory density over designs with incomplete flux closure.
  • FIG. 13 shows a plan view of a portion of a SpinRAM array in which the GMR films have paired magnetic layers, the GMR films at each memory cell are paired, each memory cell has a fully-closed flux structure, the EAM is perpendicular to the longitudinal axis of the GMR strips, and the GMR strips are co-linear with the word lines.
  • FIG. 14 shows a cross-section of two adjacent memory cells represented by cross-section line A-A in FIG. 13 .
  • the left-hand half of the array includes the “top” GMR strips (i.e., sense lines) 1302 that obscure the corresponding “bottom” GMR strips 1303 from the depicted perspective.
  • the right-hand half of the array is shown without the “top” GMR strips 1302 so that the underlying structures (i.e., word lines 1306 , digit lines 1308 , and “bottom” GMR strips 1303 ) may be more clearly illustrated. Insulators are not shown in FIG. 13 for clarity.
  • top and “bottom” are relative terms used for illustrative purposes and may or may not correspond to how those terms relate to a local gravitational field. It should also be noted that the depicted structures are not shown to scale.
  • Each memory cell 1304 is located at the coincidence of a top GMR sense line 1302 , a bottom GMR sense line 1303 , a word line 1306 , and a digit line 1308 .
  • GMR sense lines 1302 and 1303 are co-linear with word lines 1306 . That is, the longitudinal axes of GMR sense lines 1302 and 1303 are perpendicular to the view of FIG. 14 (i.e., extending into and out of the page). Similar to the array of FIG.
  • digit lines 1308 are serpentine structures so that the drive fields generated by currents in digit lines 1308 and word lines 1306 are aligned with each other along the same axis; in this case perpendicular to the longitudinal axes of GMR sense lines 1302 and 1303 .
  • the EAM of paired GMR sense lines 1302 and 1303 is also perpendicular to the longitudinal axes of these sense lines, the cell configuration corresponds to the configuration discussed above with reference to FIG. 12 .
  • Non-conductive magnetic keepers 1310 along with top and bottom GMR sense lines 1302 and 1303 form a fully-closed flux structure at each memory cell 1304 .
  • keepers 1310 are in parallel with memory cells 1304 , keepers 1310 are constructed (at least in part) from a non-conductive magnetic material to avoid providing a shorting path for the sense current in GMR sense lines 1302 and 1303 .
  • keepers 1310 may be constructed using, for example, a magnetically soft ferrite. “Soft” in this context refers to material having high permeability & low coercivity. In some cases, the keepers may be constructed entirely from such a material. In other cases, the keepers may be constructed using more than one type of material as long as shorting of GMR sense lines 1302 and 1303 is avoided.
  • GMR sense lines 1302 and 1303 are constructed with alternating sections of GMR film (at each memory cell) and non-magnetic conductors (between memory cells) as represented by the dashed lines on GMR sense lines 1302 .
  • these intervening non-magnetic segments of the GMR sense lines allow for greater density in that the digit lines may be moved closer together or even overlap as discussed above with reference to FIG. 2 . They also allow for memory cell aspect ratios in the more desirable range of approximately 1 to 1.2.

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Abstract

Magnetic random-access memory (RAM) cells and arrays are described based on magnetoresistive thin-film structures.

Description

RELATED APPLICATION DATA
The present application is a reissue of U.S. patent application Ser. No. 15/272,228, now U.S. Pat. No. 9,741,923, which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 62/232,977 entitled SpinRAM filed on Sep. 25, 2015, the entire disclosure of which is incorporated herein by reference for all purposes.
BACKGROUND
In order to realize the full potential of magnetic random access memory (RAM), whether based on tunnel magnetoresistance (TMR) or giant magnetoresistance (GMR), fundamental challenges at the basic cell design need to be addressed. Such challenges include (1) scalability (e.g., decreasing drive currents and stable error rates with decreasing feature size); (2) endurance (e.g., the number of read/write cycles before cell breakdown); and (3) thermal stability of stored information (e.g., stability against errors due to thermally-induced transitions between two states that represent different bit values, an effect that increases with decreasing element volume and comes into play at deep nanoscale feature sizes).
Cell design features that we have conceived to enable scalability, increased endurance, and thermal stability include (1) a closed-flux cell structure, (2) parallel drive lines at the memory cell, and (3) increased film thickness. Each of these design features is described in more detail below.
An issue that transcends the individual cell design is the compatibility of magnetic RAM fabrication technology with CMOS processing. Some success with regard to this issue has already been demonstrated by commercial magnetic RAM. Another higher level issue is capacity (e.g., sufficient write and read margins for large arrays). We found that the issues attendant to scalability and capacity can be treated as distinct.
The issue of thermal stability has been resolved conceptually. See, for example, U.S. Pat. No. 7,911,830 entitled Scalable Nonvolatile Memory issued Mar. 22, 2011, the entire disclosure of which is incorporated herein by reference for all purposes.
We determined that a critical factor for scalability is control of the demagnetizing field Hd, i.e., the field produced by the magnetization M according to: V·Hd=−4π∇·M. The presence of Hd in a magnetic RAM (e.g., due to incomplete flux closure in its memory cells) causes multiple problems. Inside the memory cell the write current needs to overcome Hd to impress a given magnetization on the material, i.e., the write current must increase to write the bit value. Additionally, Hd from one cell can disturb the magnetization (i.e., change the bit values) of neighboring cells, causing errors. Increasing cell footprint can mitigate increase in error rates, but this sacrifices cell density. Hd also causes “shearing,” a decrease in the slope of the intrinsic hysteresis loop of a cell, that produces skewed minor loop operation and a resulting decrease in the signal strength of the cell's read signal. Moreover, in a cell without fully-closed flux, Hd increases strongly as feature size decreases into nanoscale.
These problems—increasing drive currents, increasing error rates, increasing cell footprint, and decreasing signal strength—are exacerbated by increasing demagnetizing fields that accompany decreasing feature size. These problems are further exacerbated by the interplay between thermal fluctuations and Hd in that the two can reinforce each other in specific configurations. To address these problems, we designed a memory cell that has a fully closed-flux and which is characterized by decisive advantages in power consumption, error rates, and memory density over designs with incomplete flux closure.
We also developed a measurement protocol to separate out the effects of demagnetizing fields from possible thermal effects in a magnetic RAM (based on either GMR or TMR) and to determine the magnitude of both. See R. Spitzer and E. Wuori, Demagnetizing Fields in Magnetic RAM, Intermag 2009, Session ET-06, the entire disclosure of which is incorporated herein by reference for all purposes.
Capacity is linked to the signal strength provided by the film (GMR or TMR) used in the memory cell. We chose GMR films for our cell design, despite the smaller signal of presently available GMR structures than that of TMR, for three reasons: (i) simplicity of cell design—the GMR cell size is about one-half that of the TMR cell size, and requires fewer than one-half the number of masking steps; (ii) the method for addressing thermal stability at deep nanoscale lends itself much more readily to GMR than to TMR structures; (iii) the functional memory components of our magnetic RAM—the memory array without support electronics—may be constructed with metals and insulators alone (no semiconductors). This provides the potential for monolithic 3D structures (vertically replicated 2D arrays). The storage density of such a 3D SpinRAM with 4 levels of 2D arrays can exceed that of a hard disk at 30 nm feature size and, for many mainstream applications (e.g., ones that depend on a specific number of input/output operations per second) it will likely be strongly economically competitive with hard disks. Additional information and examples are provided in U.S. Pat. No. 6,992,919 entitled All-Metal Three-Dimensional Circuits and Memories issued Jan. 31, 2006, the entire disclosure of which is incorporated herein by reference for all purposes.
To realize the strong sense signal needed for high capacity, we developed a ferromagnetically-coupled GMR superlattice with low drive fields and potential for significantly higher useful GMR values than currently available, well upwards of 50%. Examples of such a superlattice structure are described in U.S. Pat. No. 8,619,467 entitled High GMR Structure With Low Drive Fields issued Dec. 31, 2013, the entire disclosure of which is incorporated herein by reference for all purposes.
The issue of cell endurance is addressed by our crosspoint magnetic RAM with a coincident-current architecture and tied to the configuration of the drive lines in the memory array as described, for example, in U.S. Pat. No. 7,911,830 incorporated herein by reference above.
Despite these successes in the advancement of magnetic RAM design, further improvement continues to be our goal.
SUMMARY
According to a particular class of implementations, a memory includes a plurality of first signal lines, a plurality of second signal lines, and a plurality of first thin-film structures exhibiting magnetoresistance. The first signal lines, the second signal lines, and the first thin-film structures form an array of memory cells. Each memory cell includes (i) a portion of a corresponding one of the first thin-film structures; (ii) a portion of a corresponding one of the first signal lines coinciding with the portion of the corresponding first thin-film structure and electrically isolated therefrom; (iii) a portion of a corresponding one of the second signal lines coinciding with the portion of the corresponding first signal line and the portion of the corresponding first thin-film structure, the portion of the corresponding second signal line being electrically isolated from the corresponding first signal line and the corresponding first thin-film structure; and (iv) one or more keeper elements in direct contact with the portion of the corresponding first thin-film structure such that the portion of the corresponding first thin-film structure and the one or more keeper elements form at least part of a fully-closed-flux structure of the memory cell. For each memory cell, the portion of the corresponding first thin-film structure has an easy axis of magnetization perpendicular to a longitudinal axis of the portion of the corresponding first thin-film structure. The first and second signal lines are configured to generate magnetizing fields at each memory cell that are perpendicular to the longitudinal axis of the portion of the corresponding first thin-film structure.
According to a specific implementation, the memory includes a plurality of second thin-film structures exhibiting magnetoresistance, and each memory cell includes a portion of a corresponding one of the second thin-film structures. The portion of the corresponding second thin-film structure for each memory cell coincides with and is electrically isolated from the corresponding first signal line, the corresponding second signal line, and the corresponding first thin-film structure. For each memory cell, the portion of the corresponding second thin-film structure forms part of the fully-closed flux structure.
According to a specific implementation, the first and second signal lines are configured such that, for each memory cell, a primary direction of current flow in the portion of the corresponding first signal line is parallel to a primary direction of current flow in the portion of the corresponding second signal line.
According to a specific implementation, at each memory cell, the portion of the corresponding first thin-film structure and the portions of the corresponding first and second signals lines are co-linear. According to a more specific implementation, each of the first thin-film structures includes sections of non-magnetic conductors between adjacent memory cells.
According to a specific implementation, the first thin-film structure includes at least one high-coercivity magnetic layer and at least one low-coercivity magnetic layer. According to a more specific implementation, the first thin-film structure includes a pair of low-coercivity magnetic layers. According to another more specific implementation, the first thin-film structure comprises a ferromagnetically-coupled superlattice having multiple periods of the high and low-coercivity layers.
According to a specific implementation, each memory cell is characterized by an aspect ratio of approximately 1 to 1.2.
According to another class of implementations, a memory cell includes (i) a portion of a first thin-film structure; (ii) a first signal line coinciding with the portion of the first thin-film structure and electrically isolated therefrom; (iii) a second signal line coinciding with the first signal line and the portion of the first thin-film structure, the second signal line being electrically isolated from the first signal line and the first thin-film structure; and (iv) one or more keeper elements in direct contact with the portion of the first thin-film structure such that the portion of the first thin-film structure and the one or more keeper elements form at least part of a fully-closed-flux structure of the memory cell. The portion of the first thin-film structure has an easy axis of magnetization perpendicular to a longitudinal axis of the first thin-film structure. The first and second signal lines are configured to generate magnetizing fields that are perpendicular to the longitudinal axis of the first thin-film structure.
According to a specific implementation, the memory cell includes a portion of a second thin-film structure coinciding with and electrically isolated from the first signal line, the second signal line, and the first thin-film structure. the portion of the second thin-film structure forms part of the fully-closed flux structure.
According to a specific implementation, the first and second signal lines are configured such that a primary direction of current flow in the first signal line at the memory cells is parallel to a primary direction of current flow in the second signal line at the memory cell.
According to a specific implementation, the portion of the first thin-film structure and the first and second signals lines are co-linear at the memory cell. According to a more specific implementation, the first thin-film structure includes sections of non-magnetic conductors on either side of the memory cell.
According to a specific implementation, the portion of the first thin-film structure includes at least one high-coercivity magnetic layer and at least one low-coercivity magnetic layer. According to a more specific implementation, the portion of the first thin-film structure includes a pair of low-coercivity magnetic layers. According to another more specific implementation, the portion of the first thin-film structure comprises a ferromagnetically-coupled superlattice having multiple periods of the high and low-coercivity layers.
According to another class of implementations, a memory cell includes (i) a portion of a first thin-film structure exhibiting giant magnetoresistance, the first thin film structure including a high-coercivity magnetic layer and a corresponding pair of low-coercivity magnetic layers; (ii) a first signal line coinciding with the portion of the first thin-film structure and electrically isolated therefrom; (iii) a second signal line coinciding with the first signal line and the portion of the first thin-film structure, the second signal line being electrically isolated from the first signal line and the first thin-film structure; (iv) a portion of a second thin-film structure coinciding with and electrically isolated from the first signal line, the second signal line, and the first thin-film structure, the second thin-film structure exhibiting giant magnetoresistance and including a high-coercivity magnetic layer and a corresponding pair of low-coercivity magnetic layers; and (v) one or more keeper elements in direct contact with the portion of the first thin-film structure and the portion of the second thin-film structure such that the portion of the first thin-film structure, the portion of the second thin-film structure, and the one or more keeper elements form a fully-closed-flux structure of the memory cell. The portion of the first thin-film structure has an easy axis of magnetization perpendicular to a longitudinal axis of the first thin-film structure. The portion of the second thin-film structure has an easy axis of magnetization perpendicular to a longitudinal axis of the second thin-film structure. The first and second signal lines are configured to generate magnetizing fields that are perpendicular to the longitudinal axes of both the first and second thin-film structures.
A further understanding of the nature and advantages of various implementations may be realized by reference to the remaining portions of the specification and the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a simplified representation of the layout of a SpinRAM array.
FIG. 2 shows a simplified representation of the layout of another SpinRAM array.
FIG. 3 shows an example of a structure of a GMR film for use with SpinRAM arrays.
FIG. 4 shows a cross-section of a SpinRAM memory cell.
FIG. 5 shows a cross-section of another SpinRAM memory cell.
FIG. 6 shows the physical organization of 3D SpinRAM array.
FIG. 7 illustrates chip-scale interconnectivity for a 3D SpinRAM array.
FIG. 8 shows the R-H curve of a bulk GMR material.
FIGS. 9-12 show the R-H curves for patterned GMR films having different characteristics.
FIG. 13 shows a simplified representation of the layout of another SpinRAM array.
FIG. 14 shows a cross-section of another SpinRAM memory cell.
FIG. 15 includes Table 1 which provides a summary of results for GMR-film and drive-line characteristics in FIGS. 9-12, with no keepers.
DETAILED DESCRIPTION
Reference will now be made in detail to specific implementations. Examples of these implementations are illustrated in the accompanying drawings. It should be noted that these examples are described for illustrative purposes and are not intended to limit the scope of this disclosure. Rather, alternatives, modifications, and equivalents of the described implementations are included within the scope of this disclosure as defined by the appended claims. In addition, specific details may be provided in order to promote a thorough understanding of the described implementations. Some implementations within the scope of this disclosure may be practiced without some or all of these details. Further, well known features may not have been described in detail for the sake of clarity.
The present application describes various implementations of memory cells and memory architectures collectively referred to as SpinRAM. As will be discussed, particular implementations are projected to enable SpinRAM arrays with feature sizes decreasing into deep nanoscale.
According to a particular class of implementations, SpinRAM is implemented as a coincident-current architecture. An example of the physical layout of a SpinRAM array is shown in the plan view of FIG. 1. The dimensions shown are not to scale. The memory cells include portions of the GMR sense lines 102. The cells are thus in series, though they are not necessarily structurally distinct entities in the GMR film. That is, the GMR film portions of the cells may be part of one continuous structure. In the depicted implementation, the physical locations of the cells—the active parts of the GMR line—are determined by the portions of the GMR film that coincide with the overlay of the straight word lines 104 and serpentine digit lines 106 where these drive lines are co-linear. The co-linearity of the drive lines ensures that the drive fields at the cell location are co-linear.
This design choice—co-linear word and digit lines at the storage location—was implemented to improve cell endurance. That is, there is a cumulative disturb mechanism—magnetization creep—that limits endurance in cell configurations based on architectures with a geometry in which easy-axis and hard-axis drive fields act concurrently. It can cause a film to become demagnetized and lose its information content. This form of disturb, which is distinct from that caused by demagnetizing fields, generally arises for perpendicular drive lines. The problem is avoided, or at least mitigated, with co-linear word and digit lines at the memory cell. This design choice also allows the ends of the keepers 108 to be positioned closely to or in contact with the GMR film, which improves flux closure. Each keeper is constructed from one or more magnetic materials used to help close the flux of the corresponding cell. Magnetization creep is described in Magnetization Creep in Nickel-Iron Films via the Lever Mechanism, A. L. Olson and E. J. Torok, J. Appl. Phys. 37, 1297 (1966), and Magnetization Creep of Cross-Tie Walls, E. J. Torok et al., J. Appl. Phys. 40, 1222 (1969), the entire disclosures of both of which are incorporated herein by reference for all purposes.
The bit value of each cell is stored in the hard layer of the GMR film (a higher coercivity layer that switches at relatively higher field strengths; e.g. cobalt) as a magnetization direction of the cell. The soft layer (a lower coercivity layer that switches at relatively lower field strengths; e.g. permalloy) is used for readout. See further discussion of the operation below.
The size of the cell in the example array of FIG. 1 is 8F2, where F is the feature size. Cell size can be reduced to 4F2, the theoretical limit for a single-bit cell in a crosspoint memory, by fabricating alternating digit lines in two separate deposition and patterning steps and introducing additional GMR lines in between the GMR lines in the layout of FIG. 1. In such a design, the two sets of serpentine digit lines are insulated from, and partly overlap, each other. In the depicted implementation, there is no GMR film under the overlap of the digit lines, so no memory cell that could be affected by the field they produce. A simplified schematic of such a 4F2 structure is shown in FIG. 2.
FIG. 2 shows a 4F2 cell structure with two separately deposited and patterned sets of serpentine digit lines 202 and 204. The two sets of digit lines are insulated from—and partly overlap—each other. As shown, GMR sense line 206 does not coincide with the overlap of sense lines 202 and 204, so no memory cell are affected by the field they produce. The keeper layers are not shown. Again, the dimensions shown are not to scale.
Yet denser structures can be realized by making cells containing more than one bit. We have fabricated dibit SpinRAM cells by deposition of additional layers in the GMR films. This is a natural extension of the single-bit cell structure, in that GMR films are already 3D constructs. We also have designs for a quadbit structure, which will result in an effective 1F2 area per bit.
It takes eight masks to produce the 8F2 SpinRAM structure and, if CMOS support circuitry is used, an additional two masking layers to connect it to this circuitry. There are two additional masking steps in going from 8F2 to 4F2; one additional step from 1 bit per cell to dibit; and three additional steps from dibit to quadbit. Additional information and examples of multibit cells are provided in U.S. Pat. No. 6,594,175 entitled High Density Giant Magnetoresistive Memory Cell issued Jul. 15, 2003, the entire disclosure of which is incorporated herein by reference for all purposes.
Functional components of a SpinRAM memory cell are based on structured magnetic films. A generic feature of a SpinRAM array is that it is made entirely of metals and insulators—no semiconductors. This enables unique SpinRAM capabilities. For example, it can be fabricated on top of an underlying semiconductor IC such as, for example, a CMOS processor. It also enables fabrication of 3D monolithic memories by incorporating replicated 2D arrays into a vertically integrated process in the same production line as the 2D structures. The combination of scalable SpinRAM with 3D capability enables a nonvolatile memory with a density greater than that of hard disk. And because of its all-metal construction, SpinRAM is inherently radiation hard.
SpinRAM operation involves a dynamic role for both the hard layer(s) and the soft layer(s) of the multilayer thin-film structure. The bit value is stored as a magnetization direction in the hard layer which may be constructed from, for example, cobalt. A write operation is achieved by coincident half-select currents in word and digit lines that combine into the full-select current required to impress a specific magnetization on the memory cell where the two lines coincide.
The soft layer (which may be constructed from, for example, permalloy) is used to effect a read operation by applying a current pulse that switches the soft layer of all cells in the selected word line. The resistance of the GMR element is relatively low for parallel orientations of the magnetization directions in the soft and hard layers, and relatively high for antiparallel orientations. This difference in resistance is used to determine the direction of the hard-layer magnetization, and therefore the bit value of the cell. Several methods may be used. The following methods are simply provided as examples.
One method is to apply a full-select bipolar word-current pulse. The cell to be read is selected by the sense line that intersects the word line at this cell. In the nondestructive-readout variant, a sample-and-hold circuit stores the sense signal for one magnetization orientation of the soft layer; this signal is then compared to that for the opposite soft-layer magnetization. The comparison yields the orientation of the hard layer. In a destructive-readout variant, the sense line is connected to the input of an amplifier with autonull capability. The amplifier is then autonulled (i.e., an automatic bias current causes the amplifier output to be adjusted to zero during the time the sense line is connected). The data bit is next written to ‘0’ using the write-current circuit. If the bit value was already ‘0’, no change in amplifier output occurs and a ‘0’ is stored in the output latch. If the bit value was a ‘1’, the state of the sense line changes, the amplifier produces a nonzero output, and a ‘1 is stored in the output latch. The original datum is then rewritten from value stored by the latch.
An alternative method is to store one bit in two cells located on neighboring sense lines, configured so that the soft and hard layers are parallel in one cell and antiparallel in the other. A differential amplifier will see a signed signal that will establish the magnetization of the hard layer. This is a nondestructive readout and is expected to be faster than using a bipolar pulse, but it halves the storage density.
A readout-related issue in this architecture is that the number of cells that can be placed on a line is limited by noise and the GMR value. The signal-to-noise ratio of the sense-line output in this architecture is proportional to GMR and inversely proportional to the square root of both the bandwidth and the number of cells/line. It therefore affects both the read speed and memory capacity. GMR values in conventional films are too low to meet the capacity requirements of commercial memories. As mentioned above, we have developed a GMR film structure that raises the useful GMR value so as to enable high-capacity memories. Examples of this type of structure are described in U.S. Pat. No. 8,619,467 incorporated herein by reference above.
According to some implementations, the GMR films in the SpinRAM cells are double pseudo spin valve structures with one or more periods including layers permalloy/copper/cobalt/copper/permalloy as shown in FIG. 3. According to a particular implementation, the permalloy is dusted with cobalt to inhibit diffusion, and the cobalt contains 10% iron to minimize magnetostriction. In a bulk (unpatterned) film the cobalt switches at a field of about 10 Oe; the permalloy, at about 2 Oe.
SpinRAM cells with partially-closed flux (e.g., see FIG. 4) have been fabricated and tested at 5 μm, 500 nm, 100 nm feature sizes. The metallic keeper 402 is separated from the GMR film 404 in this design by the thin insulation layer labeled “insulation 1” in FIG. 4 in order not to short the signal in the GMR film. The gap created by insulation 1 results in a magnetic discontinuity in the magnetic circuit between the keeper and the storage element (the GMR film).
Test results showed that, though the cell shown in FIG. 4 could be successfully operated, the drive currents exceeded twice those expected of a cell with closed flux. Analysis of the results showed that the source of the problem was the gap, which causes significantly increased demagnetizing fields Hd as feature size approaches the gap size. This presents an obstacle to scalability unless gap thickness is correspondingly reduced. It was found that, below a feature size of about 90 nm, the gap would have to be made so thin as to short the signal in the GMR film. Increasing Hd, in turn, increases drive currents and error rates.
Alternative approaches to magnetic RAM (e.g., magnetic tunneling junction (MTJ) MRAM) have large and increasing drive currents and increasing error rates with decreasing feature size F. Both of these factors indicate the presence of large Hd in MTJ MRAMs; likely caused by gaps in their cell designs.
An example of an implementation of SpinRAM cells with fully-closed flux is shown in FIG. 5. In the depicted implementation, each of the two adjacent cells includes sections of two GMR films 502 and 504 (i.e., “paired” GMR films) as opposed to the single GMR film 404 (i.e., an “unpaired” GMR film) shown in FIG. 4. The cell cross sections in FIG. 5 are perpendicular to the plane of the array in FIG. 1 with the horizontal direction of the GMR films 502 and 504 corresponding to the horizontal direction of the GMR film strips 102 in the plane of FIG. 1. The drive line currents are perpendicular to the plane of the cell cross sections (i.e., into and out of the page). These currents produce either clockwise or counterclockwise-circulating magnetic fields around the drive lines parallel to the plane of the cross sections. These magnetic fields are contained by the fully-closed flux structures formed by GMR films 502 and 504, and non-conductive magnetic keeper elements 506.
We determined that, in order to avoid large demagnetizing fields, (1) each cell preferably has fully-closed flux (e.g., as shown in FIG. 5); (2) the GMR films preferably have paired magnetic layers (e.g., the two permalloy layers in FIG. 3); and (3) the cell preferably has paired GMR films (e.g., films 502 and 504 of FIG. 5). Provided these design features are met, SpinRAM drive currents and power consumption are projected to decrease with feature size into deep nanoscale, with error rates remaining stable. In some implementations, the cells depicted in FIG. 5 may incorporate ferromagnetically coupled GMR superlattices as operating elements in the cell structure. In addition, such cells may be implemented without semiconductor elements, thereby enabling 3D monolithic capability.
That is, implementing a SpinRAM cell without semiconductors obviates a major obstacle that characterizes the fabrication of 3D semiconductor circuits. It allows SpinRAM structures to be stacked vertically and electrically connected, as needed, by interconnecting layers. The vertical disposition of SpinRAM structures modifies the physical deployment of the system building blocks without affecting the logical and electronic functionality of the system.
Vertical manufacturing technology enables building nonvolatile memory structures with the all-metal support electronics—sense amplifiers, decode circuitry, bit and word drivers, data buffers—physically deployed above, beneath, or alongside the memory cell array. This significantly reduces the overall physical area of the memory component. Examples of all-metal support electronics are described in U.S. Pat. No. 5,929,636 entitled All-Metal, Giant Magnetoresistive, Solid-State Component issued Jul. 27, 1999, the entire disclosure of which is incorporated herein by reference.
Vertical manufacturing capability creates the potential for 3D SpinRAM to exceed the density of mechanical-magnetic storage (hard disk drives). In addition, SpinRAM consumes little power because only accessed lines and associated support electronics are powered, so that, unlike hard-disk storage in data centers, power density remains substantially constant with increasing capacity. Furthermore, a 3D structure may significantly reduce the cost of electronic components as the cost of an IC is more nearly proportional to its area rather than its volume. A simplified schematic of such a structure is shown in FIG. 6.
Physically, the development of such a 3D structure may involve a highly modular construction. The basic module, referred to herein as a “tile” 602, is a self-contained memory block, i.e., a memory cell array and associated circuitry. Multiple tiles are physically organized into a 2D construction referred to herein as a “floor” 604. Multiple floors are stacked to form the 3D “die” 606. Each tile 602 has a three-level structure: 1) the memory cell array; 2) connections to support electronics (address logic, sense amplifiers) at the periphery; and 3) connection stratum (for intra-die connectivity). The advantage of such a three-level tile structure is that the overhead and connections do not increase the footprint appreciably (i.e., nearly 100% cell-array efficiency). A simplified schematic of intra-die interconnectivity is shown in FIG. 7.
Logically, the 3D structure appears linear as the tiles are contiguously connected in a linear address space. Floors are transparent to the selection logic. Intra-tile and inter-tile (horizontal) connectivity is achieved via a dedicated connection stratum 702. Inter-floor (vertical) connectivity 704 is achieved via a dedicated area at the floor edges which increases floor area by about 2%-5%. The tiles are connected to an internal bus. The number of data and control lines does not increase with component capacity. The number of address lines increases slightly. Such a 3D structure differs fundamentally from the packaging of multiple wafers in a single module. Additional information and examples are provided in U.S. Pat. No. 6,992,919 incorporated herein by reference above.
To analyze the extent of flux closure needed for scalability into deep subnanoscale, we implemented a partially-closed flux cell design with a gap as shown in and described above with reference to FIG. 4. We fabricated and tested this design at feature sizes F ranging from 5 μm down to 100 nm. We found that drive currents and error rates increased with decreasing F, and that drive currents at fixed cell-feature size depend on gap thickness.
We simulated performance of the cell design of FIG. 4 into nanoscale. We found that write currents increase rapidly as feature size shrinks below a micron. We believe this to be due to the sharp rise in the demagnetizing field Hd at nanoscale dimensions. We also found that to reduce Hd to an acceptable level, gap thickness has to be decreased correspondingly so as not to exceed strip width. At feature size below about 90 nm, the gap would have to be made so thin as to short the signal in the GMR film. The requirement that the gap layer must remain thick enough to be reliably short free prevents miniaturization of the cell design of FIG. 4 into deep nanoscale.
To analyze the optimal GMR film structure, we analyzed restrictions on the structure of GMR films needed to minimize demagnetizing fields. Our theoretical results showed that narrow GMR film strips with either unpaired magnetic layers or paired magnetic layers of wide separation have large demagnetizing fields Hd. At micronscale, Hd is significantly lower for paired magnetic layers than it is for a stand-alone film strip, indicating that the large demagnetizing fields in unpaired films can be well controlled at this feature size by pairing the magnetic layers, provided the spacer thickness between them is kept small. This pairing of magnetic layers was incorporated into the GMR film and is illustrated in FIG. 3 and has been used in our SpinRAM cell designs. We also fabricated GMR films at micronscale with and without the paired layers. We found that Hd in films with paired layers was more than an order of magnitude lower than in the unpaired-layer films, confirming the theoretical results.
We also analyzed demagnetizing fields of GMR films with paired layers at nanoscale feature sizes. We found that the demagnetizing field, even of paired magnetic layers, increases greatly from micronscale to nanoscale. We found that we can compensate for this increase by using paired GMR films and magnetic keepers to form a closed-flux memory cell structure as shown, for example, in FIG. 5.
We also analyzed the restrictions on the choices of geometric cell parameters imposed by the requirements of stability of the magnetized state and maintaining low switching fields. We found that the aspect ratio of the cell (i.e., length-to-width) was best kept between 1.2 and 1. We also found that the aspect ratio, the separation of the magnetic layers, and the layer thicknesses should not be varied independently in that changes in one parameter typically required compensation by changes in the other two in order to maintain both stability and low switching field.
To determine the relative orientation of patterned GMR films and the drive field required for a viable SpinRAM cell, we fabricated a set of GMR films with paired layers of composition (the symbol “Pe” is used for permalloy)/Pe 6 nm/Cu 2 nm/Co 6 nm/Cu 2 nm/Pe 4 nm/. The R-H curve of a bulk film (i.e., not cut into strips) is shown in FIG. 8. The depicted curve is the desired behavior for GMR film strips patterned to nanoscale.
In the four configurations of patterned GMR films discussed below, the thin strips are cut perpendicular to the easy axis defined by the direction of the magnetic field present during film deposition (EAM). We used e-beam lithography at the Cornell Nanotechnology Facility to pattern films with paired layers into strips of widths ranging from 5 μm down to 100 nm. The results varied depending on whether the GMR films in the cell are paired or unpaired, on feature size, and on the relative orientations of the GMR strip and the drive fields.
Measurements on an unpaired GMR film showed no GMR effect for either of the two configurations of the in-plane drive field relative to the EAM (i.e., the easy axis defined by the magnetic field impressed during deposition). The switching field for a 600 nm-wide strip with the applied field H perpendicular to the EAM (see the R-H curve of FIG. 9) was an order of magnitude higher than that for a wide strip. The switching field for a 140 nm-wide strip with the drive field parallel to the EAM (see the R-H curve of FIG. 10) was two orders of magnitude higher than that for a wide strip.
In both FIGS. 9 and 10, the EAM is perpendicular to the strip, but the shape-anisotropy easy axis is in the direction of the strip. Theoretical analysis indicates that narrow strips of either unpaired films or paired films of very wide separation have large demagnetizing fields, and that permalloy and cobalt switch together rather than separately because the differences in anisotropy and coercivity of permalloy and cobalt are overwhelmed by the shape anisotropy and stray field of the strips in an unpaired GMR film. Each of the R-H curve loops has the shape and low resistance change typical of anisotropic magnetoresistance (AMR) rather that of GMR.
For paired films at feature sizes corresponding to those of the unpaired films, there is still no GMR effect for the configuration with the drive field in the direction along the strip (see the R-H curve of FIG. 11). By contrast, the configuration with the in-plane drive field perpendicular to the GMR strip (see the R-H curve of FIG. 12) does show the GMR effect, and the switch takes place at a value on the order of, though larger than, that of the wide strip. The use of paired GMR films thus substantially cancels the demagnetizing field and greatly lowers the switching threshold of nanoscale memory elements. Note that in this configuration, the GMR strip is parallel and co-linear with the word line rather than perpendicular as shown in FIGS. 1 and 2.
We redesigned the memory cell so as to eliminate the gap entirely resulting in a cell design with a fully-closed flux as shown in FIG. 5. We simulated performance of this cell design down to deep nanoscale. We found that drive currents decrease and error rates remain low with decreasing feature size.
The orientation of the GMR strip (co-linear with the word line) allows for a similar increase in density as described above with reference to the array of FIG. 2 without the need for adding GMR strips relative to the array shown in FIG. 1. This is because the overlapping, serpentine digit lines now intersect with the vertical GMR strips at more locations to create memory cells.
When the GMR strip is co-linear with the word line, the resulting area of the memory element (overlap of the two drive lines and the GMR line) is now 1F×3F, i.e., three squares in a vertical line with one another; where a square can be thought of as the area of the intersection of a horizontal and vertical line. This aspect ratio may be undesirably far from unity. Therefore, according to some implementations, configurations are contemplated that reduce this area closer to 1F×1F. According to one such implementation, the parts of the GMR line that correspond to the two outer squares in the overlap region of the GMR line are replaced by non-magnetic conductors. This reduces the area of the memory cell to 1F×1F with the non-magnetic conductor portions of the GMR line being between adjacent memory cells that share that line. It also avoids having two adjacent digit lines interacting with the same portion of the GMR line (e.g., where the digit lines overlap as shown in FIG. 2).
The results represented by the R-H curves of FIGS. 9-12 for patterned films are summarized in Table 1. Note that the low value of the switching field for the observed GMR is obtained without the use of keepers, an important element of the memory cell that are expected to lower the switching field further. “EAM” is the easy axis defined by the magnetic field impressed during deposition. “Paired” and “Unpaired” refers to the GMR films (rather than the layers of the GMR films).
As described herein, SpinRAM feature size can be decreased into deep nanoscale, provided the cell geometry and parameters are designed appropriately. These may include, for example, that (1) the GMR films have paired magnetic layers (e.g., as shown in FIG. 3); (2) the GMR films in the memory cell are paired (e.g., as shown in FIG. 5); (3) magnetic flux is closed in the memory cell (e.g., as in the cell of FIG. 5); (4) the easy axis defined by the direction of the magnetic field present during film deposition (EAM) is perpendicular to the strip length; and/or (5) the cell aspect ratio is approximately 1. In addition, the design with fully-closed flux has decisive advantages in power consumption, error rates, and memory density over designs with incomplete flux closure.
FIG. 13 shows a plan view of a portion of a SpinRAM array in which the GMR films have paired magnetic layers, the GMR films at each memory cell are paired, each memory cell has a fully-closed flux structure, the EAM is perpendicular to the longitudinal axis of the GMR strips, and the GMR strips are co-linear with the word lines. FIG. 14 shows a cross-section of two adjacent memory cells represented by cross-section line A-A in FIG. 13.
The left-hand half of the array includes the “top” GMR strips (i.e., sense lines) 1302 that obscure the corresponding “bottom” GMR strips 1303 from the depicted perspective. The right-hand half of the array is shown without the “top” GMR strips 1302 so that the underlying structures (i.e., word lines 1306, digit lines 1308, and “bottom” GMR strips 1303) may be more clearly illustrated. Insulators are not shown in FIG. 13 for clarity. It should be understood that the terms “top” and “bottom” are relative terms used for illustrative purposes and may or may not correspond to how those terms relate to a local gravitational field. It should also be noted that the depicted structures are not shown to scale.
Each memory cell 1304 is located at the coincidence of a top GMR sense line 1302, a bottom GMR sense line 1303, a word line 1306, and a digit line 1308. In contrast with the array of FIG. 1, GMR sense lines 1302 and 1303 are co-linear with word lines 1306. That is, the longitudinal axes of GMR sense lines 1302 and 1303 are perpendicular to the view of FIG. 14 (i.e., extending into and out of the page). Similar to the array of FIG. 1, digit lines 1308 are serpentine structures so that the drive fields generated by currents in digit lines 1308 and word lines 1306 are aligned with each other along the same axis; in this case perpendicular to the longitudinal axes of GMR sense lines 1302 and 1303. And because the EAM of paired GMR sense lines 1302 and 1303 is also perpendicular to the longitudinal axes of these sense lines, the cell configuration corresponds to the configuration discussed above with reference to FIG. 12. Non-conductive magnetic keepers 1310, along with top and bottom GMR sense lines 1302 and 1303 form a fully-closed flux structure at each memory cell 1304.
Because keepers 1310 are in parallel with memory cells 1304, keepers 1310 are constructed (at least in part) from a non-conductive magnetic material to avoid providing a shorting path for the sense current in GMR sense lines 1302 and 1303. According to various implementations, keepers 1310 may be constructed using, for example, a magnetically soft ferrite. “Soft” in this context refers to material having high permeability & low coercivity. In some cases, the keepers may be constructed entirely from such a material. In other cases, the keepers may be constructed using more than one type of material as long as shorting of GMR sense lines 1302 and 1303 is avoided.
According to a particular implementation, GMR sense lines 1302 and 1303 are constructed with alternating sections of GMR film (at each memory cell) and non-magnetic conductors (between memory cells) as represented by the dashed lines on GMR sense lines 1302. As will be appreciated, these intervening non-magnetic segments of the GMR sense lines allow for greater density in that the digit lines may be moved closer together or even overlap as discussed above with reference to FIG. 2. They also allow for memory cell aspect ratios in the more desirable range of approximately 1 to 1.2.
It will be understood by those skilled in the art that changes in the form and details of the implementations described herein may be made without departing from the scope of this disclosure. In addition, although various advantages, aspects, and objects have been described with reference to various implementations, the scope of this disclosure should not be limited by reference to such advantages, aspects, and objects. Rather, the scope of this disclosure should be determined with reference to the appended claims.

Claims (20)

What is claimed is:
1. A memory, comprising:
a plurality of first signal lines;
a plurality of second signal lines; and
a plurality of first thin-film structures exhibiting magnetoresistance, each of the first thin-film structures having a longitudinal axis;
a plurality of second thin-film structures exhibiting magnetoresistance, each of the second thin-film structures having a longitudinal axis;
wherein the first signal lines, the second signal lines, and the first thin-film structures, and the second thin-film structures form an array of memory cells, each memory cell comprising:
a portion of a corresponding one of the first thin-film structures;
a portion of a corresponding one of the second thin-film structures;
a portion of a corresponding one of the first signal lines coinciding with the portion of the corresponding one of the first thin-film structure structures and the portion of the corresponding one of the second thin-film structures and electrically isolated therefrom;
a portion of a corresponding one of the second signal lines coinciding with the portion of the corresponding one of the first signal line and lines, the portion of the corresponding one of the first thin-film structure structures, and the portion of the corresponding one of the second thin-film structures, the portion of the corresponding one of the second signal line lines being electrically isolated from the corresponding one of the first signal line and lines, the corresponding one of the first thin-film structure structures, and the corresponding one of the second thin-film structures; and
one or morea plurality of keeper elements in direct contact with the portion of the corresponding one of the first thin-film structurestructures and the portion of the corresponding one of the second thin-film structures such that the portion of the corresponding one of the first thin-film structurestructures, the portion of the corresponding one of the second thin-film structures, and the one or more keeper elements form at least part of a fully-closed-flux structure of the memory cell; and
wherein, for each memory cell, the portion of the corresponding one of the first thin-film structure has an easy axis of magnetization perpendicular to a the longitudinal axis of the corresponding one of the first thin-film structures and in a plane of the portion of the corresponding one of the first thin-film structure structures, and the portion of the corresponding one of the second thin-film structures has an easy axis of magnetization perpendicular to the longitudinal axis of the corresponding one of the second thin-film structures and in a plane of the portion of the corresponding one of the second thin-film structures, and wherein the first and second signal lines are configured to generate magnetizing fields at each memory cell that have components in the planes of the corresponding portions of the corresponding one of the first thin-film structures and the corresponding one of the second thin-film structures that are perpendicular to the longitudinal axis of the portion axes of the corresponding one of the first thin-film structures and the corresponding one of the second thin-film structure structures.
2. The memory of claim 1, further comprising a plurality of second thin-film structures exhibiting magnetoresistance, each memory cell further comprising a portion of a corresponding one of the second thin-film structures, the portion of the corresponding second thin-film structure for each memory cell coinciding with and being electrically isolated from the corresponding first signal line, the corresponding second signal line, and the corresponding first thin-film structure, and wherein, for each memory cell, the portion of the corresponding second thin-film structure forms part of the fully-closed flux structure.
3. The memory of claim 1, wherein the first and second signal lines are configured such that, for each memory cell, a primary direction of current flow in the portion of the corresponding one of the first signal line lines is parallel to a primary direction of current flow in the portion of the corresponding one of the second signal line lines.
4. The memory of claim 1, wherein at each memory cell, the portion of the corresponding one of the first thin-film structure structures and the portions of the corresponding one of the first signal lines and the corresponding one of the second signals lines are co-linear.
5. The memory of claim 4, wherein each of the first thin-film structures includes sections of non-magnetic conductors between adjacent memory cells.
6. The memory of claim 1, wherein each of the first thin-film structure structures includes at least one high-coercivity magnetic layer and at least one low-coercivity magnetic layer.
7. The memory of claim 6, wherein each of the first thin-film structure structures includes a pair of low-coercivity magnetic layers.
8. The memory of claim 7, wherein each of the first thin-film structure structures includes a first permalloy layer, a first copper layer, a cobalt layer, a second copper layer, and a second permalloy layer.
9. The memory of claim 6, wherein each of the first thin-film structure structures comprises a ferromagnetically-coupled superlattice having multiple periods of the high and low-coercivity layers.
10. The memory of claim 1, wherein each memory cell is characterized by an aspect ratio of approximately 1 to 1.2.
11. A memory cell comprising:
a portion of a first thin-film structure, the first thin-film structure having a longitudinal axis;
a portion of a second thin-film structure, the second thin-film structure having a longitudinal axis;
a first signal line coinciding with the portion of the first thin-film structure and the portion of the second thin-film structure, the first signal line being electrically isolated therefrom;
a second signal line coinciding with the first signal line and, the portion of the first thin-film structure, and the portion of the second thin-film structure, the second signal line being electrically isolated from the first signal line and the first thin-film structure; and
one or morea plurality of keeper elements in direct contact with the portion of the first thin-film structure and the portion of the second-thin film structure such that the portion of the first thin-film structure, the portion of the second thin-film structure, and the one or more keeper elements form at least part of a fully-closed-flux structure of the memory cell; and
wherein, the portion of the first thin-film structure has an easy axis of magnetization perpendicular to a the longitudinal axis of the first thin-film structure and in a plane of the first thin-film structure, wherein the second thin-film structure has an easy axis of magnetization perpendicular to the longitudinal axis of the second thin-film structure and in a plane of the second thin-film structure, and wherein the first and second signal lines are configured to generate magnetizing fields having components in the planes of the first and second thin-film structures that are perpendicular to the longitudinal axis axes of the first and second thin-film structure structures.
12. The memory cell of claim 11, further comprising a portion of a second thin-film structure coinciding with and electrically isolated from the first signal line, the second signal line, and the first thin-film structure, wherein the portion of the second thin-film structure forms part of the fully-closed flux structure.
13. The memory cell of claim 11, wherein the first and second signal lines are configured such that a primary direction of current flow in the first signal line at the memory cells is parallel to a primary direction of current flow in the second signal line at the memory cell.
14. The memory cell of claim 11, wherein the portion of the first thin-film structure and the first and second signals lines are co-linear at the memory cell.
15. The memory cell of claim 14, wherein the first thin-film structure includes sections of non-magnetic conductors on either side of the memory cell.
16. The memory cell of claim 11, wherein the portion of the first thin-film structure includes at least one high-coercivity magnetic layer and at least one low-coercivity magnetic layer.
17. The memory cell of claim 16, wherein the portion of the first thin-film structure includes a pair of low-coercivity magnetic layers.
18. The memory cell of claim 17, wherein the portion of the first thin-film structure includes a first permalloy layer, a first copper layer, a cobalt layer, a second copper layer, and a second permalloy layer.
19. The memory cell of claim 16, wherein the portion of the first thin-film structure comprises a ferromagnetically-coupled superlattice having multiple periods of the high and low-coercivity layers.
20. A memory cell comprising:
a portion of a first thin-film structure exhibiting giant magnetoresistance, the first thin film structure including a high-coercivity magnetic layer and a corresponding pair of low-coercivity magnetic layers, the first thin-film structure having a longitudinal axis;
a first signal line coinciding with the portion of the first thin-film structure and electrically isolated therefrom;
a second signal line coinciding with the first signal line and the portion of the first thin-film structure, the second signal line being electrically isolated from the first signal line and the first thin-film structure;
a portion of a second thin-film structure coinciding with and electrically isolated from the first signal line, the second signal line, and the first thin-film structure, the second thin-film structure exhibiting giant magnetoresistance and including a high-coercivity magnetic layer and a corresponding pair of low-coercivity magnetic layers, the second thin-film structure having a longitudinal axis oriented in parallel with the longitudinal axis of the first thin-film structure; and
one or morea plurality of keeper elements in direct contact with the portion of the first thin-film structure and the portion of the second thin-film structure such that the portion of the first thin-film structure, the portion of the second thin-film structure, and the one or more keeper elements form a fully-closed-flux structure of the memory cell; and
wherein, the portion of the first thin-film structure has an easy axis of magnetization perpendicular to a the longitudinal axis of the first thin-film structure and in a plane of the first thin-film structure, the portion of the second thin-film structure has an easy axis of magnetization perpendicular to a the longitudinal axis of the second thin-film structure and in a plane of the second thin-film structure, and wherein the first and second signal lines are configured to conduct currents having a primary direction of current flow parallel to the longitudinal axes of the first and second thin-film structures and to thereby generate magnetizing fields having components in the planes of the first and second thin-film structures that are perpendicular to the longitudinal axes of both the first and second thin-film structures.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10762940B2 (en) 2016-12-09 2020-09-01 Integrated Magnetoelectronics Corporation Narrow etched gaps or features in multi-period thin-film structures
US11355554B2 (en) * 2020-05-08 2022-06-07 Micron Technology, Inc. Sense lines in three-dimensional memory arrays, and methods of forming the same
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Citations (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2911627A (en) 1954-08-31 1959-11-03 Nat Res Dev Magnetic core storage systems
US3493943A (en) * 1965-10-05 1970-02-03 Massachusetts Inst Technology Magnetoresistive associative memory
US3972786A (en) 1974-06-28 1976-08-03 Ampex Corporation Mechanically enhanced magnetic memory
WO1987000959A1 (en) 1985-08-08 1987-02-12 David Cope Data storage apparatus for digital data processing system
US4751677A (en) 1986-09-16 1988-06-14 Honeywell Inc. Differential arrangement magnetic memory cell
US4780848A (en) 1986-06-03 1988-10-25 Honeywell Inc. Magnetoresistive memory with multi-layer storage cells having layers of limited thickness
US4829476A (en) 1987-07-28 1989-05-09 Honeywell Inc. Differential magnetoresistive memory sensing
US4980859A (en) 1989-04-07 1990-12-25 Xicor, Inc. NOVRAM cell using two differential decouplable nonvolatile memory elements
US5051695A (en) 1984-06-25 1991-09-24 The United States Of Americas As Represented By The Secretary Of The Navy Thin film vector magnetometer
US5173873A (en) 1990-06-28 1992-12-22 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration High speed magneto-resistive random access memory
US5237529A (en) 1991-02-01 1993-08-17 Richard Spitzer Microstructure array and activation system therefor
US5251170A (en) 1991-11-04 1993-10-05 Nonvolatile Electronics, Incorporated Offset magnetoresistive memory structures
US5389838A (en) 1992-10-09 1995-02-14 International Business Machines Corporation Device and method of managing asynchronous events in a finite state machine
US5432734A (en) 1993-08-30 1995-07-11 Mitsubishi Denki Kabushiki Kaisha Magnetoresistive element and devices utilizing the same
US5442508A (en) 1994-05-25 1995-08-15 Eastman Kodak Company Giant magnetoresistive reproduce head having dual magnetoresistive sensor
US5477482A (en) 1993-10-01 1995-12-19 The United States Of America As Represented By The Secretary Of The Navy Ultra high density, non-volatile ferromagnetic random access memory
US5477143A (en) 1994-01-11 1995-12-19 Honeywell Inc. Sensor with magnetoresistors disposed on a plane which is parallel to and displaced from the magnetic axis of a permanent magnet
US5515314A (en) 1994-05-27 1996-05-07 Fujitsu Limited Storage device
WO1996025740A1 (en) 1995-02-13 1996-08-22 Integrated Microtransducer Electronics Corporation Nonvolatile magnetoresistive memory with fully closed-flux operation
US5561368A (en) 1994-11-04 1996-10-01 International Business Machines Corporation Bridge circuit magnetic field sensor having spin valve magnetoresistive elements formed on common substrate
US5563839A (en) 1995-03-30 1996-10-08 Simtek Corporation Semiconductor memory device having a sleep mode
US5565236A (en) 1993-10-29 1996-10-15 International Business Machines Corporation Method of forming a giant magnetoresistance sensor
US5585986A (en) 1995-05-15 1996-12-17 International Business Machines Corporation Digital magnetoresistive sensor based on the giant magnetoresistance effect
US5640343A (en) 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
US5640754A (en) 1993-11-08 1997-06-24 Commissariat A L'energie Atomique Process of producing a magnetic read head having a multilayer magnetoresistant element and a concentrator
US5650958A (en) 1996-03-18 1997-07-22 International Business Machines Corporation Magnetic tunnel junctions with controlled magnetic response
US5650889A (en) 1994-02-07 1997-07-22 Hitachi, Ltd. Magnetic recording medium containing heavy rare gas atoms, and a magnetic transducing system using the medium
US5652445A (en) 1995-04-21 1997-07-29 Johnson; Mark B. Hybrid hall effect device and method of operation
US5654566A (en) 1995-04-21 1997-08-05 Johnson; Mark B. Magnetic spin injected field effect transistor and method of operation
US5661449A (en) 1994-08-29 1997-08-26 Tdk Corporation Magnetic multilayer film, method for making, and magnetoresistance device
US5682345A (en) 1995-07-28 1997-10-28 Micron Quantum Devices, Inc. Non-volatile data storage unit method of controlling same
WO1997041601A1 (en) 1996-05-02 1997-11-06 Integrated Microtransducer Electronics Corporation All-metal, giant magnetoresistive, solid-state component
US5686837A (en) 1994-04-15 1997-11-11 U.S. Philips Corporation Magnetic field sensor and instrument comprising such a sensor
US5852574A (en) 1997-12-24 1998-12-22 Motorola, Inc. High density magnetoresistive random access memory device and operating method thereof
US5892708A (en) 1992-09-24 1999-04-06 Nonvolatile Electronics, Incorporated Magnetoresistive memory using large fraction of memory cell films for data storage
US5903708A (en) 1994-05-30 1999-05-11 Sony Corporation Magneto-resistance effect device with improved thermal resistance
US5920500A (en) 1996-08-23 1999-07-06 Motorola, Inc. Magnetic random access memory having stacked memory cells and fabrication method therefor
US5969978A (en) 1998-09-30 1999-10-19 The United States Of America As Represented By The Secretary Of The Navy Read/write memory architecture employing closed ring elements
US5986962A (en) 1998-07-23 1999-11-16 International Business Machines Corporation Internal shadow latch
US5989406A (en) 1995-08-08 1999-11-23 Nanosciences Corporation Magnetic memory having shape anisotropic magnetic elements
US6034886A (en) 1998-08-31 2000-03-07 Stmicroelectronics, Inc. Shadow memory for a SRAM and method
US6055179A (en) 1998-05-19 2000-04-25 Canon Kk Memory device utilizing giant magnetoresistance effect
US6104632A (en) 1998-05-18 2000-08-15 Canon Kabushiki Kaisha Magnetic thin film memory and recording and reproducing method and apparatus using such a memory
US6129957A (en) 1999-10-12 2000-10-10 Headway Technologies, Inc. Method of forming a second antiferromagnetic exchange-coupling layer for magnetoresistive (MR) and giant MR (GMR) applications
US6134138A (en) 1999-07-30 2000-10-17 Honeywell Inc. Method and apparatus for reading a magnetoresistive memory
WO2000072324A1 (en) 1999-05-25 2000-11-30 Honeywell Inc. Local shielding for memory cells
US6166944A (en) 1998-04-20 2000-12-26 Kyoto University Data storing apparatus including integrated magnetic memory cells and semiconductor devices
US6169292B1 (en) 1994-08-31 2001-01-02 Semiconductor Energy Laboratory Co., Ltd. Thin film type monolithic semiconductor device
US6278594B1 (en) 1998-10-13 2001-08-21 Storage Technology Corporation Dual element magnetoresistive read head with integral element stabilization
EP1132917A2 (en) 2000-03-03 2001-09-12 Infineon Technologies AG Integrated memory with memory cells having a magneto-resistive memory effect
US6292336B1 (en) 1999-09-30 2001-09-18 Headway Technologies, Inc. Giant magnetoresistive (GMR) sensor element with enhanced magnetoresistive (MR) coefficient
US20020005717A1 (en) 2000-07-11 2002-01-17 Richard Spitzer Low power magnetic anomaly sensor
WO2002005268A2 (en) 2000-07-11 2002-01-17 Integrated Magnetoelectronics Corporation All metal giant magnetoresistive memory
WO2002005470A2 (en) 2000-07-11 2002-01-17 Integrated Magnetoelectronics Corporation Magnetoresistive trimming of gmr circuits
US20020009840A1 (en) 2000-07-11 2002-01-24 Integrated Magnetoelectronics Corporation High density giant magnetoresistive memory cell
US6353552B2 (en) 1997-07-16 2002-03-05 Altera Corporation PLD with on-chip memory having a shadow register
US20020037595A1 (en) 2000-09-28 2002-03-28 Keiji Hosotani Semiconductor memory device utilizing tunnel magneto resistive effects and method for manufacturing the same
WO2002078100A1 (en) 2001-03-23 2002-10-03 Integrated Magnetoelectronics Corporation A transpinnor-based switch and applications
US20020154455A1 (en) 2000-03-09 2002-10-24 Lenssen Kars-Michiel Hubert Magnetic device with a coupling layer and method of manufacturing and operation of such device
US20020180431A1 (en) 2001-03-23 2002-12-05 Integrated Magnetoelectronics Corporation Transpinnor-based sample-and-hold circuit and applications
US6493257B1 (en) 2002-03-27 2002-12-10 International Business Machines Corporation CMOS state saving latch
US6542000B1 (en) 1999-07-30 2003-04-01 Iowa State University Research Foundation, Inc. Nonvolatile programmable logic devices
US20030214835A1 (en) 2002-05-16 2003-11-20 Hasan Nejad Stacked 1t-nmtj mram structure
US20030231077A1 (en) 2002-04-11 2003-12-18 Integrated Magnetoelectronics Corporation Transpinnor-based transmission line transceivers and applications
US20040010671A1 (en) 2002-05-31 2004-01-15 Nokia Corporation Method and memory adapter for handling data of a mobile device using a non-volatile memory
US20040037109A1 (en) 2002-08-21 2004-02-26 Witcraft William F. Method for building a magnetic keeper or flux concentrator used for writing magnetic bits on a MRAM device
US20040061166A1 (en) 2002-09-19 2004-04-01 Hyeong-Jun Kim Magnetoresistive memory device and method for fabricating the same
US20040075152A1 (en) 2002-04-19 2004-04-22 Integrated Magnetoelectronics Corporation Interfaces between semiconductor circuitry and transpinnor-based circuitry
US20040136231A1 (en) 2003-01-10 2004-07-15 Yiming Huai Magnetostatically coupled magnetic elements utilizing spin transfer and an mram device using the magnetic element
US20040183198A1 (en) 2002-12-20 2004-09-23 Integrated Magnetoelectronics Corporation All-metal three-dimensional circuits and memories
US20040196704A1 (en) 2003-04-04 2004-10-07 Integrated Magnetoelectronics Corporation Displays with all-metal electronics
US20050018476A1 (en) 2003-07-23 2005-01-27 Tdk Corporation Magnetoresistive element, magnetic memory cell, and magnetic memory device, and method for manufacturing the same
US6865109B2 (en) 2003-06-06 2005-03-08 Seagate Technology Llc Magnetic random access memory having flux closure for the free layer and spin transfer write mechanism
US20050083743A1 (en) 2003-09-09 2005-04-21 Integrated Magnetoelectronics Corporation A California Corporation Nonvolatile sequential machines
US20050232001A1 (en) 2004-02-23 2005-10-20 Renesas Technology Corp. Semiconductor integrated circuit device and magnetic memory device capable of maintaining data integrity
US20050248888A1 (en) 2001-09-17 2005-11-10 Headway Technologies, Inc. Multilayered structures comprising magnetic nano-oxide layers for current perpendicular to plane gmr heads
US20050269612A1 (en) 2004-05-11 2005-12-08 Integrated Magnetoelectronics Solid-state component based on current-induced magnetization reversal
US6992935B2 (en) 2002-12-26 2006-01-31 Renesas Technology Corp. Nonvolatile memory device efficiently changing functions of field programmable gate array at high speed
US20060186342A1 (en) 2005-01-19 2006-08-24 Integrated Magnetoelectronics Corporation Radiation detector
US20080285331A1 (en) 2007-05-17 2008-11-20 Integrated Magnetoelectronics Corp. Scalable nonvolatile memory
US20090244957A1 (en) 2008-03-25 2009-10-01 Seagate Technology Llc Multilevel magnetic storage device
US20110211388A1 (en) 2010-02-22 2011-09-01 Integrated Magnetoelectronics Corp. High gmr structure with low drive fields
US20180166097A1 (en) 2016-12-09 2018-06-14 Integrated Magnetoelectronics Corp. Narrow etched gaps or features in multi-period thin-film structures

Patent Citations (109)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2911627A (en) 1954-08-31 1959-11-03 Nat Res Dev Magnetic core storage systems
US3493943A (en) * 1965-10-05 1970-02-03 Massachusetts Inst Technology Magnetoresistive associative memory
US3972786A (en) 1974-06-28 1976-08-03 Ampex Corporation Mechanically enhanced magnetic memory
US5051695A (en) 1984-06-25 1991-09-24 The United States Of Americas As Represented By The Secretary Of The Navy Thin film vector magnetometer
WO1987000959A1 (en) 1985-08-08 1987-02-12 David Cope Data storage apparatus for digital data processing system
US4780848A (en) 1986-06-03 1988-10-25 Honeywell Inc. Magnetoresistive memory with multi-layer storage cells having layers of limited thickness
US4751677A (en) 1986-09-16 1988-06-14 Honeywell Inc. Differential arrangement magnetic memory cell
US4829476A (en) 1987-07-28 1989-05-09 Honeywell Inc. Differential magnetoresistive memory sensing
US4980859A (en) 1989-04-07 1990-12-25 Xicor, Inc. NOVRAM cell using two differential decouplable nonvolatile memory elements
US5173873A (en) 1990-06-28 1992-12-22 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration High speed magneto-resistive random access memory
US5237529A (en) 1991-02-01 1993-08-17 Richard Spitzer Microstructure array and activation system therefor
US5592413A (en) 1991-02-01 1997-01-07 Spitzer; Richard Microstructure array and activation system therefor
US5491338A (en) 1991-02-01 1996-02-13 Spitzer; Richard High resolution imaging and measuring dynamic surface effects of substrate surfaces
US5251170A (en) 1991-11-04 1993-10-05 Nonvolatile Electronics, Incorporated Offset magnetoresistive memory structures
US5892708A (en) 1992-09-24 1999-04-06 Nonvolatile Electronics, Incorporated Magnetoresistive memory using large fraction of memory cell films for data storage
US5389838A (en) 1992-10-09 1995-02-14 International Business Machines Corporation Device and method of managing asynchronous events in a finite state machine
US5432734A (en) 1993-08-30 1995-07-11 Mitsubishi Denki Kabushiki Kaisha Magnetoresistive element and devices utilizing the same
US5477482A (en) 1993-10-01 1995-12-19 The United States Of America As Represented By The Secretary Of The Navy Ultra high density, non-volatile ferromagnetic random access memory
US5565236A (en) 1993-10-29 1996-10-15 International Business Machines Corporation Method of forming a giant magnetoresistance sensor
US5640754A (en) 1993-11-08 1997-06-24 Commissariat A L'energie Atomique Process of producing a magnetic read head having a multilayer magnetoresistant element and a concentrator
US5477143A (en) 1994-01-11 1995-12-19 Honeywell Inc. Sensor with magnetoresistors disposed on a plane which is parallel to and displaced from the magnetic axis of a permanent magnet
US5650889A (en) 1994-02-07 1997-07-22 Hitachi, Ltd. Magnetic recording medium containing heavy rare gas atoms, and a magnetic transducing system using the medium
US5686837A (en) 1994-04-15 1997-11-11 U.S. Philips Corporation Magnetic field sensor and instrument comprising such a sensor
US5442508A (en) 1994-05-25 1995-08-15 Eastman Kodak Company Giant magnetoresistive reproduce head having dual magnetoresistive sensor
US5515314A (en) 1994-05-27 1996-05-07 Fujitsu Limited Storage device
US5903708A (en) 1994-05-30 1999-05-11 Sony Corporation Magneto-resistance effect device with improved thermal resistance
US5661449A (en) 1994-08-29 1997-08-26 Tdk Corporation Magnetic multilayer film, method for making, and magnetoresistance device
US6169292B1 (en) 1994-08-31 2001-01-02 Semiconductor Energy Laboratory Co., Ltd. Thin film type monolithic semiconductor device
US5561368A (en) 1994-11-04 1996-10-01 International Business Machines Corporation Bridge circuit magnetic field sensor having spin valve magnetoresistive elements formed on common substrate
US5587943A (en) 1995-02-13 1996-12-24 Integrated Microtransducer Electronics Corporation Nonvolatile magnetoresistive memory with fully closed flux operation
WO1996025740A1 (en) 1995-02-13 1996-08-22 Integrated Microtransducer Electronics Corporation Nonvolatile magnetoresistive memory with fully closed-flux operation
EP0809846A1 (en) 1995-02-13 1997-12-03 Integrated Magnetoelectronics Nonvolatile magnetoresistive memory with fully closed-flux operation
US5563839A (en) 1995-03-30 1996-10-08 Simtek Corporation Semiconductor memory device having a sleep mode
US5654566A (en) 1995-04-21 1997-08-05 Johnson; Mark B. Magnetic spin injected field effect transistor and method of operation
US5652445A (en) 1995-04-21 1997-07-29 Johnson; Mark B. Hybrid hall effect device and method of operation
US5585986A (en) 1995-05-15 1996-12-17 International Business Machines Corporation Digital magnetoresistive sensor based on the giant magnetoresistance effect
US5682345A (en) 1995-07-28 1997-10-28 Micron Quantum Devices, Inc. Non-volatile data storage unit method of controlling same
US5989406A (en) 1995-08-08 1999-11-23 Nanosciences Corporation Magnetic memory having shape anisotropic magnetic elements
US5793697A (en) 1996-03-18 1998-08-11 International Business Machines Corporation Read circuit for magnetic memory array using magnetic tunnel junction devices
US5650958A (en) 1996-03-18 1997-07-22 International Business Machines Corporation Magnetic tunnel junctions with controlled magnetic response
US5640343A (en) 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
WO1997041601A1 (en) 1996-05-02 1997-11-06 Integrated Microtransducer Electronics Corporation All-metal, giant magnetoresistive, solid-state component
US5929636A (en) 1996-05-02 1999-07-27 Integrated Magnetoelectronics All-metal giant magnetoresistive solid-state component
US6031273A (en) 1996-05-02 2000-02-29 Integrated Magnetoelectronics All-metal, giant magnetoresistive, solid-state component
US5920500A (en) 1996-08-23 1999-07-06 Motorola, Inc. Magnetic random access memory having stacked memory cells and fabrication method therefor
US6353552B2 (en) 1997-07-16 2002-03-05 Altera Corporation PLD with on-chip memory having a shadow register
US5852574A (en) 1997-12-24 1998-12-22 Motorola, Inc. High density magnetoresistive random access memory device and operating method thereof
US6166944A (en) 1998-04-20 2000-12-26 Kyoto University Data storing apparatus including integrated magnetic memory cells and semiconductor devices
US6104632A (en) 1998-05-18 2000-08-15 Canon Kabushiki Kaisha Magnetic thin film memory and recording and reproducing method and apparatus using such a memory
US6055179A (en) 1998-05-19 2000-04-25 Canon Kk Memory device utilizing giant magnetoresistance effect
US5986962A (en) 1998-07-23 1999-11-16 International Business Machines Corporation Internal shadow latch
US6034886A (en) 1998-08-31 2000-03-07 Stmicroelectronics, Inc. Shadow memory for a SRAM and method
US5969978A (en) 1998-09-30 1999-10-19 The United States Of America As Represented By The Secretary Of The Navy Read/write memory architecture employing closed ring elements
US6278594B1 (en) 1998-10-13 2001-08-21 Storage Technology Corporation Dual element magnetoresistive read head with integral element stabilization
WO2000072324A1 (en) 1999-05-25 2000-11-30 Honeywell Inc. Local shielding for memory cells
US6134138A (en) 1999-07-30 2000-10-17 Honeywell Inc. Method and apparatus for reading a magnetoresistive memory
US6542000B1 (en) 1999-07-30 2003-04-01 Iowa State University Research Foundation, Inc. Nonvolatile programmable logic devices
US6292336B1 (en) 1999-09-30 2001-09-18 Headway Technologies, Inc. Giant magnetoresistive (GMR) sensor element with enhanced magnetoresistive (MR) coefficient
US6129957A (en) 1999-10-12 2000-10-10 Headway Technologies, Inc. Method of forming a second antiferromagnetic exchange-coupling layer for magnetoresistive (MR) and giant MR (GMR) applications
EP1132917A2 (en) 2000-03-03 2001-09-12 Infineon Technologies AG Integrated memory with memory cells having a magneto-resistive memory effect
US20020154455A1 (en) 2000-03-09 2002-10-24 Lenssen Kars-Michiel Hubert Magnetic device with a coupling layer and method of manufacturing and operation of such device
US20020029462A1 (en) 2000-07-11 2002-03-14 Integrated Magnetoelectronics Corporation Magnetoresistive trimming of GMR circuits
US20020005717A1 (en) 2000-07-11 2002-01-17 Richard Spitzer Low power magnetic anomaly sensor
US20020009840A1 (en) 2000-07-11 2002-01-24 Integrated Magnetoelectronics Corporation High density giant magnetoresistive memory cell
US20020024842A1 (en) 2000-07-11 2002-02-28 Integrated Magnetoelectronics Corporation All metal giant magnetoresistive memory
US6594175B2 (en) 2000-07-11 2003-07-15 Integrated Magnetoelectronics Corp High density giant magnetoresistive memory cell
WO2002005268A2 (en) 2000-07-11 2002-01-17 Integrated Magnetoelectronics Corporation All metal giant magnetoresistive memory
US6469927B2 (en) 2000-07-11 2002-10-22 Integrated Magnetoelectronics Magnetoresistive trimming of GMR circuits
WO2002005470A2 (en) 2000-07-11 2002-01-17 Integrated Magnetoelectronics Corporation Magnetoresistive trimming of gmr circuits
US6483740B2 (en) 2000-07-11 2002-11-19 Integrated Magnetoelectronics Corporation All metal giant magnetoresistive memory
US6538437B2 (en) 2000-07-11 2003-03-25 Integrated Magnetoelectronics Corporation Low power magnetic anomaly sensor
US20020037595A1 (en) 2000-09-28 2002-03-28 Keiji Hosotani Semiconductor memory device utilizing tunnel magneto resistive effects and method for manufacturing the same
US20020180431A1 (en) 2001-03-23 2002-12-05 Integrated Magnetoelectronics Corporation Transpinnor-based sample-and-hold circuit and applications
US20020180432A1 (en) 2001-03-23 2002-12-05 Integrated Magnetoelectronics Corporation, A California Corporation Transpinnor-based switch and applications
WO2002078100A1 (en) 2001-03-23 2002-10-03 Integrated Magnetoelectronics Corporation A transpinnor-based switch and applications
US6573713B2 (en) 2001-03-23 2003-06-03 Integrated Magnetoelectronics Corporation Transpinnor-based switch and applications
US6738284B2 (en) 2001-03-23 2004-05-18 Integrated Magnetoelectronics Corporation Transpinnor-based sample-and-hold circuit and applications
US20050248888A1 (en) 2001-09-17 2005-11-10 Headway Technologies, Inc. Multilayered structures comprising magnetic nano-oxide layers for current perpendicular to plane gmr heads
US6493257B1 (en) 2002-03-27 2002-12-10 International Business Machines Corporation CMOS state saving latch
US20030231077A1 (en) 2002-04-11 2003-12-18 Integrated Magnetoelectronics Corporation Transpinnor-based transmission line transceivers and applications
US6859063B2 (en) 2002-04-11 2005-02-22 Integrated Magnetoelectronics Corporation Transpinnor-based transmission line transceivers and applications
US7224566B2 (en) 2002-04-19 2007-05-29 Integrated Magnetoelectronics Corporation Interfaces between semiconductor circuitry and transpinnor-based circuitry
US20040075152A1 (en) 2002-04-19 2004-04-22 Integrated Magnetoelectronics Corporation Interfaces between semiconductor circuitry and transpinnor-based circuitry
US20030214835A1 (en) 2002-05-16 2003-11-20 Hasan Nejad Stacked 1t-nmtj mram structure
US20040010671A1 (en) 2002-05-31 2004-01-15 Nokia Corporation Method and memory adapter for handling data of a mobile device using a non-volatile memory
US20040037109A1 (en) 2002-08-21 2004-02-26 Witcraft William F. Method for building a magnetic keeper or flux concentrator used for writing magnetic bits on a MRAM device
US20040061166A1 (en) 2002-09-19 2004-04-01 Hyeong-Jun Kim Magnetoresistive memory device and method for fabricating the same
US6992919B2 (en) 2002-12-20 2006-01-31 Integrated Magnetoelectronics Corporation All-metal three-dimensional circuits and memories
US20040183198A1 (en) 2002-12-20 2004-09-23 Integrated Magnetoelectronics Corporation All-metal three-dimensional circuits and memories
US6992935B2 (en) 2002-12-26 2006-01-31 Renesas Technology Corp. Nonvolatile memory device efficiently changing functions of field programmable gate array at high speed
US20040136231A1 (en) 2003-01-10 2004-07-15 Yiming Huai Magnetostatically coupled magnetic elements utilizing spin transfer and an mram device using the magnetic element
US20040196704A1 (en) 2003-04-04 2004-10-07 Integrated Magnetoelectronics Corporation Displays with all-metal electronics
US7005852B2 (en) 2003-04-04 2006-02-28 Integrated Magnetoelectronics Corporation Displays with all-metal electronics
US6865109B2 (en) 2003-06-06 2005-03-08 Seagate Technology Llc Magnetic random access memory having flux closure for the free layer and spin transfer write mechanism
US20050018476A1 (en) 2003-07-23 2005-01-27 Tdk Corporation Magnetoresistive element, magnetic memory cell, and magnetic memory device, and method for manufacturing the same
US20050083743A1 (en) 2003-09-09 2005-04-21 Integrated Magnetoelectronics Corporation A California Corporation Nonvolatile sequential machines
US20050232001A1 (en) 2004-02-23 2005-10-20 Renesas Technology Corp. Semiconductor integrated circuit device and magnetic memory device capable of maintaining data integrity
US20050269612A1 (en) 2004-05-11 2005-12-08 Integrated Magnetoelectronics Solid-state component based on current-induced magnetization reversal
US20060186342A1 (en) 2005-01-19 2006-08-24 Integrated Magnetoelectronics Corporation Radiation detector
US7220968B2 (en) 2005-01-19 2007-05-22 Integrated Magnetoelectronics Corporation Radiation detector having all-metal circuitry operation of which is based on electron spin
US7911830B2 (en) * 2007-05-17 2011-03-22 Integrated Magnetoelectronics Scalable nonvolatile memory
US20080285331A1 (en) 2007-05-17 2008-11-20 Integrated Magnetoelectronics Corp. Scalable nonvolatile memory
US20110211387A1 (en) 2007-05-17 2011-09-01 Integrated Magnetoelectronics Corp. Scalable nonvolatile memory
US8300455B2 (en) * 2007-05-17 2012-10-30 Integrated Magnetoelectronics Scalable nonvolatile memory
US20090244957A1 (en) 2008-03-25 2009-10-01 Seagate Technology Llc Multilevel magnetic storage device
US20110211388A1 (en) 2010-02-22 2011-09-01 Integrated Magnetoelectronics Corp. High gmr structure with low drive fields
US8619467B2 (en) 2010-02-22 2013-12-31 Integrated Magnetoelectronics High GMR structure with low drive fields
US20180166097A1 (en) 2016-12-09 2018-06-14 Integrated Magnetoelectronics Corp. Narrow etched gaps or features in multi-period thin-film structures
US10170171B2 (en) 2016-12-09 2019-01-01 Integrated Magnetoelectronics Corporation 3D spinram

Non-Patent Citations (80)

* Cited by examiner, † Cited by third party
Title
Albon, C., "Integration of tunneling magnetoresistive sensors for high resolutive magnetic particle detection", PhD Thesis in Physics, Department of Physics, Bielefeld University (Nov. 2009), 128 pages.
Awschalom et al., "Spintronics", Scientific American, www.sciam.com, Jun. 2002.
Barna et al., "The Transpinnor: An Active Spin-Based Device" Non-Volatile Memory Technology Symposium 2002, Nov. 4-6, 2002.
Blaszyk et al., "Hall Effect and Magnetoresistance in Magnetic Multilayers with Alternating In-Plane and Out-of-Plane Anisotropies," Proceedings of the Conference New Materials for Magnetoelectronics-Mag-El-Mat, vol. 11370, No. 75, May 10, 2007.
Buschow, K.H.J., "Handbook of Magnetic Materials", vol. 17, Elsevier Science (Dec. 2007), 596 pages.
C. H. Marrows, et al. "Finite size scaling effects in giant magnetoresistance multilayers", vol. 18, 2006, pp. 243-252.
C. H. Marrows, et al., J. Phys: Condens, "Giant Magnetoresistance and Oscillatory Exahange Coupling in Disordered Co/Cu multilayers", vol. 11, 1999, pp. 81-88.
C. H. Marrows, et al., Physical Review B., Impurity Scattering from δ-layers in giant magnetoresistance systems, vol. 63, 220405-1 to 220405-.
Callaby, D.R. et al., Solid State Memory Study Final Report, Technical Report No. RE-0013, National Media Lab, St. Paul, MN (Feb. 1994).
Dieny, et al., "Spin-transfer effect anditsuse in spintronic components", Int. J. Nanotechnol, vol. 7, Nos. 4/5/6/7/8, 2010, pp. 591-613.
Extended European Search Report dated Feb. 19, 2019, Application No. EP 16 849 573.7.
G. Zorpette, IEEE Spectrum, "The Quest for the Spin Tarnsistor", vol. 38, Dec. 2001, pp. 30-35.
Gallagher, W.J. et al., "Development of the magnet tunnel junction MRAM at IBM: From first juncitons to a 16-Mb MRAM demonstrator chip", IBM J. Res. & Dev. vol. 50—No. 1 (Jan. 2006), 20 pages.
Gallagher, W.J. et al., "High-speed 128Kbit MRAM Core in a 0.18μm CMOS Technology Utilizing PtMn-based Magnetic Tunnel Junctions", Non-Volatile Memory Technology Symposium, NVMTS (Nov. 2003), 27 pages.
GB Examination Report dated Feb. 9, 2007 from GB0604381.4.
GB Examination Report dated May 8, 2007 from GB0604381.4
GB Examination Report dated Sep. 8, 2006 from GB0604381.4.
Grünberg, "Layered Magnetic Structures: History, Highlights, Applications", Physics Today, May 2001.
H. Kano, et al., Appl. Phys. Lett., "Substrate temperature effect on giant magnetoresistanc eof sputtered Co/Cu multilayers", vol. 63, No. 20, Nov. 15, 1993, pp. 2839-2841.
H.W. Schumacher et al., "Current-induced precessional magnetization reversal", Applied Physics Letters, vol. 83, No. 11, pp. 2205-2207, Sep. 15, 2003.
Harrison, R.W., "Laser Scanning Surface Profilomete", IBM Technical Disclosure Bullentin, 13(3): 789-790 (Aug. 1970).
Hylton, T.L., et al, "Giant Magnetoresistance at Low Fields in Discontinuous NiFe—Ag Multilayer Thin Films", Science, 261:1021-1024 (Aug. 1993).
International Preliminary Report on Patentability dated Mar. 27, 2018, Application No. PCT/US16/053046.
International Search Report dated Dec. 8, 2016, Application No. PCT/US16/053046.
International Search Report dated May 5, 2011, Application No. PCT/US11/25448.
J. Colino, et al., Physical Review B, "Connection between giant magnetoresistance and structure in molecular-beam epitaxy and sputtered Fe/Cr superlattices", vol. 53, No. 2, Jan. 1, 1996, pp. 766-769.
J. Mathon, et al., "Physical Review B," Theory of tunneling magnetoresistance of an epitaxial Fe/MgO/Fe(001) junction, vol. 63, 220403(R), 2001, pp. 220403-1-220403-4.
J.L. Brown, "1-Mb Memory Chip Using Giant Magnetoresistive Memory Cells," Sep. 1994, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A, vol. 17, No. 3, pp. 373-379.
J.M. Daughton, "Magnetoresistive Memory Technology," Jul. 28-Aug. 2, 1991, Int'l Workshop on Science and Technology of Thin Films for the 21st Century, vol. 216, pp. 162-168.
Jaquelin K. Spong, et al., "Giant Magnetoresistive Spin Valve Bridge Sensor", Mar. 1996, IEEE Transactions on Magnetics, vol. 32, No. 2, pp. 366-371.
Jones, K., "Texas Instruments Plans Large Expansion", The New York Times (Aug. 20, 1993).
K.-M.H. Lenssen, "Expectations of MRAM in Comparison with Other Non-Volatile Memory Technologies", Non-Volatile Memory Technology Symposium 2000, Nov. 15-16, 2000.
K.-M.H. Lenssen, "Magnetic Random Access Memory (MRAM) and its prospects", Non-Volatile Memory Technology Symposium 2001, Nov. 7-8, 2001.
K.T.M. Ranmuthu et al., "New Low Current Memory Modes with Giant Magneto-Resistance Materials," Apr. 13, 1993, Digests of International Magnetics Conference, 2 pages.
Kabos et al., "Metastable States in Large Angle Magnetization Rotations", IEEE Transactions of Magnetics, vol. 36, No. 5, pp. 3050-3052, Sep. 2000.
Katti et al., IEEE Circuits and Devices, Mar. 2001, pp. 26-34.
Klostermann, U.K. et al., "Influence of a magnetic seed line on the switching behaviour of submicrometre sized magnetic tunnel junctions", published online at stacks.iop.org/JPhysD/34/2117 (Jul. 2001), pp. 2117-2122.
L. Jiang, et al., Applied Physics Express, vol. 2 , 083002, pp. 083002-1-083002-3.
Mark Johnson, "Bipolar Spin Switch", Apr. 16, 1996, Science, vol. 260, pp. 320-323.
Mark Johnson, "The All-Metal Spin Transistor", May 1994, IEEE Spectrum, pp. 47-51.
National Media Laboratory Spring Review on Solid-State Memory Technologies, Proc. 1994 Spring Conference on Solid-State Memory Technologies, Pasadena, CA, (May 23-25, 1994), pp. 3-8, 97, 121, 123-133.
Notification Concerning Transmittal of International Preliminary Report on Patentability dated Mar. 23, 2006 for PCT/US2004/029317.
Notification Concerning Transmittal of International Preliminary Report on Patentability dated Oct. 16, 2008 for PCT/US2004/009418.
Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority dated Feb. 22, 2005 for PCT/US2004/029317.
Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority dated Oct. 15, 2008 for PCT/US2008/063781.
Notification of Transmittal of the International Search Report and the Written Opinion of the Interntional Searching Authority dated May 28, 2008 for PCT/US04/09418.
Notification of Transmittal of the International Search Report dated Jul. 1, 2004 for PCT/US03/39262.
Parkin, S., "Spin-Polarized Current in Spin Valves and Magnetic Tunnel Junctions", Abstract, MRS Bulletin, vol. 31 (May 2006), pp. 389-394.
Parkin, S.S.P, et al., "Oscillatory Magnetic Exchange Coupling through Thin Copper Layers", Physical Review Letters, 66(16): 2152-2155 (Apr. 1991).
Paul a. Packan, "Pushing the Limits", Sep. 24, 1999, science Mag, vol. 285, pp. 2079-2081.
Pratt, W.P., et al., "Perpendicular Giant Magnetoresistances of Ag/Co Multilayers", Physical Review Letters, 66 (23): 3060-3063 (Jun. 1991).
Prejbeanu, et al., "Thermally assisted MRAM", J. Phys.: Condens Matter, 2007, pp. 1-26.
Prinz, "Magnetoelectronics", www.sciencemag.org, Science, vol. 282, Nov. 27, 1998.
R. J. Celotta, et al., Journal of Magnetism and Magnetic Materials, Oscillatory magnetic coupling in Fe/Ag/Fe(100) sandwich structures 127:205-213 (1993).
Richter, R., "Logic gates realized with spin dependent tunneling elements", Disseration; Department of Physics, Bielefeld University (Sep. 2002), 125 pages.
Russek et al., "Time and Frequency Domain Measurements of Ferromagnetic Resonance in Small-Spin Valve", IEEE Transactions on Magnetics, vol. 36, No. 5, pp. 2560-2562, Sep. 2000.
S. A. Wolf, "Spintronics: A Spin-Based Electronics Vision for the Future", www.sciencemag.org, Science, vol. 294, Nov. 16, 2001.
S. Chikazumi, Physics of Magnetism, Section 5.3, entitled "Ferrimagnetic Oxides and Compounds," John Wiley & Sons (1964).
S. Das Sarma, American Scientist, "Spintronic", vol. 89, 2001, 516.
S. Ikeda, et al., Applied Physics Letters, "Tunnel magnetoresistance of 604% at 300 K by suppresion of Ta diffusion in CoFeB/MgO/CoFeB pseudo-spin-valves annealed at high temperature", vol. 93, 082508, 2008, 4 pp.
S. M. Bedair, et al., "Spintronic Memories to Revolutionize Data Storage", IEEE Spectrum, Nov. 2010, pp. 1-5.
S. S. Parkin, Appl. Phys. Lett., "Giant magnetoresistance in antiferromagnetic Co/Cu multilayers", vol. 58, No. 23, Jun. 10, 1991, pp. 2710-2712.
S. S. Parkin, et al., "Giant tunneling magnetoresistance at room temperature with MgO (100) tunnel barriers", Nature Materials, vol. 3, Dec. 2004, pp. 862-867.
S. S. Parkin, Physical Review Letters, "Origin of Enhanced Magnetoresistance of Magnetic Multilayers: Spin-Dependent Scattering from Magnetic Interface States", vol. 71, No. 10, Sep. 6, 1993, pp. 1641-1644.
S. Yuasa, et al., Nature Materials, "Giant Room-temperature magnetoresistance in single-crystal Fe/MgO/Fe magnetic tunnel junctions", vol. 3, Dec. 2004, pp. 868-871.
Schmalhorst, J. et al, "Switching stability of magnetic tunnel junctions with an artificial antiferromagnet", J Appl. Phys. vol. 77, No. 21 (Nov. 2000), pp. 3456.
Schmalhorst, J. et al, "Temperature stability of Co/AI203/Co junctions", J Appl. Phys. vol. 87, No. 9 (May 2000), pp. 5191.
Sousa, et al., "Non-volatile magnetic random access memories (MRAM)", Physics, Oct. 25, 2005, preprint submitted to Elsevier Science, 10 pages.
Spitzer and Torok, "A New Kind of Memory", The Industrial Physicist, Jun. 2000.
Spitzer and Wuoi, Demagnetizing Fields in Magnetic RAM, Dec. 2008, Integrated Magneto-Electronics Dec. 2008.
T. Choy, "Electron Transport Theory in Magnetic Nanostructures", A Disseration presented to the Graduate School of the University of Florida, 2001.
T. Shinjo and H. Yamamoto, Journal of the Physical Society of Japan, "Large Magnetoresistance of Field-Induced Giant Ferrimagnetic Multilayers", vol. 59, No. 9, Sep. 1990, pp. 3061-3064.
Torok et al., "Measurement of the Easy-Axis and Hk Probability Density Functions for Thin Ferromagnetic Films Using the Longitudinal Permeability Hysteresis Loop", Journal of Applied Physics, 33, No. 10, Oct. 1962, pp. 3037-3041.
Torok, et al, "Longitudinal Permeability in Thin Permalloy Films", Journal of Applied Physics, 34, No. 4, (Part 2), Apr. 1963, pp. 1064-1066.
W. H. Butler, et al., Physical Review B, "Spin-dependent tunning conductance of Fe/MgO/Fe sandwiches", vol. 63,054416, 2001, pp. 054416-1-.
Wang et al., Fabrication and properties of spin dependent tunneling junctions with CoFeHfO as free layers, Journal of Applied Physics, vol. 89, No. 11, Jun. 1, 2001.
X. Zhu et al., "A Novel Vertical MRAM Design".
Xiao, et al., "Giant Magnetoresistance in Nonmultilayer Magnetic Systems", Physical Review Letters, vol. 68, No. 25, 22 Jun. 1992, pp. 3749-3752.
Zhang, S., "Theory of Giant Magnetoresistance in Magnetic Granular Films",Appl. Phys. Lett., 61(15): 1855-1857 (Oct. 1992).
Zhu, J. et al, "Ultrahigh density vertical magnetoresistive random access memory (invited)", J Appl. Phys. vol. 87, No. 9 (May 2000), pp. 6668.

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