[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

USRE40983E1 - Method to plate C4 to copper stud - Google Patents

Method to plate C4 to copper stud Download PDF

Info

Publication number
USRE40983E1
USRE40983E1 US10/677,166 US67716603A USRE40983E US RE40983 E1 USRE40983 E1 US RE40983E1 US 67716603 A US67716603 A US 67716603A US RE40983 E USRE40983 E US RE40983E
Authority
US
United States
Prior art keywords
layer
metal
tantalum
recess
nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/677,166
Inventor
Cyprian E. Uzoh
Daniel C. Edelstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US10/677,166 priority Critical patent/USRE40983E1/en
Application granted granted Critical
Publication of USRE40983E1 publication Critical patent/USRE40983E1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03602—Mechanical treatment, e.g. polishing, grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12299—Workpiece mimicking finished stock having nonrectangular or noncircular cross section
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12361—All metal or with adjacent metals having aperture or cut

Definitions

  • the present invention relates to a process for plating a conductive material to a conductive feature in and/or on a substrate. More particularly, the present invention concerns electroplating a conductive material to a metal feature in and/or on a substrate using a highly conducting barrier film to conduct electrical current. In particular, the present invention provides methods for electroplating a solder ball utilized in a controlled collapse chip connection (C4) process to a metal feature provided in and/or on a substrate. Additionally, the present invention provides semiconductor structures prepared according to processes of the present invention.
  • C4 controlled collapse chip connection
  • metal film may be deposited over the entire patterned substrate surfaces to fill trenches and vias. This metal deposition may then be followed by metal planarization to remove metal overburden and to isolate and define the wiring pattern.
  • metal deposition is by electroplating or by electroless plating processes, the plating may be preceded by the deposition of a plating base or seed layer over the entire surface of the patterned wafer or substrate. Also, layers that may improve adhesion, and/or prevent conductor/insulator interactions and/or interdiffusion may be deposited between the plating base or seed layer and the insulator.
  • Severe dishing and insulator erosion in large metal features is a source of yield loss, especially when the occur at lower levels. Here they cause trapped metal defects at the next higher level.
  • the longer time needed to remove the thicker metal overburden of the smallest metal lines and vias is one of the main culprits responsible for the low thruput and yield losses in the metal CMP process.
  • this last metal wiring level which may include Cu, Al, Au, Ni, W, ⁇ -Ta, and/or other metals and/or alloys with low resistivity, typically contains very wide metal lines for power bussing and large pads for wirebonds or C4 solder balls. In the CMP process, these relatively large metal structures are sensitive to dishing because of the prolonged polishing time.
  • conductive elements such as solder balls may be attached to portions of the wiring.
  • conductive elements include solder balls for a C4 process.
  • patterns for a C4 process are created utilizing standard lithography techniques. According to such processes, a seed layer may be patterned, followed by lead-tin plating.
  • an object of the present invention is to provide a process for selectively plating metal utilizing more than one metal as an electrode.
  • One of the metals serves as a seed layer for plating and may be patterned.
  • Another metal may act as a current carrying conductor during plating.
  • an object of the present invention is to provide a process that permits attaching C4 solder balls directly to a final metal level in and/or on a substrate without requiring the utilization of a mask typical of traditional processes.
  • An advantage of the present invention is that it provides a less expensive process that known process for producing similar results.
  • Another advantage of the present invention is that it may utilize a barrier metal to carry plating current.
  • a further advantage of the present invention is that it may eliminate plating of metal on pins.
  • An additional advantage of the present invention is that it may provide higher productivity as compared to known processes.
  • the present invention provides a method for plating a second metal directly to a first without utilizing a mask.
  • a semiconductor substrate is provided including at least one metal feature of a first metal and at least one insulating layer covering said metal feature and the substrate. At least one recess is formed in the at least one insulating layer, thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature.
  • a plating seed layer is formed over the at least one barrier layer.
  • a photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed.
  • a second metal is plated to the plating seed layer in the recess.
  • a semiconductor substrate including at least one metal feature of a first metal and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer, thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer is formed over the at least one barrier layer. A pad is provided in the at least one recess for preventing removal of portions of the seed layer in the at least one recess. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. The pad is removed. A second metal is electroplated to the plating seed layer in the recess.
  • aspects of the present invention provide a semiconductor structure including a semiconductor substrate. At least one metal feature of a first metal is provided in the substrate. At least one insulating layer at least partially covers the at least one metal feature. At least one recess is located in the at least one insulating layer over the at least one metal feature. At least one conductive barrier layer is located over the at least one electrical insulating layer and over a portion of the at least one metal feature under the at least one recess. At least one plating seed layer is located over a portion of the conductive barrier layer within the recess. A second metal is electroplated to the seed layer in the recesses.
  • FIG. 1 represents a cross-sectional view of an embodiment of the present invention with a C4 opening etched over last metal;
  • FIG. 2 represents a cross-sectional view of an embodiment of the present invention illustrating a copper seedlayer after touch-up polishing to remove resist and copper seed-layer outside a depression, while leaving resist in the depression;
  • FIG. 3 represents a cross-sectional view of an embodiment of the present invention illustrating a state in a process according to the present invention in which resist has been stripped, solder plated and reflowed, a barrier removed, copper seed layer consumed by solder reflow and a C4 ball arranged in a recess and joined to the structure.
  • the present invention relates to electroplating a second metal on a metal feature of a first metal wherein the metal feature is arranged in and/or on a substrate.
  • the present invention permits the second metal to be electroplated without utilizing a mask.
  • methods of the present invention utilize a highly conducting barrier film alpha-Ta to carry current and selectively plate recesses in semiconducting and non-semiconducting substrates.
  • the methods according to the present invention include providing a substrate.
  • Various features may be provide in the substrate for accomplishing various tasks.
  • the various features made of conductive material may be provided in and/or on the substrate.
  • One example of such a feature is a metal last formed in the substrate.
  • the last is made of copper.
  • other features may be provided in the substrate having other forms and functions and made of other conductive materials.
  • a substrate such as a chip carrier.
  • a number of processes are available for attaching devices to a substrate. Many such processes may include providing electrical connections between a device and a substrate as well as attaching the device to the substrate.
  • a conductive barrier film of ⁇ -Ta, TaN/ ⁇ -Ta, ⁇ -Ta/TaN, or TaN/ ⁇ -Ta/TaN with resistivity in the range of 14 to 50 micro-ohm cm is sputtered at least in at least one recess over a metal feature in a substrate.
  • This is followed by the deposition of a plating base or seed layer over the barrier layer.
  • a photoresist is deposited and patterned over the plating seed layer.
  • the photoresist and seed layer are removed on all the field regions above the at least one recess, exposing the barrier layer.
  • the photoresist remaining in the at least one recess is removed exposing the seed layer in the at least one recess.
  • the substrate may then be electroplated, using the workpiece as the cathode. Accordingly, plating occurs on the seed layer in the at least one recess and not on other parts of the semiconductor substrate.
  • a barrier film of ⁇ -Ta, TaN/ ⁇ -Ta, ⁇ -Ta/TaN, or TaN/ ⁇ -Ta/TaN may be sputtered at least over the at least one recess in the substrate.
  • a plating base or seed layer is deposited.
  • the seed layer may then be polished off outside the at least one recess.
  • the at least one recess may then be plated using the barrier film without seed layers at the periphery of the substrate wafers for electrical contact.
  • semiconductor substrates that includes at least one semiconductor or circuit structure located on at least one of major surface.
  • a substrate 1 may be provided.
  • Typical semiconductor substrates include silicon and group III-V semiconductors.
  • At least one feature made of a conducting material may be provided in and/or on the substrate.
  • the substrate shown in FIG. 1 includes a last 3 formed in the substrate.
  • the last in the substrate shown in FIG. 1 is copper.
  • the last is surrounded by a layer 2 of an insulating material.
  • the substrate and the conductive feature may be covered by at least one layer of an electrically insulating material.
  • the insulating layer be thermally grown or deposited such as by chemical vapor deposition or physical vapor deposition. Typically, the insulating layer is about 2000 to about 30,000 ⁇ thick, and more typically about 4000 to about 20,000 ⁇ thick.
  • the substrate and the conductive feature are covered by an insulating layer made up of an oxide/nitride layer 5 .
  • a layer of polyimide 7 is deposited on the oxide/nitride layer 5 .
  • a polyimide passivation 8 layer made of, for example, a nitride and/or another hard insulator, may be deposited over the polyimide. The passivation layer may help to prevent the polyimide layer from picking up moisture and/or scratches, for example.
  • At least one recess 9 may be formed through the at least one insulating layer.
  • the at least one recess is formed to as to expose at least a portion of the at least one conductive feature.
  • Each conductive feature may have at least one recess formed exposing the conductive feature. More than one recess may be formed over some conductive features.
  • the recess 9 exposes a portion of the last metal 3 .
  • the recess may be formed according to known photolithography techniques.
  • the recess may be formed during the deposition of the at least one insulating layer.
  • the at least one recess may be formed in the at least one insulating layer after formation of the at least one insulating layer.
  • a conductive barrier 11 may be provided over the insulating layer.
  • the conductive barrier may include a layer of tantalum nitride first sputter deposited over the insulating layer, the walls of the recess, and the exposed conductive feature to a thickness of about 15 ⁇ to about 500 ⁇ and more typically to a thickness of about 50 to about 300 to act as adhesion promoting layer between the insulating layer and subsequently to be applied tantalum layer. Then, a tantalum layer may be sputtered over the layer of tantalum nitride, where it may form ⁇ -Ta spontaneously.
  • the thickness of the tantalum layer is about 500 ⁇ to about 3000 ⁇ A and more typically about 1000 ⁇ to about 2000 ⁇ .
  • ⁇ -Ta may be deposited directly over the insulator by sputtering methods.
  • the thickness of the ⁇ -Ta is about 500 ⁇ to about 5000 ⁇ , and more typically about 1000 ⁇ to about 3000.
  • a seed layer 13 may be deposited over the barrier layer 11 including on the walls and bottom of the recess(es).
  • the preferred seed layer is copper, which can be deposited by sputtering or evaporation and preferably by sputtering.
  • the copper may be sputtered employing temperatures of less than about 150° C., preferably less than about 100° C., such as about 100° C. to about ⁇ 10° C.
  • the sputtering may be carried out in the absence of an anneal.
  • the sputtering is typically carried out to provide a seed layer of about 100 ⁇ to about 2000 ⁇ and preferably about 400 ⁇ to about 1000 ⁇ .
  • the copper seed layer may be deposited by CVD methods or by electroless plating method or by an electrolytic plating method.
  • a photoresist may be deposited over the seed layer. Any of the well known photosensitive resist materials known in the art can be employed. The resist is typically applied by spinning on or by spraying.
  • the photoresist employed can be a positive photoresist or a negative photoresist.
  • a positive photoresist material is one which on exposure to imaging radiation, is capable of being rendered soluble in a solvent in which the unexposed resist is not soluble.
  • a negative resist material is one which is capable of polymerizing and/or insolubilizing upon exposure to imaging radiation.
  • An example of a type of photoresist material is based upon phenolic-formaldehyde Novolak polymers.
  • a particular example of such is Shipley AZ-1350 which is a m-cresol formaldehyde novolak polymer composition.
  • Such is a positive resist composition and includes therein a diazo ketone such as 2-diazo-1-naphthol-5-sulfonic acid ester.
  • the photoresist may be selectively removed everywhere except for in the recess(es).
  • the resist remaining in the recess(es) may protects protect the seed layer in the recesses (both the side walls and bottom of the recesses).
  • the seed layer lying outside of the recesses may be removed simultaneously with the photoresist. Actually, since the seed layer lies under the photoresist, the seed layer may be removed subsequent to the removal of the photoresist. They may be removed by the same process.
  • Both the photoresist and the seed layer may be removed by a process such as chemical-mechanical polishing.
  • the chemical-mechanical polishing may employ, for example, an aqueous polishing slurry containing abrasive particles such as colloidal silica.
  • the portions 15 of the resist layer remaining in the recess(es) that protected the seed layer within the recesses from removal is removed.
  • the resist may be removed by dissolving in a suitable solvent for the photoresist material.
  • photoresist may not be utilized.
  • Such an embodiment may utilize a very hard pad to prevent dishing of the seed layer in the depression.
  • a hard polishing pad such as IC 1000 or IC 100/Suba IV from Rodel Inc., may be used to polish off the seed layer.
  • One possible disadvantage of not using photoresist is that slurry utilized in chemical-mechanical polishing techniques may enter the recess. The slurry typically would then need to be removed. One way to remove the slurry is in a megasonic cleaning solution.
  • conductive metal 17 such as lead-tin or other terminal metallurgies
  • the barrier layer 11 may act as a cathode terminal for carrying the electroplating current.
  • lead-tin solders plating, commercial solder plating baths such as NF 800 HS or NF 72 BC from Technic Inc., Rhode Island, may be used.
  • Other proprietary commercially available lead-tin solders, eutectic solders, lead-free solders and/or other platable terminal metallurgies may be utilized.
  • the electroplating is continued until a desired amount of the conductive metal is plated in the recess(es). This usually takes about 10 min. to about 90 min, more typically about 20 min. to about 75 min.
  • the thickness of the electroplated metal or alloy is typically about 25 ⁇ to about 200 ⁇ , and more typically about 40 ⁇ to about 75 ⁇ .
  • the metal being plated will not plate on the barrier layer due to the formation of a very thin oxide layer when contacting the electroplating bath.
  • the oxide layer may be described as a “superficial” layer. This oxide layer will form naturally if the barrier layer is a tantalum layer such as that described above.
  • the oxide layer may be formed by momentarily reversing the polarity of the field, rendering the workpiece anodic, prior to the electroplating. The polarity change may be brief, such as about 10 seconds. Formation of the oxide layer may also be described as “anodization”.
  • the current density should be such that at the end of the current reversal, sufficient copper is left in the recesses for plating to initiate.
  • the barrier layer 11 may be removed down to the polyimide or polyimide passivation layer, after the solder reflow.
  • the barrier layer may be removed by utilizing the electroplated metal as a mask.
  • no lithograph step is required to define the seed layer since the chemical-mechanical polishing step makes the seed layer self-aligning to the recess(es). Not requiring a lithographic step simplifies the process. Additionally, the process may be less costly as compared to typical lithographically defined C4 processes. This simplification and cost advantage may be realized in any process requiring similar selective plating of metal(s).

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemically Coating (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess, using the barrier layer to conduct electrical current.

Description

RELATED APPLICATIONS
This application is a divisional application of application Ser. No. 09/004,808 filed Jan. 9, 1998 now U.S. Pat. No. 6,251,528.
TECHNICAL FIELD
The present invention relates to a process for plating a conductive material to a conductive feature in and/or on a substrate. More particularly, the present invention concerns electroplating a conductive material to a metal feature in and/or on a substrate using a highly conducting barrier film to conduct electrical current. In particular, the present invention provides methods for electroplating a solder ball utilized in a controlled collapse chip connection (C4) process to a metal feature provided in and/or on a substrate. Additionally, the present invention provides semiconductor structures prepared according to processes of the present invention.
BACKGROUND OF THE INVENTION
Various techniques have been investigated and utilized for attaching conductive material to semiconductor chips. These methods include the lift-off process, thru-mask methods, metal reactive ion etch (RIE) and metal and insulator damascene and various combinations of the above-listed methods. The lift-off and thru-mask methods are more valuable for large features, such as those typically encountered in chip packaging. Unlike the lift-off process and the thru-mask methods, the metal RIE and insulator damascene methods have been the process of choice for chip metallizations where the ground rules are typically below one micron.
In accordance with the damascene process, metal film may be deposited over the entire patterned substrate surfaces to fill trenches and vias. This metal deposition may then be followed by metal planarization to remove metal overburden and to isolate and define the wiring pattern. When metal deposition is by electroplating or by electroless plating processes, the plating may be preceded by the deposition of a plating base or seed layer over the entire surface of the patterned wafer or substrate. Also, layers that may improve adhesion, and/or prevent conductor/insulator interactions and/or interdiffusion may be deposited between the plating base or seed layer and the insulator.
In the metal RIE methods, blanket metal film is etched to define the conductor pattern. The gaps between the metal lines and vias are then filled with insulators. In high performance applications, the dielectric is planarized to define a flat metal level. One of the main advantages of the damascene process as compared to metal RIE is that it is often easier to etch an insulator as opposed to metal. Also, insulator gap fill and planarization may be more problematic.
In the metal damascene process, all the recesses in the insulator are first filled with metal before metal polishing. However, during the metal deposition into trenches and vias, all the narrower features become filled before their wider counterparts. Thus, all features with width less than 2 microns will be filled before those with width greater than 5 microns. Hence, to fill trenches or test pads with width of 50 microns, the smaller recesses typically with widths less than 5 microns are overplated. During metal chemical-mechanical polishing (CMP), the additional time needed to remove the excess metal overburden on the overplated smaller features causes dishing on the larger features. Also, because of the prolonged polishing times, insulator adjacent may severely erode. Severe dishing and insulator erosion in large metal features is a source of yield loss, especially when the occur at lower levels. Here they cause trapped metal defects at the next higher level. The longer time needed to remove the thicker metal overburden of the smallest metal lines and vias is one of the main culprits responsible for the low thruput and yield losses in the metal CMP process.
Moreover, this last metal wiring level, which may include Cu, Al, Au, Ni, W, α-Ta, and/or other metals and/or alloys with low resistivity, typically contains very wide metal lines for power bussing and large pads for wirebonds or C4 solder balls. In the CMP process, these relatively large metal structures are sensitive to dishing because of the prolonged polishing time.
After formation of wiring according to the above-described processes, further processing may be carried out on the substrate. For example, conductive elements, such as solder balls may be attached to portions of the wiring. One example of conductive elements that may be attached include solder balls for a C4 process.
Typically, patterns for a C4 process are created utilizing standard lithography techniques. According to such processes, a seed layer may be patterned, followed by lead-tin plating.
SUMMARY OF INVENTION
Broadly, an object of the present invention is to provide a process for selectively plating metal utilizing more than one metal as an electrode. One of the metals serves as a seed layer for plating and may be patterned. Another metal may act as a current carrying conductor during plating.
According to a particular application, an object of the present invention is to provide a process that permits attaching C4 solder balls directly to a final metal level in and/or on a substrate without requiring the utilization of a mask typical of traditional processes.
An advantage of the present invention is that it provides a less expensive process that known process for producing similar results.
Another advantage of the present invention is that it may utilize a barrier metal to carry plating current.
A further advantage of the present invention is that it may eliminate plating of metal on pins.
An additional advantage of the present invention is that it may provide higher productivity as compared to known processes.
In accordance with these and other objects and advantages, the present invention provides a method for plating a second metal directly to a first without utilizing a mask. A semiconductor substrate is provided including at least one metal feature of a first metal and at least one insulating layer covering said metal feature and the substrate. At least one recess is formed in the at least one insulating layer, thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is plated to the plating seed layer in the recess.
Aspects of the present invention also provide a method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature of a first metal and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer, thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer is formed over the at least one barrier layer. A pad is provided in the at least one recess for preventing removal of portions of the seed layer in the at least one recess. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. The pad is removed. A second metal is electroplated to the plating seed layer in the recess.
Furthermore, aspects of the present invention provide a semiconductor structure including a semiconductor substrate. At least one metal feature of a first metal is provided in the substrate. At least one insulating layer at least partially covers the at least one metal feature. At least one recess is located in the at least one insulating layer over the at least one metal feature. At least one conductive barrier layer is located over the at least one electrical insulating layer and over a portion of the at least one metal feature under the at least one recess. At least one plating seed layer is located over a portion of the conductive barrier layer within the recess. A second metal is electroplated to the seed layer in the recesses.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
SUMMARY OF THE DRAWINGS
The above objects and advantages of the present invention will be more clearly understood when considered in conjunction with the accompanying drawings, in which:
FIG. 1 represents a cross-sectional view of an embodiment of the present invention with a C4 opening etched over last metal;
FIG. 2 represents a cross-sectional view of an embodiment of the present invention illustrating a copper seedlayer after touch-up polishing to remove resist and copper seed-layer outside a depression, while leaving resist in the depression; and
FIG. 3 represents a cross-sectional view of an embodiment of the present invention illustrating a state in a process according to the present invention in which resist has been stripped, solder plated and reflowed, a barrier removed, copper seed layer consumed by solder reflow and a C4 ball arranged in a recess and joined to the structure.
BEST AND VARIOUS MODES FOR CARRYING OUT THE INVENTION
As described above, the present invention relates to electroplating a second metal on a metal feature of a first metal wherein the metal feature is arranged in and/or on a substrate. The present invention permits the second metal to be electroplated without utilizing a mask.
To carry out this process, methods of the present invention utilize a highly conducting barrier film alpha-Ta to carry current and selectively plate recesses in semiconducting and non-semiconducting substrates. The methods according to the present invention include providing a substrate. Various features may be provide in the substrate for accomplishing various tasks.
For example, the various features made of conductive material may be provided in and/or on the substrate. One example of such a feature is a metal last formed in the substrate. According to one example, the last is made of copper. However, as stated above, other features may be provided in the substrate having other forms and functions and made of other conductive materials.
Often, it is desired to attach devices, such as semiconductor chips, to a substrate, such as a chip carrier. A number of processes are available for attaching devices to a substrate. Many such processes may include providing electrical connections between a device and a substrate as well as attaching the device to the substrate.
An example of a device attachment method is the C4 process. This process is described in detail in U.S. Pat. No. 5,089,440 issued Feb. 18, 1992, to Christie et al., the entire disclosure of which is hereby incorporated by reference. Such methods are also described in U.S. Pat. Nos. 3,401,126 and 3,429,040 to Miller, the entire disclosure of which is hereby incorporated by reference. The present invention is particularly useful in such processes. However, usefulness of the present invention is by no means limited to such processes. In fact, the present invention may be useful in any application for selectively plating one metal to another metal utilizing more than one metal as an electrode.
According to the present invention, a conductive barrier film of α-Ta, TaN/α-Ta, α-Ta/TaN, or TaN/α-Ta/TaN with resistivity in the range of 14 to 50 micro-ohm cm is sputtered at least in at least one recess over a metal feature in a substrate. This is followed by the deposition of a plating base or seed layer over the barrier layer. A photoresist is deposited and patterned over the plating seed layer. The photoresist and seed layer are removed on all the field regions above the at least one recess, exposing the barrier layer. The photoresist remaining in the at least one recess is removed exposing the seed layer in the at least one recess. The substrate may then be electroplated, using the workpiece as the cathode. Accordingly, plating occurs on the seed layer in the at least one recess and not on other parts of the semiconductor substrate.
According to an alternate embodiment of the present invention, a barrier film of α-Ta, TaN/α-Ta, α-Ta/TaN, or TaN/α-Ta/TaN may be sputtered at least over the at least one recess in the substrate. A plating base or seed layer is deposited. The seed layer may then be polished off outside the at least one recess. The at least one recess may then be plated using the barrier film without seed layers at the periphery of the substrate wafers for electrical contact.
Further aspects of the present invention are concerned with semiconductor substrates that includes at least one semiconductor or circuit structure located on at least one of major surface.
In accordance with the present invention, as shown in FIG. 1, a substrate 1 may be provided. Typical semiconductor substrates include silicon and group III-V semiconductors.
At least one feature made of a conducting material may be provided in and/or on the substrate. The substrate shown in FIG. 1 includes a last 3 formed in the substrate. The last in the substrate shown in FIG. 1 is copper. The last is surrounded by a layer 2 of an insulating material.
The substrate and the conductive feature may be covered by at least one layer of an electrically insulating material. The insulating layer be thermally grown or deposited such as by chemical vapor deposition or physical vapor deposition. Typically, the insulating layer is about 2000 to about 30,000 Å thick, and more typically about 4000 to about 20,000 Å thick.
In the embodiment shown in FIG. 1, the substrate and the conductive feature are covered by an insulating layer made up of an oxide/nitride layer 5. In the embodiment shown in FIG. 1, a layer of polyimide 7 is deposited on the oxide/nitride layer 5. A polyimide passivation 8 layer made of, for example, a nitride and/or another hard insulator, may be deposited over the polyimide. The passivation layer may help to prevent the polyimide layer from picking up moisture and/or scratches, for example.
In the particular application of the present invention shown in FIG. 1, at least one recess 9 may be formed through the at least one insulating layer. The at least one recess is formed to as to expose at least a portion of the at least one conductive feature. Each conductive feature may have at least one recess formed exposing the conductive feature. More than one recess may be formed over some conductive features.
In the embodiment shown in FIG. 1, the recess 9 exposes a portion of the last metal 3. The recess may be formed according to known photolithography techniques. The recess may be formed during the deposition of the at least one insulating layer. Alternatively, the at least one recess may be formed in the at least one insulating layer after formation of the at least one insulating layer.
Next, a conductive barrier 11 may be provided over the insulating layer. Preferably, the conductive barrier may include a layer of tantalum nitride first sputter deposited over the insulating layer, the walls of the recess, and the exposed conductive feature to a thickness of about 15 Å to about 500 Å and more typically to a thickness of about 50 to about 300 to act as adhesion promoting layer between the insulating layer and subsequently to be applied tantalum layer. Then, a tantalum layer may be sputtered over the layer of tantalum nitride, where it may form α-Ta spontaneously. Typically, the thickness of the tantalum layer is about 500 Å to about 3000 Å A and more typically about 1000 Å to about 2000 Å. Also, α-Ta may be deposited directly over the insulator by sputtering methods. Typically, the thickness of the α-Ta is about 500 Å to about 5000 Å, and more typically about 1000 Å to about 3000.
After the deposition of the barrier layer, a seed layer 13 may be deposited over the barrier layer 11 including on the walls and bottom of the recess(es). The preferred seed layer is copper, which can be deposited by sputtering or evaporation and preferably by sputtering. The copper may be sputtered employing temperatures of less than about 150° C., preferably less than about 100° C., such as about 100° C. to about −10° C. The sputtering may be carried out in the absence of an anneal. The sputtering is typically carried out to provide a seed layer of about 100 Å to about 2000 Å and preferably about 400 Å to about 1000 Å. Also, the copper seed layer may be deposited by CVD methods or by electroless plating method or by an electrolytic plating method.
After formation of the seed layer, a photoresist may be deposited over the seed layer. Any of the well known photosensitive resist materials known in the art can be employed. The resist is typically applied by spinning on or by spraying.
The photoresist employed can be a positive photoresist or a negative photoresist. A positive photoresist material is one which on exposure to imaging radiation, is capable of being rendered soluble in a solvent in which the unexposed resist is not soluble. A negative resist material is one which is capable of polymerizing and/or insolubilizing upon exposure to imaging radiation.
An example of a type of photoresist material is based upon phenolic-formaldehyde Novolak polymers. A particular example of such is Shipley AZ-1350 which is a m-cresol formaldehyde novolak polymer composition. Such is a positive resist composition and includes therein a diazo ketone such as 2-diazo-1-naphthol-5-sulfonic acid ester.
The photoresist may be selectively removed everywhere except for in the recess(es). The resist remaining in the recess(es) may protects protect the seed layer in the recesses (both the side walls and bottom of the recesses). The seed layer lying outside of the recesses may be removed simultaneously with the photoresist. Actually, since the seed layer lies under the photoresist, the seed layer may be removed subsequent to the removal of the photoresist. They may be removed by the same process.
Both the photoresist and the seed layer may be removed by a process such as chemical-mechanical polishing. The chemical-mechanical polishing may employ, for example, an aqueous polishing slurry containing abrasive particles such as colloidal silica.
Next, the portions 15 of the resist layer remaining in the recess(es) that protected the seed layer within the recesses from removal is removed. The resist may be removed by dissolving in a suitable solvent for the photoresist material.
According to an alternative embodiment, photoresist may not be utilized. Such an embodiment may utilize a very hard pad to prevent dishing of the seed layer in the depression. A hard polishing pad, such as IC 1000 or IC 100/Suba IV from Rodel Inc., may be used to polish off the seed layer. One possible disadvantage of not using photoresist is that slurry utilized in chemical-mechanical polishing techniques may enter the recess. The slurry typically would then need to be removed. One way to remove the slurry is in a megasonic cleaning solution.
After removal of the resist, if necessary, conductive metal 17, such as lead-tin or other terminal metallurgies, is electroplated on the portions of the seed layer remaining in the recesses, to result in the structure shown in FIG. 3. During the electroplating, the barrier layer 11 may act as a cathode terminal for carrying the electroplating current. For lead-tin solders, plating, commercial solder plating baths such as NF 800 HS or NF 72 BC from Technic Inc., Rhode Island, may be used. Other proprietary commercially available lead-tin solders, eutectic solders, lead-free solders and/or other platable terminal metallurgies may be utilized.
The electroplating is continued until a desired amount of the conductive metal is plated in the recess(es). This usually takes about 10 min. to about 90 min, more typically about 20 min. to about 75 min. The thickness of the electroplated metal or alloy is typically about 25μ to about 200μ, and more typically about 40μ to about 75μ.
In the case of exposed α-Ta, the metal being plated will not plate on the barrier layer due to the formation of a very thin oxide layer when contacting the electroplating bath. The oxide layer may be described as a “superficial” layer. This oxide layer will form naturally if the barrier layer is a tantalum layer such as that described above. In another embodiment, the oxide layer may be formed by momentarily reversing the polarity of the field, rendering the workpiece anodic, prior to the electroplating. The polarity change may be brief, such as about 10 seconds. Formation of the oxide layer may also be described as “anodization”. The current density should be such that at the end of the current reversal, sufficient copper is left in the recesses for plating to initiate.
Next, the barrier layer 11 may be removed down to the polyimide or polyimide passivation layer, after the solder reflow. The barrier layer may be removed by utilizing the electroplated metal as a mask.
According to the process of the present invention, no lithograph step is required to define the seed layer since the chemical-mechanical polishing step makes the seed layer self-aligning to the recess(es). Not requiring a lithographic step simplifies the process. Additionally, the process may be less costly as compared to typical lithographically defined C4 processes. This simplification and cost advantage may be realized in any process requiring similar selective plating of metal(s).
The foregoing description of the invention illustrates and describes the present invention. Additionally, the disclosure shows and describes only the preferred embodiments of the invention but, as mentioned above, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings and/or the skill or knowledge of the relevant art. The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.

Claims (62)

1. A method for plating a second metal directly to a first metal, said method comprisingthe steps of :
providing a semiconductor substrate including at least one metal feature and at least one insulating layer covering said metal feature and said substrate;
forming at least one recess in said at least one insulating layer thereby exposing at least a portion of said metal feature;
forming at least one conductive barrier layer over said insulating layer and said exposed portion of said metal feature;
forming a plating seed layer of a first metal over said at least one barrier layer;
depositing a photoresist layer over said plating seed layer and in said at least one recess;
removing portions of said photoresist layer and portions of said plating seed layer outside of said at least one recess;
removing photoresist remaining in said at least one recess; and
electroplating a second metal to said plating seed layer in said recess without utilizing a lithographic mask.
2. The method according to claim 1, wherein said metal feature is a metal last provided in said semiconductor substrate.
3. The method according to claim 1, wherein said conductive barrier is provided by sputter deposition of a layer of at least one nitride of tantalum on said insulating layer and said exposed portion of said metal feature and subsequent sputter deposition of a layer of tantalum on said tantalum nitride layer, such that the layer including the nitride of tantalum layer of tantalum on said tantalum nitride layer is in the α-phase.
4. The method according to claim 3, wherein said tantalum nitride layer is about 10 Å to about 1000 Å thick and said tantalum layer is about 500 Å to about 5000 Å thick.
5. The method according to claim 1, wherein said seed layer is formed by electrolytic or electroless plating of said first metal.
6. The method according to claim 5, wherein said seed layer is copper.
7. The method according to claim 6, wherein said copper is sputter coated on said conductive barrier layerof tantalum .
8. The method according to claim 7, wherein said layer of tantalum is α-Ta/TaN layer.
9. The method according to claim 6, wherein said copper layer is about 1000 Å to about 20,000 Å thick.
10. The method according to claim 3, wherein said tantalum is alpha tantalum.
11. The method of claim 3, wherein said tantalum layer is TaN/α-Ta/TaN-laminate.
12. The method according to claim 1, wherein said portions of said photoresist layer and said plating seed layer outside of said at least one recess are removed by chemical-mechanical polishing.
13. The method according to claim 1, wherein said photoresist is spun on said plating seed layer.
14. The method according to claim 1, wherein said barrier layer forms a conductor for said electroplating of said second metal.
15. The method according to claim 1, wherein said second metal is a solder ball made of an alloy of lead and tin, plated lead-free solder or other platable terminal metallurgies.
16. The method according to claim 1, further comprising the step of :
removing said at least one conductive barrier layer from horizontal portions between saidrecesses at least one recess.
17. The method according to claim 16, wherein said electroplated second metal acts as a mask for the removal of said at least one conductive barrier layer.
18. The method according to claim 1, wherein said at least one metal feature is formed in said substrate.
19. The method according to claim 1, wherein said insulating layer includes a layer of an oxide and a nitride and at least one layer of a polyimide.
20. The method of claim 19, further comprisingthe step of :
forming a layer of at least one nitride or other passivation layer over the polyimide.
21. The method according to claim 1, wherein said second metal is a solder ball.
22. A method for plating a second metal directly to a first metal, said method comprisingthe steps of :
providing a semiconductor substrate including at least one metal feature and at least one insulating layer covering said metal feature and said substrate;
forming at least one recess in said at least one insulating layer thereby exposing at least a portion of said metal feature;
forming at least one conductive barrier layer over said insulating layer and said exposed portion of said metal feature;
forming a plating seed layer of a first metal over said at least one barrier layer;
providing a pad in said at least one recess for preventing removal of portions of said seed layer in said at least one recess;
removing portions of said plating seed layer outside of said at least one recess;
removing said pad; and
electroplating a second metal to said plating seed layer in said recess without utilizing a lithographic mask.
23. The method of claim 22, further comprisingthe step of :
utilizing a hard polishing pad to remove said seed layer outside of said recess.
24. A method for plating a second metal directly to a first metal, said method comprising:
providing a semiconductor substrate including at least one metal feature and at least one insulating layer covering said metal feature and said substrate;
forming at least one recess in said at least one insulating layer thereby exposing at least a portion of said metal feature;
forming at least one conductive barrier layer over said insulating layer and said exposed portion of said metal feature;
forming a plating seed layer of a first metal over said at least one barrier layer;
removing portions of said plating seed layer outside of said at least one recess; and
electroplating a second metal to said plating seed layer in said recess without utilizing a lithographic mask.
25. The method according to claim 24, wherein said metal feature is a metal last provided in said semiconductor substrate.
26. The method according to claim 24, wherein said conductive barrier is provided by sputter deposition of a layer of at least one nitride of tantalum on said insulating layer and said exposed portion of said metal feature and subsequent sputter deposition of a layer of tantalum on said tantalum nitride layer, such that the layer including the nitride of tantalum is in the α-phase.
27. The method according to claim 26, wherein said tantalum nitride layer is about 10 Å to about 1000 Å thick and said tantalum layer is about 500 Å to about 5000 Å thick.
28. The method according to claim 24, wherein said seed layer is formed by electrolytic or electroless plating of said first metal.
29. The method according to claim 28, wherein said seed layer is copper.
30. The method according to claim 29, wherein said copper is sputter coated on said conductive barrier layer.
31. The method according to claim 30, wherein said layer of tantalum is α-Ta/TaN layer.
32. The method according to claim 28, wherein said copper layer is about 1000 Å to about 20,000 Å thick.
33. The method according to claim 26, wherein said tantalum is alpha tantalum.
34. The method of claim 26, wherein said tantalum layer is TaN/α-Ta/TaN-laminate.
35. The method according to claim 24, wherein said seed layer outside of said recess is removed by chemical-mechanical polishing.
36. The method according to claim 24, wherein said barrier.
37. The method according to claim 24, wherein said second metal is a solder ball made of an alloy of lead and tin, plated lead-free solder or other platable terminal metallurgies.
38. The method according to claim 24, further comprising:
removing said at least one conductive barrier layer from horizontal portions between said at least one recess.
39. The method according to claim 38, wherein said electroplated second metal acts as a mask for the removal of said at least one conductive barrier layer.
40. The method according to claim 24, wherein said at least one metal feature is formed in said substrate.
41. The method according to claim 24, wherein said insulating layer includes a layer of an oxide and a nitride and at least one layer of a polyimide.
42. The method of claim 41 further comprising
forming a layer of at least one nitride or other passivation layer over the polyimide.
43. The method according to claim 24, wherein said second metal is a solder ball.
44. The method according to claim 22, wherein said metal feature is a metal last provided in said semiconductor substrate.
45. The method according to claim 22, wherein said conductive barrier is provided by sputter deposition of a layer of at least one nitride of tantalum on said insulating layer and said exposed portion of said metal feature and subsequent sputter deposition of a layer of tantalum on said tantalum nitride layer, such that the layer including the nitride of tantalum is in the α-phase.
46. The method according to claim 45, wherein said tantalum nitride layer is about 10 Å to about 1000 Å thick and said tantalum layer is about 500 Å to about 5000 Å thick.
47. The method according to claim 22, wherein said seed layer is formed by electrolytic or electroless plating of said first metal.
48. The method according to claim 47, wherein said seed layer is copper.
49. The method according to claim 48, wherein said copper is sputter coated on said conductive barrier layer.
50. The method according to claim 49, wherein said layer of tantalum is α-Ta/TaN layer.
51. The method according to claim 48, wherein said copper layer is about 1000 Å to about 20,000 Å thick.
52. The method according to claim 45, wherein said tantalum is alpha tantalum.
53. The method of claim 45, wherein said tantalum layer is TaN/α-Ta/TaN-laminate.
54. The method according to claim 22, wherein said portions of said seed layer outside of said recess are removed by chemical-mechanical polishing.
55. The method according to claim 22, wherein said barrier layer forms a conductor for said electroplating of said second metal.
56. The method according to claim 22, wherein said second metal is a solder ball made of an alloy of lead and tin, plated lead-free solder or other platable terminal metallurgies.
57. The method according to claim 22, further comprising the step of:
removing said at least one conductive barrier layer from horizontal portions between said at least one recess.
58. The method according to claim 57, wherein said electroplated second metal acts as a mask for the removal of said at least one conductive barrier layer.
59. The method according to claim 22, wherein said at least one metal feature is formed in said substrate.
60. The method according to claim 22, wherein said insulating layer includes a layer of an oxide and a nitride and at least one layer of a polyimide.
61. The method of claim 60, further comprising:
forming a layer of at least one nitride or other passivation layer over the polyimide.
62. The method according to claim 22, wherein said second metal is a solder ball.
US10/677,166 1998-01-09 2003-10-02 Method to plate C4 to copper stud Expired - Lifetime USRE40983E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/677,166 USRE40983E1 (en) 1998-01-09 2003-10-02 Method to plate C4 to copper stud

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/004,808 US6251528B1 (en) 1998-01-09 1998-01-09 Method to plate C4 to copper stud
US09/389,232 US6297140B1 (en) 1998-01-09 1999-09-03 Method to plate C4 to copper stud
US10/677,166 USRE40983E1 (en) 1998-01-09 2003-10-02 Method to plate C4 to copper stud

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/389,232 Reissue US6297140B1 (en) 1998-01-09 1999-09-03 Method to plate C4 to copper stud

Publications (1)

Publication Number Publication Date
USRE40983E1 true USRE40983E1 (en) 2009-11-17

Family

ID=21712626

Family Applications (4)

Application Number Title Priority Date Filing Date
US09/004,808 Expired - Fee Related US6251528B1 (en) 1998-01-09 1998-01-09 Method to plate C4 to copper stud
US09/389,232 Ceased US6297140B1 (en) 1998-01-09 1999-09-03 Method to plate C4 to copper stud
US09/887,443 Abandoned US20010032787A1 (en) 1998-01-09 2001-06-25 Method to plate C4 to copper stud
US10/677,166 Expired - Lifetime USRE40983E1 (en) 1998-01-09 2003-10-02 Method to plate C4 to copper stud

Family Applications Before (3)

Application Number Title Priority Date Filing Date
US09/004,808 Expired - Fee Related US6251528B1 (en) 1998-01-09 1998-01-09 Method to plate C4 to copper stud
US09/389,232 Ceased US6297140B1 (en) 1998-01-09 1999-09-03 Method to plate C4 to copper stud
US09/887,443 Abandoned US20010032787A1 (en) 1998-01-09 2001-06-25 Method to plate C4 to copper stud

Country Status (2)

Country Link
US (4) US6251528B1 (en)
JP (1) JP3245122B2 (en)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1222641C (en) * 1998-02-12 2005-10-12 Acm研究公司 Plating apparatus and method
JP2000216184A (en) * 1999-01-25 2000-08-04 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof
TW444288B (en) * 1999-01-27 2001-07-01 Shinko Electric Ind Co Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device
US6355153B1 (en) * 1999-09-17 2002-03-12 Nutool, Inc. Chip interconnect and packaging deposition methods and structures
US7105434B2 (en) 1999-10-02 2006-09-12 Uri Cohen Advanced seed layery for metallic interconnects
US6610151B1 (en) * 1999-10-02 2003-08-26 Uri Cohen Seed layers for interconnects and methods and apparatus for their fabrication
US6924226B2 (en) * 1999-10-02 2005-08-02 Uri Cohen Methods for making multiple seed layers for metallic interconnects
US6429531B1 (en) * 2000-04-18 2002-08-06 Motorola, Inc. Method and apparatus for manufacturing an interconnect structure
US20060118425A1 (en) * 2000-04-19 2006-06-08 Basol Bulent M Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate
US6368484B1 (en) * 2000-05-09 2002-04-09 International Business Machines Corporation Selective plating process
JP2002026515A (en) * 2000-07-07 2002-01-25 Toshiba Corp Printed wiring board and its manufacturing method
US6921551B2 (en) 2000-08-10 2005-07-26 Asm Nutool, Inc. Plating method and apparatus for controlling deposition on predetermined portions of a workpiece
US6511912B1 (en) * 2000-08-22 2003-01-28 Micron Technology, Inc. Method of forming a non-conformal layer over and exposing a trench
TW455965B (en) * 2000-08-29 2001-09-21 Phoenix Prec Technology Corp Method for forming solder bumpers on IC package substrate and structure formed by the same
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US6667230B2 (en) * 2001-07-12 2003-12-23 Taiwan Semiconductor Manufacturing Co., Ltd. Passivation and planarization process for flip chip packages
FR2828009B1 (en) * 2001-07-25 2003-10-10 Novatec METHOD OF MAKING BOSSES HAVING IMPROVED THERMOMECHANICAL PERFORMANCE
US6661098B2 (en) * 2002-01-18 2003-12-09 International Business Machines Corporation High density area array solder microjoining interconnect structure and fabrication method
US7449099B1 (en) * 2004-04-13 2008-11-11 Novellus Systems, Inc. Selectively accelerated plating of metal features
TW558782B (en) * 2002-09-10 2003-10-21 Siliconware Precision Industries Co Ltd Fabrication method for strengthened flip-chip solder bump
US7565137B2 (en) * 2002-10-25 2009-07-21 At&T Mobility Ii Llc Delivery of network services
US7294241B2 (en) * 2003-01-03 2007-11-13 Chartered Semiconductor Manufacturing Ltd. Method to form alpha phase Ta and its application to IC manufacturing
KR100572825B1 (en) * 2003-07-31 2006-04-25 동부일렉트로닉스 주식회사 Method of manufacturing metal layer of semiconductor device
US20050098605A1 (en) * 2003-11-06 2005-05-12 International Business Machines Corporation Apparatus and method for low pressure wirebond
US7068138B2 (en) * 2004-01-29 2006-06-27 International Business Machines Corporation High Q factor integrated circuit inductor
TWI253888B (en) * 2004-12-09 2006-04-21 Advanced Semiconductor Eng Method of packaging flip chip and method of forming pre-solders on substrate thereof
US7282433B2 (en) 2005-01-10 2007-10-16 Micron Technology, Inc. Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
US8500985B2 (en) 2006-07-21 2013-08-06 Novellus Systems, Inc. Photoresist-free metal deposition
US7833893B2 (en) * 2007-07-10 2010-11-16 International Business Machines Corporation Method for forming conductive structures
US20090065365A1 (en) * 2007-09-11 2009-03-12 Asm Nutool, Inc. Method and apparatus for copper electroplating
US7868453B2 (en) * 2008-02-15 2011-01-11 International Business Machines Corporation Solder interconnect pads with current spreading layers
US8211776B2 (en) 2010-01-05 2012-07-03 International Business Machines Corporation Integrated circuit line with electromigration barriers
CN102738385B (en) * 2011-04-08 2014-11-05 美新半导体（无锡）有限公司 Packaging method and packaging structure of triaxial magnetic sensor
DE102011110171B3 (en) * 2011-08-16 2012-11-29 Rena Gmbh Forming metallic conductor pattern on surface of substrate made of semiconductor material, comprises providing discrete textured areas of semiconductor material, and carrying out galvanic deposition of metallic seed layer and metal layer
US9123726B2 (en) 2013-01-18 2015-09-01 International Business Machines Corporation Selective local metal cap layer formation for improved electromigration behavior
US9076847B2 (en) 2013-01-18 2015-07-07 International Business Machines Corporation Selective local metal cap layer formation for improved electromigration behavior
US9604338B2 (en) * 2015-08-04 2017-03-28 Texas Instruments Incorporated Method to improve CMP scratch resistance for non planar surfaces
US10957664B2 (en) * 2019-05-29 2021-03-23 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
JP7439652B2 (en) * 2020-06-02 2024-02-28 トヨタ自動車株式会社 Manufacturing method of wiring board

Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155055A (en) * 1976-06-18 1977-12-23 Matsushita Electric Ind Co Ltd Production of semiconductor device
US4840302A (en) * 1988-04-15 1989-06-20 International Business Machines Corporation Chromium-titanium alloy
US5010389A (en) * 1989-07-26 1991-04-23 International Business Machines Corporation Integrated circuit substrate with contacts thereon for a packaging structure
JPH03190240A (en) * 1989-12-20 1991-08-20 Fujitsu Ltd Manufacture of semiconductor device
US5089440A (en) * 1990-03-14 1992-02-18 International Business Machines Corporation Solder interconnection structure and process for making
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
US5256274A (en) * 1990-08-01 1993-10-26 Jaime Poris Selective metal electrodeposition process
US5298459A (en) * 1988-11-21 1994-03-29 Seiko Epson Corporation Method of manufacturing semiconductor device terminal having a gold bump electrode
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5384283A (en) * 1993-12-10 1995-01-24 International Business Machines Corporation Resist protection of ball limiting metal during etch process
US5462638A (en) * 1994-06-15 1995-10-31 International Business Machines Corporation Selective etching of TiW for C4 fabrication
US5486282A (en) * 1994-11-30 1996-01-23 Ibm Corporation Electroetching process for seed layer removal in electrochemical fabrication of wafers
US5492235A (en) * 1995-12-18 1996-02-20 Intel Corporation Process for single mask C4 solder bump fabrication
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
EP0751566A2 (en) * 1995-06-30 1997-01-02 International Business Machines Corporation A thin film metal barrier for electrical interconnections
US5591480A (en) * 1995-08-21 1997-01-07 Motorola, Inc. Method for fabricating metallization patterns on an electronic substrate
US5736456A (en) * 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US5834827A (en) * 1994-06-15 1998-11-10 Seiko Epson Corporation Thin film semiconductor device, fabrication method thereof, electronic device and its fabrication method
US5872696A (en) * 1997-04-09 1999-02-16 Fujitsu Limited Sputtered and anodized capacitors capable of withstanding exposure to high temperatures
US5891802A (en) * 1997-07-23 1999-04-06 Advanced Micro Devices, Inc. Method for fabricating a metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects
US6025275A (en) * 1996-12-19 2000-02-15 Texas Instruments Incorporated Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect
US6080656A (en) * 1999-09-01 2000-06-27 Taiwan Semiconductor Manufacturing Company Method for forming a self-aligned copper structure with improved planarity
US6093647A (en) * 1998-11-03 2000-07-25 Advanced Micro Devices, Inc. Method to selectively electroplate conductive material into trenches
US6140234A (en) * 1998-01-20 2000-10-31 International Business Machines Corporation Method to selectively fill recesses with conductive metal

Patent Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155055A (en) * 1976-06-18 1977-12-23 Matsushita Electric Ind Co Ltd Production of semiconductor device
US4840302A (en) * 1988-04-15 1989-06-20 International Business Machines Corporation Chromium-titanium alloy
US5298459A (en) * 1988-11-21 1994-03-29 Seiko Epson Corporation Method of manufacturing semiconductor device terminal having a gold bump electrode
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5010389A (en) * 1989-07-26 1991-04-23 International Business Machines Corporation Integrated circuit substrate with contacts thereon for a packaging structure
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
JPH03190240A (en) * 1989-12-20 1991-08-20 Fujitsu Ltd Manufacture of semiconductor device
US5089440A (en) * 1990-03-14 1992-02-18 International Business Machines Corporation Solder interconnection structure and process for making
US5256274A (en) * 1990-08-01 1993-10-26 Jaime Poris Selective metal electrodeposition process
US5384283A (en) * 1993-12-10 1995-01-24 International Business Machines Corporation Resist protection of ball limiting metal during etch process
US5834827A (en) * 1994-06-15 1998-11-10 Seiko Epson Corporation Thin film semiconductor device, fabrication method thereof, electronic device and its fabrication method
US5462638A (en) * 1994-06-15 1995-10-31 International Business Machines Corporation Selective etching of TiW for C4 fabrication
US5503286A (en) * 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
US5543032A (en) * 1994-11-30 1996-08-06 Ibm Corporation Electroetching method and apparatus
US5486282A (en) * 1994-11-30 1996-01-23 Ibm Corporation Electroetching process for seed layer removal in electrochemical fabrication of wafers
EP0751566A2 (en) * 1995-06-30 1997-01-02 International Business Machines Corporation A thin film metal barrier for electrical interconnections
US5591480A (en) * 1995-08-21 1997-01-07 Motorola, Inc. Method for fabricating metallization patterns on an electronic substrate
US5492235A (en) * 1995-12-18 1996-02-20 Intel Corporation Process for single mask C4 solder bump fabrication
US5736456A (en) * 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US6025275A (en) * 1996-12-19 2000-02-15 Texas Instruments Incorporated Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect
US5872696A (en) * 1997-04-09 1999-02-16 Fujitsu Limited Sputtered and anodized capacitors capable of withstanding exposure to high temperatures
US5891802A (en) * 1997-07-23 1999-04-06 Advanced Micro Devices, Inc. Method for fabricating a metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects
US6140234A (en) * 1998-01-20 2000-10-31 International Business Machines Corporation Method to selectively fill recesses with conductive metal
US6093647A (en) * 1998-11-03 2000-07-25 Advanced Micro Devices, Inc. Method to selectively electroplate conductive material into trenches
US6080656A (en) * 1999-09-01 2000-06-27 Taiwan Semiconductor Manufacturing Company Method for forming a self-aligned copper structure with improved planarity

Also Published As

Publication number Publication date
US6251528B1 (en) 2001-06-26
US6297140B1 (en) 2001-10-02
JP3245122B2 (en) 2002-01-07
JPH11274208A (en) 1999-10-08
US20010032787A1 (en) 2001-10-25

Similar Documents

Publication Publication Date Title
USRE40983E1 (en) Method to plate C4 to copper stud
US7456501B1 (en) Semiconductor structure having recess with conductive metal
KR100279323B1 (en) Process for integrated circuit wiring
US6096648A (en) Copper/low dielectric interconnect formation with reduced electromigration
JP5244129B2 (en) Method for forming a contact electrode for a semiconductor chip
US7008867B2 (en) Method for forming copper bump antioxidation surface
US6426281B1 (en) Method to form bump in bumping technology
US7594322B2 (en) Methods of fabricating substrates including at least one conductive via
Datta Electrochemical processing technologies in chip fabrication: challenges and opportunities
US6384481B1 (en) Single step electroplating process for interconnect via fill and metal line patterning
US6582579B1 (en) Methods for repairing defects on a semiconductor substrate
US6737360B2 (en) Controlled potential anodic etching process for the selective removal of conductive thin films
JP2012235134A (en) Process and integration scheme for manufacturing semiconductor components including conductive components, through vias and conductive through wafer vias
US5796168A (en) Metallic interconnect pad, and integrated circuit structure using same, with reduced undercut
US5674780A (en) Method of forming an electrically conductive polymer bump over an aluminum electrode
US20070246133A1 (en) Method for Electroplating and Contact Projection Arrangement
US6589816B2 (en) Method of forming metal connection elements in integrated circuits
US20030168345A1 (en) In-situ monitor seed for copper plating
TW200535987A (en) Reverse-tone mask method for post-cmp elimination of copper overburden humps
US6699785B2 (en) Conductor abrasiveless chemical-mechanical polishing in integrated circuit interconnects
US20040196697A1 (en) Method of improving surface mobility before electroplating

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 12

SULP Surcharge for late payment

Year of fee payment: 11