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USRE40112E1 - Semiconductor package and method for fabricating the same - Google Patents

Semiconductor package and method for fabricating the same Download PDF

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Publication number
USRE40112E1
USRE40112E1 US10/825,670 US82567004A USRE40112E US RE40112 E1 USRE40112 E1 US RE40112E1 US 82567004 A US82567004 A US 82567004A US RE40112 E USRE40112 E US RE40112E
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United States
Prior art keywords
circuit board
major surface
strip
board strip
fashion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/825,670
Inventor
Won Sun Shin
Do Sung Chun
Sang Ho Lee
Seon Goo Lee
Vincent DiCaprio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amkor Technology Singapore Holding Pte Ltd
Original Assignee
Amkor Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019990018244A external-priority patent/KR20000074350A/en
Priority claimed from KR1019990037925A external-priority patent/KR100365054B1/en
Priority claimed from KR10-1999-0037928A external-priority patent/KR100369394B1/en
Priority claimed from US09/574,541 external-priority patent/US6395578B1/en
Priority to US10/825,670 priority Critical patent/USRE40112E1/en
Application filed by Amkor Technology Inc filed Critical Amkor Technology Inc
Publication of USRE40112E1 publication Critical patent/USRE40112E1/en
Application granted granted Critical
Assigned to BANK OF AMERICA, N.A. reassignment BANK OF AMERICA, N.A. PATENT SECURITY AGREEMENT Assignors: AMKOR TECHNOLOGY, INC.
Assigned to BANK OF AMERICA, N.A., AS AGENT reassignment BANK OF AMERICA, N.A., AS AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AMKOR TECHNOLOGY, INC.
Anticipated expiration legal-status Critical
Assigned to AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD. reassignment AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AMKOR TECHNOLOGY, INC.
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Definitions

  • the present invention relates to a semiconductor package and a method for fabricating the semiconductor package.
  • This application is a REI of 09 / 574 , 541 filed on May 19 , 2000 U.S. Pat. No. 6 , 395 , 578 .
  • BGA ball grid array
  • semiconductor chips which are mounted on semiconductor packages as mentioned above, have been developed toward a high performance of electric power circuits, an increase in operating frequency, and an expansion of circuit functions, in pace with the development of integration techniques and manufacturing equipment. For this reason, an increase in heat occurs inevitably during the operation of such a semiconductor chip.
  • FIG. 10 a typical BGA semiconductor package having a conventional structure involving the above mentioned problem is illustrated.
  • the BGA semiconductor package which is denoted by the reference numeral 100 ′, includes a semiconductor chip 1 ′ arranged at a central portion of the semiconductor package 100 ′.
  • the semiconductor chip 1 ′ is provided with a plurality of integrated electronic circuits.
  • a plurality of input/output pads 2 ′ are provided at an upper surface of the semiconductor chip 1 ′.
  • a circuit board 10 ′ is bonded at a central portion thereof to a lower surface of the semiconductor chip 1 ′ by means of an adhesive 3 ′.
  • the circuit board 10 ′ includes a resin substrate 15 ′.
  • a circuit pattern 12 ′ provided with bond fingers 11 ′ is formed on an upper surface of the resin substrate 15 ′ around the semiconductor chip 1 ′.
  • Another circuit pattern provided with a plurality of ball lands 13 ′ is formed on a lower surface of the resin substrate 15 ′.
  • Each of the circuit patterns is comprised of a thin film made of a conductive material such as copper (Cu). These circuit patterns are interconnected together by via holes 14 ′.
  • the exposed surface portions of the circuit patterns not covered with the bond fingers 11 ′ and ball lands 13 ′ are coated with cover coats 16 ′, respectively, so that those circuit patterns are protected from the external environment.
  • the input/output pads 2 ′ of the semiconductor chip 1 ′ are connected to the bond fingers 11 ′ on the upper surface of the circuit board 10 ′ by means of conductive wires 4 ′, respectively.
  • the upper surface of the circuit board 10 ′ is encapsulated by a resin encapsulate 20 ′.
  • the circuit board 10 ′ is mounted on a mother board (not shown) in a state in which a plurality of conductive balls 40 ′ are fused on the ball lands 13 ′, respectively, so that it serves as a medium for electrical signals between the semiconductor chip 1 ′ and mother board.
  • the semiconductor chip 1 ′ thereof exchanges electrical signals with the mother board via the input/output pads 2 ′, conductive wires 4 ′, bond fingers 11 ′, via holes 14 ′, ball lands 13 ′, and conductive balls 40 ′, respectively.
  • the above mentioned conventional BGA semiconductor package is problematic in that it has an increased thickness because the semiconductor chip is bonded to the upper surface of the circuit board having a relatively large thickness. This is contrary to the recent trend toward a miniaturization and thinness. As a result, the above mentioned semiconductor package is problematic in that it cannot be applied to a variety of miniature electronic appliances such as portable phones, cellular phones, pagers, and notebooks.
  • the conventional semiconductor package is implicated in a heat-related degradation in the electrical performance and other functions of the semiconductor chip. In severe cases, the semiconductor package and the electronic appliance using it may be so damaged as not to be inoperable.
  • an object of the invention is to provide a semiconductor package having a super-thin structure and a method for fabricating the semiconductor package.
  • Another object of the invention is to provide a semiconductor package having a structure capable of easily discharging heat from a semiconductor chip included therein, and a method for fabricating the semiconductor package.
  • the present invention provides a semiconductor package comprising: a semiconductor chip having a first major surface and a second major surface, the semiconductor chip being provided at the second major surface with a plurality of input/output pads; a circuit board including a resin substrate having a first major surface and a second major surface, a first circuit pattern formed at the first major surface and provided with a plurality of ball lands, a second circuit pattern formed at the second major surface and provided with a plurality of bond fingers connected with the ball lands by conductive via holes, cover coats respectively coating the first and second circuit patterns while allowing the bond fingers and the ball lands to be open, and a central through hole adapted to receive the semiconductor chip therein; electrical connection means for electrically connecting the input/output pads of the semiconductor chip with the bond fingers of the circuit board, respectively; a resin encapsulate for encapsulating the semiconductor chip, the electrical connection means, and the circuit board; and a plurality of conductive balls fused on the ball lands of the circuit board, respectively.
  • the semiconductor chip may be arranged in such a fashion that it is oriented, at the second major surface thereof, in the same direction as the second major surface of the circuit board provided with the bond fingers while being flush, at the first major surface thereof, with the first major surface of the circuit board provided with the ball lands and one surface of the resin encapsulate.
  • the resin encapsulate may be formed to completely or partially encapsulate the second major surface of the circuit board provided with the bond fingers.
  • the second major surface of the circuit board provided with the bond fingers may be further provided with a plurality of ball lands.
  • a plurality of conductive balls may be fused on the ball lands provided at the second major surface of the circuit board, respectively.
  • the semiconductor package may further comprises a closure member attached to the first major surface of the semiconductor chip and adapted to cover the through hole of the circuit board.
  • each of the closure members comprises an insulating tape or a copper layer.
  • the present invention provided a method for fabricating semiconductor packages comprising the steps of: preparing a circuit board strip including a plurality of unit circuit boards, the circuit board strip having a plurality of ball lands formed at a first major surface thereof, a plurality of bond fingers formed at a second major surface thereof and respectively connected with the ball lands by conductive via holes, and a plurality of through holes respectively associated with the unit circuit boards; receiving, in the through holes, semiconductor chips each having a first major surface and a second major surface provided with a plurality of input/output pads, respectively; electrically connecting the input/output pads of the semiconductor chips with associated ones of the bond fingers of the circuit board strip using connection means, respectively; encapsulating the semiconductor chips, the connection means, and the through holes of the circuit board strip using an encapsulating material; fusing conductive balls on the ball lands of the circuit board strip; and singulating the circuit board strip into semiconductor packages respectively corresponding to the unit circuit boards.
  • the circuit board strip prepared at the circuit board strip preparing step may comprise: a main strip including a resin substrate having a substantially rectangular strip shape provided with a first major surface and a second major surface; a plurality of main slots extending to a desired length in an direction transverse to a longitudinal direction of the main strip while being uniformly spaced apart from one another in the longitudinal direction of the main strip, thereby dividing the main strip into a plurality of sub-strips aligned together in the longitudinal direction of the main strip; a plurality of sub slots extending to a desired length and serving to divide each of the sub-strips into a plurality of strip portions arranged in a matrix array, each of the strip portions corresponding to one of the unit circuit boards while having one of the through holes; a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the ball lands; a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and
  • the circuit board strip prepared at the circuit board strip preparing step may comprise: a resin substrate having a substantially rectangular strip shape provided with a first major surface and a second major surface; a plurality of slots extending to a desired length and serving to divide each of the resin substrate into a plurality of substrate portions arranged in a matrix array, each of the substrate portions corresponding to one of the unit circuit boards while having one of the through holes; a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the ball lands; a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the bond fingers; and cover coats respectively coated over the first and second major surfaces of the resin substrate while allowing the bond fingers and the ball lands to be externally open.
  • the method may further comprise the step of attaching a plurality of closure members to the first major surface of the circuit board strip in such a fashion that each of the closure members covers an associated one of the through holes, prior to the strip of receiving the semiconductor chips in the through holes.
  • the method may further comprise the step of attaching a plurality of closure members to the first major surface of the main strip in such a fashion that each of the closure members covers an associated one of the through holes, prior to the step of receiving the semiconductor chips in the through holes.
  • the closure member attaching step may comprise the steps of preparing closure member strips each having closure members for an associated one of the sub-strips, and individually attaching the closure member strips to the sub-strips, respectively, in such a fashion that each of the closure member strips is arranged to cover the main slot formed at one side of an associated one of the sub-strips.
  • the closure member attaching step may comprise the steps of preparing a single closure member strip having closure members for all sub-strips of the circuit board strip while having small singulation apertures at a region corresponding to each of the main slots, and attaching the closure member strip to the main strip in such a fashion that the closure member strip is arranged to allow each of the small singulation apertures to be aligned with an associated one of the main slots.
  • closure members are removed after the encapsulating step, e.g., before or after the conductive ball fusing step, or after the singulation step.
  • the closure members may be removed by inserting a planar bar into each of the main slots in a direction from the second major surface of the circuit board strip to the first major surface of the second board strip, thereby detaching an associated one of the closure members from the circuit board strip at one side of the associated closure member.
  • Each of the closure members may comprise an insulating tape, an ultraviolet tape, or a copper layer.
  • the encapsulating step may be carried out to form an encapsulate completely encapsulating the second major surface of the circuit board strip.
  • the singulation step may be carried out in such a fashion that the encapsulate and the circuit board strip are simultaneously singulated.
  • the encapsulating step may comprise the steps of interposing the circuit board strip between a pair of molds, one of which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated one of the cavities while facing an associated one of the gates at a central portion thereof, and injecting the encapsulating material into each of the cavities through an associated one of the gates in such a fashion that it flows outwardly from the central portion of the second major surface of the associated semiconductor chip along the second major surface.
  • the circuit board strip prepared at the circuit board strip preparing step may be further provided with a plurality of ball lands at the second major surface thereof having the bond fingers.
  • the conductive ball fusing step further comprises the step of fusing a plurality of conductive balls on the ball lands provided at the second major surface of the circuit board strip having the bond fingers.
  • a circuit board which has a through hole of a desired size adapted to receive a semiconductor chip, thereby allowing the thickness of the semiconductor chip to be offset by the thickness of the circuit board. Accordingly, it is possible to fabricate semiconductor packages having a super-thin structure.
  • the semiconductor chip is outwardly exposed at one major surface thereof without being encapsulated by an encapsulate. Accordingly, heat generated from the semiconductor chip can be easily discharged into the atmosphere. This results in an improvement in the thermal and electrical performance of the semiconductor chip.
  • the circuit board may be completely encapsulated at one major surface thereof by an encapsulate. In this case, it is possible to effectively prevent a bending phenomenon of the circuit board.
  • closure members during the fabrication of semiconductor packages according to the present invention achieves an easy encapsulating process.
  • closer member strips may be used, each of which has closure members for one sub strip of a circuit board strip.
  • the closure member strips are individually attached to the sub-strips of the circuit board strip.
  • a single closure member strip may be used which has closure members for all sub-strips of the circuit board strip while having small singulation apertures or slits.
  • the encapsulating process involved in the fabrication of semiconductor packages is conducted in such a fashion that it proceeds from the second major surface of each semiconductor chip in accordance with the present invention. Accordingly, it is possible to achieve a uniform encapsulation while suppressing the occurrence of a wire sweeping phenomenon.
  • FIGS. 1 to 5 are cross-sectional views respectively illustrating semiconductor packages according to various exemplary embodiments of the present invention.
  • FIGS. 6A and 6B are a top view and a bottom view respectively illustrating an exemplary circuit board strip useful in the fabrication of the semiconductor packages described herein;
  • FIGS. 7A to 7 F are cross-sectional views respectively illustrating stages in a semiconductor package fabricating method according to the present invention.
  • FIGS. 8A and 8B are bottom views each illustrating an alternative method for attaching closure members in the exemplary fabrication method
  • FIG. 9 is a cross-sectional view illustrating an encapsulating method usable in the exemplary fabrication method described.
  • FIG. 10 is a cross-sectional view illustrating a typical BGA semiconductor package having a conventional structure.
  • FIGS. 1 to 5 semiconductor packages according to various embodiments of the present invention are illustrated, respectively.
  • the semiconductor package which is denoted by the reference numeral 101 , includes a semiconductor chip 30 having a first major surface 30 a (a lower surface in FIG. 1 ) and a second major surface 30 b (an upper surface in FIG. 1 ).
  • a plurality of input/output pads 31 are formed at the second major surface 30 b of the semiconductor chip 30 .
  • the semiconductor chip 30 is arranged in such a fashion that it is received in a through hole 12 formed 10 through a circuit board 10 to have a desired size.
  • the through hole 12 has a size larger than the area of the first or second surface 30 a or 30 b of the semiconductor chip 30 .
  • the circuit board 10 includes a resin substrate 17 having a first major surface 11 a (a lower surface in FIG. 1 ) and a second major surface 11 b (an upper surface of FIG. 1 ).
  • the through hole 12 is centrally formed through the resin substrate 17 .
  • the resin substrate 17 is provided at the first major surface 11 a thereof with a conductive circuit pattern 18 having a plurality of ball lands 18 b.
  • the conductive circuit pattern 18 is arranged around the through hole 12 .
  • the resin substrate 17 is also provided at the second major surface 11 b thereof with another conductive circuit pattern 18 having a plurality of bond fingers 18 a.
  • the conductive circuit patterns 18 on the first and second major surfaces of the circuit board 10 are electrically connected to each other by conductive via holes 20 .
  • Each of the bond fingers 18 a is plated with gold (Au) or silver (Ag) in order to allow an easy bonding of a conductive connecting means 40 (e.g., a bond wire) thereto.
  • a conductive connecting means 40 e.g., a bond wire
  • Each of the ball lands 18 b is plated with gold (Au), silver (Ag), nickel (Ni), or palladium (Pd) in order to allow an easy bonding of a conductive ball 60 thereto.
  • the resin substrate 17 is made of a bismaleimide triazine (BT) epoxy resin exhibiting a hardness.
  • BT bismaleimide triazine
  • the resin substrate 17 is not limited to the above mentioned material.
  • the conductive circuit patterns 18 are coated with cover coats 19 in such a fashion that the bond fingers 18 a and ball lands 18 b are externally open through the cover coats 19 , respectively, so that they are protected from physical, chemical, electrical, and mechanical damage externally applied thereto.
  • the input/output pads 31 of the semiconductor chip 30 are electrically interconnected with the bond fingers 18 a on the circuit board 10 via the conductive connecting means 40 , respectively.
  • the conductive connecting means 40 may comprise conductive wires, such as gold (Au) wires or aluminum (Al) wires, or leads extending from respective bond fingers 18 a.
  • the semiconductor chip 30 and conductive connecting means 40 are encapsulated by a resin encapsulate 50 so that they are protected from external physical, chemical, and mechanical damage.
  • the resin encapsulate 50 may be formed in such a fashion that it completely encapsulates the entire upper surface of the circuit board 10 , as shown in FIG. 1 . Where the resin encapsulate 50 completely encapsulates the entire upper surface of the circuit board 10 , there is an advantage in that it is possible to prevent the circuit board 10 from being bent.
  • the resin encapsulate 50 may be formed in such a fashion that it partially encapsulates the upper surface of the circuit board 10 at a region where the semiconductor chip 30 , connecting means 40 , and bond fingers 18 a are arranged, as shown in FIG. 2 .
  • the resin encapsulate 50 may be formed using an epoxy molding compound so that it is molded using a mold. The use of such a molding compound may be implemented in the case of FIGS. 1 and 2 .
  • a liquid encapsulating resin may be used to form the resin encapsulate 50 . In this case, the encapsulation process may be carried out using a dispenser. The use of such a liquid encapsulating resin may be implemented in the case of FIG. 3 . Where the liquid encapsulating resin is used, a dam 25 may be formed on the upper surface of the circuit board 10 , as shown in FIG. 3 , in order to prevent the liquid encapsulating resin from flowing beyond a desired encapsulating region. In the case of FIG.
  • the liquid encapsulating resin may also be used.
  • the present invention is not limited by the material of the resin encapsulate.
  • Semiconductor packages of FIGS. 2 and 3 are denoted by the reference numerals 102 and 103 , respectively.
  • the semiconductor package is formed in such a fashion that the second major surface 30 b of the semiconductor chip 30 and the circuit board surface formed with the bond fingers 18 a, that is, the second major surface 11 b of the circuit board 10 , are oriented in the same direction. Also, the first major surface 30 a of the semiconductor chip 30 , the circuit board surface formed with the ball lands 18 b, that is, the first major surface 11 a of the circuit board 10 , and the lower surface of the resin encapsulate 50 are flush with one another. Accordingly, the semiconductor package has a thin structure. In addition, the first major surface 20 a of the semiconductor chip 30 is exposed without being covered with the resin encapsulate 50 , so that is can easily discharge heat generated therefrom.
  • an insulating tape or a copper layer may be attached, as a closure means, to the first major surface 30 a of the semiconductor chip 30 in such a fashion that it covers the through hole 12 of the circuit board 10 .
  • the insulating tape is used as the closure means, it is adapted to protect the first major surface 30 a of the semiconductor chip 30 from external damage.
  • the copper layer is used as the closure means, it is adapted to improve the heat discharge performance of the semiconductor chip 30 .
  • a plurality of conductive balls 60 made of tin (Sn), lead (Pb), or an alloy thereof are fused on the ball lands 18 b provided at the first major surface 11 a of the resin substrate 17 , respectively, in order to allow the semiconductor package to be subsequently mounted on a mother board (not shown).
  • the circuit pattern 18 formed on the second major surface 11 b of the resin substrate 17 may also be provided with a plurality of ball lands 18 b, as in a semiconductor package 104 illustrated in FIG. 4 .
  • the ball lands 18 b formed on the second major surface 11 b of the resin substrate 17 are not covered with the cover coat 19 covering the associated circuit pattern 18 in such a fashion that they are open.
  • a plurality of semiconductor packages having the above mentioned structure can be laminated together. That is, the lamination of a number of semiconductor packages can be achieved under the condition in which a plurality of conductive balls 60 are additionally fused on the ball lands 18 b formed at the second major surface 11 b of the resin substrate 17 in the semiconductor package 105 of FIG. 5 .
  • FIGS. 6A and 6B are a top view and a bottom view respectively illustrating a circuit board strip used in the fabrication of the semiconductor package according to the present invention. Now, the structure of the circuit board strip will be described in brief, with reference to FIGS. 6A and 6B .
  • elements respectively corresponding to those in FIGS. 1 to 5 are denoted by the same reference numerals.
  • the circuit board strip which is denoted by the reference numeral 10 - 1 , includes a main strip 16 comprising a resin substrate 17 , circuit patterns 18 , and cover coats 19 .
  • the resin substrate 17 has a substantially rectangular plate structure having a first major surface 11 a ( FIG. 6B ) and a second major surface 11 b (FIG. 6 A).
  • the main strip 16 is divided into a plurality of sub-strips 14 aligned together in the longitudinal direction of the main strip 16 by a plurality of main slots 15 .
  • Main slots 15 extend through resin substrate 17 at a side of each sub-strip 14 .
  • Sub-strips 14 extend to a desired length in a direction transverse to the longitudinal direction of the main strip 16 while being uniformly spaced apart from one another in the longitudinal direction of the main strip 16 .
  • a plurality of through holes 12 which are adapted to receive semiconductor chips (not shown) therein, respectively, are formed at each sub strip 14 in such a fashion that they are arranged in the form of a matrix array.
  • Each sub strip 14 is divided by sub slots 13 having a desired length into a rectangular matrix of strip portions, each of which corresponds to a unit circuit board 10 of FIGS. 1-5 .
  • Each unit circuit board 10 in each sub strip 14 includes an associated one of the through holes 12 provided at the sub strip 14 .
  • the sub slots 13 and main slots 15 are formed through the resin substrate 17 .
  • the circuit patterns 18 are formed on the first and second major surfaces 11 a and 11 b of the resin substrate 17 between the through hole 12 and the sub slots 13 .
  • the circuit patterns 18 are typically comprised of a copper thin film.
  • the cover coats 19 are coated over the exposed surfaces of the circuit patterns 18 and resin substrate 17 in order to protect the circuit patterns 18 from the external environment.
  • the cover coats 19 are typically made of a polymeric resin.
  • One circuit pattern 18 of each unit circuit board is provided with a plurality of bond fingers 18 a to be subsequently connected with a semiconductor chip whereas the other circuit pattern 18 of the unit circuit board is provided with a plurality of ball lands 18 b on which conductive balls are to be subsequently fused, respectively.
  • the bond fingers 18 a and ball lands 18 b are externally open through the associated cover coats 19 , respectively.
  • the circuit pattern 18 formed on the second major surface 11 b of the resin substrate 17 may have both the bond fingers 18 a and the ball lands 18 b.
  • the ball lands 18 b may be provided only at the first major surface 11 a of the resin substrate 17 , as shown in FIG. 6 B.
  • Each bond finger 18 a is electrically connected with a ball land 18 b by conductive via (not shown) through resin substrate 17 .
  • the ball lands 18 b have been illustrated as being arranged along two lines, as shown in FIGS. 6A and 6B , they may be arrange along three through five lines. It will be appreciated by those persons skilled in the art that such an arrangement is optional. In other words, the present invention is not limited by the number of lines on which the ball lands 18 b are arranged.
  • FIGS. 7A to 7 F illustrate a semiconductor package fabricating method according to the present invention. Now, the fabrication method will be described with reference to FIGS. 7A to 7 F.
  • a circuit board strip which may have the structure of FIG. 6A or 6 B, is used in order to achieve a simultaneous fabrication of a number of semiconductor packages.
  • the following description will be made in conjunction with the case in which the circuit board strip of FIG. 6A or 6 B is used.
  • the illustration of the sub slots 13 that are along the four edges of each rectangular unit circuit board 10 of strip 10 - 1 are omitted.
  • a circuit board strip which is the circuit board strip 10 of FIG. 6A or 6 B, is first prepared, as shown in FIG. 7 A.
  • a semiconductor chip 30 is inserted into each of the through holes 12 of the circuit board strip 10 , respectively, in such a fashion that the input/output pads 31 of each semiconductor chip 30 are oriented in the same direction as the bond fingers 18 a formed on the circuit board strip 10 .
  • closure members 70 Prior to the insertion of the semiconductor chips 30 , closure members 70 are attached to the lower surface of the circuit board strip 10 in such a fashion that each of them covers an associated one of the through holes 12 , as shown in FIG. 7 B. In this case, each semiconductor chip 30 , which is subsequently received in an associated one of the through holes 12 , is seated on an associated one of the closure members 70 at the first major surface 30 a thereof.
  • closure members 70 insulating tapes may be used. Ultraviolet tapes may be used which can be easily peeled using ultraviolet rays. Alternatively, heat sensitive tapes may be used.
  • copper layers exhibiting a superior heat discharge property also may be attached to the circuit board strip 10 . In such a case, the closure members 70 are not removed after the completion of the package fabrication.
  • closure members 70 may be attached to the circuit board strip 10 - 1 in such a fashion that they cover the entire lower surface of the circuit board strip 10 - 1 . This will be described in more detail, in conjunction with FIGS. 8A and 8B .
  • connection means 40 In order to electrically connect the input/output pads 31 of each semiconductor chip 30 with the associated bond fingers 18 a of the circuit board strip 10 , conductive wires, such as gold wires or aluminum wires, or leads extending from respective bond fingers 18 a are then electrically connected, as connection means 40 , between the input/output pads 31 and the associated bond fingers 18 a, respectively, as shown in FIG. 7 C.
  • a resin encapsulate 50 is formed using an encapsulating resin, such as an epoxy molding compound or a liquid encapsulating resin, in such a fashion that it encapsulates the entire upper surface of each semiconductor chip 30 , the enter upper surface of the circuit board strip 10 , and the connection means 40 , as shown in FIG. 7 D.
  • the resin encapsulate 50 may be formed in such a fashion that it partially encapsulates desired upper surface portions of the circuit board strip 10 while completely encapsulating the upper surface of each semiconductor chip 30 and the connection means 40 .
  • the encapsulating extent of the resin encapsulate 50 is optional.
  • a plurality of conductive balls 60 are fused on the ball lands 18 b provided at the lower surface of the circuit board strip 10 in order to allow each unit circuit board of the circuit board strip 10 to be mounted to a mother board in a subsequent process, as shown in FIG. 7 E.
  • circuit board strip 10 is provided with ball lands 18 b not only at the lower surface thereof, but also at the upper surface thereof formed with the bond fingers 18 a, conductive balls 60 are also fused on the ball lands 18 b of that upper surface.
  • a plurality of semiconductor packages can be laminated together in a subsequent process.
  • the fusing of the conductive balls 60 may be achieved using a variety of appropriate methods.
  • a screen printing method may be used.
  • a sticky flux exhibiting a high viscosity is first applied, in the shape of dots, to the ball lands 18 b.
  • Conductive balls 60 are then temporarily bonded to the flux dots, respectively.
  • the resultant circuit board strip 10 is subsequently put into a furnace so that the conductive balls 60 are fused on the associated ball lands 18 b, respectively.
  • circuit board strip 10 is then singulated into individual semiconductor packages, each corresponding to one unit circuit board, using a desired singulation tool 80 , as shown in FIG. 7 F.
  • the singulation tool 80 (e.g., a saw) passes through regions defined between adjacent sub slots (not shown).
  • Removal of the closure members 70 may be conducted, to externally expose respective first major surfaces 30 a of the semiconductor chips 30 , before or after a formation of input/output terminals achieved by the fusing of the conductive balls on the ball lands 18 b, or after the singulation process. It is also possible to deliver the semiconductor packages in a state in which the closure members 70 are not removed, for example, where the closure member is made of a copper layer.
  • the singulation processes for the resin encapsulate 50 and the circuit board strip 10 are simultaneously conducted. In this case, semiconductor packages having a structure shown in FIG. 1 are produced.
  • FIGS. 8A and 8B are bottom views each illustrating another attaching method for the closure members usable in the semiconductor package fabricating method according to the present invention.
  • each closure member strip is used, each of which provides in interconnected form the closure member 70 for each unit circuit board 10 of one sub strip 14 of the circuit board strip 10 - 1 . That is, the closure member strips are individually attached to the sub-strips 14 of the circuit board strip 10 - 1 . In this case, it is preferred that each closure member strip be arranged in such a fashion that it covers the main slot 15 formed at one side of the sub strip covered therewith.
  • each closure member strip has the above mentioned arrangement is to achieve an easy removal of the closure members 70 . That is, the closure members 70 of each closure member strip can be easily detached from the associated sub strip 14 of the circuit board strip 10 - 1 by inserting a planar bar (not shown) into the main slot 15 formed at one side of the sub strip 14 , thereby pushing the closure member strip in such a fashion that it is detached from the sub strip 14 . At this time, the planar bar moves in a direction from the second major surface 11 b of the circuit board strip 10 - 1 to the first major surface 11 a.
  • a single closure member strip is used which provides in interconnected form a closure member 70 for each unit circuit board 10 of all sub-strips 14 of the circuit board strip 10 - 1 having small singulation apertures or slits 71 at a region corresponding to each main slot 15 of the circuit board strip 10 - 1 .
  • the closure members 70 for all sub-strips 14 are simultaneously attached to those sub-strips 14 .
  • the reason why the closure member strip has the above mentioned arrangement in the case of FIG. 8B is to achieve an easy removal of the closure members 70 . That is, the closure members 70 of the closure member strip can be easily detached from the circuit board strip 10 by inserting a planar bar (not shown) into each main slot 15 of the circuit board strip 10 , thereby pushing the closure member strip, in particular, the portion thereof formed with the singulation apertures 71 , in such a fashion that it is detached from the circuit board strip 10 .
  • the closure member strip utilizes an easy singulation configuration, applied to the technical field of postage-stamps, using small singulation apertures.
  • FIG. 9 illustrates an encapsulating method usable in the semiconductor package fabricating method according to the present invention.
  • a mold which includes an upper mold 91 having cavities 93 and gates 94 , and a lower mold 92 .
  • the circuit board strip 10 is interposed between the upper and lower molds 91 and 92 in such a fashion that the second major surface 30 a of each semiconductor chip 30 faces an associated one of the cavities 93 while facing an associated one of the gates 94 at the central portion thereof.
  • each semiconductor chip 30 is encapsulated.
  • this encapsulating method it is possible to minimize a wire sweeping phenomenon occurring during the encapsulating process, as compared to conventional encapsulating methods in which the encapsulation proceeds from one side of the circuit board.
  • the reason why a minimized wire sweeping phenomenon occurs in accordance with the present invention is because a maximum pressure of the encapsulating resin is applied to the central portion of the second major surface of each semiconductor chip while being gradually reduced toward the peripheral portion of the second major surface where wires are arranged.
  • a circuit board which has a through hole of a desired size adapted to receive a semiconductor chip, thereby allowing the thickness of the semiconductor chip to be offset by the thickness of the circuit board. Accordingly, it is possible to fabricate semiconductor packages having a super-thin structure.
  • the semiconductor chip is outwardly exposed at one major surface thereof without being encapsulated by an encapsulate. Accordingly, heat generated from the semiconductor chip can be easily discharged into the atmosphere. This results in an improvement in the thermal and electrical performances of the semiconductor chip.
  • the circuit board may be completely encapsulated at one major surface thereof by an encapsulate. In this case, it is possible to effectively prevent a bending phenomenon of the circuit board.
  • closure members during the fabrication of semiconductor packages according to the present invention achieves an easy encapsulating process.
  • closure member strips may be used, each of which has closure members for one sub strip of a circuit board strip. In this case, the closure member strips are individually attached to the sub-strips of the circuit board strip.
  • a single closure member strip may be used which has closure members for all sub-strips of the circuit board strip while having small singulation apertures or slits.
  • the encapsulating process involved in the fabrication of semiconductor packages is conducted in such a fashion that it proceeds from the second major surface of each semiconductor chip in accordance with the present invention. Accordingly, it is possible to achieve a uniform encapsulation while suppressing the occurrence of a wire sweeping phenomenon.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed. An embodiment of a semiconductor package includes a semiconductor chip having a first major surface and a second major surface, the semiconductor chip being provided at the second major surface with a plurality of input/output pads; a circuit board including a resin substrate having a first major surface and a second major surface, a first circuit pattern formed at the first major surface and provided with a plurality of ball lands, a second circuit pattern formed at the second major surface and provided with a plurality of bond fingers connected with he ball lands by conductive via holes through the resin substrate, cover coats respectively coating the first and second circuit patterns while allowing the bond fingers and the ball lands to be exposed therethrough, and a central through hole adapted to receive the semiconductor chip therein; electrical conductors that electrically connect the input/output pads of the semiconductor chip with the bond fingers of the circuit board, respectively; a resin encapsulate that covers the semiconductor chip, the electrical conductors, and at least part of the circuit board; and, a plurality of conductive balls fused on the ball lands of the circuit board, respectively.

Description

BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to a semiconductor package and a method for fabricating the semiconductor package. This application is a REI of 09/574,541 filed on May 19, 2000 U.S. Pat. No. 6,395,578.
II. Description of the Prior Art
Recently, semiconductor devices have been developed to have a thinner and more miniature structure. For such semiconductor devices, there are ball grid array (BGA) semiconductor packages, chip scale semiconductor packages, and micro BGA semiconductor packages.
Also, semiconductor chips, which are mounted on semiconductor packages as mentioned above, have been developed toward a high performance of electric power circuits, an increase in operating frequency, and an expansion of circuit functions, in pace with the development of integration techniques and manufacturing equipment. For this reason, an increase in heat occurs inevitably during the operation of such a semiconductor chip.
Referring to FIG. 10, a typical BGA semiconductor package having a conventional structure involving the above mentioned problem is illustrated.
As shown in FIG. 10, the BGA semiconductor package, which is denoted by the reference numeral 100′, includes a semiconductor chip 1′ arranged at a central portion of the semiconductor package 100′. The semiconductor chip 1′ is provided with a plurality of integrated electronic circuits. A plurality of input/output pads 2′ are provided at an upper surface of the semiconductor chip 1′. A circuit board 10′ is bonded at a central portion thereof to a lower surface of the semiconductor chip 1′ by means of an adhesive 3′.
The circuit board 10′ includes a resin substrate 15′. A circuit pattern 12′ provided with bond fingers 11′ is formed on an upper surface of the resin substrate 15′ around the semiconductor chip 1′. Another circuit pattern provided with a plurality of ball lands 13′ is formed on a lower surface of the resin substrate 15′. Each of the circuit patterns is comprised of a thin film made of a conductive material such as copper (Cu). These circuit patterns are interconnected together by via holes 14′. The exposed surface portions of the circuit patterns not covered with the bond fingers 11′ and ball lands 13′ are coated with cover coats 16′, respectively, so that those circuit patterns are protected from the external environment.
The input/output pads 2′ of the semiconductor chip 1′ are connected to the bond fingers 11′ on the upper surface of the circuit board 10′ by means of conductive wires 4′, respectively. In order to protect the conductive wires 4′ from the external environment, the upper surface of the circuit board 10′ is encapsulated by a resin encapsulate 20′.
The circuit board 10′ is mounted on a mother board (not shown) in a state in which a plurality of conductive balls 40′ are fused on the ball lands 13′, respectively, so that it serves as a medium for electrical signals between the semiconductor chip 1′ and mother board.
In the BGA semiconductor package 100′ having the above mentioned configuration, the semiconductor chip 1′ thereof exchanges electrical signals with the mother board via the input/output pads 2′, conductive wires 4′, bond fingers 11′, via holes 14′, ball lands 13′, and conductive balls 40′, respectively.
However, the above mentioned conventional BGA semiconductor package is problematic in that it has an increased thickness because the semiconductor chip is bonded to the upper surface of the circuit board having a relatively large thickness. This is contrary to the recent trend toward a miniaturization and thinness. As a result, the above mentioned semiconductor package is problematic in that it cannot be applied to a variety of miniature electronic appliances such as portable phones, cellular phones, pagers, and notebooks.
Furthermore, in spite of the increasing heat generated at the semiconductor chip, as mentioned above, there is no appropriate heat discharge means in the conventional semiconductor package. As a result, the conventional semiconductor package is implicated in a heat-related degradation in the electrical performance and other functions of the semiconductor chip. In severe cases, the semiconductor package and the electronic appliance using it may be so damaged as not to be inoperable.
Although a semiconductor package has been proposed, which is provided with a heat discharge plate or heat sink for easily discharging heat generated from the semiconductor chip, the provision of such a heat discharge plate causes another problem because it serves to further increase the thickness of the semiconductor package while increasing the manufacturing costs.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above mentioned problems involved in the prior art, and an object of the invention is to provide a semiconductor package having a super-thin structure and a method for fabricating the semiconductor package.
Another object of the invention is to provide a semiconductor package having a structure capable of easily discharging heat from a semiconductor chip included therein, and a method for fabricating the semiconductor package.
In accordance with one aspect, the present invention provides a semiconductor package comprising: a semiconductor chip having a first major surface and a second major surface, the semiconductor chip being provided at the second major surface with a plurality of input/output pads; a circuit board including a resin substrate having a first major surface and a second major surface, a first circuit pattern formed at the first major surface and provided with a plurality of ball lands, a second circuit pattern formed at the second major surface and provided with a plurality of bond fingers connected with the ball lands by conductive via holes, cover coats respectively coating the first and second circuit patterns while allowing the bond fingers and the ball lands to be open, and a central through hole adapted to receive the semiconductor chip therein; electrical connection means for electrically connecting the input/output pads of the semiconductor chip with the bond fingers of the circuit board, respectively; a resin encapsulate for encapsulating the semiconductor chip, the electrical connection means, and the circuit board; and a plurality of conductive balls fused on the ball lands of the circuit board, respectively.
The semiconductor chip may be arranged in such a fashion that it is oriented, at the second major surface thereof, in the same direction as the second major surface of the circuit board provided with the bond fingers while being flush, at the first major surface thereof, with the first major surface of the circuit board provided with the ball lands and one surface of the resin encapsulate.
The resin encapsulate may be formed to completely or partially encapsulate the second major surface of the circuit board provided with the bond fingers.
The second major surface of the circuit board provided with the bond fingers may be further provided with a plurality of ball lands.
A plurality of conductive balls may be fused on the ball lands provided at the second major surface of the circuit board, respectively.
The semiconductor package may further comprises a closure member attached to the first major surface of the semiconductor chip and adapted to cover the through hole of the circuit board.
Preferably, each of the closure members comprises an insulating tape or a copper layer.
In accordance with another aspect, the present invention provided a method for fabricating semiconductor packages comprising the steps of: preparing a circuit board strip including a plurality of unit circuit boards, the circuit board strip having a plurality of ball lands formed at a first major surface thereof, a plurality of bond fingers formed at a second major surface thereof and respectively connected with the ball lands by conductive via holes, and a plurality of through holes respectively associated with the unit circuit boards; receiving, in the through holes, semiconductor chips each having a first major surface and a second major surface provided with a plurality of input/output pads, respectively; electrically connecting the input/output pads of the semiconductor chips with associated ones of the bond fingers of the circuit board strip using connection means, respectively; encapsulating the semiconductor chips, the connection means, and the through holes of the circuit board strip using an encapsulating material; fusing conductive balls on the ball lands of the circuit board strip; and singulating the circuit board strip into semiconductor packages respectively corresponding to the unit circuit boards.
The circuit board strip prepared at the circuit board strip preparing step may comprise: a main strip including a resin substrate having a substantially rectangular strip shape provided with a first major surface and a second major surface; a plurality of main slots extending to a desired length in an direction transverse to a longitudinal direction of the main strip while being uniformly spaced apart from one another in the longitudinal direction of the main strip, thereby dividing the main strip into a plurality of sub-strips aligned together in the longitudinal direction of the main strip; a plurality of sub slots extending to a desired length and serving to divide each of the sub-strips into a plurality of strip portions arranged in a matrix array, each of the strip portions corresponding to one of the unit circuit boards while having one of the through holes; a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the ball lands; a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the bond fingers; and cover coats respectively coated over the first and second major surfaces of the resin substrate while allowing the bond fingers and the ball lands to be externally open.
Alternatively, the circuit board strip prepared at the circuit board strip preparing step may comprise: a resin substrate having a substantially rectangular strip shape provided with a first major surface and a second major surface; a plurality of slots extending to a desired length and serving to divide each of the resin substrate into a plurality of substrate portions arranged in a matrix array, each of the substrate portions corresponding to one of the unit circuit boards while having one of the through holes; a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the ball lands; a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the bond fingers; and cover coats respectively coated over the first and second major surfaces of the resin substrate while allowing the bond fingers and the ball lands to be externally open.
The method may further comprise the step of attaching a plurality of closure members to the first major surface of the circuit board strip in such a fashion that each of the closure members covers an associated one of the through holes, prior to the strip of receiving the semiconductor chips in the through holes.
The method may further comprise the step of attaching a plurality of closure members to the first major surface of the main strip in such a fashion that each of the closure members covers an associated one of the through holes, prior to the step of receiving the semiconductor chips in the through holes.
The closure member attaching step may comprise the steps of preparing closure member strips each having closure members for an associated one of the sub-strips, and individually attaching the closure member strips to the sub-strips, respectively, in such a fashion that each of the closure member strips is arranged to cover the main slot formed at one side of an associated one of the sub-strips.
Alternatively, the closure member attaching step may comprise the steps of preparing a single closure member strip having closure members for all sub-strips of the circuit board strip while having small singulation apertures at a region corresponding to each of the main slots, and attaching the closure member strip to the main strip in such a fashion that the closure member strip is arranged to allow each of the small singulation apertures to be aligned with an associated one of the main slots.
The closure members are removed after the encapsulating step, e.g., before or after the conductive ball fusing step, or after the singulation step.
The closure members may be removed by inserting a planar bar into each of the main slots in a direction from the second major surface of the circuit board strip to the first major surface of the second board strip, thereby detaching an associated one of the closure members from the circuit board strip at one side of the associated closure member.
Each of the closure members may comprise an insulating tape, an ultraviolet tape, or a copper layer.
The encapsulating step may be carried out to form an encapsulate completely encapsulating the second major surface of the circuit board strip.
The singulation step may be carried out in such a fashion that the encapsulate and the circuit board strip are simultaneously singulated.
The encapsulating step may comprise the steps of interposing the circuit board strip between a pair of molds, one of which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated one of the cavities while facing an associated one of the gates at a central portion thereof, and injecting the encapsulating material into each of the cavities through an associated one of the gates in such a fashion that it flows outwardly from the central portion of the second major surface of the associated semiconductor chip along the second major surface.
The circuit board strip prepared at the circuit board strip preparing step may be further provided with a plurality of ball lands at the second major surface thereof having the bond fingers. In this case, the conductive ball fusing step further comprises the step of fusing a plurality of conductive balls on the ball lands provided at the second major surface of the circuit board strip having the bond fingers.
In accordance with the present invention, a circuit board is used which has a through hole of a desired size adapted to receive a semiconductor chip, thereby allowing the thickness of the semiconductor chip to be offset by the thickness of the circuit board. Accordingly, it is possible to fabricate semiconductor packages having a super-thin structure.
In accordance with the present invention, the semiconductor chip is outwardly exposed at one major surface thereof without being encapsulated by an encapsulate. Accordingly, heat generated from the semiconductor chip can be easily discharged into the atmosphere. This results in an improvement in the thermal and electrical performance of the semiconductor chip.
In accordance with the present invention, the circuit board may be completely encapsulated at one major surface thereof by an encapsulate. In this case, it is possible to effectively prevent a bending phenomenon of the circuit board.
In addition, the use of closure members during the fabrication of semiconductor packages according to the present invention achieves an easy encapsulating process.
For such closure members, closer member strips may be used, each of which has closure members for one sub strip of a circuit board strip. In this case, the closure member strips are individually attached to the sub-strips of the circuit board strip. Alternatively, a single closure member strip may be used which has closure members for all sub-strips of the circuit board strip while having small singulation apertures or slits. By virtue of such a single closure member strip or closure member strips, an easy removal of closure members is achieved.
Also, the encapsulating process involved in the fabrication of semiconductor packages is conducted in such a fashion that it proceeds from the second major surface of each semiconductor chip in accordance with the present invention. Accordingly, it is possible to achieve a uniform encapsulation while suppressing the occurrence of a wire sweeping phenomenon.
BRIEF DESCRIPTION OF THE DRAWINGS
The above objects, and other features and advantages of the present invention will become more apparent after a reading of the following detailed description when taken in conjunction with the drawings, in which:
FIGS. 1 to 5 are cross-sectional views respectively illustrating semiconductor packages according to various exemplary embodiments of the present invention;
FIGS. 6A and 6B are a top view and a bottom view respectively illustrating an exemplary circuit board strip useful in the fabrication of the semiconductor packages described herein;
FIGS. 7A to 7F are cross-sectional views respectively illustrating stages in a semiconductor package fabricating method according to the present invention;
FIGS. 8A and 8B are bottom views each illustrating an alternative method for attaching closure members in the exemplary fabrication method;
FIG. 9 is a cross-sectional view illustrating an encapsulating method usable in the exemplary fabrication method described; and
FIG. 10 is a cross-sectional view illustrating a typical BGA semiconductor package having a conventional structure.
 DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
Referring to FIGS. 1 to 5, semiconductor packages according to various embodiments of the present invention are illustrated, respectively.
In accordance with the embodiment of the present invention illustrated in FIG. 1, the semiconductor package, which is denoted by the reference numeral 101, includes a semiconductor chip 30 having a first major surface 30a (a lower surface in FIG. 1) and a second major surface 30b (an upper surface in FIG. 1). A plurality of input/output pads 31 are formed at the second major surface 30b of the semiconductor chip 30.
The semiconductor chip 30 is arranged in such a fashion that it is received in a through hole 12 formed 10 through a circuit board 10 to have a desired size. The through hole 12 has a size larger than the area of the first or second surface 30a or 30b of the semiconductor chip 30. The circuit board 10 includes a resin substrate 17 having a first major surface 11a (a lower surface in FIG. 1) and a second major surface 11b (an upper surface of FIG. 1). The through hole 12 is centrally formed through the resin substrate 17. The resin substrate 17 is provided at the first major surface 11a thereof with a conductive circuit pattern 18 having a plurality of ball lands 18b. The conductive circuit pattern 18 is arranged around the through hole 12. The resin substrate 17 is also provided at the second major surface 11b thereof with another conductive circuit pattern 18 having a plurality of bond fingers 18a. The conductive circuit patterns 18 on the first and second major surfaces of the circuit board 10 are electrically connected to each other by conductive via holes 20.
Each of the bond fingers 18a is plated with gold (Au) or silver (Ag) in order to allow an easy bonding of a conductive connecting means 40 (e.g., a bond wire) thereto. 30 Each of the ball lands 18b is plated with gold (Au), silver (Ag), nickel (Ni), or palladium (Pd) in order to allow an easy bonding of a conductive ball 60 thereto. Preferably, the resin substrate 17 is made of a bismaleimide triazine (BT) epoxy resin exhibiting a hardness. Of course, the resin substrate 17 is not limited to the above mentioned material.
The conductive circuit patterns 18 are coated with cover coats 19 in such a fashion that the bond fingers 18a and ball lands 18b are externally open through the cover coats 19, respectively, so that they are protected from physical, chemical, electrical, and mechanical damage externally applied thereto.
The input/output pads 31 of the semiconductor chip 30 are electrically interconnected with the bond fingers 18a on the circuit board 10 via the conductive connecting means 40, respectively. The conductive connecting means 40 may comprise conductive wires, such as gold (Au) wires or aluminum (Al) wires, or leads extending from respective bond fingers 18a.
Meanwhile, the semiconductor chip 30 and conductive connecting means 40 are encapsulated by a resin encapsulate 50 so that they are protected from external physical, chemical, and mechanical damage. The resin encapsulate 50 may be formed in such a fashion that it completely encapsulates the entire upper surface of the circuit board 10, as shown in FIG. 1. Where the resin encapsulate 50 completely encapsulates the entire upper surface of the circuit board 10, there is an advantage in that it is possible to prevent the circuit board 10 from being bent. Alternatively, the resin encapsulate 50 may be formed in such a fashion that it partially encapsulates the upper surface of the circuit board 10 at a region where the semiconductor chip 30, connecting means 40, and bond fingers 18a are arranged, as shown in FIG. 2. The resin encapsulate 50 may be formed using an epoxy molding compound so that it is molded using a mold. The use of such a molding compound may be implemented in the case of FIGS. 1 and 2. On the other hand, a liquid encapsulating resin may be used to form the resin encapsulate 50. In this case, the encapsulation process may be carried out using a dispenser. The use of such a liquid encapsulating resin may be implemented in the case of FIG. 3. Where the liquid encapsulating resin is used, a dam 25 may be formed on the upper surface of the circuit board 10, as shown in FIG. 3, in order to prevent the liquid encapsulating resin from flowing beyond a desired encapsulating region. In the case of FIG. 1 or 2, the liquid encapsulating resin may also be used. In other words, the present invention is not limited by the material of the resin encapsulate. Semiconductor packages of FIGS. 2 and 3 are denoted by the reference numerals 102 and 103, respectively.
In either case of FIG. 1, 2 or 3, the semiconductor package is formed in such a fashion that the second major surface 30b of the semiconductor chip 30 and the circuit board surface formed with the bond fingers 18a, that is, the second major surface 11b of the circuit board 10, are oriented in the same direction. Also, the first major surface 30a of the semiconductor chip 30, the circuit board surface formed with the ball lands 18b, that is, the first major surface 11a of the circuit board 10, and the lower surface of the resin encapsulate 50 are flush with one another. Accordingly, the semiconductor package has a thin structure. In addition, the first major surface 20a of the semiconductor chip 30 is exposed without being covered with the resin encapsulate 50, so that is can easily discharge heat generated therefrom.
Although not shown, an insulating tape or a copper layer may be attached, as a closure means, to the first major surface 30a of the semiconductor chip 30 in such a fashion that it covers the through hole 12 of the circuit board 10. Where the insulating tape is used as the closure means, it is adapted to protect the first major surface 30a of the semiconductor chip 30 from external damage. On the other hand, where the copper layer is used as the closure means, it is adapted to improve the heat discharge performance of the semiconductor chip 30.
A plurality of conductive balls 60 made of tin (Sn), lead (Pb), or an alloy thereof are fused on the ball lands 18b provided at the first major surface 11a of the resin substrate 17, respectively, in order to allow the semiconductor package to be subsequently mounted on a mother board (not shown).
The circuit pattern 18 formed on the second major surface 11b of the resin substrate 17 may also be provided with a plurality of ball lands 18b, as in a semiconductor package 104 illustrated in FIG. 4. As shown in FIG. 4, the ball lands 18b formed on the second major surface 11b of the resin substrate 17 are not covered with the cover coat 19 covering the associated circuit pattern 18 in such a fashion that they are open. This means that a plurality of semiconductor packages having the above mentioned structure can be laminated together. That is, the lamination of a number of semiconductor packages can be achieved under the condition in which a plurality of conductive balls 60 are additionally fused on the ball lands 18b formed at the second major surface 11b of the resin substrate 17 in the semiconductor package 105 of FIG. 5.
FIGS. 6A and 6B are a top view and a bottom view respectively illustrating a circuit board strip used in the fabrication of the semiconductor package according to the present invention. Now, the structure of the circuit board strip will be described in brief, with reference to FIGS. 6A and 6B. In FIGS. 6A and 6B, elements respectively corresponding to those in FIGS. 1 to 5 are denoted by the same reference numerals.
As shown in FIGS. 6A and 6B, the circuit board strip, which is denoted by the reference numeral 10-1, includes a main strip 16 comprising a resin substrate 17, circuit patterns 18, and cover coats 19. The resin substrate 17 has a substantially rectangular plate structure having a first major surface 11a (FIG. 6B) and a second major surface 11b (FIG. 6A). The main strip 16 is divided into a plurality of sub-strips 14 aligned together in the longitudinal direction of the main strip 16 by a plurality of main slots 15. Main slots 15 extend through resin substrate 17 at a side of each sub-strip 14. Sub-strips 14 extend to a desired length in a direction transverse to the longitudinal direction of the main strip 16 while being uniformly spaced apart from one another in the longitudinal direction of the main strip 16. A plurality of through holes 12, which are adapted to receive semiconductor chips (not shown) therein, respectively, are formed at each sub strip 14 in such a fashion that they are arranged in the form of a matrix array. Each sub strip 14 is divided by sub slots 13 having a desired length into a rectangular matrix of strip portions, each of which corresponds to a unit circuit board 10 of FIGS. 1-5. Each unit circuit board 10 in each sub strip 14 includes an associated one of the through holes 12 provided at the sub strip 14.
The sub slots 13 and main slots 15 are formed through the resin substrate 17.
In each unit circuit board 10 of circuit board strip 10-1, the circuit patterns 18 are formed on the first and second major surfaces 11a and 11b of the resin substrate 17 between the through hole 12 and the sub slots 13. The circuit patterns 18 are typically comprised of a copper thin film.
In each unit circuit board 10, the cover coats 19 are coated over the exposed surfaces of the circuit patterns 18 and resin substrate 17 in order to protect the circuit patterns 18 from the external environment. The cover coats 19 are typically made of a polymeric resin.
One circuit pattern 18 of each unit circuit board is provided with a plurality of bond fingers 18a to be subsequently connected with a semiconductor chip whereas the other circuit pattern 18 of the unit circuit board is provided with a plurality of ball lands 18b on which conductive balls are to be subsequently fused, respectively. The bond fingers 18a and ball lands 18b are externally open through the associated cover coats 19, respectively.
As shown in FIG. 6A, the circuit pattern 18 formed on the second major surface 11b of the resin substrate 17 may have both the bond fingers 18a and the ball lands 18b. Alternatively, the ball lands 18b may be provided only at the first major surface 11a of the resin substrate 17, as shown in FIG. 6B. Each bond finger 18a is electrically connected with a ball land 18b by conductive via (not shown) through resin substrate 17. Although the ball lands 18b have been illustrated as being arranged along two lines, as shown in FIGS. 6A and 6B, they may be arrange along three through five lines. It will be appreciated by those persons skilled in the art that such an arrangement is optional. In other words, the present invention is not limited by the number of lines on which the ball lands 18b are arranged.
FIGS. 7A to 7F illustrate a semiconductor package fabricating method according to the present invention. Now, the fabrication method will be described with reference to FIGS. 7A to 7F.
In accordance with the semiconductor package fabricating method of the present invention, a circuit board strip, which may have the structure of FIG. 6A or 6B, is used in order to achieve a simultaneous fabrication of a number of semiconductor packages. The following description will be made in conjunction with the case in which the circuit board strip of FIG. 6A or 6B is used. For the simplicity of description, the illustration of the sub slots 13 that are along the four edges of each rectangular unit circuit board 10 of strip 10-1 are omitted.
In accordance with the fabricating method of the present invention, a circuit board strip, which is the circuit board strip 10 of FIG. 6A or 6B, is first prepared, as shown in FIG. 7A.
Thereafter, a semiconductor chip 30 is inserted into each of the through holes 12 of the circuit board strip 10, respectively, in such a fashion that the input/output pads 31 of each semiconductor chip 30 are oriented in the same direction as the bond fingers 18a formed on the circuit board strip 10.
Prior to the insertion of the semiconductor chips 30, closure members 70 are attached to the lower surface of the circuit board strip 10 in such a fashion that each of them covers an associated one of the through holes 12, as shown in FIG. 7B. In this case, each semiconductor chip 30, which is subsequently received in an associated one of the through holes 12, is seated on an associated one of the closure members 70 at the first major surface 30a thereof.
For the closure members 70, insulating tapes may be used. Ultraviolet tapes may be used which can be easily peeled using ultraviolet rays. Alternatively, heat sensitive tapes may be used. For the closure members 70, copper layers exhibiting a superior heat discharge property also may be attached to the circuit board strip 10. In such a case, the closure members 70 are not removed after the completion of the package fabrication.
Alternatively, the closure members 70 may be attached to the circuit board strip 10-1 in such a fashion that they cover the entire lower surface of the circuit board strip 10-1. This will be described in more detail, in conjunction with FIGS. 8A and 8B.
In order to electrically connect the input/output pads 31 of each semiconductor chip 30 with the associated bond fingers 18a of the circuit board strip 10, conductive wires, such as gold wires or aluminum wires, or leads extending from respective bond fingers 18a are then electrically connected, as connection means 40, between the input/output pads 31 and the associated bond fingers 18a, respectively, as shown in FIG. 7C.
Subsequently, a resin encapsulate 50 is formed using an encapsulating resin, such as an epoxy molding compound or a liquid encapsulating resin, in such a fashion that it encapsulates the entire upper surface of each semiconductor chip 30, the enter upper surface of the circuit board strip 10, and the connection means 40, as shown in FIG. 7D. Alternatively, the resin encapsulate 50 may be formed in such a fashion that it partially encapsulates desired upper surface portions of the circuit board strip 10 while completely encapsulating the upper surface of each semiconductor chip 30 and the connection means 40. The encapsulating extent of the resin encapsulate 50 is optional.
The encapsulating process will be described in more detail, in conjunction with FIG. 9.
Thereafter, a plurality of conductive balls 60 are fused on the ball lands 18b provided at the lower surface of the circuit board strip 10 in order to allow each unit circuit board of the circuit board strip 10 to be mounted to a mother board in a subsequent process, as shown in FIG. 7E.
In the case in which the circuit board strip 10 is provided with ball lands 18b not only at the lower surface thereof, but also at the upper surface thereof formed with the bond fingers 18a, conductive balls 60 are also fused on the ball lands 18b of that upper surface. In this case, a plurality of semiconductor packages can be laminated together in a subsequent process.
The fusing of the conductive balls 60 may be achieved using a variety of appropriate methods. For example, a screen printing method may be used. In accordance with this screen printing method, a sticky flux exhibiting a high viscosity is first applied, in the shape of dots, to the ball lands 18b. Conductive balls 60 are then temporarily bonded to the flux dots, respectively. The resultant circuit board strip 10 is subsequently put into a furnace so that the conductive balls 60 are fused on the associated ball lands 18b, respectively.
Finally, the circuit board strip 10 is then singulated into individual semiconductor packages, each corresponding to one unit circuit board, using a desired singulation tool 80, as shown in FIG. 7F.
In the singulation process, the singulation tool 80 (e.g., a saw) passes through regions defined between adjacent sub slots (not shown).
Removal of the closure members 70 may be conducted, to externally expose respective first major surfaces 30a of the semiconductor chips 30, before or after a formation of input/output terminals achieved by the fusing of the conductive balls on the ball lands 18b, or after the singulation process. It is also possible to deliver the semiconductor packages in a state in which the closure members 70 are not removed, for example, where the closure member is made of a copper layer.
Where the resin encapsulate 50 is formed to completely encapsulate the entire upper surface of the circuit board strip 10, the singulation processes for the resin encapsulate 50 and the circuit board strip 10 are simultaneously conducted. In this case, semiconductor packages having a structure shown in FIG. 1 are produced.
FIGS. 8A and 8B are bottom views each illustrating another attaching method for the closure members usable in the semiconductor package fabricating method according to the present invention.
In accordance with the attaching method of FIG. 8A, a plurality of closure member strips are used, each of which provides in interconnected form the closure member 70 for each unit circuit board 10 of one sub strip 14 of the circuit board strip 10-1. That is, the closure member strips are individually attached to the sub-strips 14 of the circuit board strip 10-1. In this case, it is preferred that each closure member strip be arranged in such a fashion that it covers the main slot 15 formed at one side of the sub strip covered therewith.
The reason why each closure member strip has the above mentioned arrangement is to achieve an easy removal of the closure members 70. That is, the closure members 70 of each closure member strip can be easily detached from the associated sub strip 14 of the circuit board strip 10-1 by inserting a planar bar (not shown) into the main slot 15 formed at one side of the sub strip 14, thereby pushing the closure member strip in such a fashion that it is detached from the sub strip 14. At this time, the planar bar moves in a direction from the second major surface 11b of the circuit board strip 10-1 to the first major surface 11a.
In accordance with the attaching method of FIG. 8B, a single closure member strip is used which provides in interconnected form a closure member 70 for each unit circuit board 10 of all sub-strips 14 of the circuit board strip 10-1 having small singulation apertures or slits 71 at a region corresponding to each main slot 15 of the circuit board strip 10-1. In this case, the closure members 70 for all sub-strips 14 are simultaneously attached to those sub-strips 14.
Similar to the case of FIG. 8A, the reason why the closure member strip has the above mentioned arrangement in the case of FIG. 8B is to achieve an easy removal of the closure members 70. That is, the closure members 70 of the closure member strip can be easily detached from the circuit board strip 10 by inserting a planar bar (not shown) into each main slot 15 of the circuit board strip 10, thereby pushing the closure member strip, in particular, the portion thereof formed with the singulation apertures 71, in such a fashion that it is detached from the circuit board strip 10. In this case, the closure member strip utilizes an easy singulation configuration, applied to the technical field of postage-stamps, using small singulation apertures.
FIG. 9 illustrates an encapsulating method usable in the semiconductor package fabricating method according to the present invention.
In accordance with the encapsulating method shown in FIG. 9, a mold is used which includes an upper mold 91 having cavities 93 and gates 94, and a lower mold 92. First, the circuit board strip 10 is interposed between the upper and lower molds 91 and 92 in such a fashion that the second major surface 30a of each semiconductor chip 30 faces an associated one of the cavities 93 while facing an associated one of the gates 94 at the central portion thereof.
An encapsulating resin is then injected into each cavity 93 of the upper mold 91 through an associated one of the gates 94 in such a fashion that it flows outwardly from the central portion of the second major surface 30a of each semiconductor chip 30 along the second major surface 30a. Thus, each semiconductor chip 30 is encapsulated. In accordance with this encapsulating method, it is possible to minimize a wire sweeping phenomenon occurring during the encapsulating process, as compared to conventional encapsulating methods in which the encapsulation proceeds from one side of the circuit board. The reason why a minimized wire sweeping phenomenon occurs in accordance with the present invention is because a maximum pressure of the encapsulating resin is applied to the central portion of the second major surface of each semiconductor chip while being gradually reduced toward the peripheral portion of the second major surface where wires are arranged.
As apparent from the above description, in accordance with the present invention, a circuit board is used which has a through hole of a desired size adapted to receive a semiconductor chip, thereby allowing the thickness of the semiconductor chip to be offset by the thickness of the circuit board. Accordingly, it is possible to fabricate semiconductor packages having a super-thin structure.
In accordance with the present invention, the semiconductor chip is outwardly exposed at one major surface thereof without being encapsulated by an encapsulate. Accordingly, heat generated from the semiconductor chip can be easily discharged into the atmosphere. This results in an improvement in the thermal and electrical performances of the semiconductor chip.
In accordance with the present invention, the circuit board may be completely encapsulated at one major surface thereof by an encapsulate. In this case, it is possible to effectively prevent a bending phenomenon of the circuit board.
In addition, the use of closure members during the fabrication of semiconductor packages according to the present invention achieves an easy encapsulating process. For such closure members, closure member strips may be used, each of which has closure members for one sub strip of a circuit board strip. In this case, the closure member strips are individually attached to the sub-strips of the circuit board strip. Alternatively, a single closure member strip may be used which has closure members for all sub-strips of the circuit board strip while having small singulation apertures or slits. By virtue of such a single closure member strip or closure member strips, an easy removal of closure members is achieved.
Also, the encapsulating process involved in the fabrication of semiconductor packages is conducted in such a fashion that it proceeds from the second major surface of each semiconductor chip in accordance with the present invention. Accordingly, it is possible to achieve a uniform encapsulation while suppressing the occurrence of a wire sweeping phenomenon.
Other embodiments of semiconductor packages and methods of making them are disclosed in U.S. patent application Ser. No. 09/566,069, which was filed with the U.S. Patent and Trademark Office on May 5, 2000, and in U.S. patent application Ser. No. 09/574,006, which was filed on the same day as the present application. Both of these applications are incorporated herein by reference in their entireties.
Although embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims (35)

1. A method for fabricating semiconductor packages, the method comprising:
providing a circuit board strip including a plurality of unit circuit boards, each unit circuit board having a plurality of first ball lands formed at a first major surface thereof, a plurality of bond fingers formed at an opposite second major surface thereof, vias through the circuit board each electrically connected between a bond finger and a first ball land, and a through hole between the first and second major surfaces;
receiving in each through hole a semiconductor chip having a first major surface, and an opposite second major surface provided with a plurality of input/output pads thereon, wherein the second major surface of the chip faces in the same direction as the first second major surface of the respective circuit board;
electrically connecting the input/output pads of each semiconductor chip with associated ones of the bond fingers of the respective circuit board;
encapsulating the semiconductor chips, and filling the through holes of each unit circuit board of the circuit board strip using an encapsulating material;
fusing conductive balls on the first ball lands of each unit circuit board;
singulating the circuit board strip into semiconductor packages respectively corresponding to the unit circuit boards.
2. The method of claim 1, wherein the circuit board strip comprises:
a main strip including a resin substrate having a substantially rectangular strip shape, a first major surface and a second major surface;
a plurality of main slots extending to a desired length in a direction transverse to a longitudinal direction of the main strip while being uniformly spaced apart from one another in the longitudinal direction of the main strip, thereby dividing the main strip into a plurality of sub-strips aligned together in the longitudinal direction of the main strip;
a plurality of sub slots extending to a desired length and serving to divide each of the sub-strips into a plurality of strip portions arranged in a matrix array, each of the strip portions corresponding to one of the unit circuit boards having one of the through holes;
a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the first ball lands;
a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the bond fingers; and
cover coats respectively coated over the first and second major surfaces of the resin substrate while allowing the bond fingers and the ball lands to be exposed therethrough.
3. The method of claim 1, wherein the circuit board strip comprises:
a resin substrate having a substantially rectangular strip shape provided with a first major surface and a second major surface;
a plurality of slots extending to a desired length and serving to divide each of the resin substrate into a plurality of substrate portions arranged in a matrix array, each of the substrate portions corresponding to one of the unit circuit boards having one of the through holes;
a plurality of first circuit patterns each formed on the first major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the ball lands;
a plurality of second circuit patterns each formed on the second major surface of the resin substrate for an associated one of the strip portions and provided with associated ones of the bond fingers; and
cover coats respectively coated over the first and second major surfaces of the resin substrate while allowing the bond fingers and the ball lands to be exposed therethrough.
4. The method of claim 1, further comprising attaching one or more closure members to the first surface of the substrate strip so that each through hole is covered thereby prior to receiving the semiconductor chip in the respective through hole.
5. The method of claim 2, further comprising:
attaching a plurality of closure members to the first major surface of the circuit board strip in such a fashion that the closure members simultaneously cover associated ones of the through holes, prior to the step of receiving the semiconductor chips in the through holes.
6. The method according to claim 3, further comprising the step of:
attaching a plurality of closure members to the first major surface of the circuit board strip in such a fashion that the closure members simualtaneously cover associated ones of the through holes, prior to the step of receiving the semiconductor chips in the through holes.
7. The method according to claim 5, wherein attaching the closure member comprises:
preparing closure member strips each having closure members for an associated one of the sub-strips; and
individually attaching the closure member strips to the sub-strips, respectively, in such a fashion that each of the closure member strips is arranged to cover the main slot formed at one side of an associated one of the sub-strips.
8. The method according to claim 5, wherein attaching the closure member comprises:
preparing a single closure member strip having closure members for all sub-strips of the circuit board strip while having small singulation apertures at a region corresponding to each of the main slots; and
attaching the closure member strip to the main strip in such a fashion that the closure member strip is arranged to allow each of the small singulation apertures to be aligned with an associated one of the main slots.
9. The method of claim 4, wherein the one or more closure members are removed after encapsulating the semiconductor chips.
10. The method of claim 5, wherein the closure members are removed after encapsulating the semiconductor chips.
11. The method of claim 6, wherein the closure members are removed after encapsulating the semiconductor chips.
12. The method of claim 7, wherein the closure members are removed after encapsulating the semiconductor chips by inserting a bar into one or more of the main slots in a direction from the second major surface of the circuit board strip to the first major surface of the second board strip, thereby detaching an associated one of the closure members from the circuit board strip at one side of the associated closure member.
13. The method of claim 8, wherein the closure members are removed after encapsulating the semiconductor chips by inserting a bar into one or more of the main slots in a direction from the second major surface of the circuit board strip to the first major surface of the second board strip, thereby detaching an associated one of the closure members from the circuit board strip at one side of the associated closure member.
14. The method of claim 4, wherein each closure member is selected from the group consisting of an insulating tape, an ultraviolet tape, and a copper layer.
15. The method of claim 5, wherein each of the closure members is selected from the group consisting of an insulating tape, an ultraviolet tape, and a copper layer.
16. The method of claim 6, wherein each of the closure members is selected from the group consisting of an insulating tape, an ultraviolet tape, and a copper layer.
17. The method of claim 4, wherein a unitary body of encapsulant material covers the second major surface of all of the unit circuit boards of the circuit board strip.
18. The method according to claim 5, wherein a unitary body of encapsulant material covers the second major surface of all of the unit circuit boards of the circuit broad strip.
19. The method according to claim 6, wherein a unitary body of encapsulant material covers the second major surface all of the unit circuit board of the circuit board strip.
20. The method according to claim 17, wherein singulating the circuit board strip is carried out in such a fashion that the encapsulant material and the circuit board strip are simultaneously split.
21. The method according to claim 18, wherein singulating the circuit board strip is carried out in such a fashion that the encapsulant material and the circuit board strip are simultaneously split.
22. The method according to claim 19, wherein singulating the circuit board strip is carried out in such a fashion that the encapsulant material and the circuit board strip are simultaneously split.
23. The method of claim 1, wherein encapsulating the circuit board strip comprises:
interposing the circuit board strip between a pair of mold dies, one of which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated cavity and a gate into the cavity; and
injecting the encapsulating material into each of the cavities through the associated gate in such a fashion that it flows outwardly from a central portion of the second major surface of the associated semiconductor chip along the second major surface.
24. The method of claim 2, wherein the encapsulating the circuit board strip comprises:
interposing the circuit board strip between a pair of mold dies, one of which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated cavity and a gate into the cavity; and
injecting the encapsulating material into each of the cavities through the associated gate in such a fashion that it flows outwardly from a central portion of the second major surface of the associated semiconductor chip along the second major surface.
25. The method of claim 4, wherein the encapsulating the circuit board strip comprises:
interposing the circuit board strip between a pair of mold dies, one of which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated cavity and a gate into the cavity; and
injecting the encapsulating material into each of the cavities through the associated gate in such a fashion that it flows outwardly from a central portion of the second major surface of the associated semiconductor chip along the second major surface, fills the through hole, and contacts the closure member.
26. The method of claim 9, wherein the encapsulating the circuit board strip comprises:
interposing the circuit board strip between a pair of mold dies, one or which has cavities and gates, in such a fashion that the second major surface of each of the semiconductor chips faces an associated cavity and a gate into the cavity; and
injecting the encapsulating material into each of the cavities through the associated gate in such a fashion that it flows outwardly from a central portion of the second major surfaces of the associated semiconductor chip along the second major surface, fills the through hole, and contacts the closure member.
27. The method of claim 1, wherein each unit circuit board of the circuit board strip is further provided with a plurality of second ball lands at the second major surface thereof.
28. The method of claim 2, wherein each unit circuit board of the circuit board strip is further provided with a plurality of second ball lands at the second major surface thereof.
29. The method of claim 3, wherein each unit circuit board of the circuit board strip is further provided with a plurality of second ball lands at the second major surface thereof.
30. The method of claim 27, further comprising fusing a plurality of conductive balls on the second ball lands.
31. The method of claim 28, further comprising fusing a plurality of conductive balls on the second ball lands.
32. The method of claim 29, further comprising fusing a plurality of conductive balls on the second ball lands.
33. The method of claim 4, wherein each unit circuit board of the circuit board strip is further provided with a plurality of second ball lands at the second major surface thereof.
34. The method of claim 33, wherein the one or more closure members are removed after encapsulating the semiconductor chips.
35. The method of claim 34, further comprising fusing a plurality of conductive balls on the second ball lands.
US10/825,670 1999-05-20 2004-04-14 Semiconductor package and method for fabricating the same Expired - Lifetime USRE40112E1 (en)

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KR1019990037925A KR100365054B1 (en) 1999-09-07 1999-09-07 substrate for semiconductor package and manufacturing method of semiconductor package using it
US09/574,541 US6395578B1 (en) 1999-05-20 2000-05-19 Semiconductor package and method for fabricating the same
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080085572A1 (en) * 2006-10-05 2008-04-10 Advanced Chip Engineering Technology Inc. Semiconductor packaging method by using large panel size

Citations (106)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3838984A (en) 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
US3851221A (en) 1972-11-30 1974-11-26 P Beaulieu Integrated circuit package
US4398235A (en) 1980-09-11 1983-08-09 General Motors Corporation Vertical integrated circuit package integration
US4530152A (en) 1982-04-01 1985-07-23 Compagnie Industrielle Des Telecommunications Cit-Alcatel Method for encapsulating semiconductor components using temporary substrates
US4567643A (en) 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
US4707724A (en) 1984-06-04 1987-11-17 Hitachi, Ltd. Semiconductor device and method of manufacturing thereof
US4729061A (en) 1985-04-29 1988-03-01 Advanced Micro Devices, Inc. Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom
US4730232A (en) 1986-06-25 1988-03-08 Westinghouse Electric Corp. High density microelectronic packaging module for high speed chips
US4756080A (en) 1986-01-27 1988-07-12 American Microsystems, Inc. Metal foil semiconductor interconnection method
US4763188A (en) 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
JPH0199248A (en) * 1987-10-13 1989-04-18 Mitsubishi Electric Corp Semiconductor device
US4982265A (en) 1987-06-24 1991-01-01 Hitachi, Ltd. Semiconductor integrated circuit device and method of manufacturing the same
US4996587A (en) 1989-04-10 1991-02-26 International Business Machines Corporation Integrated semiconductor chip package
US5012323A (en) 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5025306A (en) 1988-08-09 1991-06-18 Texas Instruments Incorporated Assembly of semiconductor chips
US5040052A (en) 1987-12-28 1991-08-13 Texas Instruments Incorporated Compact silicon module for high density integrated circuits
JPH0456262A (en) * 1990-06-25 1992-02-24 Matsushita Electron Corp Semiconductor integrated circuit device
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
US5140404A (en) 1990-10-24 1992-08-18 Micron Technology, Inc. Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape
EP0503201A2 (en) * 1990-12-20 1992-09-16 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board and method for manufacturing same
US5157480A (en) 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
US5165067A (en) 1989-12-01 1992-11-17 Inmos Limited Semiconductor chip packages
JPH04368154A (en) * 1991-06-15 1992-12-21 Sony Corp Semiconductor device
JPH0575015A (en) * 1991-09-13 1993-03-26 Sharp Corp Semiconductor device
US5198888A (en) 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
JPH05136656A (en) * 1991-11-13 1993-06-01 Murata Mfg Co Ltd Card type electronic tuner
US5229647A (en) 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5241133A (en) 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
US5291061A (en) 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5323060A (en) 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US5334875A (en) 1987-12-28 1994-08-02 Hitachi, Ltd. Stacked semiconductor memory device and semiconductor memory module containing the same
US5347429A (en) 1990-11-14 1994-09-13 Hitachi, Ltd. Plastic-molded-type semiconductor device
US5394010A (en) 1991-03-13 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor assembly having laminated semiconductor devices
US5422435A (en) 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5426563A (en) 1992-08-05 1995-06-20 Fujitsu Limited Three-dimensional multichip module
US5432729A (en) 1993-04-23 1995-07-11 Irvine Sensors Corporation Electronic module comprising a stack of IC chips each interacting with an IC chip secured to the stack
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5463253A (en) 1990-03-15 1995-10-31 Fujitsu Limited Semiconductor device having a plurality of chips
US5473196A (en) 1993-02-02 1995-12-05 Matra Marconi Space France Semiconductor memory component comprising stacked memory modules
US5474957A (en) 1994-05-09 1995-12-12 Nec Corporation Process of mounting tape automated bonded semiconductor chip on printed circuit board through bumps
US5474958A (en) 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
US5491612A (en) 1995-02-21 1996-02-13 Fairchild Space And Defense Corporation Three-dimensional modular assembly of integrated circuits
US5495394A (en) 1994-12-19 1996-02-27 At&T Global Information Solutions Company Three dimensional die packaging in multi-chip modules
US5514907A (en) 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
US5545922A (en) 1994-06-28 1996-08-13 Intel Corporation Dual sided integrated circuit chip package with offset wire bonds and support block cavities
US5569625A (en) 1992-01-08 1996-10-29 Fujitsu Limited Process for manufacturing a plural stacked leadframe semiconductor device
US5581498A (en) 1993-08-13 1996-12-03 Irvine Sensors Corporation Stack of IC chips in lieu of single IC chip
US5583378A (en) 1994-05-16 1996-12-10 Amkor Electronics, Inc. Ball grid array integrated circuit package with thermal conductor
US5594275A (en) 1993-11-18 1997-01-14 Samsung Electronics Co., Ltd. J-leaded semiconductor package having a plurality of stacked ball grid array packages
US5602059A (en) 1994-09-08 1997-02-11 Shinko Electric Industries Co., Ltd. Semiconductor device and method for manufacturing same
US5604376A (en) 1994-06-30 1997-02-18 Digital Equipment Corporation Paddleless molded plastic semiconductor chip package
US5614766A (en) 1991-09-30 1997-03-25 Rohm Co., Ltd. Semiconductor device with stacked alternate-facing chips
US5620928A (en) 1995-05-11 1997-04-15 National Semiconductor Corporation Ultra thin ball grid array using a flex tape or printed wiring board substrate and method
US5625221A (en) 1994-03-03 1997-04-29 Samsung Electronics Co., Ltd. Semiconductor assembly for a three-dimensional integrated circuit package
US5637912A (en) 1994-08-22 1997-06-10 International Business Machines Corporation Three-dimensional monolithic electronic module having stacked planar arrays of integrated circuit chips
US5637536A (en) 1993-08-13 1997-06-10 Thomson-Csf Method for interconnecting semiconductor chips in three dimensions, and component resulting therefrom
US5640047A (en) 1995-09-25 1997-06-17 Mitsui High-Tec, Inc. Ball grid assembly type semiconductor device having a heat diffusion function and an electric and magnetic shielding function
US5639695A (en) * 1994-11-02 1997-06-17 Motorola, Inc. Low-profile ball-grid array semiconductor package and method
US5646828A (en) 1995-02-24 1997-07-08 Lucent Technologies Inc. Thin packaging of multi-chip modules with enhanced thermal/power management
US5650593A (en) 1994-05-26 1997-07-22 Amkor Electronics, Inc. Thermally enhanced chip carrier package
US5652185A (en) 1995-04-07 1997-07-29 National Semiconductor Corporation Maximized substrate design for grid array based assemblies
US5668405A (en) 1994-09-14 1997-09-16 Nec Corporation Semiconductor device with a film carrier tape
US5677569A (en) 1994-10-27 1997-10-14 Samsung Electronics Co., Ltd. Semiconductor multi-package stack
US5682062A (en) 1995-06-05 1997-10-28 Harris Corporation System for interconnecting stacked integrated circuits
US5689135A (en) 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US5696031A (en) 1996-11-20 1997-12-09 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US5696666A (en) 1995-10-11 1997-12-09 Motorola, Inc. Low profile exposed die chip carrier package
US5721452A (en) 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5723900A (en) 1993-09-06 1998-03-03 Sony Corporation Resin mold type semiconductor device
US5729051A (en) 1994-09-22 1998-03-17 Nec Corporation Tape automated bonding type semiconductor device
US5739581A (en) 1995-11-17 1998-04-14 National Semiconductor Corporation High density integrated circuit package assembly with a heatsink between stacked dies
US5739585A (en) 1995-11-27 1998-04-14 Micron Technology, Inc. Single piece package for semiconductor die
US5744827A (en) 1995-11-28 1998-04-28 Samsung Electronics Co., Ltd. Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements
US5760471A (en) 1994-04-20 1998-06-02 Fujitsu Limited Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic package
US5763939A (en) 1994-09-30 1998-06-09 Nec Corporation Semiconductor device having a perforated base film sheet
US5767528A (en) 1996-02-20 1998-06-16 Fujitsu Limited Semiconductor device including pad portion for testing
US5777387A (en) 1995-09-29 1998-07-07 Nec Corporation Semiconductor device constructed by mounting a semiconductor chip on a film carrier tape
US5783870A (en) 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
US5786239A (en) 1995-09-20 1998-07-28 Sony Corporation Method of manufacturing a semiconductor package
US5793108A (en) 1995-05-30 1998-08-11 Sharp Kabushiki Kaisha Semiconductor integrated circuit having a plurality of semiconductor chips
US5798014A (en) 1995-02-02 1998-08-25 Hestia Technologies, Inc. Methods of making multi-tier laminate substrates for electronic device packaging
US5801439A (en) 1994-04-20 1998-09-01 Fujitsu Limited Semiconductor device and semiconductor device unit for a stack arrangement
US5815372A (en) 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US5819398A (en) 1995-07-31 1998-10-13 Sgs-Thomson Microelectronics, Ltd. Method of manufacturing a ball grid array package
US5835355A (en) 1997-09-22 1998-11-10 Lsi Logic Corporation Tape ball grid array package with perforated metal stiffener
US5835988A (en) 1996-03-27 1998-11-10 Mitsubishi Denki Kabushiki Kaisha Packed semiconductor device with wrap around external leads
US5854741A (en) 1995-11-17 1998-12-29 Amkor Electronics, Inc. Unit printed circuit board carrier frame for ball grid array semiconductor packages and method for fabricating ball grid array semiconductor packages using the same
US5859471A (en) 1992-11-17 1999-01-12 Shinko Electric Industries Co., Ltd. Semiconductor device having tab tape lead frame with reinforced outer leads
US5861666A (en) 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
US5866949A (en) 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
US5872025A (en) 1995-07-26 1999-02-16 International Business Machines Corporation Method for stacked three dimensional device manufacture
US5883426A (en) 1996-04-18 1999-03-16 Nec Corporation Stack module
US5885849A (en) 1995-03-28 1999-03-23 Tessera, Inc. Methods of making microelectronic assemblies
US5886412A (en) 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5894108A (en) 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
US5895965A (en) 1996-09-20 1999-04-20 Hitachi, Ltd. Semiconductor device
US5903052A (en) 1998-05-12 1999-05-11 Industrial Technology Research Institute Structure for semiconductor package for improving the efficiency of spreading heat
US5909633A (en) 1996-11-29 1999-06-01 Matsushita Electric Industrial Co., Ltd. Method of manufacturing an electronic component
US5917242A (en) 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US5930599A (en) 1996-02-19 1999-07-27 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US6093970A (en) * 1994-11-22 2000-07-25 Sony Corporation Semiconductor device and method for manufacturing the same
US6172419B1 (en) * 1998-02-24 2001-01-09 Micron Technology, Inc. Low profile ball grid array package
US6235554B1 (en) * 1995-11-27 2001-05-22 Micron Technology, Inc. Method for fabricating stackable chip scale semiconductor package
US6395578B1 (en) * 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6515356B1 (en) * 1999-05-07 2003-02-04 Amkor Technology, Inc. Semiconductor package and method for fabricating the same

Patent Citations (112)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851221A (en) 1972-11-30 1974-11-26 P Beaulieu Integrated circuit package
US3838984A (en) 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
US4398235A (en) 1980-09-11 1983-08-09 General Motors Corporation Vertical integrated circuit package integration
US4530152A (en) 1982-04-01 1985-07-23 Compagnie Industrielle Des Telecommunications Cit-Alcatel Method for encapsulating semiconductor components using temporary substrates
US4567643A (en) 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
US4707724A (en) 1984-06-04 1987-11-17 Hitachi, Ltd. Semiconductor device and method of manufacturing thereof
US4729061A (en) 1985-04-29 1988-03-01 Advanced Micro Devices, Inc. Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom
US4756080A (en) 1986-01-27 1988-07-12 American Microsystems, Inc. Metal foil semiconductor interconnection method
US4730232A (en) 1986-06-25 1988-03-08 Westinghouse Electric Corp. High density microelectronic packaging module for high speed chips
US4763188A (en) 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
US5587341A (en) 1987-06-24 1996-12-24 Hitachi, Ltd. Process for manufacturing a stacked integrated circuit package
US4982265A (en) 1987-06-24 1991-01-01 Hitachi, Ltd. Semiconductor integrated circuit device and method of manufacturing the same
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
JPH0199248A (en) * 1987-10-13 1989-04-18 Mitsubishi Electric Corp Semiconductor device
US5198888A (en) 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US5334875A (en) 1987-12-28 1994-08-02 Hitachi, Ltd. Stacked semiconductor memory device and semiconductor memory module containing the same
US5040052A (en) 1987-12-28 1991-08-13 Texas Instruments Incorporated Compact silicon module for high density integrated circuits
US5025306A (en) 1988-08-09 1991-06-18 Texas Instruments Incorporated Assembly of semiconductor chips
US4996587A (en) 1989-04-10 1991-02-26 International Business Machines Corporation Integrated semiconductor chip package
US5273938A (en) 1989-09-06 1993-12-28 Motorola, Inc. Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5012323A (en) 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5165067A (en) 1989-12-01 1992-11-17 Inmos Limited Semiconductor chip packages
US5463253A (en) 1990-03-15 1995-10-31 Fujitsu Limited Semiconductor device having a plurality of chips
JPH0456262A (en) * 1990-06-25 1992-02-24 Matsushita Electron Corp Semiconductor integrated circuit device
US5140404A (en) 1990-10-24 1992-08-18 Micron Technology, Inc. Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape
US5347429A (en) 1990-11-14 1994-09-13 Hitachi, Ltd. Plastic-molded-type semiconductor device
EP0503201A2 (en) * 1990-12-20 1992-09-16 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board and method for manufacturing same
US5715147A (en) 1990-12-20 1998-02-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US5241133A (en) 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
US5157480A (en) 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
US5394010A (en) 1991-03-13 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor assembly having laminated semiconductor devices
US5229647A (en) 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
JPH04368154A (en) * 1991-06-15 1992-12-21 Sony Corp Semiconductor device
JPH0575015A (en) * 1991-09-13 1993-03-26 Sharp Corp Semiconductor device
US5614766A (en) 1991-09-30 1997-03-25 Rohm Co., Ltd. Semiconductor device with stacked alternate-facing chips
JPH05136656A (en) * 1991-11-13 1993-06-01 Murata Mfg Co Ltd Card type electronic tuner
US5569625A (en) 1992-01-08 1996-10-29 Fujitsu Limited Process for manufacturing a plural stacked leadframe semiconductor device
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5502289A (en) 1992-05-22 1996-03-26 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5422435A (en) 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5495398A (en) 1992-05-22 1996-02-27 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5426563A (en) 1992-08-05 1995-06-20 Fujitsu Limited Three-dimensional multichip module
US5859471A (en) 1992-11-17 1999-01-12 Shinko Electric Industries Co., Ltd. Semiconductor device having tab tape lead frame with reinforced outer leads
US5473196A (en) 1993-02-02 1995-12-05 Matra Marconi Space France Semiconductor memory component comprising stacked memory modules
US5291061A (en) 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5432729A (en) 1993-04-23 1995-07-11 Irvine Sensors Corporation Electronic module comprising a stack of IC chips each interacting with an IC chip secured to the stack
US5474958A (en) 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
US5323060A (en) 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US5581498A (en) 1993-08-13 1996-12-03 Irvine Sensors Corporation Stack of IC chips in lieu of single IC chip
US5637536A (en) 1993-08-13 1997-06-10 Thomson-Csf Method for interconnecting semiconductor chips in three dimensions, and component resulting therefrom
US5723900A (en) 1993-09-06 1998-03-03 Sony Corporation Resin mold type semiconductor device
US5594275A (en) 1993-11-18 1997-01-14 Samsung Electronics Co., Ltd. J-leaded semiconductor package having a plurality of stacked ball grid array packages
US5625221A (en) 1994-03-03 1997-04-29 Samsung Electronics Co., Ltd. Semiconductor assembly for a three-dimensional integrated circuit package
US5760471A (en) 1994-04-20 1998-06-02 Fujitsu Limited Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic package
US5801439A (en) 1994-04-20 1998-09-01 Fujitsu Limited Semiconductor device and semiconductor device unit for a stack arrangement
US5474957A (en) 1994-05-09 1995-12-12 Nec Corporation Process of mounting tape automated bonded semiconductor chip on printed circuit board through bumps
US5583378A (en) 1994-05-16 1996-12-10 Amkor Electronics, Inc. Ball grid array integrated circuit package with thermal conductor
US5650593A (en) 1994-05-26 1997-07-22 Amkor Electronics, Inc. Thermally enhanced chip carrier package
US5545922A (en) 1994-06-28 1996-08-13 Intel Corporation Dual sided integrated circuit chip package with offset wire bonds and support block cavities
US5604376A (en) 1994-06-30 1997-02-18 Digital Equipment Corporation Paddleless molded plastic semiconductor chip package
US5637912A (en) 1994-08-22 1997-06-10 International Business Machines Corporation Three-dimensional monolithic electronic module having stacked planar arrays of integrated circuit chips
US5602059A (en) 1994-09-08 1997-02-11 Shinko Electric Industries Co., Ltd. Semiconductor device and method for manufacturing same
US5668405A (en) 1994-09-14 1997-09-16 Nec Corporation Semiconductor device with a film carrier tape
US5729051A (en) 1994-09-22 1998-03-17 Nec Corporation Tape automated bonding type semiconductor device
US5763939A (en) 1994-09-30 1998-06-09 Nec Corporation Semiconductor device having a perforated base film sheet
US5677569A (en) 1994-10-27 1997-10-14 Samsung Electronics Co., Ltd. Semiconductor multi-package stack
US5639695A (en) * 1994-11-02 1997-06-17 Motorola, Inc. Low-profile ball-grid array semiconductor package and method
US6093970A (en) * 1994-11-22 2000-07-25 Sony Corporation Semiconductor device and method for manufacturing the same
US5495394A (en) 1994-12-19 1996-02-27 At&T Global Information Solutions Company Three dimensional die packaging in multi-chip modules
US5798014A (en) 1995-02-02 1998-08-25 Hestia Technologies, Inc. Methods of making multi-tier laminate substrates for electronic device packaging
US5491612A (en) 1995-02-21 1996-02-13 Fairchild Space And Defense Corporation Three-dimensional modular assembly of integrated circuits
US5646828A (en) 1995-02-24 1997-07-08 Lucent Technologies Inc. Thin packaging of multi-chip modules with enhanced thermal/power management
US5783870A (en) 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
US5514907A (en) 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
US5885849A (en) 1995-03-28 1999-03-23 Tessera, Inc. Methods of making microelectronic assemblies
US5652185A (en) 1995-04-07 1997-07-29 National Semiconductor Corporation Maximized substrate design for grid array based assemblies
US5620928A (en) 1995-05-11 1997-04-15 National Semiconductor Corporation Ultra thin ball grid array using a flex tape or printed wiring board substrate and method
US5793108A (en) 1995-05-30 1998-08-11 Sharp Kabushiki Kaisha Semiconductor integrated circuit having a plurality of semiconductor chips
US5682062A (en) 1995-06-05 1997-10-28 Harris Corporation System for interconnecting stacked integrated circuits
US5872025A (en) 1995-07-26 1999-02-16 International Business Machines Corporation Method for stacked three dimensional device manufacture
US5819398A (en) 1995-07-31 1998-10-13 Sgs-Thomson Microelectronics, Ltd. Method of manufacturing a ball grid array package
US5721452A (en) 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5886412A (en) 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5861666A (en) 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
US5786239A (en) 1995-09-20 1998-07-28 Sony Corporation Method of manufacturing a semiconductor package
US5640047A (en) 1995-09-25 1997-06-17 Mitsui High-Tec, Inc. Ball grid assembly type semiconductor device having a heat diffusion function and an electric and magnetic shielding function
US5777387A (en) 1995-09-29 1998-07-07 Nec Corporation Semiconductor device constructed by mounting a semiconductor chip on a film carrier tape
US5696666A (en) 1995-10-11 1997-12-09 Motorola, Inc. Low profile exposed die chip carrier package
US5739581A (en) 1995-11-17 1998-04-14 National Semiconductor Corporation High density integrated circuit package assembly with a heatsink between stacked dies
US5854741A (en) 1995-11-17 1998-12-29 Amkor Electronics, Inc. Unit printed circuit board carrier frame for ball grid array semiconductor packages and method for fabricating ball grid array semiconductor packages using the same
US5739585A (en) 1995-11-27 1998-04-14 Micron Technology, Inc. Single piece package for semiconductor die
US6235554B1 (en) * 1995-11-27 2001-05-22 Micron Technology, Inc. Method for fabricating stackable chip scale semiconductor package
US5744827A (en) 1995-11-28 1998-04-28 Samsung Electronics Co., Ltd. Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements
US5689135A (en) 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US5930599A (en) 1996-02-19 1999-07-27 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US5767528A (en) 1996-02-20 1998-06-16 Fujitsu Limited Semiconductor device including pad portion for testing
US5835988A (en) 1996-03-27 1998-11-10 Mitsubishi Denki Kabushiki Kaisha Packed semiconductor device with wrap around external leads
US5883426A (en) 1996-04-18 1999-03-16 Nec Corporation Stack module
US5917242A (en) 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US5895965A (en) 1996-09-20 1999-04-20 Hitachi, Ltd. Semiconductor device
US5696031A (en) 1996-11-20 1997-12-09 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US5909633A (en) 1996-11-29 1999-06-01 Matsushita Electric Industrial Co., Ltd. Method of manufacturing an electronic component
US5866949A (en) 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
US5894108A (en) 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
US5815372A (en) 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US5835355A (en) 1997-09-22 1998-11-10 Lsi Logic Corporation Tape ball grid array package with perforated metal stiffener
US6172419B1 (en) * 1998-02-24 2001-01-09 Micron Technology, Inc. Low profile ball grid array package
US5903052A (en) 1998-05-12 1999-05-11 Industrial Technology Research Institute Structure for semiconductor package for improving the efficiency of spreading heat
US6515356B1 (en) * 1999-05-07 2003-02-04 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6717248B2 (en) * 1999-05-07 2004-04-06 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6395578B1 (en) * 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Shin et al., U.S. Appl. No. 10/785,528, filed Feb. 24, 2004, entitled "Semiconductor Package and Method for Fabricating the Same".

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080085572A1 (en) * 2006-10-05 2008-04-10 Advanced Chip Engineering Technology Inc. Semiconductor packaging method by using large panel size

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