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US8674491B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US8674491B2
US8674491B2 US13/103,107 US201113103107A US8674491B2 US 8674491 B2 US8674491 B2 US 8674491B2 US 201113103107 A US201113103107 A US 201113103107A US 8674491 B2 US8674491 B2 US 8674491B2
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circuit layer
semiconductor device
silicon
electrically connected
bumps
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US20120153454A1 (en
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Chun-Kai Liu
John H. Lau
Ming-Ji Dai
Ra-Min Tain
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/38—Cooling arrangements using the Peltier effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1094—Conducting structures comprising nanotubes or nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling

Definitions

  • This disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a thermoelectric cooling mechanism.
  • the chip often suffers from severe heat dissipation insufficiency.
  • the heat dissipation insufficiency issue in the 3D stacked IC is even severe.
  • the heat generation per unit area is increased accordingly. Therefore, quickly dissipating the heat of the chip out of the tiny interior of the 3D stacked IC is of critically importance.
  • thermoelectric elements formed from semiconductor thermoelectric materials do not need any liquid or gas as coolant and have the advantages of continuous work capability, no pollution, no moving parts, no noise, long life, small volume and light weight. Therefore, the thermoelectric elements have been widely used in cooling or heating apparatus.
  • traditional thermoelectric elements have a large volume and require a separate power supply circuit. As such, they can only be attached to an outside of the 3D stacked IC, which still cannot effectively help cool the interior high temperature area.
  • the semiconductor device includes a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer.
  • the silicon substrate has a first surface, a second surface opposite to the first surface, and a plurality of through holes.
  • the silicon nanowire clusters are disposed in the through holes, respectively.
  • the first circuit layer is disposed on the first surface and electrically connected to the silicon nanowire clusters.
  • the second circuit layer is disposed on the second surface and electrically connected to the silicon nanowire clusters.
  • FIG. 1 is a schematic diagram illustrating a cross-section of a semiconductor device according to an exemplary embodiment.
  • FIG. 2A to FIG. 2G are schematic diagrams illustrating the process of forming the silicon nanowire clusters and TSVs.
  • FIG. 3 is a schematic diagram illustrating a semiconductor device according to another exemplary embodiment.
  • FIG. 4 is a schematic diagram illustrating a semiconductor device according to another exemplary embodiment.
  • FIG. 5 is a schematic diagram illustrating a semiconductor device according to another exemplary embodiment.
  • FIG. 6 is a schematic diagram illustrating a semiconductor device according to another exemplary embodiment.
  • FIG. 7 is a schematic diagram illustrating a semiconductor device according to another exemplary embodiment.
  • FIG. 8 is a schematic diagram illustrating a semiconductor device according to still another exemplary embodiment.
  • Exemplary Embodiments of this disclosure provide a semiconductor device.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment.
  • the semiconductor device 100 of the embodiment includes a silicon substrate 110 , a plurality of silicon nanowire clusters 120 , a first circuit layer 130 and a second circuit layer 140 .
  • the silicon substrate 110 has a first surface 112 , a second surface 114 opposite to the first surface 112 , and a plurality of through holes 116 .
  • Each silicon nanowire cluster 120 is disposed in a corresponding each of the through holes 116 .
  • the first circuit layer 130 is disposed on the first surface 112 and electrically connected to the silicon nanowire clusters 120 .
  • the second circuit layer 140 is disposed on the second surface 114 and electrically connected to the silicon nanowire clusters 120 .
  • the silicon nanowire clusters 120 are, for example, directly formed from the silicon substrate 110 .
  • Each silicon nanowire cluster 120 is, for example, a P-type nanowire cluster or N-type nanowire cluster.
  • Electric current flows through the first circuit layer 130 , the second circuit layer 140 and the P- and N-type silicon nanowire clusters 120 to produce thermoelectric effect which takes chip's heat on the first circuit layer 130 side or the second circuit layer 140 side away to thereby achieve heat dissipation.
  • the silicon nanowire clusters 120 are directly disposed in the silicon substrate 110 and the needed electric current path is formed by the circuit layers on the surfaces of the silicon substrate 110 , the semiconductor device 100 of the embodiment can achieve excellent heat dissipation efficiency under a limited size thereof.
  • the semiconductor device 100 may also be used in a 3D tacked IC where the silicon nanowire clusters 120 are disposed around the hot spot in the interior of the 3D stacked IC to effectively dissipate heat of the hot spot thus increasing the reliability of the 3D stacked IC.
  • All the silicon nanowire clusters 120 of the embodiment are connected with one another to form a single thermoelectric element. It is noted, however, that the silicon nanowire clusters 120 may also be divided into groups to form multiple individual thermoelectric elements and the cold end of each thermoelectric element may be positioned adjacent the first circuit layer 130 or the second circuit layer 140 with as many cold ends being close to the hot source as possible. Therefore, the thermoelectric element design can be rather flexible.
  • the semiconductor device 100 of the embodiment further includes an insulation filling material 150 filled in the through holes 116 .
  • the insulation filling material 150 is applied along the walls of the through holes 116 and between the silicon nanowires of the silicon nanowire clusters 120 to thereby properly position the silicon nanowire clusters 120 .
  • the insulation filling material 150 is, for example, silicon oxide or another insulation material. It is noted, however, that the insulation filling material 150 is not necessarily filled between the silicon nanowires of the silicon nanowire clusters 120 . Instead, air may be used to achieve the insulation result.
  • the semiconductor device 100 of the embodiment further includes at least one through silicon via (TSV) 160 defined through the silicon substrate 110 and electrically connected with the first circuit layer 130 and the second circuit layer 140 .
  • TSV through silicon via
  • the embodiment takes a plurality of TSVs 160 as an example.
  • the TSVs 160 are used to electrically connect the first circuit layer 130 with the second circuit layer 140 .
  • the TSVs 160 can not only be used for signal transmission, but they also can be electrically connected to the silicon nanowire clusters 120 to act as power supplying circuits for the silicon nanowire clusters 120 . Therefore, even if the silicon nanowire clusters 120 are disposed inside the 3D stacked IC, the silicon nanowire clusters 120 can still obtain the needed power via the TSVs 160 , without the need of additional power supplying circuits that cannot easily be integrated into the 3D stacked IC, thus significantly increasing the utility.
  • Using the embedded silicon nanowire clusters 120 to dissipate heat also alleviates the contact thermal resistance problem caused by the traditional heat dissipation elements which need to be attached or adhered to an IC outside.
  • the semiconductor device 100 of the embodiment further includes at least one integrated circuit (IC) unit 170 and an insulation layer 180 .
  • IC integrated circuit
  • the two IC units 170 are both disposed on the first surface 112 and one insulation layer 180 covers the IC units 170 .
  • the first circuit layer 130 is disposed on the insulation layer 180 and electrically connected with the IC units 170 and silicon nanowire clusters 120 via several openings of the insulation layer 180 .
  • the other insulation layer 180 is disposed between the second surface 114 and the second circuit layer 140 .
  • the IC units 170 of the embodiment may be logic circuit units, memory units or another type of IC units. In other words, the semiconductor device 100 of the embodiment may be any single-function or multi-function chip. It is not intended to limit the position of each IC unit 170 to being concentrated on specific area as shown in FIG. 1 . Rather, the IC units 170 can be distributed over the first surface 112 at multiple areas.
  • FIG. 2A to FIG. 2G illustrate the process of forming the silicon nanowire clusters and TSVs.
  • a patterned silicon dioxide layer L 10 is formed on the silicon substrate 110 using a photolithography and etching process, and the silicon dioxide layer L 10 is then used as a mask to etch through holes P 12 and P 14 with different depth.
  • the silicon substrate 110 has been formed with IC units thereon in a wafer factory and has a reserved area without IC units or other circuits thereat such that through holes can be formed at the reserved area in subsequent procedures.
  • insulation material e.g.
  • silicon dioxide silicon dioxide
  • metal are sequentially filled into the through hole P 12 , and a plurality of silver nano-particles are applied to the through hole P 14 .
  • an electroless chemical etching process is performed on a portion of the silicon substrate 110 that is under the silver nano-particles 122 (shown in FIG. 2B ) of the through hole P 14 using solution such as hydrofluoric acid, thereby forming a silicon nanowire cluster 120 comprising many silicon nanowires.
  • the silver nano-particles 122 are removed from the through hole P 14 (shown in FIG. 2C ), and a first circuit layer 130 is formed using photolithography and etching process and plating process.
  • the first circuit layer 130 connects to both of the metal in the through hole P 12 and the silicon nanowire cluster 120 in the through hole P 14 .
  • a carrier plate 50 is disposed on the silicon substrate 110 and bonded to the first circuit layer 130 .
  • the silicon substrate 110 is thinned from its bottom side until the metal in the through hole P 12 and the silicon nanowire cluster 120 in the through hole P 14 are exposed. Referring to FIG.
  • a second circuit layer 140 is formed on the second surface 114 of the silicon substrate 110 .
  • a patterned silicon dioxide layer L 12 can be formed on the second surface 114 of the silicon substrate 110 .
  • the silicon dioxide layer L 12 is used to prevent the second circuit layer 140 from directly contacting the silicon substrate 110 .
  • the second circuit layer 140 connects to the metal in the through hole P 12 and the silicon nanowire cluster 120 in the through hole P 14 .
  • the metal in the through hole P 12 is the TSV 160 of FIG. 1 .
  • a semiconductor device similar to that of FIG. 1 can be formed by removing the carrier plate 50 . If a bump process can be performed prior to removal of the carrier plate 50 to form bumps (not shown). It is noted that methods and materials used in the process described above are merely illustrative rather than limiting.
  • the nanowire structures formed by chemical etching have rough surfaces which help reduce thermal conductivity and hence increase the thermoelectric figure of merit (ZT value) of the thermoelectric material.
  • the rough surfaces of the nanowire structures can significantly increase the scattering probability of phonons during transmission in the material and reduce the average free path of the phonons, thus significantly reducing the thermal conductivity and increasing the ZT value of the thermoelectric material.
  • the traditional silicon material has a rather high thermal conductivity which is about 150 W/m-K but has poor electrically conductive characteristics.
  • small-scale nanowire structures with wire diameter of 50 nanometers and rough surfaces can have a thermal conductivity as low as 1/100 of that of silicon bulk and a ZT value larger than 0.6. Therefore, the small-scale nanowire structures have the potential to increase the material's electrically conductive performance.
  • the chemical etching process is directly performed on the silicon substrate (e.g. silicon wafer) to obtain thermoelectric modules with nanowire clusters.
  • An experimental measurement conducted on a nanowire structure that has not undergone wire diameter uniformity control shows that its thermal conductivity is 55-68 W/m-K which is about 1 ⁇ 2 of that of the silicon bulk.
  • the silicon nanowire clusters of the embodiment can bring the following advantages. Firstly, the silicon nanowire clusters can provide good thermoelectric conversion efficiency. Secondly, the substrate and the silicon nanowire clusters are fabricated from the same silicon substrate and, therefore, the substrate and the silicon nanowire clusters have reduced interface electric resistance and thermal resistance therebetween. In addition, the doping technology for P-type and N-type doping of silicon material is mature and therefore the doping process can be controlled. Besides, by using the electroless chemical etching process to fabricate the nanowire structures, a large quantity of large-area silicon nanowire clusters can be fabricated on the silicon substrate at the same time. Moreover, the fabrication of silicon nanowire clusters is compatible with the TSV fabrication, which can help reduce fabrication cost.
  • FIG. 3 illustrates a semiconductor device according to another exemplary embodiment.
  • the semiconductor device 200 of this embodiment includes a semiconductor device 100 generally same as the semiconductor device 100 of FIG. 1 , a chip 210 , an organic substrate 220 , and a circuit board 230 .
  • the circuit board 230 includes a circuit layer 232 .
  • the organic substrate 220 includes circuit layers 222 and 224 .
  • the chip 210 includes a circuit layer 212 .
  • the first circuit layer 130 of the semiconductor device 100 may be electrically connected to the circuit layer 212 of the chip 210 via a plurality of bumps 240 or other components.
  • FIG. 4 illustrates a semiconductor device according to another exemplary embodiment.
  • the semiconductor device 300 of the embodiment includes a semiconductor device 100 generally same as the semiconductor device 100 of FIG. 1 , a chip 310 , an organic substrate 220 , a silicon substrate 320 , and a circuit board 230 .
  • the difference between the semiconductor device 300 of the embodiment and the semiconductor device 200 of FIG. 3 lies in the chip 310 and silicon substrate 320 .
  • the chip 310 includes TSVs 312 , a circuit layer 314 and a circuit layer 316 .
  • the TSVs 312 electrically connect the circuit layer 314 with the circuit layer 316 .
  • the silicon substrate 320 includes TSVs 322 , a circuit layer 324 and a circuit layer 326 .
  • the TSVs 322 electrically connect the circuit layer 324 and the circuit layer 326 .
  • the second circuit layer 140 of the semiconductor device 100 is electrically connected to the circuit layer 324 of the silicon substrate 320 via a plurality of bumps 240 or other components.
  • the circuit layer 326 of the silicon substrate 320 is electrically connected to the circuit layer 222 of the organic substrate 220 .
  • the circuit layer 222 of the organic substrate 220 is electrically connected to the circuit layer 224 .
  • the circuit layer 224 of the organic substrate 220 is electrically connected to the circuit layer 232 of the circuit board 230 via a plurality of bumps 240 and other components.
  • FIG. 5 illustrates a semiconductor device according to another exemplary embodiment.
  • the semiconductor device 400 of the embodiment is similar to the semiconductor device 300 of FIG. 4 except that the circuit layer 324 of the silicon substrate 320 is electrically connected to the circuit layer 222 of the organic substrate 220 via at least one conducting wire 328 .
  • FIG. 6 illustrates a semiconductor device according to another exemplary embodiment.
  • the semiconductor device 500 of the embodiment is similar to the semiconductor device 300 of FIG. 4 except that the semiconductor device 500 does not include an organic substrate.
  • the circuit layer 326 of the silicon substrate 320 is electrically connected to the circuit layer 232 of the circuit board 230 via bumps 240 or other components, and an underfill material 510 is filled between the silicon substrate 320 and circuit board 230 .
  • FIG. 7 illustrates a semiconductor device according to another exemplary embodiment.
  • the semiconductor device 600 of the embodiment is similar to the semiconductor device 500 of FIG. 6 except that the semiconductor device 600 further includes a heat sink 610 .
  • the heat sink 610 is disposed on the chip 310 .
  • the silicon nanowire clusters 120 of the semiconductor device 100 take the heat of the IC units 170 away and the heat is further transferred to the heat sink 610 via the TSVs 312 of the chip 310 to enhance heat dissipation efficiency.
  • the heat may be transferred between the heat sink 610 and the TSVs 312 of the chip 312 via the circuit layer 314 and heat conductive members 612 .
  • the portion of the circuit layer 314 for heat transfer may be, for example, used to transfer heat and do not transmit electricity or electric signal.
  • the heat conductive members 612 and the bumps 240 may be formed with the same process.
  • FIG. 8 illustrates a semiconductor device according to still another exemplary embodiment.
  • the semiconductor device 700 of the embodiment is similar to the semiconductor device 500 except that one end of the TSV 712 is connected to a redistribution circuit 714 on one side of the silicon substrate 710 .
  • the silicon nanowire clusters for establishing the thermoelectric cooling mechanism are directly formed in the silicon substrate, i.e. directly formed in the chip. Therefore, the hot spot of a single IC or a 3D stacked IC can be cooled.
  • the silicon nanowire clusters can be disposed inside the 3D stacked IC without designing additional power supply paths.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 99144951, filed Dec. 21, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
TECHNICAL FIELD
This disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a thermoelectric cooling mechanism.
BACKGROUND
The trend of future semiconductor packaging process development is toward high precision processes for high power, high density, low cost, light, thin, short and small semiconductor devices, and 3D stacked IC technology is one example of such processes. One of the most challenging factors is heat dissipation. Hot spot formed at local high temperature area inside the 3D stacked IC causes heat and stress concentrations which bring a thermal stress issue and hence affect the product reliability. Therefore, the hot spot issue has become a bottleneck of 3D stacked IC technology. Study shows that the hot spot issue may significantly increase the need for chip heat dissipation, such that the thermal resistance of heat dissipation elements needs to be further reduced, e.g. even reduced to one-second to one-third of its current value. As such, the chip often suffers from severe heat dissipation insufficiency. The heat dissipation insufficiency issue in the 3D stacked IC is even severe. With the increase in heat generation density in stacked ICs, the heat generation per unit area is increased accordingly. Therefore, quickly dissipating the heat of the chip out of the tiny interior of the 3D stacked IC is of critically importance.
Thermoelectric elements formed from semiconductor thermoelectric materials do not need any liquid or gas as coolant and have the advantages of continuous work capability, no pollution, no moving parts, no noise, long life, small volume and light weight. Therefore, the thermoelectric elements have been widely used in cooling or heating apparatus. However, traditional thermoelectric elements have a large volume and require a separate power supply circuit. As such, they can only be attached to an outside of the 3D stacked IC, which still cannot effectively help cool the interior high temperature area.
SUMMARY
A semiconductor device is introduced herein. The semiconductor device includes a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface, and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes, respectively. The first circuit layer is disposed on the first surface and electrically connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and electrically connected to the silicon nanowire clusters.
Several exemplary embodiments accompanied with figures are described in detail below to further describe the invention in details.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram illustrating a cross-section of a semiconductor device according to an exemplary embodiment.
FIG. 2A to FIG. 2G are schematic diagrams illustrating the process of forming the silicon nanowire clusters and TSVs.
FIG. 3 is a schematic diagram illustrating a semiconductor device according to another exemplary embodiment.
FIG. 4 is a schematic diagram illustrating a semiconductor device according to another exemplary embodiment.
FIG. 5 is a schematic diagram illustrating a semiconductor device according to another exemplary embodiment.
FIG. 6 is a schematic diagram illustrating a semiconductor device according to another exemplary embodiment.
FIG. 7 is a schematic diagram illustrating a semiconductor device according to another exemplary embodiment.
FIG. 8 is a schematic diagram illustrating a semiconductor device according to still another exemplary embodiment.
 DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS
Exemplary Embodiments of this disclosure provide a semiconductor device.
FIG. 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. Referring to FIG. 1, the semiconductor device 100 of the embodiment includes a silicon substrate 110, a plurality of silicon nanowire clusters 120, a first circuit layer 130 and a second circuit layer 140. The silicon substrate 110 has a first surface 112, a second surface 114 opposite to the first surface 112, and a plurality of through holes 116. Each silicon nanowire cluster 120 is disposed in a corresponding each of the through holes 116. The first circuit layer 130 is disposed on the first surface 112 and electrically connected to the silicon nanowire clusters 120. The second circuit layer 140 is disposed on the second surface 114 and electrically connected to the silicon nanowire clusters 120.
In the embodiment, the silicon nanowire clusters 120 are, for example, directly formed from the silicon substrate 110. Each silicon nanowire cluster 120 is, for example, a P-type nanowire cluster or N-type nanowire cluster. Electric current flows through the first circuit layer 130, the second circuit layer 140 and the P- and N-type silicon nanowire clusters 120 to produce thermoelectric effect which takes chip's heat on the first circuit layer 130 side or the second circuit layer 140 side away to thereby achieve heat dissipation. Because, in the embodiment, the silicon nanowire clusters 120 are directly disposed in the silicon substrate 110 and the needed electric current path is formed by the circuit layers on the surfaces of the silicon substrate 110, the semiconductor device 100 of the embodiment can achieve excellent heat dissipation efficiency under a limited size thereof. In addition, the semiconductor device 100 may also be used in a 3D tacked IC where the silicon nanowire clusters 120 are disposed around the hot spot in the interior of the 3D stacked IC to effectively dissipate heat of the hot spot thus increasing the reliability of the 3D stacked IC. All the silicon nanowire clusters 120 of the embodiment are connected with one another to form a single thermoelectric element. It is noted, however, that the silicon nanowire clusters 120 may also be divided into groups to form multiple individual thermoelectric elements and the cold end of each thermoelectric element may be positioned adjacent the first circuit layer 130 or the second circuit layer 140 with as many cold ends being close to the hot source as possible. Therefore, the thermoelectric element design can be rather flexible.
The semiconductor device 100 of the embodiment further includes an insulation filling material 150 filled in the through holes 116. The insulation filling material 150 is applied along the walls of the through holes 116 and between the silicon nanowires of the silicon nanowire clusters 120 to thereby properly position the silicon nanowire clusters 120. The insulation filling material 150 is, for example, silicon oxide or another insulation material. It is noted, however, that the insulation filling material 150 is not necessarily filled between the silicon nanowires of the silicon nanowire clusters 120. Instead, air may be used to achieve the insulation result. The semiconductor device 100 of the embodiment further includes at least one through silicon via (TSV) 160 defined through the silicon substrate 110 and electrically connected with the first circuit layer 130 and the second circuit layer 140. The embodiment takes a plurality of TSVs 160 as an example. The TSVs 160 are used to electrically connect the first circuit layer 130 with the second circuit layer 140. The TSVs 160 can not only be used for signal transmission, but they also can be electrically connected to the silicon nanowire clusters 120 to act as power supplying circuits for the silicon nanowire clusters 120. Therefore, even if the silicon nanowire clusters 120 are disposed inside the 3D stacked IC, the silicon nanowire clusters 120 can still obtain the needed power via the TSVs 160, without the need of additional power supplying circuits that cannot easily be integrated into the 3D stacked IC, thus significantly increasing the utility. Using the embedded silicon nanowire clusters 120 to dissipate heat also alleviates the contact thermal resistance problem caused by the traditional heat dissipation elements which need to be attached or adhered to an IC outside.
The semiconductor device 100 of the embodiment further includes at least one integrated circuit (IC) unit 170 and an insulation layer 180. As one example, two IC units 170 and two insulation layers 180 are illustrated in the embodiment. The two IC units 170 are both disposed on the first surface 112 and one insulation layer 180 covers the IC units 170. The first circuit layer 130 is disposed on the insulation layer 180 and electrically connected with the IC units 170 and silicon nanowire clusters 120 via several openings of the insulation layer 180. The other insulation layer 180 is disposed between the second surface 114 and the second circuit layer 140. The IC units 170 of the embodiment may be logic circuit units, memory units or another type of IC units. In other words, the semiconductor device 100 of the embodiment may be any single-function or multi-function chip. It is not intended to limit the position of each IC unit 170 to being concentrated on specific area as shown in FIG. 1. Rather, the IC units 170 can be distributed over the first surface 112 at multiple areas.
FIG. 2A to FIG. 2G illustrate the process of forming the silicon nanowire clusters and TSVs. Referring to FIG. 2A, firstly, a patterned silicon dioxide layer L10 is formed on the silicon substrate 110 using a photolithography and etching process, and the silicon dioxide layer L10 is then used as a mask to etch through holes P12 and P14 with different depth. Generally, the silicon substrate 110 has been formed with IC units thereon in a wafer factory and has a reserved area without IC units or other circuits thereat such that through holes can be formed at the reserved area in subsequent procedures. Referring to FIG. 2B, insulation material (e.g. silicon dioxide) and metal are sequentially filled into the through hole P12, and a plurality of silver nano-particles are applied to the through hole P14. Referring to FIG. 2C, an electroless chemical etching process is performed on a portion of the silicon substrate 110 that is under the silver nano-particles 122 (shown in FIG. 2B) of the through hole P14 using solution such as hydrofluoric acid, thereby forming a silicon nanowire cluster 120 comprising many silicon nanowires.
Referring to FIG. 2D, the silver nano-particles 122 are removed from the through hole P14 (shown in FIG. 2C), and a first circuit layer 130 is formed using photolithography and etching process and plating process. The first circuit layer 130 connects to both of the metal in the through hole P12 and the silicon nanowire cluster 120 in the through hole P14. Referring to FIG. 2E, a carrier plate 50 is disposed on the silicon substrate 110 and bonded to the first circuit layer 130. Referring to FIG. 2F, the silicon substrate 110 is thinned from its bottom side until the metal in the through hole P12 and the silicon nanowire cluster 120 in the through hole P14 are exposed. Referring to FIG. 2G, a second circuit layer 140 is formed on the second surface 114 of the silicon substrate 110. Prior to forming the second circuit layer 140, a patterned silicon dioxide layer L12 can be formed on the second surface 114 of the silicon substrate 110. The silicon dioxide layer L12 is used to prevent the second circuit layer 140 from directly contacting the silicon substrate 110. The second circuit layer 140 connects to the metal in the through hole P12 and the silicon nanowire cluster 120 in the through hole P14. The metal in the through hole P12 is the TSV 160 of FIG. 1. Subsequently, a semiconductor device similar to that of FIG. 1 can be formed by removing the carrier plate 50. If a bump process can be performed prior to removal of the carrier plate 50 to form bumps (not shown). It is noted that methods and materials used in the process described above are merely illustrative rather than limiting.
In the embodiment described above, the nanowire structures formed by chemical etching have rough surfaces which help reduce thermal conductivity and hence increase the thermoelectric figure of merit (ZT value) of the thermoelectric material. The rough surfaces of the nanowire structures can significantly increase the scattering probability of phonons during transmission in the material and reduce the average free path of the phonons, thus significantly reducing the thermal conductivity and increasing the ZT value of the thermoelectric material.
In general, the traditional silicon material has a rather high thermal conductivity which is about 150 W/m-K but has poor electrically conductive characteristics. However, small-scale nanowire structures with wire diameter of 50 nanometers and rough surfaces can have a thermal conductivity as low as 1/100 of that of silicon bulk and a ZT value larger than 0.6. Therefore, the small-scale nanowire structures have the potential to increase the material's electrically conductive performance. Although one single nanowire can be advantageous in thermoelectric performance, there are difficulties and constraints in its practical application. In the embodiment, the chemical etching process is directly performed on the silicon substrate (e.g. silicon wafer) to obtain thermoelectric modules with nanowire clusters. An experimental measurement conducted on a nanowire structure that has not undergone wire diameter uniformity control shows that its thermal conductivity is 55-68 W/m-K which is about ½ of that of the silicon bulk.
In short, using the silicon nanowire clusters of the embodiment can bring the following advantages. Firstly, the silicon nanowire clusters can provide good thermoelectric conversion efficiency. Secondly, the substrate and the silicon nanowire clusters are fabricated from the same silicon substrate and, therefore, the substrate and the silicon nanowire clusters have reduced interface electric resistance and thermal resistance therebetween. In addition, the doping technology for P-type and N-type doping of silicon material is mature and therefore the doping process can be controlled. Besides, by using the electroless chemical etching process to fabricate the nanowire structures, a large quantity of large-area silicon nanowire clusters can be fabricated on the silicon substrate at the same time. Moreover, the fabrication of silicon nanowire clusters is compatible with the TSV fabrication, which can help reduce fabrication cost.
The following gives several exemplary architectures of 3D stacked IC utilizing the technique described above, where those additional elements for each exemplary 3D stacked IC can be arranged and combined in a manner different than described herein depending upon actual requirements.
FIG. 3 illustrates a semiconductor device according to another exemplary embodiment. Referring to FIG. 3, the semiconductor device 200 of this embodiment includes a semiconductor device 100 generally same as the semiconductor device 100 of FIG. 1, a chip 210, an organic substrate 220, and a circuit board 230. The circuit board 230 includes a circuit layer 232. The organic substrate 220 includes circuit layers 222 and 224. The chip 210 includes a circuit layer 212. The first circuit layer 130 of the semiconductor device 100 may be electrically connected to the circuit layer 212 of the chip 210 via a plurality of bumps 240 or other components. The second circuit layer 140 of the semiconductor device 100 is electrically connected to the circuit layer 222 of the organic substrate 220 via a plurality of bumps 240 or other components. The circuit layer 222 of the organic substrate 220 is electrically connected to the circuit layer 224. The circuit layer 224 of the organic substrate 220 is electrically connected to the circuit layer 232 of the circuit board 230 via a plurality of bumps 240 or other components. The silicon nanowire clusters 120 of the semiconductor device 100 of the embodiment can take the heat of the IC units 170 away and dissipate the heat via the circuit layers and bumps. In addition, the silicon nanowire clusters 120 of the semiconductor device 100 of the embodiment can further help dissipate heat of the chip 210. The power needed by the silicon nanowire clusters 120 can be supplied from the circuit board 230.
FIG. 4 illustrates a semiconductor device according to another exemplary embodiment. Referring to FIG. 4, the semiconductor device 300 of the embodiment includes a semiconductor device 100 generally same as the semiconductor device 100 of FIG. 1, a chip 310, an organic substrate 220, a silicon substrate 320, and a circuit board 230. The difference between the semiconductor device 300 of the embodiment and the semiconductor device 200 of FIG. 3 lies in the chip 310 and silicon substrate 320. The chip 310 includes TSVs 312, a circuit layer 314 and a circuit layer 316. The TSVs 312 electrically connect the circuit layer 314 with the circuit layer 316. The silicon substrate 320 includes TSVs 322, a circuit layer 324 and a circuit layer 326. The TSVs 322 electrically connect the circuit layer 324 and the circuit layer 326. The second circuit layer 140 of the semiconductor device 100 is electrically connected to the circuit layer 324 of the silicon substrate 320 via a plurality of bumps 240 or other components. The circuit layer 326 of the silicon substrate 320 is electrically connected to the circuit layer 222 of the organic substrate 220. The circuit layer 222 of the organic substrate 220 is electrically connected to the circuit layer 224. The circuit layer 224 of the organic substrate 220 is electrically connected to the circuit layer 232 of the circuit board 230 via a plurality of bumps 240 and other components.
FIG. 5 illustrates a semiconductor device according to another exemplary embodiment. Referring to FIG. 5, the semiconductor device 400 of the embodiment is similar to the semiconductor device 300 of FIG. 4 except that the circuit layer 324 of the silicon substrate 320 is electrically connected to the circuit layer 222 of the organic substrate 220 via at least one conducting wire 328.
FIG. 6 illustrates a semiconductor device according to another exemplary embodiment. Referring to FIG. 6, the semiconductor device 500 of the embodiment is similar to the semiconductor device 300 of FIG. 4 except that the semiconductor device 500 does not include an organic substrate. The circuit layer 326 of the silicon substrate 320 is electrically connected to the circuit layer 232 of the circuit board 230 via bumps 240 or other components, and an underfill material 510 is filled between the silicon substrate 320 and circuit board 230.
FIG. 7 illustrates a semiconductor device according to another exemplary embodiment. Referring to FIG. 7, the semiconductor device 600 of the embodiment is similar to the semiconductor device 500 of FIG. 6 except that the semiconductor device 600 further includes a heat sink 610. The heat sink 610 is disposed on the chip 310. The silicon nanowire clusters 120 of the semiconductor device 100 take the heat of the IC units 170 away and the heat is further transferred to the heat sink 610 via the TSVs 312 of the chip 310 to enhance heat dissipation efficiency. The heat may be transferred between the heat sink 610 and the TSVs 312 of the chip 312 via the circuit layer 314 and heat conductive members 612. The portion of the circuit layer 314 for heat transfer may be, for example, used to transfer heat and do not transmit electricity or electric signal. The heat conductive members 612 and the bumps 240 may be formed with the same process.
FIG. 8 illustrates a semiconductor device according to still another exemplary embodiment. Referring to FIG. 8, the semiconductor device 700 of the embodiment is similar to the semiconductor device 500 except that one end of the TSV 712 is connected to a redistribution circuit 714 on one side of the silicon substrate 710.
In summary, in the semiconductor device of the exemplary embodiments above, the silicon nanowire clusters for establishing the thermoelectric cooling mechanism are directly formed in the silicon substrate, i.e. directly formed in the chip. Therefore, the hot spot of a single IC or a 3D stacked IC can be cooled. In addition, with the TSVs acting as the power supply paths for the silicon nanowire clusters, the silicon nanowire clusters can be disposed inside the 3D stacked IC without designing additional power supply paths.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (23)

What is claimed is:
1. A semiconductor device comprising:
a first silicon substrate comprising a first surface, a second surface opposite to the first surface, and a plurality of through holes;
a plurality silicon nanowire clusters disposed in the through holes, respectively;
a first circuit layer disposed on the first surface and electrically connected to the silicon nanowire clusters;
a second circuit layer disposed on the second surface and electrically connected to the silicon nanowire clusters;
a circuit board with a third circuit layer, wherein the second circuit layer is electrically connected to the third circuit layer via a plurality of bumps;
an organic substrate, wherein the second circuit layer is electrically connected to the third circuit layer via, sequentially, a part the bumps, the organic substrate, and the other part of the bumps; and
a second silicon substrate comprising at least one conducting wire, wherein the second circuit layer is electrically connected to the third circuit layer via, sequentially, a part the bumps, the conducting wire, the organic substrate, and the other part of the bumps.
2. The semiconductor device according to claim 1, further comprising an insulation filling material filled in the through holes.
3. The semiconductor device according to claim 1, wherein the silicon nanowire clusters are of P-type or N-type.
4. The semiconductor device according to claim 1, further comprising at least one through silicon via defined through the first silicon substrate and electrically connecting the first circuit layer with the second circuit layer.
5. The semiconductor device according to claim 4, wherein the through silicon via is electrically connected to the silicon nanowire clusters.
6. The semiconductor device according to claim 1, further comprising at least one integrated circuit unit and an insulation layer disposed on the first surface, wherein the insulation layer covers the integrated circuit unit, and the first circuit layer is disposed on the insulation layer and electrically connected to the integrated circuit unit.
7. The semiconductor device according to claim 1, further comprising a chip disposed on the first surface of the first silicon substrate and electrically connected to the first circuit layer.
8. The semiconductor device according to claim 7, further comprising a heat sink, wherein the chip is disposed between the first silicon substrate and the heat sink and has at least one through silicon via in thermal contact with the silicon nanowire clusters and heat sink.
9. The semiconductor device according to claim 1, further comprising a heat sink disposed on the first surface of the first silicon substrate and in thermal contact with the silicon nanowire clusters.
10. A semiconductor device comprising:
a first silicon substrate comprising a first surface, a second surface opposite to the first surface, and a plurality of through holes;
a plurality silicon nanowire clusters disposed in the through holes, respectively;
a first circuit layer disposed on the first surface and electrically connected to the silicon nanowire clusters;
a second circuit layer disposed on the second surface and electrically connected to the silicon nanowire clusters;
a chip disposed on the first surface of the first silicon substrate and electrically connected to the first circuit layer; and
a heat sink, wherein the chip is disposed between the first silicon substrate and the heat sink and has at least one through silicon via in thermal contact with the silicon nanowire clusters and heat sink.
11. The semiconductor device according to claim 10, further comprising an insulation filling material filled in the through holes.
12. The semiconductor device according to claim 10, wherein the silicon nanowire clusters are of P-type or N-type.
13. The semiconductor device according to claim 10, further comprising at least one through silicon via defined through the first silicon substrate and electrically connecting the first circuit layer with the second circuit layer.
14. The semiconductor device according to claim 13, wherein the through silicon via is electrically connected to the silicon nanowire clusters.
15. The semiconductor device according to claim 10, further comprising at least one integrated circuit unit and an insulation layer disposed on the first surface, wherein the insulation layer covers the integrated circuit unit, and the first circuit layer is disposed on the insulation layer and electrically connected to the integrated circuit unit.
16. The semiconductor device according to claim 10, further comprising a circuit board with a third circuit layer, wherein the second circuit layer is electrically connected to the third circuit layer.
17. The semiconductor device according to claim 16, wherein the second circuit layer is connected to the third circuit layer via a plurality of bumps.
18. The semiconductor device according to claim 17, further comprising an organic substrate, wherein the second circuit layer is electrically connected to the third circuit layer via, sequentially, a part of the bumps, the organic substrate, and the other part of the bumps.
19. The semiconductor device according to claim 17, further comprising a second silicon substrate, wherein the second circuit board is electrically connected to the third circuit layer via, sequentially, a part of the bumps, the second silicon substrate, and the other part of the bumps.
20. The semiconductor device according to claim 19, wherein the second silicon substrate has at least one through silicon via, and the second circuit layer is electrically connected to the third circuit layer via, sequentially, a part of the bumps, the through silicon via, and the other part of the bumps.
21. The semiconductor device according to claim 19, further comprising an organic substrate, wherein the second circuit layer is electrically connected to the third circuit layer via, sequentially, a part of the bumps, the second silicon substrate, the organic substrate, and the other part of the bumps.
22. The semiconductor device according to claim 21, wherein the second silicon substrate has at least one through silicon via, and the second circuit layer is electrically connected to the third circuit layer via, sequentially, a part of the bumps, the through silicon via, another part of the bumps, the organic substrate, and the other part of the bumps.
23. The semiconductor device according to claim 10, further comprising a heat sink disposed on the first surface of the first silicon substrate and in thermal contact with the silicon nanowire clusters.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140209909A1 (en) * 2012-08-29 2014-07-31 SK Hynix Inc. Semiconductor device
US20150206824A1 (en) * 2014-01-23 2015-07-23 Sandisk Technologies Inc. I/o pin capacitance reduction using tsvs
US10600761B2 (en) 2016-05-05 2020-03-24 Invensas Corporation Nanoscale interconnect array for stacked dies
US12125766B2 (en) 2021-05-06 2024-10-22 Samsung Electronics Co., Ltd. Thermoelectric cooling packages

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10032569B2 (en) * 2009-08-26 2018-07-24 University Of Maryland, College Park Nanodevice arrays for electrical energy storage, capture and management and method for their formation
DE102010029526B4 (en) 2010-05-31 2012-05-24 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Semiconductor device with a stacked chip configuration with an integrated Peltier element
KR101709959B1 (en) * 2010-11-17 2017-02-27 삼성전자주식회사 Bump structure, semiconductor package having the bump structure, and method of manufacturing the semiconductor package
CN103794581B (en) * 2012-10-29 2016-12-21 中芯国际集成电路制造(上海)有限公司 A kind of thermoelectric radiating device
US10156512B2 (en) * 2013-03-01 2018-12-18 Futurewei Technologies, Inc. System and method for measuring thermal reliability of multi-chip modules
WO2014204447A1 (en) * 2013-06-18 2014-12-24 Intel Corporation Integrated thermoelectric cooling
US9625186B2 (en) 2013-08-29 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Cooling system for 3D IC
US9748228B2 (en) * 2013-08-30 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for cooling three-dimensional integrated circuits
US9099427B2 (en) 2013-10-30 2015-08-04 International Business Machines Corporation Thermal energy dissipation using backside thermoelectric devices
CN104950077B (en) * 2014-06-06 2017-10-24 浙江北微信息科技有限公司 nanowire sensor chip preparation method
KR102334301B1 (en) * 2014-07-24 2021-12-02 삼성전자주식회사 Thermoelectric element, method of manufacturing the same and semiconductor device including the same
US9984191B2 (en) 2014-08-29 2018-05-29 Taiwan Semiconductor Manufacturing Company Cell layout and structure
US9368442B1 (en) * 2014-12-28 2016-06-14 Unimicron Technology Corp. Method for manufacturing an interposer, interposer and chip package structure
US9746889B2 (en) * 2015-05-11 2017-08-29 Qualcomm Incorporated Package-on-package (PoP) device comprising bi-directional thermal electric cooler
KR20170019676A (en) * 2015-08-12 2017-02-22 삼성전자주식회사 Fabricating method of a semiconductor device
CN105489587A (en) * 2015-12-02 2016-04-13 苏州旭创科技有限公司 Package structure, package method and optical module
CN106920873A (en) * 2015-12-25 2017-07-04 华为技术有限公司 A kind of thermoelectric refrigerating module, Integrated Light interface chip and communication equipment
US10957626B2 (en) * 2017-12-19 2021-03-23 Thermo Electron Scientific Instruments Llc Sensor device with carbon nanotube sensor positioned on first and second substrates
TWI806218B (en) 2021-11-03 2023-06-21 群光電子股份有限公司 Electronic device and circuit board module thereof

Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050064185A1 (en) 2003-08-04 2005-03-24 Nanosys, Inc. System and process for producing nanowire composites and electronic substrates therefrom
US20050257821A1 (en) 2004-05-19 2005-11-24 Shriram Ramanathan Thermoelectric nano-wire devices
US20060032526A1 (en) 2002-12-13 2006-02-16 Cannon Kabushiki Kaisha Thermoelectric conversion material, thermoelectric conversion device and manufacturing method thereof
US20060048809A1 (en) 2004-09-09 2006-03-09 Onvural O R Thermoelectric devices with controlled current flow and related methods
US7098393B2 (en) 2001-05-18 2006-08-29 California Institute Of Technology Thermoelectric device with multiple, nanometer scale, elements
KR20060098959A (en) 2005-03-09 2006-09-19 삼성전자주식회사 Nanowires and its manufacturing method
US20060266402A1 (en) 2005-05-26 2006-11-30 An-Ping Zhang Thermal transfer and power generation devices and methods of making the same
TWI284395B (en) 2002-12-30 2007-07-21 Advanced Semiconductor Eng Thermal enhance MCM package
US20070182000A1 (en) * 2002-02-19 2007-08-09 Matsushita Electric Industrial Co., Ltd. Module part
US7267859B1 (en) 2001-11-26 2007-09-11 Massachusetts Institute Of Technology Thick porous anodic alumina films and nanowire arrays grown on a solid substrate
US20070235796A1 (en) 2004-09-13 2007-10-11 Samsung Electronics Co., Ltd. P-type doped nanowire and method of fabricating the same
CN101162717A (en) 2006-10-09 2008-04-16 台湾积体电路制造股份有限公司 Stack structure and manufacturing method thereof
US20080178921A1 (en) 2006-08-23 2008-07-31 Qi Laura Ye Thermoelectric nanowire composites
US20090020148A1 (en) 2007-07-20 2009-01-22 Boukai Akram Methods and devices for controlling thermal conductivity and thermoelectric power of semiconductor nanowires
CN101546734A (en) 2008-03-25 2009-09-30 松下电器产业株式会社 Semiconductor element and semiconductor element fabrication method
US20100155698A1 (en) 2000-08-22 2010-06-24 President And Fellows Of Harvard College Nanoscale wires and related devices
TW201025542A (en) 2008-12-30 2010-07-01 Ind Tech Res Inst IC apparatus, system and method for measuring
TW201027698A (en) 2009-01-05 2010-07-16 Taiwan Semiconductor Mfg Semiconductor device and method for forming the same
CN101836285A (en) 2007-08-21 2010-09-15 加州大学评议会 Nanostructures with high-performance thermoelectric properties
US20110056740A1 (en) * 2009-09-09 2011-03-10 Dai Nippon Printing Co., Ltd. Through-hole electrode substrate and manufacturing method thereof
US20110309357A1 (en) * 2010-06-18 2011-12-22 Industrial Technology Research Institute Measuring apparatus
US20120007132A1 (en) * 2010-07-08 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of etch microloading for through silicon vias
US20120098140A1 (en) * 2010-10-26 2012-04-26 International Business Machines Corporation Hybrid bonding techniques for multi-layer semiconductor stacks

Patent Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100155698A1 (en) 2000-08-22 2010-06-24 President And Fellows Of Harvard College Nanoscale wires and related devices
US7098393B2 (en) 2001-05-18 2006-08-29 California Institute Of Technology Thermoelectric device with multiple, nanometer scale, elements
US7267859B1 (en) 2001-11-26 2007-09-11 Massachusetts Institute Of Technology Thick porous anodic alumina films and nanowire arrays grown on a solid substrate
US20070182000A1 (en) * 2002-02-19 2007-08-09 Matsushita Electric Industrial Co., Ltd. Module part
US20060032526A1 (en) 2002-12-13 2006-02-16 Cannon Kabushiki Kaisha Thermoelectric conversion material, thermoelectric conversion device and manufacturing method thereof
TWI284395B (en) 2002-12-30 2007-07-21 Advanced Semiconductor Eng Thermal enhance MCM package
US20050064185A1 (en) 2003-08-04 2005-03-24 Nanosys, Inc. System and process for producing nanowire composites and electronic substrates therefrom
US20050257821A1 (en) 2004-05-19 2005-11-24 Shriram Ramanathan Thermoelectric nano-wire devices
US20060048809A1 (en) 2004-09-09 2006-03-09 Onvural O R Thermoelectric devices with controlled current flow and related methods
US20070235796A1 (en) 2004-09-13 2007-10-11 Samsung Electronics Co., Ltd. P-type doped nanowire and method of fabricating the same
KR20060098959A (en) 2005-03-09 2006-09-19 삼성전자주식회사 Nanowires and its manufacturing method
US20060266402A1 (en) 2005-05-26 2006-11-30 An-Ping Zhang Thermal transfer and power generation devices and methods of making the same
US20080178921A1 (en) 2006-08-23 2008-07-31 Qi Laura Ye Thermoelectric nanowire composites
CN101162717A (en) 2006-10-09 2008-04-16 台湾积体电路制造股份有限公司 Stack structure and manufacturing method thereof
US20090020148A1 (en) 2007-07-20 2009-01-22 Boukai Akram Methods and devices for controlling thermal conductivity and thermoelectric power of semiconductor nanowires
CN101836285A (en) 2007-08-21 2010-09-15 加州大学评议会 Nanostructures with high-performance thermoelectric properties
US20110114145A1 (en) * 2007-08-21 2011-05-19 The Regents Of The University Of California Nanostructures having high performance thermoelectric properties
CN101546734A (en) 2008-03-25 2009-09-30 松下电器产业株式会社 Semiconductor element and semiconductor element fabrication method
TW201025542A (en) 2008-12-30 2010-07-01 Ind Tech Res Inst IC apparatus, system and method for measuring
TW201027698A (en) 2009-01-05 2010-07-16 Taiwan Semiconductor Mfg Semiconductor device and method for forming the same
US20110056740A1 (en) * 2009-09-09 2011-03-10 Dai Nippon Printing Co., Ltd. Through-hole electrode substrate and manufacturing method thereof
US20110309357A1 (en) * 2010-06-18 2011-12-22 Industrial Technology Research Institute Measuring apparatus
US20120007132A1 (en) * 2010-07-08 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of etch microloading for through silicon vias
US20120098140A1 (en) * 2010-10-26 2012-04-26 International Business Machines Corporation Hybrid bonding techniques for multi-layer semiconductor stacks

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
"Office Action of China Counterpart Application", issued on Jan. 6, 2014, p. 1-p. 9.
"Office Action of Taiwan Counterpart Application", issued on Aug. 27, 2013, p. 1-p. 7.
Boukai et al., "Silicon nanowires as efficient thermoelectric materials," Nature letters, Jan. 10, 2008, vol. 451, doi:10-1038/nature06458, pp. 168-171.
Hochbaum et al., "Enhanced thermoelectric performance of rough silicon nanowires," Nature letters, vol. 451, Jan. 10, 2008, doi: 10.1038/nature06381, pp. 163-168.
Hochbaum et al., "Enhanced thermoelectric performance of rough silicon nanowires," NATURE, Jan. 10, 2008, pp. 163-167, vol. 451.
Seo et al., "Fabrication of precisely controlled silicon wire and cone arrays by electrochemical etching," Materials Letters 63, Dec. 14, 2009, pp. 2567-2569.
Zhang et al., "Thermoelectric performance of silicon nanowires," Applied Physics Letters 94, 213108, Aug. 18, 2009, pp. 213108-1-213108-3.
Zhang et al., "Time dependent thermoelectric performance of a bundle of silicon nanowires for on-chip cooler applications," Applied Physics Letters 95, Jan. 19, 2009, pp. 243104-1-243104-3.

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US20150206824A1 (en) * 2014-01-23 2015-07-23 Sandisk Technologies Inc. I/o pin capacitance reduction using tsvs
US9245825B2 (en) * 2014-01-23 2016-01-26 Sandisk Technologies Inc. I/O pin capacitance reduction using TSVS
US9311979B1 (en) 2014-01-23 2016-04-12 Sandisk Technologies Inc. I/O pin capacitance reduction using TSVs
US10600761B2 (en) 2016-05-05 2020-03-24 Invensas Corporation Nanoscale interconnect array for stacked dies
US12125766B2 (en) 2021-05-06 2024-10-22 Samsung Electronics Co., Ltd. Thermoelectric cooling packages

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