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US7790579B2 - Semiconductor storage device, semiconductor device, and manufacturing method therefor - Google Patents

Semiconductor storage device, semiconductor device, and manufacturing method therefor Download PDF

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Publication number
US7790579B2
US7790579B2 US11/398,534 US39853406A US7790579B2 US 7790579 B2 US7790579 B2 US 7790579B2 US 39853406 A US39853406 A US 39853406A US 7790579 B2 US7790579 B2 US 7790579B2
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semiconductor
semiconductor chip
semiconductor substrate
grinding
chip
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US20060180891A1 (en
Inventor
Kohji Kanamori
Teiichirou Nishizaka
Noriaki Kodama
Isao Katayama
Yoshihiro Matsuura
Kaoru Ishihara
Yasushi Harada
Naruaki Minenaga
Chihiro Oshita
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Renesas Electronics Corp
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NEC Electronics Corp
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Publication of US20060180891A1 publication Critical patent/US20060180891A1/en
Priority to US11/956,358 priority patent/US8039940B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/26—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device, and particularly to a thin-film semiconductor chip.
  • Thin chips are also used in the fabrication of an SiP (System in Package) or an MCP (Multi Chip Package), for which a plurality of semiconductor chips are mounted, at high density and in multiple layers, in a single package.
  • SiP System in Package
  • MCP Multi Chip Package
  • a diffusion layer and an electrode are formed on the top surface of a silicon substrate, and while the bottom surface is ground using a grindstone, a crystal defect layer is introduced. Titanium, Monel and silver are deposited, in the named order, on the bottom surface, to form the crystal defect layer and obtain an ohmic electrode.
  • an ohmic electrode is obtained by using a grindstone having a large grain size to intentionally introduce a crystal defect.
  • a semiconductor chip is sealed using a resin, and is attached, at its bottom surface, to an assembly board.
  • a crystal defect layer is deposited on the bottom surface of the semiconductor chip, an ionized contaminant from the assembly board can be prevented from entering the semiconductor chip through its bottom surface.
  • a contaminant that has passed through the resin can not be prevented from entering the semiconductor chip at a side surface.
  • a defect layer for gettering a contaminant is formed on the side surfaces of a semiconductor chip.
  • a defect layer for gettering a contaminant is formed on the bottom surface and the side surfaces of a semiconductor chip.
  • the defect layer is at least deposited on the side surfaces of the semiconductor chip, a contaminant passed through an assembly apparatus or another member can be prevented from entering the semiconductor chip at its side surfaces, or at the bottom and the side surfaces, of the chip.
  • a semiconductor chip can be protected from a contaminant, such as metal ions, during the assembly processing.
  • FIG. 1 is a diagram showing a semiconductor chip according to a first embodiment of the present invention
  • FIGS. 2A and 2B are diagrams showing a method for manufacturing a package that employs the semiconductor chip of the first embodiment
  • FIG. 3 is a diagram showing the continuation of the manufacturing method shown in FIG. 2 ;
  • FIG. 4 is a diagram showing a modification of the first embodiment.
  • FIG. 5 is a diagram showing a semiconductor device according to a second embodiment of the present invention.
  • FIG. 1 is a diagram showing a semiconductor chip according to a first embodiment of the present invention.
  • a crystal defect layer 2 for gettering a contaminant of metal ions, such as copper ions, is deposited on the side and the bottom surfaces of a semiconductor chip 1 .
  • the presence of the crystal defect layer 2 prevents a contaminant from entering the semiconductor chip 1 through its side surfaces and its bottom surface.
  • FIGS. 2A , 2 B and 3 are diagrams showing a method for manufacturing a semiconductor device according to the present invention. The manufacturing method will now be explained.
  • a diffusion layer, a source and gate electrodes and a circuit which are components of a nonvolatile memory cell, are deposited on the top surface of an 800 ⁇ m thick semiconductor substrate 3 made, for example, of silicon.
  • a passivation film 4 made of SiN or SiON, for example, is deposited on the top surface of the resultant substrate 3 . Since a fine nitride film is employed as the passivation film 4 , a heavy element, such as a copper ion, can not pass through it.
  • the bottom surface of the semiconductor substrate 3 is mechanically ground, using a grindstone, until the thickness thereof is, for example, 110 to 120 ⁇ m.
  • a grindstone should be selected that has a grain size large enough to form a crystal defect layer 2 on the bottom surface of the semiconductor substrate 3 .
  • the crystal defect layer 2 is a gettering layer for capturing a contaminant, such as a copper ion.
  • the semiconductor substrate 3 is cut, using a blade cutter or a laser cutter, to separate the semiconductor chip 1 , and the side surfaces of the chip are ground, using the grindstone, to obtain the crystal defect layer 2 for the side surfaces (see FIG. 2B ). It should be noted that so long as a defect layer that can capture a contaminant has already been obtained for the side surfaces of the semiconductor chip 1 when the semiconductor substrate 3 is cut using the blade cutter, the mechanical grinding process may not be performed.
  • a blade used for grinding the bottom surface and a blade used for cutting out the semiconductor chip 1 may have the same sharpness, and a blade #2000, for example, is employed. In this case, the side and the bottom surfaces have about the same roughness. This processing is employed to manufacture the semiconductor chip 1 .
  • the semiconductor chip 1 is mounted on the top surface of an assembly board 6 using mounting tape 11 . Then, a pad 8 on the semiconductor chip 1 and a pad 9 on the assembly board 6 are electrically connected by a wire 10 . And thereafter, a sealing resin 5 is applied to seal the semiconductor chip 1 . Finally, soldering balls 7 are attached to the bottom surface of the assembly board 6 . This processing is employed to obtain a BGA (Ball Grid Array) package.
  • BGA All Grid Array
  • the assembly board 6 is a printed board fabricated by gluing a copper foil to an insulating plate composed of a non-conductive material.
  • the printed wiring for the assembly board 6 is then formed by patterning the copper foil.
  • a solder resist coating is applied to all portions of the top surface of the printed board 6 other than the printed wiring to which the wire 10 is soldered. Since copper is diffused in the solder resist, the copper ions in the solder resist are diffused during the assembly process shown in FIGS. 2 and 3 . According to the invention, however, since the crystal defect layer 2 has been deposited on the bottom surface of the semiconductor chip 1 , the copper ions are captured by the crystal defect layer 2 and are prevented from entering the semiconductor chip 1 .
  • the copper ions are diffused throughout the sealing resin 5 and reach the side surfaces of the semiconductor chip 1 , they are absorbed by the defect layer deposited on the side surfaces of the semiconductor chip 1 and are prevented from entering the semiconductor chip 1 . Further, since the passivation film 4 has been formed on the top surface of the semiconductor chip 1 , the entry of copper ions through the top surface can also be prevented.
  • An example charge storage memory can be a flash memory or a DRAM memory.
  • FIG. 4 is a diagram showing a modification of the first embodiment wherein semiconductor chips of the invention are laminated to constitute an MCP (a Multi Chip Package).
  • This package is an assembly composed of semiconductor chips, such as a flash memory, an SRAM and a DRAM.
  • a semiconductor chip 1 for example, is a flash memory, and a semiconductor chip 12 is a DRAM. It should be noted that mounting tape 11 is not shown in FIG. 4 .
  • FIG. 5 is a diagram showing a semiconductor device according to a second embodiment of the present invention.
  • a semiconductor chip 1 is mounted on an assembly board 6 using a mounting member 12 that contains silver, so that the entire bottom surface of the semiconductor chip 1 is covered with the mounting member 12 .
  • a Schottky barrier is formed between the entire bottom surface of a semiconductor device 3 and the mounting member 12 . And since copper ions are very heavy, so long as the Schottky barrier is present, copper ions from the assembly board 6 can not pass the barrier and enter the semiconductor chip 1 .
  • a manufacturing method used to produce this semiconductor device is as follows.
  • the semiconductor chip 1 is securely mounted on the assembly board 6 by using the silver-containing mounting member 12 , so that the entire bottom surface of the chip 1 is covered with the mounting member 12 . Since the other processes are the same as those in FIGS. 2 and 3 , no further explanation for them will be given.
  • a semiconductor device employing both the first and the second embodiments can also be provided. That is, a semiconductor device is also available wherein a crystal defect layer is deposited on the bottom surface of the semiconductor chip shown in FIG. 5 , and the Schottky barrier is positioned between the defect layer and the assembly board. Furthermore, although in the second embodiment a mounting member containing silver is employed to form the Schottky barrier, so long as a Schottky barrier can be formed, another metal may be employed.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Memories (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a thin-film semiconductor chip.
2. Related Background Art
Currently, as the functions provided for cellular phones, digital AV apparatuses and IC cards continue to be improved, there is a corresponding increase in the need for highly integrated, thin and compact chips that can be mounted in these devices. Thin chips are also used in the fabrication of an SiP (System in Package) or an MCP (Multi Chip Package), for which a plurality of semiconductor chips are mounted, at high density and in multiple layers, in a single package. Hence, to satisfy the demand for thin film semiconductors, the manufacture of thin chips is required.
An example technique whereby the bottom surface of a silicon substrate is ground to obtain a thin semiconductor chip is disclosed in Japanese Patent Laid-Open Publication No. Hei 7-302769.
The following manufacturing method is disclosed in this publication.
A diffusion layer and an electrode are formed on the top surface of a silicon substrate, and while the bottom surface is ground using a grindstone, a crystal defect layer is introduced. Titanium, Monel and silver are deposited, in the named order, on the bottom surface, to form the crystal defect layer and obtain an ohmic electrode. As the objective of this publication, an ohmic electrode is obtained by using a grindstone having a large grain size to intentionally introduce a crystal defect.
Generally, a semiconductor chip is sealed using a resin, and is attached, at its bottom surface, to an assembly board. According to the above described manufacturing method, since a crystal defect layer is deposited on the bottom surface of the semiconductor chip, an ionized contaminant from the assembly board can be prevented from entering the semiconductor chip through its bottom surface. However, a contaminant that has passed through the resin, can not be prevented from entering the semiconductor chip at a side surface.
SUMMARY OF THE INVENTION
It is, therefore, one objective of the present invention to provide means for at least preventing a contaminant from entering a thin-film semiconductor at a side surface and, more preferably, for also preventing the contaminant from entering through the bottom surface of the chip.
For a semiconductor device according to the present invention, a defect layer for gettering a contaminant is formed on the side surfaces of a semiconductor chip.
More preferably, a defect layer for gettering a contaminant is formed on the bottom surface and the side surfaces of a semiconductor chip.
As described above, since the defect layer is at least deposited on the side surfaces of the semiconductor chip, a contaminant passed through an assembly apparatus or another member can be prevented from entering the semiconductor chip at its side surfaces, or at the bottom and the side surfaces, of the chip.
According to the present invention, as described above, a semiconductor chip can be protected from a contaminant, such as metal ions, during the assembly processing.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing a semiconductor chip according to a first embodiment of the present invention;
FIGS. 2A and 2B are diagrams showing a method for manufacturing a package that employs the semiconductor chip of the first embodiment;
FIG. 3 is a diagram showing the continuation of the manufacturing method shown in FIG. 2;
FIG. 4 is a diagram showing a modification of the first embodiment; and
FIG. 5 is a diagram showing a semiconductor device according to a second embodiment of the present invention.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The preferred embodiments of the present invention will now be described in detail while referring to the accompanying drawings, so as to more clearly define the above objective and other objectives, the features and the effects of the present invention.
FIG. 1 is a diagram showing a semiconductor chip according to a first embodiment of the present invention.
A crystal defect layer 2, for gettering a contaminant of metal ions, such as copper ions, is deposited on the side and the bottom surfaces of a semiconductor chip 1.
The presence of the crystal defect layer 2 prevents a contaminant from entering the semiconductor chip 1 through its side surfaces and its bottom surface.
FIGS. 2A, 2B and 3 are diagrams showing a method for manufacturing a semiconductor device according to the present invention. The manufacturing method will now be explained.
As shown in FIG. 2A, a diffusion layer, a source and gate electrodes and a circuit (none of them shown), which are components of a nonvolatile memory cell, are deposited on the top surface of an 800 μm thick semiconductor substrate 3 made, for example, of silicon. Then, a passivation film 4, made of SiN or SiON, for example, is deposited on the top surface of the resultant substrate 3. Since a fine nitride film is employed as the passivation film 4, a heavy element, such as a copper ion, can not pass through it. Next, the bottom surface of the semiconductor substrate 3 is mechanically ground, using a grindstone, until the thickness thereof is, for example, 110 to 120 μm. A grindstone should be selected that has a grain size large enough to form a crystal defect layer 2 on the bottom surface of the semiconductor substrate 3. The crystal defect layer 2 is a gettering layer for capturing a contaminant, such as a copper ion. Thereafter, the semiconductor substrate 3 is cut, using a blade cutter or a laser cutter, to separate the semiconductor chip 1, and the side surfaces of the chip are ground, using the grindstone, to obtain the crystal defect layer 2 for the side surfaces (see FIG. 2B). It should be noted that so long as a defect layer that can capture a contaminant has already been obtained for the side surfaces of the semiconductor chip 1 when the semiconductor substrate 3 is cut using the blade cutter, the mechanical grinding process may not be performed. Further, a blade used for grinding the bottom surface and a blade used for cutting out the semiconductor chip 1 may have the same sharpness, and a blade #2000, for example, is employed. In this case, the side and the bottom surfaces have about the same roughness. This processing is employed to manufacture the semiconductor chip 1.
As is shown in FIG. 3, the semiconductor chip 1 is mounted on the top surface of an assembly board 6 using mounting tape 11. Then, a pad 8 on the semiconductor chip 1 and a pad 9 on the assembly board 6 are electrically connected by a wire 10. And thereafter, a sealing resin 5 is applied to seal the semiconductor chip 1. Finally, soldering balls 7 are attached to the bottom surface of the assembly board 6. This processing is employed to obtain a BGA (Ball Grid Array) package.
The assembly board 6 is a printed board fabricated by gluing a copper foil to an insulating plate composed of a non-conductive material. The printed wiring for the assembly board 6 is then formed by patterning the copper foil. Thereafter a solder resist coating is applied to all portions of the top surface of the printed board 6 other than the printed wiring to which the wire 10 is soldered. Since copper is diffused in the solder resist, the copper ions in the solder resist are diffused during the assembly process shown in FIGS. 2 and 3. According to the invention, however, since the crystal defect layer 2 has been deposited on the bottom surface of the semiconductor chip 1, the copper ions are captured by the crystal defect layer 2 and are prevented from entering the semiconductor chip 1. And although the copper ions are diffused throughout the sealing resin 5 and reach the side surfaces of the semiconductor chip 1, they are absorbed by the defect layer deposited on the side surfaces of the semiconductor chip 1 and are prevented from entering the semiconductor chip 1. Further, since the passivation film 4 has been formed on the top surface of the semiconductor chip 1, the entry of copper ions through the top surface can also be prevented.
According to this embodiment, an explanation has been given for a non-volatile memory; however, the present invention is effective for other charge storage memories. That is, it is possible to prevent the occurrence of a charge storage failure caused by a contaminant, such as copper ions, that deteriorates the charge storage characteristics. An example charge storage memory can be a flash memory or a DRAM memory.
FIG. 4 is a diagram showing a modification of the first embodiment wherein semiconductor chips of the invention are laminated to constitute an MCP (a Multi Chip Package). This package is an assembly composed of semiconductor chips, such as a flash memory, an SRAM and a DRAM. A semiconductor chip 1, for example, is a flash memory, and a semiconductor chip 12 is a DRAM. It should be noted that mounting tape 11 is not shown in FIG. 4.
FIG. 5 is a diagram showing a semiconductor device according to a second embodiment of the present invention.
A semiconductor chip 1 is mounted on an assembly board 6 using a mounting member 12 that contains silver, so that the entire bottom surface of the semiconductor chip 1 is covered with the mounting member 12.
By employing the silver-containing mounting member 12, a Schottky barrier is formed between the entire bottom surface of a semiconductor device 3 and the mounting member 12. And since copper ions are very heavy, so long as the Schottky barrier is present, copper ions from the assembly board 6 can not pass the barrier and enter the semiconductor chip 1.
A manufacturing method used to produce this semiconductor device is as follows.
The semiconductor chip 1 is securely mounted on the assembly board 6 by using the silver-containing mounting member 12, so that the entire bottom surface of the chip 1 is covered with the mounting member 12. Since the other processes are the same as those in FIGS. 2 and 3, no further explanation for them will be given.
The present invention is not limited to these embodiments, and it is obvious that the embodiments can be variously modified within the scope of the technical idea of the invention. For example, a semiconductor device employing both the first and the second embodiments can also be provided. That is, a semiconductor device is also available wherein a crystal defect layer is deposited on the bottom surface of the semiconductor chip shown in FIG. 5, and the Schottky barrier is positioned between the defect layer and the assembly board. Furthermore, although in the second embodiment a mounting member containing silver is employed to form the Schottky barrier, so long as a Schottky barrier can be formed, another metal may be employed.

Claims (9)

1. A semiconductor device manufacturing method comprising the steps of:
forming a semiconductor element on a top surface of a semiconductor substrate;
grinding a bottom surface of the semiconductor substrate;
cutting the semiconductor substrate along sides for a semiconductor chip;
forming a gettering layer on the bottom surface and side surfaces of the semiconductor chip by grinding said semiconductor substrate; and
forming a passivation film on the top surface of said semiconductor chip.
2. The semiconductor device manufacturing method according to claim 1, whereby the gettering layer is deposited on the bottom surface of the semiconductor chip at a step of securing the bottom surface to an assembly board using a metal-containing mounting member, so as to form a Schottky barrier across the entire bottom surface.
3. The method according to claim 1, wherein the grinding is performed using a grindstone that has a grain size large enough to form a crystal defect layer on the bottom surface of the semiconductor substrate.
4. The method according to claim 1, wherein a blade for grinding the bottom surface and a blade for cutting out the semiconductor chip have the same sharpness.
5. The method according to claim 1, wherein said bottom surface and said side surfaces have about a same roughness.
6. A method of forming a semiconductor device comprising the steps of:
forming semiconductor elements on a top surface of a semiconductor substrate;
cutting the semiconductor substrate into at least one semiconductor chip; and
forming a gettering layer on a bottom surface of said chip opposite to said top surface and on side surfaces of said chip by grinding said semiconductor substrate.
7. The method according to claim 6, wherein the grinding is performed using a grindstone that has a grain size large enough to form a crystal defect layer on the bottom surface of the semiconductor substrate.
8. The method according to claim 6, wherein a blade for grinding the bottom surface and a blade for cutting out the semiconductor chip have the same sharpness.
9. The method according to claim 6, wherein said bottom surface and said side surfaces have about a same roughness.
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4759948B2 (en) * 2004-07-28 2011-08-31 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
KR20110050208A (en) * 2009-11-06 2011-05-13 삼성전자주식회사 Stack type semiconductor device having different backside structure chips and electronic apparatus including the same
JP5968713B2 (en) * 2012-07-30 2016-08-10 ルネサスエレクトロニクス株式会社 Semiconductor device
DE102013105729A1 (en) * 2013-06-04 2014-12-04 Infineon Technologies Ag Chip card module and method for producing a chip card module
WO2024135670A1 (en) * 2022-12-20 2024-06-27 先端システム技術研究組合 Semiconductor module

Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4630095A (en) * 1980-03-31 1986-12-16 Vlsi Technology Research Association Packaged semiconductor device structure including getter material for decreasing gas from a protective organic covering
JPH01215032A (en) 1988-02-24 1989-08-29 Hitachi Ltd Semiconductor device and manufacture thereof
JPH025530A (en) 1988-06-24 1990-01-10 Matsushita Electron Corp Gettering for impurity and crystal defect
JPH0427126A (en) 1990-05-22 1992-01-30 Mitsubishi Electric Corp Method of manufacturing semiconductor integrated circuit
US5374842A (en) * 1992-02-21 1994-12-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with a gettering sink material layer
JPH07302769A (en) 1994-04-28 1995-11-14 Shindengen Electric Mfg Co Ltd Method of manufacturing semiconductor device
US5506155A (en) * 1993-06-18 1996-04-09 Rohm Co., Ltd. Method for manufacturing a substrate for semiconductor device using a selective gettering technique
US5539245A (en) * 1991-11-18 1996-07-23 Mitsubishi Materials Silicon Corporation Semiconductor substrate having a gettering layer
CN1152797A (en) 1995-11-08 1997-06-25 富士通株式会社 Elements with resin shell capsulation and making method
US5648682A (en) * 1994-10-15 1997-07-15 Kabushiki Kaisha Toshiba Resin-sealed semiconductor device and lead frame used in a resin-sealed semiconductor device
US5721145A (en) * 1992-09-21 1998-02-24 Mitsubishi Denki Kabushiki Kaisha Method of making a semiconductor substrate having gettering effect
US5894037A (en) * 1995-11-22 1999-04-13 Nec Corporation Silicon semiconductor substrate and method of fabricating the same
US6376335B1 (en) * 2000-02-17 2002-04-23 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process
US20020047213A1 (en) * 2000-09-28 2002-04-25 Mitsuru Komiyama Multi-chip package type semiconductor device
US6492727B2 (en) * 2000-03-03 2002-12-10 Hitachi, Ltd. Semiconductor device
US20030013233A1 (en) * 2001-07-13 2003-01-16 Kazutaka Shibata Semiconductor device and method for manufacturing the same
US20030017682A1 (en) * 2001-07-04 2003-01-23 Kanta Saino Method of manufacturing a semiconductor device
US20030138979A1 (en) * 2000-04-06 2003-07-24 Koveshnikov Sergei V. Method for evaluating impurity concentrations in semiconductor substrates
JP2003224247A (en) 2002-01-29 2003-08-08 Shin Etsu Handotai Co Ltd Soi wafer and its manufacturing method
US20030162386A1 (en) * 2001-01-31 2003-08-28 Tsuyoshi Ogawa Semiconductor device and its manufacturing method
US6717252B2 (en) * 2001-12-28 2004-04-06 Oki Electric Industry Co., Ltd. Semiconductor device
US20050285232A1 (en) * 2004-06-28 2005-12-29 Tongbi Jiang Semiconductor constructions
JP2006041258A (en) * 2004-07-28 2006-02-09 Renesas Technology Corp Semiconductor chip having gettering layer and its manufacturing method

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1182353C2 (en) * 1961-03-29 1973-01-11 Siemens Ag Method for manufacturing a semiconductor component, such as a semiconductor current gate or a surface transistor, with a high-resistance n-zone between two p-zones in the semiconductor body
JPH02106939A (en) * 1988-10-17 1990-04-19 Semiconductor Energy Lab Co Ltd Manufacture of member for electronic device
US5276351A (en) * 1988-10-17 1994-01-04 Semiconductor Energy Laboratory Co., Ltd. Electronic device and a manufacturing method for the same
JPH0574781A (en) * 1991-09-12 1993-03-26 Matsushita Electron Corp Manufacture of semiconductor device
US5274913A (en) * 1991-10-25 1994-01-04 International Business Machines Corporation Method of fabricating a reworkable module
US5496775A (en) * 1992-07-15 1996-03-05 Micron Semiconductor, Inc. Semiconductor device having ball-bonded pads
US5561085A (en) * 1994-12-19 1996-10-01 Martin Marietta Corporation Structure for protecting air bridges on semiconductor chips from damage
JP3387282B2 (en) * 1995-08-03 2003-03-17 日産自動車株式会社 Semiconductor device structure and method of manufacturing the same
US5672546A (en) * 1995-12-04 1997-09-30 General Electric Company Semiconductor interconnect method and structure for high temperature applications
US5888884A (en) * 1998-01-02 1999-03-30 General Electric Company Electronic device pad relocation, precision placement, and packaging in arrays
US6268642B1 (en) * 1999-04-26 2001-07-31 United Microelectronics Corp. Wafer level package
JP2001015000A (en) * 1999-04-26 2001-01-19 Sanyo Electric Co Ltd Manufacture of electronic component, and the electronic component
JP2000353797A (en) * 1999-06-11 2000-12-19 Mitsubishi Electric Corp Semiconductor wafer and manufacture thereof
JP4545956B2 (en) * 2001-01-12 2010-09-15 ローム株式会社 Semiconductor device and manufacturing method thereof
US6791168B1 (en) * 2002-07-10 2004-09-14 Micron Technology, Inc. Semiconductor package with circuit side polymer layer and wafer level fabrication method
JP4225036B2 (en) * 2002-11-20 2009-02-18 日本電気株式会社 Semiconductor package and stacked semiconductor package
JP4554152B2 (en) * 2002-12-19 2010-09-29 株式会社半導体エネルギー研究所 Manufacturing method of semiconductor chip
US7294561B2 (en) * 2003-08-14 2007-11-13 Ibis Technology Corporation Internal gettering in SIMOX SOI silicon substrates
US7169691B2 (en) * 2004-01-29 2007-01-30 Micron Technology, Inc. Method of fabricating wafer-level packaging with sidewall passivation and related apparatus

Patent Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4630095A (en) * 1980-03-31 1986-12-16 Vlsi Technology Research Association Packaged semiconductor device structure including getter material for decreasing gas from a protective organic covering
JPH01215032A (en) 1988-02-24 1989-08-29 Hitachi Ltd Semiconductor device and manufacture thereof
JPH025530A (en) 1988-06-24 1990-01-10 Matsushita Electron Corp Gettering for impurity and crystal defect
JPH0427126A (en) 1990-05-22 1992-01-30 Mitsubishi Electric Corp Method of manufacturing semiconductor integrated circuit
US5539245A (en) * 1991-11-18 1996-07-23 Mitsubishi Materials Silicon Corporation Semiconductor substrate having a gettering layer
US5374842A (en) * 1992-02-21 1994-12-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with a gettering sink material layer
US5721145A (en) * 1992-09-21 1998-02-24 Mitsubishi Denki Kabushiki Kaisha Method of making a semiconductor substrate having gettering effect
US5506155A (en) * 1993-06-18 1996-04-09 Rohm Co., Ltd. Method for manufacturing a substrate for semiconductor device using a selective gettering technique
JPH07302769A (en) 1994-04-28 1995-11-14 Shindengen Electric Mfg Co Ltd Method of manufacturing semiconductor device
US5648682A (en) * 1994-10-15 1997-07-15 Kabushiki Kaisha Toshiba Resin-sealed semiconductor device and lead frame used in a resin-sealed semiconductor device
US6072239A (en) 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
CN1152797A (en) 1995-11-08 1997-06-25 富士通株式会社 Elements with resin shell capsulation and making method
US5894037A (en) * 1995-11-22 1999-04-13 Nec Corporation Silicon semiconductor substrate and method of fabricating the same
US6376335B1 (en) * 2000-02-17 2002-04-23 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process
US6492727B2 (en) * 2000-03-03 2002-12-10 Hitachi, Ltd. Semiconductor device
US20030138979A1 (en) * 2000-04-06 2003-07-24 Koveshnikov Sergei V. Method for evaluating impurity concentrations in semiconductor substrates
US20020047213A1 (en) * 2000-09-28 2002-04-25 Mitsuru Komiyama Multi-chip package type semiconductor device
US20030162386A1 (en) * 2001-01-31 2003-08-28 Tsuyoshi Ogawa Semiconductor device and its manufacturing method
US20030017682A1 (en) * 2001-07-04 2003-01-23 Kanta Saino Method of manufacturing a semiconductor device
US20030013233A1 (en) * 2001-07-13 2003-01-16 Kazutaka Shibata Semiconductor device and method for manufacturing the same
US6717252B2 (en) * 2001-12-28 2004-04-06 Oki Electric Industry Co., Ltd. Semiconductor device
JP2003224247A (en) 2002-01-29 2003-08-08 Shin Etsu Handotai Co Ltd Soi wafer and its manufacturing method
US20050285232A1 (en) * 2004-06-28 2005-12-29 Tongbi Jiang Semiconductor constructions
JP2006041258A (en) * 2004-07-28 2006-02-09 Renesas Technology Corp Semiconductor chip having gettering layer and its manufacturing method

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Computer Translation - JP 2003-224247. *
Japanese Patent Office issued a Japanese Office Action dated Nov. 12, 2009, Application No. 2004070537.

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US7327019B2 (en) 2008-02-05
US20060180891A1 (en) 2006-08-17
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US20080099883A1 (en) 2008-05-01
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