[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

US7522460B2 - Apparatus for controlling column selecting signal of semiconductor memory apparatus and method of controlling the same - Google Patents

Apparatus for controlling column selecting signal of semiconductor memory apparatus and method of controlling the same Download PDF

Info

Publication number
US7522460B2
US7522460B2 US11/589,811 US58981106A US7522460B2 US 7522460 B2 US7522460 B2 US 7522460B2 US 58981106 A US58981106 A US 58981106A US 7522460 B2 US7522460 B2 US 7522460B2
Authority
US
United States
Prior art keywords
column selecting
signal
selecting signal
output
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US11/589,811
Other versions
US20070104013A1 (en
Inventor
Jeong-Woo Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, JEONG-WOO
Publication of US20070104013A1 publication Critical patent/US20070104013A1/en
Priority to US12/400,969 priority Critical patent/US7760583B2/en
Application granted granted Critical
Publication of US7522460B2 publication Critical patent/US7522460B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the present invention relates to a semiconductor memory apparatus, and more particularly, to an apparatus for controlling a column selecting signal of a semiconductor memory apparatus and a method of controlling the same.
  • the operating frequency of a semiconductor memory apparatus has increased so as to write or read a large amount of data more quickly.
  • the semiconductor memory apparatus is now widely used in portable equipment, such as a notebook computer or a PMP (Portable Multimedia Player), where a battery has a predetermined runtime.
  • PMP Portable Multimedia Player
  • a column selecting signal (hereinafter, simply referred to as a “Yi”) is a very important signal that designates timings of data read and data write, which are basic memory operations.
  • the Yi is generated by a column decoder 10 and output to a cell array 20 among a plurality of cell arrays that corresponds to the Yi Further, data write operations and data read operations on corresponding cells are performed during an enable period, that is, the pulse width of the Yi, by a corresponding sense amplifier or the like.
  • the existing semiconductor memory does not generate a Yi when a power voltage level is low, causing data reading and writing errors in the semiconductor memory apparatus.
  • the above-described errors in the Yi generation become worse.
  • Embodiments of the present invention provide an apparatus and method of controlling a column selecting signal of a semiconductor memory apparatus that is capable of generating a normal column selecting signal regardless of a power supply voltage level.
  • an apparatus for controlling a column selecting signal of a semiconductor memory apparatus includes a signal control unit that outputs a second column selecting signal that is generated by controlling an enable period of a first column selecting signal, a voltage detection unit that outputs a detecting signal according to the result of a comparison between an internal voltage and a preset reference voltage, and an output control unit that selectively outputs one of the first column selecting signal or the second column selecting signal according to the detecting signal.
  • a method of controlling a column selecting signal of a semiconductor memory apparatus includes generating a first column selecting signal; generating a second column selecting signal generated by controlling an enable period of the first column selecting signal; determining a level of a voltage that is used to generate the first column selecting signal; and outputting to a corresponding cell array, one of the first column selecting signal or the second column selecting signal, according to the determination result.
  • a method of controlling a column selecting signal of a semiconductor memory apparatus includes generating a first column selecting signal; generating a second column selecting signal generated by controlling an enable period of the first column selecting signal; determining by the voltage detection unit whether an internal voltage level is equal to or greater than a reference voltage level; outputting the first column selecting signal to a corresponding cell array, when it is determined that the internal voltage level is equal to or greater than the reference voltage level; and outputting to the corresponding cell array, the second column selecting signal by the signal control unit, when it is determined that the internal voltage level is less than the reference voltage level.
  • FIG. 1 is a block diagram illustrating the structure of generating a column selecting signal of a semiconductor memory apparatus according to the related art
  • FIG. 2 is a block diagram illustrating the structure of an apparatus for controlling a column selecting signal of a semiconductor memory apparatus according to an embodiment of the present invention
  • FIG. 3 is a circuit diagram illustrating the internal structure of a signal control unit of FIG. 2 ;
  • FIG. 4 is a circuit diagram illustrating the internal structure of a voltage detection unit of FIG. 2 ;
  • FIG. 5 is a circuit diagram illustrating the internal structure of an output control unit of FIG. 2 .
  • the apparatus for controlling a column selecting signal of a semiconductor memory apparatus includes a signal control unit 100 that outputs a second column selecting signal (hereinafter, “E_Yi”), which is generated by increasing an enable period, that is, a pulse width of a first column selecting signal (hereinafter, “Yi”), which is output from a column decoder 10 , a voltage detection unit 200 that detects whether a predetermined voltage VINT(internal voltage) is equal to or greater than a preset reference voltage VREF so as to output a detecting signal DET according to the detection, and an output control unit 300 that selects and outputs one of the YI or the E_Yi that is output from the signal control unit 100 according to the detecting signal DET.
  • E_Yi second column selecting signal
  • Yi a pulse width of a first column selecting signal
  • the signal control unit 100 includes a delay section 110 that delays the Yi for a predetermined time and a logic circuit section 120 that performs an operation on the Yi and the Yi that is delayed by the delay section 110 .
  • a pulse width increment of the Yi is determined according to a delay time of the delay section 110 .
  • the delay section 110 includes a resistor, a capacitor, or a combination of a resistor and a capacitor (not shown).
  • the logic circuit section 120 has a NOR gate 121 so as to perform an OR operation and an inverter 122 that inverts the output of the NOR gate 121 .
  • the voltage detection unit 200 includes a reference voltage generating section 210 that generates a reference voltage VREF by using an external voltage VDD, a comparing section 220 that compares the reference voltage VREF with a predetermined voltage VINT so as to output a detecting signal DET according to the comparison, and a buffering section 230 that buffers an output of the comparing section 220 at a complete logic level.
  • the reference voltage generating section 210 includes at least two resistors R 0 and R 1 that are connected between an external power supply terminal VDD and a ground terminal VSS.
  • the comparing section 220 includes a differential amplifier.
  • the differential amplifier includes a first transistor N 1 that is connected to a ground terminal, second and third transistors P 1 and N 2 that are connected between an. internal power supply terminal VINT and the first transistor N 1 , and fourth and fifth transistors P 2 and N 3 that are provided between an internal power supply terminal VINT and the first transistor N 1 and are connected in parallel with the second and third transistors P 1 and N 2 .
  • gates of the second transistor P 1 and the fourth transistor P 2 are connected in common to the drain of the second transistor P 1 , the gate of the third transistor N 2 is connected to the internal power supply terminal VINT, the gate of the fifth transistor N 3 is connected to the reference voltage VREF, and the detecting signal DET is output from a connection node of the fourth transistor P 2 and the fifth transistor N 3 .
  • the output control unit 300 includes a first switching section 310 that outputs the Yi according to the detecting signal DET and a second switching section 320 that outputs the E_Yi that has been output from the signal control unit 100 according to the detection signal DET.
  • the first switching section 310 includes an inverter 311 that inverts the detecting signal DET, and a pass gate 312 that has an input terminal, which receives the Yi, a first control terminal, which receives the detecting signal DET having been inverted by the inverter 311 , and a second control terminal, which receives the detecting signal DET.
  • the second switching section 320 includes an inverter 321 that inverts the detecting signal DET, and a pass gate 322 that has an input terminal, which receives the E_Yi, a first control terminal, which receives the detecting signal DET, and a second control terminal, which receives the detecting signal DET having been inverted by the inverter 321
  • the signal control unit 100 outputs an E_Yi that is generated by increasing the pulse width of the Yi by a delay time in the delay section 110 .
  • the Yi and the E_Yi are input to the first switching section 310 and the second switching section 320 , respectively, of the output control unit 300 .
  • the reference voltage generating section 210 of the voltage detection unit 200 divides the external voltage VDD by the voltage dividing resistors R 0 and R 1 so as to generate the reference voltage VREF, and inputs the reference voltage VREF to the comparing section 220 .
  • the reference voltage VREF is used to determine whether the external voltage VDD is at a level where the Yi can normally be generated, and the reference voltage VREF is in proportion to the variation of the external voltage VDD.
  • the reference voltage VREF is generated by using a voltage used in Yi generation.
  • the voltage, which is used in the Yi generation is the external voltage VDD, for example.
  • another voltage may be used depending on various reasons, such as operating environments, design changes, changes in element characteristics, or the like. In this case, a corresponding voltage is used to generate the reference voltage VREF.
  • the comparing section 220 of the voltage detection unit 200 compares the predetermined voltage VINT with the reference voltage VREF.
  • the fourth transistor P 2 is turned on, and the detecting signal DET is correspondingly output at a high level.
  • the pass gate 312 of the first switching section 310 of the output control unit 300 is turned off, while the pass gate 322 of the second switching section 320 is turned on.
  • the E_Yi is output to the cell array 20 through the pass gate 322 of the second switching section 320 . That is, when the reference voltage VREF is generated by the external voltage VDD, the reference voltage VREF is less than the predetermined voltage VINT, which means that the external voltage VDD is at such a low voltage level that it may be impossible to normally generate the Yi. Therefore, the E_Yi that is generated by increasing the pulse width of the Yi is output.
  • the comparing section 220 of the voltage detection unit 200 compares the predetermined voltage VINT with the reference voltage VREF.
  • the fifth transistor N 3 is turned on and the detection signal DET is correspondingly output at a low level.
  • the pass gate 312 of the first switching section 310 of the output control unit 300 is turned on, while the pass gate 322 of the second switching section 320 is turned off.
  • the Yi is output to the cell array 20 through the pass gate 312 of the first switching section 310 . That is, when the reference voltage VREF is generated by the external voltage VDD, the reference voltage VREF is greater than the predetermined voltage VINT, which means the external voltage VDD is at a level sufficient to normally generate the Yi. Therefore, the Yi is output in its original state.
  • the apparatus and method of controlling a column selecting signal of a semiconductor memory apparatus can improve the reliability of the memory operation by preventing column selecting signal output errors resulting from the variation in the external voltage, by adjusting column selecting signals according to a level of the external voltage and outputting them.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)

Abstract

An apparatus for controlling a column selecting signal of semiconductor memory apparatus comprising a column decoder that outputs a first column selecting signal, a signal control unit that outputs a second column selecting signal that is generated by controlling an enable period of the first column selecting signal, and an output control unit that outputs the first column selecting signal or the second column selecting signal in response to the input of a predetermined voltage detecting signal.

Description

BACKGROUND
1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to an apparatus for controlling a column selecting signal of a semiconductor memory apparatus and a method of controlling the same.
2. Related Art
In recent years, the operating frequency of a semiconductor memory apparatus has increased so as to write or read a large amount of data more quickly. In addition, unlike when the semiconductor memory apparatus is used regardless of power consumption in a system, such as a desktop where the memory can generally use commercial power, the semiconductor memory apparatus is now widely used in portable equipment, such as a notebook computer or a PMP (Portable Multimedia Player), where a battery has a predetermined runtime.
Therefore, various power supply voltage levels in the memory are reduced so as to realize low power consumption, and the voltage levels of various control signals are correspondingly reduced.
There are various kinds of control signals that are used in the semiconductor memory apparatus. Among the control signals, a column selecting signal (hereinafter, simply referred to as a “Yi”) is a very important signal that designates timings of data read and data write, which are basic memory operations.
According to the related art, as shown in FIG. 1, the Yi is generated by a column decoder 10 and output to a cell array 20 among a plurality of cell arrays that corresponds to the Yi Further, data write operations and data read operations on corresponding cells are performed during an enable period, that is, the pulse width of the Yi, by a corresponding sense amplifier or the like.
However, as described above, the existing semiconductor memory does not generate a Yi when a power voltage level is low, causing data reading and writing errors in the semiconductor memory apparatus. In particular, when the operating frequency increases, the above-described errors in the Yi generation become worse.
SUMMARY
Embodiments of the present invention provide an apparatus and method of controlling a column selecting signal of a semiconductor memory apparatus that is capable of generating a normal column selecting signal regardless of a power supply voltage level.
According to an embodiment of the present invention, an apparatus for controlling a column selecting signal of a semiconductor memory apparatus includes a signal control unit that outputs a second column selecting signal that is generated by controlling an enable period of a first column selecting signal, a voltage detection unit that outputs a detecting signal according to the result of a comparison between an internal voltage and a preset reference voltage, and an output control unit that selectively outputs one of the first column selecting signal or the second column selecting signal according to the detecting signal.
According to another embodiment of the present invention, a method of controlling a column selecting signal of a semiconductor memory apparatus includes generating a first column selecting signal; generating a second column selecting signal generated by controlling an enable period of the first column selecting signal; determining a level of a voltage that is used to generate the first column selecting signal; and outputting to a corresponding cell array, one of the first column selecting signal or the second column selecting signal, according to the determination result.
According to still another embodiment of the present invention, a method of controlling a column selecting signal of a semiconductor memory apparatus, that includes a voltage detection unit and a signal control unit includes generating a first column selecting signal; generating a second column selecting signal generated by controlling an enable period of the first column selecting signal; determining by the voltage detection unit whether an internal voltage level is equal to or greater than a reference voltage level; outputting the first column selecting signal to a corresponding cell array, when it is determined that the internal voltage level is equal to or greater than the reference voltage level; and outputting to the corresponding cell array, the second column selecting signal by the signal control unit, when it is determined that the internal voltage level is less than the reference voltage level.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other features and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
FIG. 1 is a block diagram illustrating the structure of generating a column selecting signal of a semiconductor memory apparatus according to the related art;
FIG. 2 is a block diagram illustrating the structure of an apparatus for controlling a column selecting signal of a semiconductor memory apparatus according to an embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating the internal structure of a signal control unit of FIG. 2;
FIG. 4 is a circuit diagram illustrating the internal structure of a voltage detection unit of FIG. 2; and
FIG. 5 is a circuit diagram illustrating the internal structure of an output control unit of FIG. 2.
 DESCRIPTION OF EXEMPLARY EMBODIMENTS
Hereinafter, a detailed description of an apparatus and method of controlling a column selecting signal in a semiconductor memory apparatus according to an embodiment of the present invention will be described with reference to the accompanying drawings.
As shown in FIG. 2, the apparatus for controlling a column selecting signal of a semiconductor memory apparatus according to an embodiment of the present invention includes a signal control unit 100 that outputs a second column selecting signal (hereinafter, “E_Yi”), which is generated by increasing an enable period, that is, a pulse width of a first column selecting signal (hereinafter, “Yi”), which is output from a column decoder 10, a voltage detection unit 200 that detects whether a predetermined voltage VINT(internal voltage) is equal to or greater than a preset reference voltage VREF so as to output a detecting signal DET according to the detection, and an output control unit 300 that selects and outputs one of the YI or the E_Yi that is output from the signal control unit 100 according to the detecting signal DET.
As shown in FIG. 3, the signal control unit 100 includes a delay section 110 that delays the Yi for a predetermined time and a logic circuit section 120 that performs an operation on the Yi and the Yi that is delayed by the delay section 110. Here, a pulse width increment of the Yi is determined according to a delay time of the delay section 110. Further, the delay section 110 includes a resistor, a capacitor, or a combination of a resistor and a capacitor (not shown). The logic circuit section 120 has a NOR gate 121 so as to perform an OR operation and an inverter 122 that inverts the output of the NOR gate 121.
Turning to FIG. 4, the voltage detection unit 200 includes a reference voltage generating section 210 that generates a reference voltage VREF by using an external voltage VDD, a comparing section 220 that compares the reference voltage VREF with a predetermined voltage VINT so as to output a detecting signal DET according to the comparison, and a buffering section 230 that buffers an output of the comparing section 220 at a complete logic level. Here, the reference voltage generating section 210 includes at least two resistors R0 and R1 that are connected between an external power supply terminal VDD and a ground terminal VSS. The comparing section 220 includes a differential amplifier. At this time, the differential amplifier includes a first transistor N1 that is connected to a ground terminal, second and third transistors P1 and N2 that are connected between an. internal power supply terminal VINT and the first transistor N1, and fourth and fifth transistors P2 and N3 that are provided between an internal power supply terminal VINT and the first transistor N1 and are connected in parallel with the second and third transistors P1 and N2. At this time, gates of the second transistor P1 and the fourth transistor P2 are connected in common to the drain of the second transistor P1, the gate of the third transistor N2 is connected to the internal power supply terminal VINT, the gate of the fifth transistor N3 is connected to the reference voltage VREF, and the detecting signal DET is output from a connection node of the fourth transistor P2 and the fifth transistor N3.
As shown, in FIG. 5, the output control unit 300 includes a first switching section 310 that outputs the Yi according to the detecting signal DET and a second switching section 320 that outputs the E_Yi that has been output from the signal control unit 100 according to the detection signal DET. At this time, the first switching section 310 includes an inverter 311 that inverts the detecting signal DET, and a pass gate 312 that has an input terminal, which receives the Yi, a first control terminal, which receives the detecting signal DET having been inverted by the inverter 311, and a second control terminal, which receives the detecting signal DET. The second switching section 320 includes an inverter 321 that inverts the detecting signal DET, and a pass gate 322 that has an input terminal, which receives the E_Yi, a first control terminal, which receives the detecting signal DET, and a second control terminal, which receives the detecting signal DET having been inverted by the inverter 321
The operation according to the disclosed embodiment of the present invention will be described below.
First, when a Yi is output from the column decoder 10, the signal control unit 100 outputs an E_Yi that is generated by increasing the pulse width of the Yi by a delay time in the delay section 110.
The Yi and the E_Yi are input to the first switching section 310 and the second switching section 320, respectively, of the output control unit 300.
Meanwhile, the reference voltage generating section 210 of the voltage detection unit 200 divides the external voltage VDD by the voltage dividing resistors R0 and R1 so as to generate the reference voltage VREF, and inputs the reference voltage VREF to the comparing section 220.
At this time, the reference voltage VREF is used to determine whether the external voltage VDD is at a level where the Yi can normally be generated, and the reference voltage VREF is in proportion to the variation of the external voltage VDD. The reference voltage VREF is generated by using a voltage used in Yi generation. According to the exemplary embodiment of the present invention, the voltage, which is used in the Yi generation, is the external voltage VDD, for example. However, another voltage may be used depending on various reasons, such as operating environments, design changes, changes in element characteristics, or the like. In this case, a corresponding voltage is used to generate the reference voltage VREF.
Subsequently, the comparing section 220 of the voltage detection unit 200 compares the predetermined voltage VINT with the reference voltage VREF. When the predetermined voltage VINT is greater than the reference voltage VREF, the fourth transistor P2 is turned on, and the detecting signal DET is correspondingly output at a high level.
As the detecting signal DET is output at the high level, the pass gate 312 of the first switching section 310 of the output control unit 300 is turned off, while the pass gate 322 of the second switching section 320 is turned on.
Therefore, the E_Yi is output to the cell array 20 through the pass gate 322 of the second switching section 320. That is, when the reference voltage VREF is generated by the external voltage VDD, the reference voltage VREF is less than the predetermined voltage VINT, which means that the external voltage VDD is at such a low voltage level that it may be impossible to normally generate the Yi. Therefore, the E_Yi that is generated by increasing the pulse width of the Yi is output.
Meanwhile, the comparing section 220 of the voltage detection unit 200 compares the predetermined voltage VINT with the reference voltage VREF. Here, when the reference voltage VREF is greater than the predetermined voltage VINT, the fifth transistor N3 is turned on and the detection signal DET is correspondingly output at a low level. As the detecting signal DET is output at the low level, the pass gate 312 of the first switching section 310 of the output control unit 300 is turned on, while the pass gate 322 of the second switching section 320 is turned off.
Accordingly, the Yi is output to the cell array 20 through the pass gate 312 of the first switching section 310. That is, when the reference voltage VREF is generated by the external voltage VDD, the reference voltage VREF is greater than the predetermined voltage VINT, which means the external voltage VDD is at a level sufficient to normally generate the Yi. Therefore, the Yi is output in its original state.
It will be apparent to those skilled in the art that various modifications and changes may be made without departing from the scope and spirit of the present invention. Therefore, it should be understood that the above embodiments are not limiting, but illustrative in all aspects. The scope of the present invention is defined by the appended claims rather than by the description preceding them, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the claims.
The apparatus and method of controlling a column selecting signal of a semiconductor memory apparatus according to the embodiment of present invention can improve the reliability of the memory operation by preventing column selecting signal output errors resulting from the variation in the external voltage, by adjusting column selecting signals according to a level of the external voltage and outputting them.

Claims (9)

1. An apparatus for controlling a column selecting signal of a semiconductor memory apparatus, comprising:
a column decoder configured to output a first column selecting signal generated by a first voltage;
a signal control unit configured to output a second column selecting signal that is generated by increasing enable period of the first column selecting signal;
a voltage detection unit configured to output a detecting signal according to a result of a comparison between the first voltage and a preset second voltage; and
an output control unit configured to receive the detecting signal and output the first column selecting signal when the first voltage is higher than the second voltage and output the second column selecting signal when the second voltage is higher than the first voltage.
2. The apparatus of claim 1,
wherein the signal control unit includes:
a delay section configured to delay the first column selecting signal for a predetermined delay time; and
a logic circuit section configured to perform operations on the first column selecting signal and the first column selecting signal that is delayed by the delay section.
3. The apparatus of claim 2,
wherein an increment of an enable period of the first column selecting signal is determined by the delay time of the delay section.
4. The apparatus of claim 2,
wherein the delay section includes at least one of a resistor or a capacitor.
5. The apparatus of claim 2,
wherein the logic circuit section performs an OR operation.
6. The apparatus of claim 2,
wherein the logic circuit section includes a NOR gate.
7. The apparatus of claim 1,
wherein the output control unit includes:
a first switching section configured to output the first column selecting signal according to the detecting signal; and
a second switching section configured to output the second column selecting signal that is output from the signal control unit according to the detecting signal.
8. The apparatus of claim 7,
wherein the first switching section includes a pass gate having an input terminal configured to receive the first column selecting signal, and a first control terminal and a second control terminal configured to receive the detecting signal.
9. The apparatus of claim 7,
wherein the second switching section includes a pass gate having an input terminal configured to receive the second column selecting signal output from the signal control unit, and a first control terminal and a second control terminal configured to receive the detecting signal.
US11/589,811 2005-11-09 2006-10-31 Apparatus for controlling column selecting signal of semiconductor memory apparatus and method of controlling the same Expired - Fee Related US7522460B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/400,969 US7760583B2 (en) 2005-11-09 2009-03-10 Apparatus for controlling column selecting signal for semiconductor memory apparatus and method of controlling the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020050107056A KR100656432B1 (en) 2005-11-09 2005-11-09 Apparatus and method for controlling column selecting signal of semiconductor memory
KR10-2005-0107056 2005-11-09

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/400,969 Continuation US7760583B2 (en) 2005-11-09 2009-03-10 Apparatus for controlling column selecting signal for semiconductor memory apparatus and method of controlling the same

Publications (2)

Publication Number Publication Date
US20070104013A1 US20070104013A1 (en) 2007-05-10
US7522460B2 true US7522460B2 (en) 2009-04-21

Family

ID=37732946

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/589,811 Expired - Fee Related US7522460B2 (en) 2005-11-09 2006-10-31 Apparatus for controlling column selecting signal of semiconductor memory apparatus and method of controlling the same
US12/400,969 Expired - Fee Related US7760583B2 (en) 2005-11-09 2009-03-10 Apparatus for controlling column selecting signal for semiconductor memory apparatus and method of controlling the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/400,969 Expired - Fee Related US7760583B2 (en) 2005-11-09 2009-03-10 Apparatus for controlling column selecting signal for semiconductor memory apparatus and method of controlling the same

Country Status (3)

Country Link
US (2) US7522460B2 (en)
JP (2) JP2007134034A (en)
KR (1) KR100656432B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090175093A1 (en) * 2005-11-09 2009-07-09 Hynix Semiconductor Inc. Apparatus for controlling column selecting signal for semiconductor memory apparatus and method of controlling the same
US20130106482A1 (en) * 2011-10-26 2013-05-02 Hynix Semiconductor Inc. Signal delay circuit

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100929651B1 (en) 2007-04-02 2009-12-03 주식회사 하이닉스반도체 Semiconductor memory device
KR100852002B1 (en) 2007-05-14 2008-08-13 주식회사 하이닉스반도체 Circuit for controlling pulse width of column selection signal of semiconductor memory apparatus
KR100924347B1 (en) * 2008-01-03 2009-10-30 주식회사 하이닉스반도체 Apparatus for controlling column select signal and method thereof
US8107308B2 (en) 2009-01-13 2012-01-31 Samsung Electronics Co., Ltd. Semiconductor memory device
US8228100B2 (en) * 2010-01-26 2012-07-24 Freescale Semiconductor, Inc. Data processing system having brown-out detection circuit
TWI715093B (en) * 2019-07-01 2021-01-01 修平學校財團法人修平科技大學 Static random access memory with fast write speed
TWI709962B (en) * 2019-09-27 2020-11-11 修平學校財團法人修平科技大學 Seven-transistor dual port static random access memory with improved access speed

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608674A (en) * 1994-04-20 1997-03-04 Kabushiki Kaisha Toshiba Semiconductor memory device
US5777945A (en) 1996-07-01 1998-07-07 Lg Semicon Co., Ltd. Column decoding circuit for semiconductor memory device
US5982703A (en) 1997-12-31 1999-11-09 Hyundai Electronics Industries Co., Ltd. Super high-speed sequential column decoder
US6055210A (en) * 1998-09-28 2000-04-25 Mitsubishi Denki Kabushiki Kaisha Synchronous type semiconductor memory device
US6104659A (en) * 1998-07-16 2000-08-15 Fujitsu Limited Memory device
US6208580B1 (en) 1998-12-24 2001-03-27 Nec Corporation Semiconductor storage device including column pre-decoder circuit for preventing multiple selection of bit lines
US6335885B1 (en) * 2000-09-22 2002-01-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a delay circuit for adjusting the timing of control signals
US20050140969A1 (en) 2003-12-30 2005-06-30 Hynix Semiconductor Inc. Semiconductor memory device for reducing current consumption in operation

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05182461A (en) * 1992-01-07 1993-07-23 Nec Corp Semiconductor memory device
JPH10302467A (en) * 1997-04-22 1998-11-13 Hitachi Ltd Semiconductor integrated circuit device
KR100277848B1 (en) * 1997-12-27 2001-01-15 김영환 Semiconductor memory device
JP3727165B2 (en) * 1998-04-13 2005-12-14 Ｎｅｃエレクトロニクス株式会社 Pulse generation circuit and pulse generation method
JP2001035195A (en) * 1999-07-19 2001-02-09 Nec Ic Microcomput Syst Ltd Semiconductor memory
JP2002208282A (en) * 2001-01-09 2002-07-26 Matsushita Electric Ind Co Ltd Semiconductor memory
JP4632114B2 (en) * 2003-11-25 2011-02-16 エルピーダメモリ株式会社 Semiconductor integrated circuit device
KR100656432B1 (en) * 2005-11-09 2006-12-11 주식회사 하이닉스반도체 Apparatus and method for controlling column selecting signal of semiconductor memory

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608674A (en) * 1994-04-20 1997-03-04 Kabushiki Kaisha Toshiba Semiconductor memory device
US5777945A (en) 1996-07-01 1998-07-07 Lg Semicon Co., Ltd. Column decoding circuit for semiconductor memory device
US5982703A (en) 1997-12-31 1999-11-09 Hyundai Electronics Industries Co., Ltd. Super high-speed sequential column decoder
US6104659A (en) * 1998-07-16 2000-08-15 Fujitsu Limited Memory device
US6055210A (en) * 1998-09-28 2000-04-25 Mitsubishi Denki Kabushiki Kaisha Synchronous type semiconductor memory device
US6208580B1 (en) 1998-12-24 2001-03-27 Nec Corporation Semiconductor storage device including column pre-decoder circuit for preventing multiple selection of bit lines
US6335885B1 (en) * 2000-09-22 2002-01-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a delay circuit for adjusting the timing of control signals
US20050140969A1 (en) 2003-12-30 2005-06-30 Hynix Semiconductor Inc. Semiconductor memory device for reducing current consumption in operation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090175093A1 (en) * 2005-11-09 2009-07-09 Hynix Semiconductor Inc. Apparatus for controlling column selecting signal for semiconductor memory apparatus and method of controlling the same
US7760583B2 (en) * 2005-11-09 2010-07-20 Hynix Semiconductor Inc. Apparatus for controlling column selecting signal for semiconductor memory apparatus and method of controlling the same
US20130106482A1 (en) * 2011-10-26 2013-05-02 Hynix Semiconductor Inc. Signal delay circuit
US8692601B2 (en) * 2011-10-26 2014-04-08 SK Hynix Inc. Signal delay circuit

Also Published As

Publication number Publication date
US20070104013A1 (en) 2007-05-10
JP2012133887A (en) 2012-07-12
US20090175093A1 (en) 2009-07-09
KR100656432B1 (en) 2006-12-11
US7760583B2 (en) 2010-07-20
JP2007134034A (en) 2007-05-31

Similar Documents

Publication Publication Date Title
US7760583B2 (en) Apparatus for controlling column selecting signal for semiconductor memory apparatus and method of controlling the same
US8351292B2 (en) Semiconductor device and data processing system
US7254074B2 (en) Open digit line array architecture for a memory array
US7675350B2 (en) VPP voltage generator for generating stable VPP voltage
US7787317B2 (en) Memory circuit and tracking circuit thereof
US7633822B2 (en) Circuit and method for controlling sense amplifier of a semiconductor memory apparatus
US10825487B2 (en) Apparatuses and methods for generating a voltage in a memory
US10985753B2 (en) Apparatuses and methods for providing bias signals in a semiconductor device
US9299397B2 (en) Reducing the power consumption of memory devices utilizing data transition detection
US6958638B2 (en) Slew rate controlling method and system for output data
US7885124B2 (en) Semiconductor storage device
US20120218019A1 (en) Internal voltage generating circuit and testing method of integrated circuit using the same
US6717444B2 (en) Low power latch sense amplifier
US7543210B2 (en) Semiconductor device and test system thereof
US7034572B2 (en) Voltage level shifting circuit and method
US10373655B2 (en) Apparatuses and methods for providing bias signals according to operation modes as supply voltages vary in a semiconductor device
US9001610B2 (en) Semiconductor device generating internal voltage
US6262931B1 (en) Semiconductor memory device having voltage down convertor reducing current consumption
US20020081789A1 (en) Sense amplifier circuit for semiconductor device
US7868650B2 (en) Termination control circuit and method for global input/output line
US5578942A (en) Super VCC detection circuit
KR100245555B1 (en) Semiconductor memory device and circuit of suppling internal power voltage thereof
JP2011023462A (en) Semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, JEONG-WOO;REEL/FRAME:018485/0633

Effective date: 20061017

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20170421