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US6621097B2 - Integrated semiconductor superlattice optical modulator - Google Patents

Integrated semiconductor superlattice optical modulator Download PDF

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Publication number
US6621097B2
US6621097B2 US10/246,992 US24699202A US6621097B2 US 6621097 B2 US6621097 B2 US 6621097B2 US 24699202 A US24699202 A US 24699202A US 6621097 B2 US6621097 B2 US 6621097B2
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superlattice structure
optical beam
semiconductor substrate
superlattice
silicon
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US20030015737A1 (en
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Dmitri E. Nikonov
Mario J. Paniccia
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Intel Corp
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Intel Corp
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00Nanooptics, e.g. quantum optics or photonic crystals
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/015Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
    • G02F1/025Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/015Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
    • G02F1/017Structures with periodic or quasi periodic potential variation, e.g. superlattices, quantum wells
    • G02F1/01708Structures with periodic or quasi periodic potential variation, e.g. superlattices, quantum wells in an optical wavequide structure
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T24/00Buckles, buttons, clasps, etc.
    • Y10T24/40Buckles
    • Y10T24/4051Garment shielded

Definitions

  • the present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor optical modulators.
  • Optical waves have carrier frequencies on the order of 10 14 Hz and hence can be modulated at frequencies higher than radio-frequency waves and microwaves. Such high-frequency modulation allows an optical wave to have a high bandwidth for transmitting information such as an optic fiber link in a communication system. Optical transmission also offers immunity to electromagnetic interference, cross talk and other adverse effects suffered by electrical transmission. Further, information carried by an optical wave may be processed optically to achieve a high processing speed and parallel processing in certain applications, such as imaging through a lens system. Moreover, optical materials may be used for high-density data storage such as holographic memories. Therefore, data transmission and processing through optical waves can provide significant advantages in various aspects over their electronic counterparts.
  • optical systems and devices have limitations. This is in part because many optical technologies are still in their infancy and in part because the inherent characteristics of the optical waves and respective devices restrict their use in many applications.
  • electronic processors may be used to process the information in the electrical domain. The electronic data is then converted into optical signals for transmission over a high-speed optical link.
  • One important area for many hybrid optoelectronic systems or devices is in electronic-to-optical interfacing devices that convert electronic signals into optical signals. This conversion can be achieved by using electrically controlled optical modulators to modulate at least one parameter of an optical wave, such as the amplitude, phase, frequency, or a combination of these parameters.
  • Optical signal switches may also be based on optical modulators. Since many electronic circuits are integrated on silicon wafers, it is often desirable to use photosensitive semiconductors to construct the optical modulators in compact form and integrate them onto silicon wafers.
  • III-V elements such as GaAs and InP. It can be technically difficult to grow these materials on a silicon wafer due to their lattice mismatch.
  • One way to integrate discrete components of different semiconductor materials uses an interconnect such as an indium bump. Such integration can be limited in several aspects. It adds extra size. It can also have an increased parasitic effect.
  • a disclosed semiconductor device includes a substrate of a semiconductor material configured to have an integrated circuit element that defines a first area and a second area that are at different electrical potentials.
  • a superlattice structure is formed in the integrated circuit element relative to the first and second areas to have alternating layers formed of the semiconductor material and insulator layers formed of another material.
  • the semiconductor layers and insulator layers are configured to cause direct bandgap absorption of radiation energy in the semiconductor layers to modulate a radiation beam that passes through the superlattice structure in response to a potential difference between the first and second areas. Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.
  • FIG. 1 illustrates one embodiment of a silicon superlattice optical modulator formed in a MOSFET structure on a silicon substrate, where the layers of the superlattice in the substrate stack in a vertical direction. Light propagates vertically that is perpendicular to the substrate surfaces.
  • FIG. 2 illustrates another embodiment of a silicon superlattice optical modulator formed in a MOSFET structure on a silicon substrate, where the layers of the superlattice in the substrate stack in a horizontal direction. Light propagates horizontally that is parallel to the substrate surfaces.
  • FIG. 3 shows several horizontal silicon superlattice modulators of FIG. 2 formed in the optical path of a beam within a substrate to increase the modulation depth.
  • the present disclosure provides a semiconductor device that has an optical modulator formed of a semiconductor superlattice integrated on a substrate of a semiconductor material.
  • An integrated circuit element is formed on the substrate to define a first area and a second area that are at different electrical potentials.
  • the superlattice structure is formed in or proximate to the integrated circuit element between said first and second areas to have alternating semiconductor and insulator layers.
  • the charge layers are formed in the semiconductor layers of the superlattice due to the difference of potentials.
  • the insulator layers are formed of a material different from that of the substrate.
  • the semiconductor layers and insulator layers are configured to cause a change in the band structure of the semiconductor such that an indirect-bandgap material (such as bulk silicon) turns into a direct-bandgap material.
  • the integrated circuit element may be a transistor that is commonly used in integrated circuits. Any of the four terminals of the transistor (e.g. the gate, the source, the drain and the substrate) may be used as the first and second areas to provide the potential difference across the superlattice.
  • One embodiment of the devices and techniques presented below are in part based on the recognition that it is desirable to use silicon as the photo-sensitive material to modulate an optical wave in order to avoid the difficulty of integrating an optical modulator based on a non-silicon semiconductor onto a silicon wafer.
  • Silicon is photosensitive and can be used to modulate light.
  • silicon has an indirect bandgap structure. The probability of absorbing photons to excite electrons from the valence band to the conduction band is lower when compared to that of direct bandgap semiconductors such as III-V compounds.
  • One embodiment of the present invention is also based on the recognition that the indirect bandgap structure of silicon can be converted into a direct bandgap structure by forming a silicon superlattice.
  • This silicon superlattice includes alternating thin layers of silicon and another material. The strain between two different layers can change the indirect bandgap into a direct bandgap. This modification increases the probability of light absorption by carrier excitation.
  • An optical modulator can use this silicon superlattice to modulate light with a greater modulation depth than an indirect bandgap silicon modulator.
  • the silicon superlattice modulator can be integrated with other integrated circuits on the same silicon wafer.
  • FIG. 1 shows one embodiment of an optical modulator 100 including a silicon superlattice optical modulator structure 120 formed in a silicon semiconductor substrate 110 .
  • the silicon substrate 110 has a front side 112 surface and a back side 114 surface.
  • circuitry of the integrated circuit die is located towards the front side 112 of the integrated circuit die.
  • a vertical silicon superlattice structure 120 is formed in a region of the substrate 110 by alternating thin layers of silicon 122 and insulator layers 124 of a different material.
  • layers 122 and 124 are substantially parallel to the front side 112 .
  • Each silicon layer 122 is sandwiched between two insulator layers 124 .
  • the outermost layers of the super lattice structure 120 are insulator layers 124 .
  • the transistor gate oxide layer 125 is positioned above the front side 112 surface and the silicon charge layer 122 immediately adjacent to the layer 125 is coplanar with the front side 112 surface.
  • insulator layers 124 may be formed of a semiconductor compound having silicon such as silicon oxide (e.g., SiO 2 ), silicon nitride, or a silicon compound having both oxygen and nitrogen.
  • silicon oxide e.g., SiO 2
  • silicon nitride silicon nitride
  • silicon compound having both oxygen and nitrogen The properties of layers 122 and 124 are configured so that the bandgap in the silicon layers 122 turns into a direct bandgap.
  • the superlattice in one embodiment is grown such as to cause stress in the semiconductor material.
  • the Gamma-valley of the conduction band of silicon decreases its energy and the X-valley increases its energy. Therefore, for sufficiently thin layers of silicon, the bandgap turns to a direct one (in the ⁇ -valley).
  • the interaction of light causes electron transitions between the ⁇ -valley of the valence band and the X-valley of the conduction band, which are phonon-assisted.
  • the transitions are between the Gamma valleys, which do not require a phonon, and therefore are much more probable.
  • the silicon superlattice structure 120 is designed to fit into a common structure associated with standard circuit fabrication, such as for example a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • FIG. 1 An n-channel MOSFET is shown in FIG. 1 as an example. If a p-channel MOSFET were to be used, the types of dopants in the device would be reversed.
  • the silicon substrate 110 and the silicon layers 122 are p-doped. Two n-doped doped regions 130 and 132 are formed adjacent to the region where the superlattice structure 120 is located.
  • the transistor gate oxide layer 125 is adjacent to the superlattice structure 120 .
  • An optically transparent gate electrode 140 is formed over the layer 125 to supply a desired electrical potential.
  • conducting materials such as doped polysilicon can be used to construct the gate electrode 140 .
  • an n-doped polysilicon layer may be used.
  • the optical modulator 100 further includes a conducting reflective layer 150 formed over the transparent gate electrode 140 to supply the potential and to reflect optical beam 160 .
  • Conducting materials such as metals and silicon compound with a metal element (e.g., TiSi and CoSi) may be used.
  • optical beam may be reflected by another reflective layer in the integrated circuit die such as for example a conductor disposed behind gate 140 in an insulating or dielectric isolation layer of the integrated circuit die.
  • the doped regions 130 and 132 are kept at a common electrical potential (e.g., grounded at approximately 0 V) that is different from the potential of the gate electrode 140 .
  • This configuration provides a desired potential difference on the superlattice structure 120 to create a charge and electric field distribution in layers 122 .
  • a normal n-MOSFET uses the regions 130 and 132 as its source and drain.
  • only one of the doped regions 130 and 132 may be used along with the gate electrode 140 to apply a desired electrical potential difference on the superlattice structure 120 .
  • the elements in the optical modulator 100 are fabricated in a similar way to a known MOSFET except for the silicon superlattice structure 120 .
  • the substrate 110 may be first prepared to form all of the alternating superlattice layers 122 and 124 of the superlattice structure 120 except the transistor gate oxide layer 125 . This can be done by, e.g., molecular beam epitaxy or chemical vapor deposition or the like. Then standard MOS fabrication steps can be used to complete the top gate insulator layer 125 and the rest of the optical modulator 100 .
  • This aspect of the optical modulator 100 is useful for the integration of such optical modulators into integrated circuits, because it in general does not require any special processing steps unique to the optical modulator 100 beyond standard MOS processing steps. Therefore, other circuits such as for example driver circuitry for the optical modulator 100 can be fabricated with the MOS processing on the same substrate.
  • an input radiation or optical beam 160 is directed into the optical modulator 100 through the back side 114 surface.
  • its frequency should be chosen such that it is smaller or approximately equal to the frequency of the transition across the bandgap (to avoid strong absorption due to interband transitions) and, at the same time, not too small (to avoid absorption in intraband transitions which increases at smaller frequencies). This range is around the minimum of absorption in the semiconductor material.
  • optical beam 160 propagates through the substrate 110 , the silicon superlattice structure 120 , and the transparent gate 140 to reach the reflector 150 .
  • the reflector 150 directs the beam back to the superlattice structure 120 for the second time before it exits through the back side 114 as a modulated output beam 162 .
  • the potential difference applied to the superlattice structure 120 is modulated in response to a signal on the integrated circuit to change the charge carrier density and the electric field in the layers 122 . This causes the absorption coefficient and the index of refraction of the layers 122 to change. Therefore, the input beam 160 is modulated in response to the signal on the integrated circuit die. Such modulation may be used to transfer electronic data onto the modulated optical beam 162 .
  • a modulation depth of about 5% to 10% can be achieved with a few layers 122 and 124 in the superlattice 120 . Higher modulation depth may be achieved by increasing the number of layers 122 and 124 .
  • An alternative implementation of the above optical modulator 100 is to replace the transparent gate electrode 140 and the conducting reflector 150 by a single optically-reflective gate electrode.
  • FIG. 2 shows one alternative embodiment of an optical modulator 200 of a silicon superlattice optical modulator where the layers of a superlattice 201 are oriented substantially perpendicular to the substrate front side 112 and back side 114 .
  • this horizontal superlattice 201 may be formed by, e.g., ion implantation or the like.
  • the potentials to the gate 140 and the doped region 132 are the same, e.g., at 0 V, and the potential at the doped region 130 is set to produce a desired voltage across the superlattice 201 .
  • layers 125 , 140 , and 150 of the gate structure may be eliminated since the two doped regions 130 and 132 can provide the electrical voltage to the superlattice 201 .
  • two reflectors 210 and 220 may be formed in the substrate 110 on both sides of the superlattice 201 so that an input optical beam 230 entering through the back side 114 can be reflected by the reflector 210 to pass through superlattice 201 and can be further reflected by the reflector 220 toward the back side 114 to exit the modulator 200 as a modulated output beam 240 .
  • two reflectors 210 and 220 may be optical diffraction gratings formed in the substrate 110 .
  • Interfaces with a material having a refractive index less than silicon may also constructed to reflect the beam based on the total internal reflection, such as for example the surfaces of oxide isolating integrated circuits from one another. Such interfaces may be angled with respect to the front side 112 surface so that the a beam propagating within the substrate 110 either substantially parallel to or perpendicular to the substrate surface has an incident angle to the interfaces greater than the critical angle for the total internal reflection.
  • the number of superlattice layers in the horizontal superlattice modulator 200 can be increased to increase the modulation depth.
  • two or more horizontal superlattice structures 201 may be formed within the same substrate in an optical path to increase the modulation depth.
  • FIG. 3 shows one embodiment of an integrated silicon optical modulator 300 having a linear array of a plurality of horizontal superlattice structures 310 , 320 , and 330 in the same substrate 110 .
  • Four doped regions 341 , 342 , 343 , and 344 are formed to provide an electrical bias to the three superlattice structures 310 , 320 , and 330 .
  • the doped region 342 is a shared region located between the superlattice structures 310 and 320 .
  • the doped regions 320 and 330 share the doped region 343 .
  • doped regions 341 and 343 may be at a common potential while regions 342 and 344 may be set at another common potential.
  • two reflectors 210 and 220 are formed at either end of the superlattice linear array so that an input beam is directed to pass all three superlattice structures 310 , 320 , and 330 .

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Abstract

Apparatuses and methods for modulating an optical signal that include a superlattice structure. The superlattice structure is designed to convert the indirect bandgap structure of silicon into a direct bandgap structure to achieve more efficient optical absorption. The apparatus can be fabricated based on a structure of a circuit element by using standard fabrication processes for silicon integrated circuits such as metal oxide semiconductor processing.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional of U.S. patent application Ser. No. 09/435,057 filed Oct. 25, 1999 now U.S. Pat. No. 6,501,092.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor optical modulators.
2. Background Information
Optical waves have carrier frequencies on the order of 1014 Hz and hence can be modulated at frequencies higher than radio-frequency waves and microwaves. Such high-frequency modulation allows an optical wave to have a high bandwidth for transmitting information such as an optic fiber link in a communication system. Optical transmission also offers immunity to electromagnetic interference, cross talk and other adverse effects suffered by electrical transmission. Further, information carried by an optical wave may be processed optically to achieve a high processing speed and parallel processing in certain applications, such as imaging through a lens system. Moreover, optical materials may be used for high-density data storage such as holographic memories. Therefore, data transmission and processing through optical waves can provide significant advantages in various aspects over their electronic counterparts.
However, current optical systems and devices have limitations. This is in part because many optical technologies are still in their infancy and in part because the inherent characteristics of the optical waves and respective devices restrict their use in many applications. As a result, there has been an effort in integrating certain optical systems and devices with electronic systems and devices to form hybrid optoelectronic systems and devices so as to take the advantages of both optical and electronic sides and to avoid their respective shortcomings. For example, electronic processors may be used to process the information in the electrical domain. The electronic data is then converted into optical signals for transmission over a high-speed optical link.
One important area for many hybrid optoelectronic systems or devices is in electronic-to-optical interfacing devices that convert electronic signals into optical signals. This conversion can be achieved by using electrically controlled optical modulators to modulate at least one parameter of an optical wave, such as the amplitude, phase, frequency, or a combination of these parameters.
Optical signal switches may also be based on optical modulators. Since many electronic circuits are integrated on silicon wafers, it is often desirable to use photosensitive semiconductors to construct the optical modulators in compact form and integrate them onto silicon wafers.
Many highly photosensitive semiconductor materials are compounds made from III-V elements, such as GaAs and InP. It can be technically difficult to grow these materials on a silicon wafer due to their lattice mismatch. One way to integrate discrete components of different semiconductor materials uses an interconnect such as an indium bump. Such integration can be limited in several aspects. It adds extra size. It can also have an increased parasitic effect.
SUMMARY OF THE INVENTION
An apparatus and method for a radiation beam modulator are disclosed. In one embodiment, a disclosed semiconductor device includes a substrate of a semiconductor material configured to have an integrated circuit element that defines a first area and a second area that are at different electrical potentials. A superlattice structure is formed in the integrated circuit element relative to the first and second areas to have alternating layers formed of the semiconductor material and insulator layers formed of another material. The semiconductor layers and insulator layers are configured to cause direct bandgap absorption of radiation energy in the semiconductor layers to modulate a radiation beam that passes through the superlattice structure in response to a potential difference between the first and second areas. Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example and not limitation in the accompanying figures.
FIG. 1 illustrates one embodiment of a silicon superlattice optical modulator formed in a MOSFET structure on a silicon substrate, where the layers of the superlattice in the substrate stack in a vertical direction. Light propagates vertically that is perpendicular to the substrate surfaces.
FIG. 2 illustrates another embodiment of a silicon superlattice optical modulator formed in a MOSFET structure on a silicon substrate, where the layers of the superlattice in the substrate stack in a horizontal direction. Light propagates horizontally that is parallel to the substrate surfaces.
FIG. 3 shows several horizontal silicon superlattice modulators of FIG. 2 formed in the optical path of a beam within a substrate to increase the modulation depth.
DETAILED DESCRIPTION
A method and an apparatus providing an optical or radiation modulator is disclosed. In the following description numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.
The present disclosure provides a semiconductor device that has an optical modulator formed of a semiconductor superlattice integrated on a substrate of a semiconductor material. An integrated circuit element is formed on the substrate to define a first area and a second area that are at different electrical potentials. The superlattice structure is formed in or proximate to the integrated circuit element between said first and second areas to have alternating semiconductor and insulator layers. The charge layers are formed in the semiconductor layers of the superlattice due to the difference of potentials. The insulator layers are formed of a material different from that of the substrate. The semiconductor layers and insulator layers are configured to cause a change in the band structure of the semiconductor such that an indirect-bandgap material (such as bulk silicon) turns into a direct-bandgap material. Interaction of light with electrons in the states across the direct bandgap provides a stronger modulation of a radiation beam in response to a potential difference between the first and second areas. In one embodiment, the integrated circuit element may be a transistor that is commonly used in integrated circuits. Any of the four terminals of the transistor (e.g. the gate, the source, the drain and the substrate) may be used as the first and second areas to provide the potential difference across the superlattice.
One embodiment of the devices and techniques presented below are in part based on the recognition that it is desirable to use silicon as the photo-sensitive material to modulate an optical wave in order to avoid the difficulty of integrating an optical modulator based on a non-silicon semiconductor onto a silicon wafer. Silicon is photosensitive and can be used to modulate light. However, silicon has an indirect bandgap structure. The probability of absorbing photons to excite electrons from the valence band to the conduction band is lower when compared to that of direct bandgap semiconductors such as III-V compounds.
One embodiment of the present invention is also based on the recognition that the indirect bandgap structure of silicon can be converted into a direct bandgap structure by forming a silicon superlattice. This silicon superlattice includes alternating thin layers of silicon and another material. The strain between two different layers can change the indirect bandgap into a direct bandgap. This modification increases the probability of light absorption by carrier excitation. An optical modulator can use this silicon superlattice to modulate light with a greater modulation depth than an indirect bandgap silicon modulator. In addition, the silicon superlattice modulator can be integrated with other integrated circuits on the same silicon wafer.
Further, it is recognized that it is desirable to construct a silicon superlattice optical modulator based on a circuit element that is commonly used in integrated circuits formed on a silicon wafer. This integrates the fabrication of one embodiment of the presently described optical modulator with the standard fabrication processes for integrated circuits. Hence, processing steps unique for fabricating the optical modulator are reduced.
FIG. 1 shows one embodiment of an optical modulator 100 including a silicon superlattice optical modulator structure 120 formed in a silicon semiconductor substrate 110. The silicon substrate 110 has a front side 112 surface and a back side 114 surface. In one embodiment, circuitry of the integrated circuit die is located towards the front side 112 of the integrated circuit die. A vertical silicon superlattice structure 120 is formed in a region of the substrate 110 by alternating thin layers of silicon 122 and insulator layers 124 of a different material. In one embodiment, layers 122 and 124 are substantially parallel to the front side 112. Each silicon layer 122 is sandwiched between two insulator layers 124. In one embodiment, the outermost layers of the super lattice structure 120 are insulator layers 124. The transistor gate oxide layer 125 is positioned above the front side 112 surface and the silicon charge layer 122 immediately adjacent to the layer 125 is coplanar with the front side 112 surface.
In one embodiment, insulator layers 124 may be formed of a semiconductor compound having silicon such as silicon oxide (e.g., SiO2), silicon nitride, or a silicon compound having both oxygen and nitrogen. The properties of layers 122 and 124 are configured so that the bandgap in the silicon layers 122 turns into a direct bandgap. For this, the superlattice in one embodiment is grown such as to cause stress in the semiconductor material. As can be appreciated to those having skill in the art, under strain, the Gamma-valley of the conduction band of silicon decreases its energy and the X-valley increases its energy. Therefore, for sufficiently thin layers of silicon, the bandgap turns to a direct one (in the Γ-valley). In an indirect-bandgap semiconductor, the interaction of light causes electron transitions between the Γ-valley of the valence band and the X-valley of the conduction band, which are phonon-assisted. In a direct bandgap semiconductor, the transitions are between the Gamma valleys, which do not require a phonon, and therefore are much more probable.
The silicon superlattice structure 120 is designed to fit into a common structure associated with standard circuit fabrication, such as for example a metal-oxide-semiconductor field-effect transistor (MOSFET). An n-channel MOSFET is shown in FIG. 1 as an example. If a p-channel MOSFET were to be used, the types of dopants in the device would be reversed. The silicon substrate 110 and the silicon layers 122 are p-doped. Two n-doped doped regions 130 and 132 are formed adjacent to the region where the superlattice structure 120 is located. The transistor gate oxide layer 125 is adjacent to the superlattice structure 120. An optically transparent gate electrode 140 is formed over the layer 125 to supply a desired electrical potential. In one embodiment, conducting materials such as doped polysilicon can be used to construct the gate electrode 140. For the n-MOSFET as shown, an n-doped polysilicon layer may be used. In one embodiment, the optical modulator 100 further includes a conducting reflective layer 150 formed over the transparent gate electrode 140 to supply the potential and to reflect optical beam 160. Conducting materials such as metals and silicon compound with a metal element (e.g., TiSi and CoSi) may be used. In another embodiment, optical beam may be reflected by another reflective layer in the integrated circuit die such as for example a conductor disposed behind gate 140 in an insulating or dielectric isolation layer of the integrated circuit die.
In one embodiment, the doped regions 130 and 132 are kept at a common electrical potential (e.g., grounded at approximately 0 V) that is different from the potential of the gate electrode 140. This configuration provides a desired potential difference on the superlattice structure 120 to create a charge and electric field distribution in layers 122. In comparison, a normal n-MOSFET uses the regions 130 and 132 as its source and drain. In another embodiment, only one of the doped regions 130 and 132 may be used along with the gate electrode 140 to apply a desired electrical potential difference on the superlattice structure 120.
Hence, the elements in the optical modulator 100 are fabricated in a similar way to a known MOSFET except for the silicon superlattice structure 120. The substrate 110 may be first prepared to form all of the alternating superlattice layers 122 and 124 of the superlattice structure 120 except the transistor gate oxide layer 125. This can be done by, e.g., molecular beam epitaxy or chemical vapor deposition or the like. Then standard MOS fabrication steps can be used to complete the top gate insulator layer 125 and the rest of the optical modulator 100. This aspect of the optical modulator 100 is useful for the integration of such optical modulators into integrated circuits, because it in general does not require any special processing steps unique to the optical modulator 100 beyond standard MOS processing steps. Therefore, other circuits such as for example driver circuitry for the optical modulator 100 can be fabricated with the MOS processing on the same substrate.
In operation, an input radiation or optical beam 160 is directed into the optical modulator 100 through the back side 114 surface. In order to transmit the optical beam 160 through the substrate 110, its frequency should be chosen such that it is smaller or approximately equal to the frequency of the transition across the bandgap (to avoid strong absorption due to interband transitions) and, at the same time, not too small (to avoid absorption in intraband transitions which increases at smaller frequencies). This range is around the minimum of absorption in the semiconductor material.
In one embodiment, optical beam 160 propagates through the substrate 110, the silicon superlattice structure 120, and the transparent gate 140 to reach the reflector 150. The reflector 150 directs the beam back to the superlattice structure 120 for the second time before it exits through the back side 114 as a modulated output beam 162. In one embodiment, the potential difference applied to the superlattice structure 120 is modulated in response to a signal on the integrated circuit to change the charge carrier density and the electric field in the layers 122. This causes the absorption coefficient and the index of refraction of the layers 122 to change. Therefore, the input beam 160 is modulated in response to the signal on the integrated circuit die. Such modulation may be used to transfer electronic data onto the modulated optical beam 162.
A modulation depth of about 5% to 10% can be achieved with a few layers 122 and 124 in the superlattice 120. Higher modulation depth may be achieved by increasing the number of layers 122 and 124.
An alternative implementation of the above optical modulator 100 is to replace the transparent gate electrode 140 and the conducting reflector 150 by a single optically-reflective gate electrode.
FIG. 2 shows one alternative embodiment of an optical modulator 200 of a silicon superlattice optical modulator where the layers of a superlattice 201 are oriented substantially perpendicular to the substrate front side 112 and back side 114. In one embodiment, this horizontal superlattice 201 may be formed by, e.g., ion implantation or the like. In one embodiment, the potentials to the gate 140 and the doped region 132 are the same, e.g., at 0 V, and the potential at the doped region 130 is set to produce a desired voltage across the superlattice 201. In another embodiment, layers 125, 140, and 150 of the gate structure may be eliminated since the two doped regions 130 and 132 can provide the electrical voltage to the superlattice 201.
In one embodiment, two reflectors 210 and 220 may be formed in the substrate 110 on both sides of the superlattice 201 so that an input optical beam 230 entering through the back side 114 can be reflected by the reflector 210 to pass through superlattice 201 and can be further reflected by the reflector 220 toward the back side 114 to exit the modulator 200 as a modulated output beam 240. In one embodiment two reflectors 210 and 220 may be optical diffraction gratings formed in the substrate 110. Interfaces with a material having a refractive index less than silicon may also constructed to reflect the beam based on the total internal reflection, such as for example the surfaces of oxide isolating integrated circuits from one another. Such interfaces may be angled with respect to the front side 112 surface so that the a beam propagating within the substrate 110 either substantially parallel to or perpendicular to the substrate surface has an incident angle to the interfaces greater than the critical angle for the total internal reflection.
Similar to the vertical superlattice modulator 100 of FIG. 1, the number of superlattice layers in the horizontal superlattice modulator 200 can be increased to increase the modulation depth. In addition, two or more horizontal superlattice structures 201 may be formed within the same substrate in an optical path to increase the modulation depth.
FIG. 3 shows one embodiment of an integrated silicon optical modulator 300 having a linear array of a plurality of horizontal superlattice structures 310, 320, and 330 in the same substrate 110. Four doped regions 341, 342, 343, and 344 are formed to provide an electrical bias to the three superlattice structures 310, 320, and 330. The doped region 342 is a shared region located between the superlattice structures 310 and 320. Similarly, the doped regions 320 and 330 share the doped region 343. In one embodiment, doped regions 341 and 343 may be at a common potential while regions 342 and 344 may be set at another common potential. In one embodiment, two reflectors 210 and 220 are formed at either end of the superlattice linear array so that an input beam is directed to pass all three superlattice structures 310, 320, and 330.
In the foregoing detailed description, the method and apparatus of the present invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present invention. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.

Claims (10)

What is claimed is:
1. A method for modulating an optical beam, comprising:
directing the optical beam through a back side of a semiconductor substrate of an integrated circuit die, the semiconductor substrate having a front side and the back side, the optical beam directed through a superlattice structure disposed in the semiconductor substrate, the superlattice structure having alternating layers formed of the semiconductor substrate and insulator layers;
directing the optical beam back out the through the back side of the semiconductor substrate; and
modulating a potential difference across the alternating layers of the superlattice structure in response to a signal on the integrated circuit die.
2. The method of claim 1 further comprising:
directing the optical beam through a second superlattice structure disposed in the semiconductor substrate, the second superlattice structure having alternating layers formed of the semiconductor substrate and insulator layers; and
modulating a potential difference across the alternating layers of the second superlattice structure in response to the signal on the integrated circuit die.
3. The method of claim 1 wherein directing the optical beam back out the through the back side of the semiconductor substrate comprises deflecting the optical beam through the superlattice structure such that the optical beam passes through the superlattice structure at least twice before exiting the semiconductor substrate through the back side.
4. The method of claim 1 further comprising deflecting the optical beam prior to directing the optical beam through the superlattice structure.
5. The method of claim 1 wherein modulating the potential difference across the alternating layers of the superlattice structure comprises modulating a potential difference between any two of a transistor gate, drain, source and substrate of integrated circuit die proximate to the superlattice structure.
6. An apparatus for modulating an optical beam, comprising:
means for directing the optical beam through a back side of a semiconductor substrate of an integrated circuit die, the semiconductor substrate having a front side and the back side, the optical beam directed through a superlattice structure disposed in the semiconductor substrate, the superlattice structure having alternating layers formed of the semiconductor substrate and insulator layers;
means for directing the optical beam back out the through the back side of the semiconductor substrate; and
means for modulating a potential difference across the alternating layers of the superlattice structure in response to a signal on the integrated circuit die.
7. The apparatus of claim 6 further comprising:
means for directing the optical beam through a second superlattice structure disposed in the semiconductor substrate, the second superlattice structure having alternating layers formed of the semiconductor substrate and insulator layers; and
means for modulating a potential difference across the alternating layers of the second superlattice structure in response to the signal on the integrated circuit die.
8. The apparatus of claim 6 wherein the means for directing the optical beam further comprises means for deflecting the optical beam through the superlattice structure such that the optical beam passes through the superlattice structure at least twice before exiting the semiconductor substrate through the back side.
9. The apparatus of claim 6 further comprising means for deflecting the optical beam prior to directing the optical beam through the superlattice structure.
10. The apparatus of claim 6 wherein the means for modulating the potential difference further comprises means for modulating a potential difference between any two of a transistor gate, drain, source and substrate of integrated circuit die proximate to the superlattice structure.
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Cited By (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040208445A1 (en) * 1999-03-03 2004-10-21 Rj Mears Llc Optical filter device with aperiodically arranged grating elements
US6830964B1 (en) 2003-06-26 2004-12-14 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US6833294B1 (en) 2003-06-26 2004-12-21 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US20040266116A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Methods of fabricating semiconductor structures having improved conductivity effective mass
US20050032260A1 (en) * 2003-06-26 2005-02-10 Rj Mears, Llc Method for making an intetgrated circuit comprising a waveguide having an energy band engineered superlattice
US20050170590A1 (en) * 2003-06-26 2005-08-04 Rj Mears, Llc. Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US20050167649A1 (en) * 2003-06-26 2005-08-04 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US20050167653A1 (en) * 2003-06-26 2005-08-04 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US20050170591A1 (en) * 2003-06-26 2005-08-04 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US20050279991A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Semiconductor device including a superlattice having at least one group of substantially undoped layers
US20050282330A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
US20060011905A1 (en) * 2003-06-26 2006-01-19 Rj Mears, Llc Semiconductor device comprising a superlattice dielectric interface layer
US20060019454A1 (en) * 2003-06-26 2006-01-26 Rj Mears, Llc Method for making a semiconductor device comprising a superlattice dielectric interface layer
US20060202189A1 (en) * 2003-06-26 2006-09-14 Rj Mears, Llc Semiconductor device including a memory cell with a negative differential resistance (ndr) device
US20060220118A1 (en) * 2003-06-26 2006-10-05 Rj Mears, Llc Semiconductor device including a dopant blocking superlattice
US20060226502A1 (en) * 2003-06-26 2006-10-12 Rj Mears, Llc Microelectromechanical Systems (MEMS) Device Including a Superlattice
US7123792B1 (en) 1999-03-05 2006-10-17 Rj Mears, Llc Configurable aperiodic grating device
US20060231857A1 (en) * 2003-06-26 2006-10-19 Rj Mears, Llc Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device
US20060243964A1 (en) * 2003-06-26 2006-11-02 Rj Mears, Llc Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US20060261327A1 (en) * 2003-06-26 2006-11-23 Rj Mears, Llc Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US20060270169A1 (en) * 2003-06-26 2006-11-30 Rj Mears, Llc Method for Making a Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
US20060267130A1 (en) * 2003-06-26 2006-11-30 Rj Mears, Llc Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
US20060273299A1 (en) * 2003-06-26 2006-12-07 Rj Mears, Llc Method for making a semiconductor device including a dopant blocking superlattice
US7153763B2 (en) 2003-06-26 2006-12-26 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US20060289049A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
US20060292889A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc FINFET Including a Superlattice
US20060292818A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
US20060292765A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a FINFET Including a Superlattice
US20070007508A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US20070012909A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US20070012999A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-On Resistance
US20070012912A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US20070012911A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-On Resistance
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US20070063186A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
US20070063185A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Semiconductor device including a front side strained superlattice layer and a back side stress layer
US20070161138A1 (en) * 2005-12-22 2007-07-12 Rj Mears, Llc Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US20070158640A1 (en) * 2005-12-22 2007-07-12 Rj Mears, Llc Electronic device including a poled superlattice having a net electrical dipole moment
US20070197006A1 (en) * 2006-02-21 2007-08-23 Rj Mears, Llc Method for making a semiconductor device comprising a lattice matching layer
US20080179588A1 (en) * 2007-01-25 2008-07-31 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US20080197340A1 (en) * 2007-02-16 2008-08-21 Rj Mears, Llc Multiple-wavelength opto-electronic device including a superlattice
US20080197341A1 (en) * 2007-02-16 2008-08-21 Rj Mears, Llc Method for making a multiple-wavelength opto-electronic device including a superlattice
US20080258134A1 (en) * 2007-04-23 2008-10-23 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (sti) regions with maskless superlattice deposition following sti formation and related structures
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US9275996B2 (en) 2013-11-22 2016-03-01 Mears Technologies, Inc. Vertical semiconductor devices including superlattice punch through stop layer and related methods
US9406753B2 (en) 2013-11-22 2016-08-02 Atomera Incorporated Semiconductor devices including superlattice depletion layer stack and related methods
US9558939B1 (en) 2016-01-15 2017-01-31 Atomera Incorporated Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source
US9716147B2 (en) 2014-06-09 2017-07-25 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US9721790B2 (en) 2015-06-02 2017-08-01 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9899479B2 (en) 2015-05-15 2018-02-20 Atomera Incorporated Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6587605B2 (en) * 1999-01-06 2003-07-01 Intel Corporation Method and apparatus for providing optical interconnection
US6512385B1 (en) 1999-07-26 2003-01-28 Paul Pfaff Method for testing a device under test including the interference of two beams
US7501023B2 (en) * 2001-07-06 2009-03-10 Technologies And Devices, International, Inc. Method and apparatus for fabricating crack-free Group III nitride semiconductor materials
US9952161B2 (en) 2001-12-06 2018-04-24 Attofemto, Inc. Methods for obtaining and analyzing digital interferometric data for computer testing and developing semiconductor and anisotropic devices and materials
US8462350B2 (en) 2001-12-06 2013-06-11 Attofemto, Inc. Optically enhanced holographic interferometric testing methods for the development and evaluation of semiconductor devices, materials, wafers, and for monitoring all phases of development and manufacture
US7733499B2 (en) 2001-12-06 2010-06-08 Attofemto, Inc. Method for optically testing semiconductor devices
NL1023376C2 (en) * 2003-05-09 2004-11-15 Lionix B V Thin layer and method for manufacturing a thin layer.
US20050251175A1 (en) * 2004-05-07 2005-11-10 Ethicon Endo-Surgery, Inc. Anchors for use in attachment of bladder tissues to pelvic floor tissues following a prostatectomy
EP1774575A2 (en) * 2004-05-17 2007-04-18 Cambrios Technology Corp. Biofabrication of transistors including field effect transistors
US7638852B2 (en) 2006-05-09 2009-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making wafer structure for backside illuminated color image sensor
US7656000B2 (en) * 2007-05-24 2010-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Photodetector for backside-illuminated sensor
US7999342B2 (en) * 2007-09-24 2011-08-16 Taiwan Semiconductor Manufacturing Company, Ltd Image sensor element for backside-illuminated sensor
US8233798B2 (en) * 2007-09-25 2012-07-31 Levinson Frank H Parallel transmission of data streams in a star-configured network
KR101467237B1 (en) * 2013-07-01 2014-12-01 성균관대학교산학협력단 Semiconductor device having superlattice-structured thin film laminated by semiconducting thin film and insulating thin film
US9507180B2 (en) 2013-11-04 2016-11-29 Futurewei Technologies, Inc. Patterned poly silicon structure as top electric contact to MOS-type optical modulators

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055887A (en) * 1986-10-08 1991-10-08 Semiconductor Energy Laboratory Co., Ltd. Fet with a super lattice channel
US6060723A (en) * 1997-07-18 2000-05-09 Hitachi, Ltd. Controllable conduction device
WO2002061498A1 (en) * 2001-01-30 2002-08-08 3Dv Systems, Ltd. Optical modulator

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4865427A (en) 1981-01-12 1989-09-12 Massachusetts Institute Of Technology Spatial light modulator
EP0063626B1 (en) 1981-04-28 1985-07-17 International Business Machines Corporation Bus arrangement for interconnectiong circuit chips
US5159700A (en) 1984-01-16 1992-10-27 Texas Instruments Incorporated Substrate with optical communication systems between chips mounted thereon and monolithic integration of optical I/O on silicon substrates
US4695120A (en) 1985-09-26 1987-09-22 The United States Of America As Represented By The Secretary Of The Army Optic-coupled integrated circuits
US4758092A (en) 1986-03-04 1988-07-19 Stanford University Method and means for optical detection of charge density modulation in a semiconductor
US4761620A (en) 1986-12-03 1988-08-02 American Telephone And Telegraph Company, At&T Bell Laboratories Optical reading of quantum well device
FR2622706B1 (en) 1987-11-03 1992-01-17 Thomson Csf DYNAMIC OPTICAL INTERCONNECTION DEVICE FOR INTEGRATED CIRCUITS
EP0335104A3 (en) 1988-03-31 1991-11-06 Siemens Aktiengesellschaft Arrangement to optically couple one or a plurality of optical senders to one or a plurality of optical receivers of one or a plurality of integrated circuits
DE3834335A1 (en) 1988-10-08 1990-04-12 Telefunken Systemtechnik SEMICONDUCTOR CIRCUIT
EP0430041B1 (en) * 1989-11-22 1996-02-07 Daido Tokushuko Kabushiki Kaisha Light-emitting diode having light reflecting layer
US5198684A (en) 1990-08-15 1993-03-30 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device with optical transmit-receive means
US5061027A (en) 1990-09-04 1991-10-29 Motorola, Inc. Solder-bump attached optical interconnect structure utilizing holographic elements and method of making same
US5153770A (en) 1991-06-27 1992-10-06 Xerox Corporation Total internal reflection electro-optic modulator
US5625636A (en) 1991-10-11 1997-04-29 Bryan; Robert P. Integration of photoactive and electroactive components with vertical cavity surface emitting lasers
US5237434A (en) 1991-11-05 1993-08-17 Mcnc Microelectronic module having optical and electrical interconnects
US5276748A (en) 1991-11-22 1994-01-04 Texas Instruments Incorporated Vertically-coupled arrow modulators or switches on silicon
JP2830591B2 (en) 1992-03-12 1998-12-02 日本電気株式会社 Semiconductor optical function device
US5432630A (en) 1992-09-11 1995-07-11 Motorola, Inc. Optical bus with optical transceiver modules and method of manufacture
EP0600267B1 (en) 1992-12-03 1998-01-28 Siemens Aktiengesellschaft Optical bidirectional transmit/receive module
JP3244205B2 (en) 1993-06-17 2002-01-07 信越半導体株式会社 Semiconductor device
US6728113B1 (en) 1993-06-24 2004-04-27 Polychip, Inc. Method and apparatus for non-conductively interconnecting integrated circuits
JP3586293B2 (en) * 1994-07-11 2004-11-10 ソニー株式会社 Semiconductor light emitting device
DE4440976A1 (en) 1994-11-17 1996-05-23 Ant Nachrichtentech Optical transmitter and receiver with a surface emitting laser
US5605856A (en) 1995-03-14 1997-02-25 University Of North Carolina Method for designing an electronic integrated circuit with optical inputs and outputs
US5568574A (en) 1995-06-12 1996-10-22 University Of Southern California Modulator-based photonic chip-to-chip interconnections for dense three-dimensional multichip module integration
US5835646A (en) 1995-09-19 1998-11-10 Fujitsu Limited Active optical circuit sheet or active optical circuit board, active optical connector and optical MCM, process for fabricating optical waveguide, and devices obtained thereby
US5872360A (en) 1996-12-12 1999-02-16 Intel Corporation Method and apparatus using an infrared laser based optical probe for measuring electric fields directly from active regions in an integrated circuit
US5864642A (en) 1997-02-10 1999-01-26 Motorola, Inc. Electro-optic device board
US6154475A (en) * 1997-12-04 2000-11-28 The United States Of America As Represented By The Secretary Of The Air Force Silicon-based strain-symmetrized GE-SI quantum lasers

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055887A (en) * 1986-10-08 1991-10-08 Semiconductor Energy Laboratory Co., Ltd. Fet with a super lattice channel
US6060723A (en) * 1997-07-18 2000-05-09 Hitachi, Ltd. Controllable conduction device
US6211531B1 (en) * 1997-07-18 2001-04-03 Hitachi, Ltd. Controllable conduction device
WO2002061498A1 (en) * 2001-01-30 2002-08-08 3Dv Systems, Ltd. Optical modulator

Cited By (127)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040208445A1 (en) * 1999-03-03 2004-10-21 Rj Mears Llc Optical filter device with aperiodically arranged grating elements
US6993222B2 (en) 1999-03-05 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
US7123792B1 (en) 1999-03-05 2006-10-17 Rj Mears, Llc Configurable aperiodic grating device
US20070007508A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US20060270169A1 (en) * 2003-06-26 2006-11-30 Rj Mears, Llc Method for Making a Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US20040262595A1 (en) * 2003-06-26 2004-12-30 Rj Mears Llc Semiconductor device including band-engineered superlattice
US20040266045A1 (en) * 2003-06-26 2004-12-30 Rj Mears Llc. Method for making semiconductor device including band-engineered superlattice
US20040262597A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice
US20040261695A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc. Method for making semiconductor device including band-engineered superlattice
US20040262596A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc. Semiconductor device including band-engineered superlattice
US20050032260A1 (en) * 2003-06-26 2005-02-10 Rj Mears, Llc Method for making an intetgrated circuit comprising a waveguide having an energy band engineered superlattice
US20050029511A1 (en) * 2003-06-26 2005-02-10 Rj Mears, Llc Integrated circuit comprising an active optical device having an energy band engineered superlattice
US20050031247A1 (en) * 2003-06-26 2005-02-10 Rj Mears, Llc Integrated circuit comprising a waveguide having an energy band engineered superlattice
US20050029509A1 (en) * 2003-06-26 2005-02-10 Rj Mears, Llc Electronic device comprising active optical devices with an energy band engineered superlattice
US20050032247A1 (en) * 2003-06-26 2005-02-10 Rj Mears, Llp Method for making an integrated circuit comprising an active optical device having an energy band engineered superlattice
US20050029510A1 (en) * 2003-06-26 2005-02-10 Rj Mears, Llc Method for making electronic device comprising active optical devices with an energy band engineered superlattice
US6878576B1 (en) 2003-06-26 2005-04-12 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US20050090048A1 (en) * 2003-06-26 2005-04-28 Rj Mears, Llc Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US20050087737A1 (en) * 2003-06-26 2005-04-28 Rj Mears, Llc Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US20050087738A1 (en) * 2003-06-26 2005-04-28 R.J. Mears Llc Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
US20050087736A1 (en) * 2003-06-26 2005-04-28 Rj Mears, Llc. Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
US6891188B2 (en) 2003-06-26 2005-05-10 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US6897472B2 (en) 2003-06-26 2005-05-24 Rj Mears, Llc Semiconductor device including MOSFET having band-engineered superlattice
US20050110003A1 (en) * 2003-06-26 2005-05-26 Rj Mears, Llc Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions
US20050170590A1 (en) * 2003-06-26 2005-08-04 Rj Mears, Llc. Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US20050167649A1 (en) * 2003-06-26 2005-08-04 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US20050167653A1 (en) * 2003-06-26 2005-08-04 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US20050170591A1 (en) * 2003-06-26 2005-08-04 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US6927413B2 (en) 2003-06-26 2005-08-09 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US20050173696A1 (en) * 2003-06-26 2005-08-11 Rj Mears, Llc Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
US20050173697A1 (en) * 2003-06-26 2005-08-11 Rj Mears, Llc Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
US20050184286A1 (en) * 2003-06-26 2005-08-25 Rj Mears, Llc, State Of Incorporation: Delaware Semiconductor device including mosfet having band-engineered superlattice
US6952018B2 (en) 2003-06-26 2005-10-04 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US6958486B2 (en) 2003-06-26 2005-10-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US20050279991A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Semiconductor device including a superlattice having at least one group of substantially undoped layers
US20050282330A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
US20060011905A1 (en) * 2003-06-26 2006-01-19 Rj Mears, Llc Semiconductor device comprising a superlattice dielectric interface layer
US20060019454A1 (en) * 2003-06-26 2006-01-26 Rj Mears, Llc Method for making a semiconductor device comprising a superlattice dielectric interface layer
US20040266046A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7018900B2 (en) 2003-06-26 2006-03-28 Rj Mears, Llc Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US7034329B2 (en) 2003-06-26 2006-04-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
US7033437B2 (en) 2003-06-26 2006-04-25 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7071119B2 (en) 2003-06-26 2006-07-04 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
US20060202189A1 (en) * 2003-06-26 2006-09-14 Rj Mears, Llc Semiconductor device including a memory cell with a negative differential resistance (ndr) device
US7109052B2 (en) 2003-06-26 2006-09-19 Rj Mears, Llc Method for making an integrated circuit comprising a waveguide having an energy band engineered superlattice
US20060220118A1 (en) * 2003-06-26 2006-10-05 Rj Mears, Llc Semiconductor device including a dopant blocking superlattice
US20060226502A1 (en) * 2003-06-26 2006-10-12 Rj Mears, Llc Microelectromechanical Systems (MEMS) Device Including a Superlattice
US6833294B1 (en) 2003-06-26 2004-12-21 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US20060231857A1 (en) * 2003-06-26 2006-10-19 Rj Mears, Llc Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device
US20060243964A1 (en) * 2003-06-26 2006-11-02 Rj Mears, Llc Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US20060261327A1 (en) * 2003-06-26 2006-11-23 Rj Mears, Llc Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US20070012909A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US20060267130A1 (en) * 2003-06-26 2006-11-30 Rj Mears, Llc Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
US20060273299A1 (en) * 2003-06-26 2006-12-07 Rj Mears, Llc Method for making a semiconductor device including a dopant blocking superlattice
US7153763B2 (en) 2003-06-26 2006-12-26 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US20060289049A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
US20060292889A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc FINFET Including a Superlattice
US20060292818A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
US20060292765A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a FINFET Including a Superlattice
US6830964B1 (en) 2003-06-26 2004-12-14 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US20040266116A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Methods of fabricating semiconductor structures having improved conductivity effective mass
US20040262628A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US7202494B2 (en) 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
US20070012999A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-On Resistance
US20070012912A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US20070012911A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-On Resistance
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US20070063186A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
US20070063185A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Semiconductor device including a front side strained superlattice layer and a back side stress layer
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US7227174B2 (en) 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7229902B2 (en) 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US7612366B2 (en) 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7598515B2 (en) 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7586116B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7586165B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US7535041B2 (en) 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7265002B2 (en) 2003-06-26 2007-09-04 Rj Mears, Llc Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
US7279699B2 (en) 2003-06-26 2007-10-09 Rj Mears, Llc Integrated circuit comprising a waveguide having an energy band engineered superlattice
US7279701B2 (en) 2003-06-26 2007-10-09 Rj Mears, Llc Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions
US7288457B2 (en) 2003-06-26 2007-10-30 Rj Mears, Llc Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions
US7303948B2 (en) 2003-06-26 2007-12-04 Mears Technologies, Inc. Semiconductor device including MOSFET having band-engineered superlattice
US7531828B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7531850B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7531829B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7432524B2 (en) 2003-06-26 2008-10-07 Mears Technologies, Inc. Integrated circuit comprising an active optical device having an energy band engineered superlattice
US7435988B2 (en) 2003-06-26 2008-10-14 Mears Technologies, Inc. Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
US7436026B2 (en) 2003-06-26 2008-10-14 Mears Technologies, Inc. Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7446334B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Electronic device comprising active optical devices with an energy band engineered superlattice
US7446002B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US7491587B2 (en) 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US20070187667A1 (en) * 2005-12-22 2007-08-16 Rj Mears, Llc Electronic device including a selectively polable superlattice
US7517702B2 (en) 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US20070161138A1 (en) * 2005-12-22 2007-07-12 Rj Mears, Llc Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US20070158640A1 (en) * 2005-12-22 2007-07-12 Rj Mears, Llc Electronic device including a poled superlattice having a net electrical dipole moment
US20070166928A1 (en) * 2005-12-22 2007-07-19 Rj Mears, Llc Method for making an electronic device including a selectively polable superlattice
US20070194298A1 (en) * 2006-02-21 2007-08-23 Rj Mears, Llc Semiconductor device comprising a lattice matching layer
US7718996B2 (en) 2006-02-21 2010-05-18 Mears Technologies, Inc. Semiconductor device comprising a lattice matching layer
US20070197006A1 (en) * 2006-02-21 2007-08-23 Rj Mears, Llc Method for making a semiconductor device comprising a lattice matching layer
US7700447B2 (en) 2006-02-21 2010-04-20 Mears Technologies, Inc. Method for making a semiconductor device comprising a lattice matching layer
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7928425B2 (en) 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US20080179588A1 (en) * 2007-01-25 2008-07-31 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US7863066B2 (en) 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US20080197341A1 (en) * 2007-02-16 2008-08-21 Rj Mears, Llc Method for making a multiple-wavelength opto-electronic device including a superlattice
US20080197340A1 (en) * 2007-02-16 2008-08-21 Rj Mears, Llc Multiple-wavelength opto-electronic device including a superlattice
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US8389974B2 (en) 2007-02-16 2013-03-05 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US20080258134A1 (en) * 2007-04-23 2008-10-23 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (sti) regions with maskless superlattice deposition following sti formation and related structures
US7812339B2 (en) 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
US9972685B2 (en) 2013-11-22 2018-05-15 Atomera Incorporated Vertical semiconductor devices including superlattice punch through stop layer and related methods
US9275996B2 (en) 2013-11-22 2016-03-01 Mears Technologies, Inc. Vertical semiconductor devices including superlattice punch through stop layer and related methods
US9406753B2 (en) 2013-11-22 2016-08-02 Atomera Incorporated Semiconductor devices including superlattice depletion layer stack and related methods
US10170560B2 (en) 2014-06-09 2019-01-01 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
US9716147B2 (en) 2014-06-09 2017-07-25 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US10084045B2 (en) 2014-11-25 2018-09-25 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US9899479B2 (en) 2015-05-15 2018-02-20 Atomera Incorporated Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
US9941359B2 (en) 2015-05-15 2018-04-10 Atomera Incorporated Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
US9721790B2 (en) 2015-06-02 2017-08-01 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9558939B1 (en) 2016-01-15 2017-01-31 Atomera Incorporated Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source

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