US6535452B2 - Semiconductor memory device having error correction function for data reading during refresh operation - Google Patents
Semiconductor memory device having error correction function for data reading during refresh operation Download PDFInfo
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- US6535452B2 US6535452B2 US10/097,621 US9762102A US6535452B2 US 6535452 B2 US6535452 B2 US 6535452B2 US 9762102 A US9762102 A US 9762102A US 6535452 B2 US6535452 B2 US 6535452B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1032—Simple parity
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/06—Sense amplifier related aspects
- G11C2207/065—Sense amplifier drivers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/108—Wide data ports
Definitions
- the present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device which automatically carries out a refresh operation inside the device without requiring an external refresh command, and reads data during the refresh operation while attending to error correction.
- DRAMs dynamic random access memories
- data are read from memory cells corresponding to a selected word line, and are amplified by sense amplifiers, followed by supplying data from the sense amplifier of a selected column to the exterior of the device.
- a DRAM is typically provided with a plurality of data input/output pins DQ, which outputs a plurality of data bits simultaneously.
- the plurality of DQ pins are associated with a single column line rather than associating a single DQ pin with a single column line. Namely, a plurality of sense amplifiers are connected to a single column line, and data of these sense amplifiers are input/output in parallel from/to the plurality of DQ pins.
- the operation of core circuits inside the memory devices need to be made faster. It is difficult, however, to speed up the operation of core circuits because of limitations such as wire delays.
- provision may be made not only to read data corresponding to the plurality of DQ pins in parallel from the memory core, but also to read serially output data in parallel from the memory core, then subjecting the data to parallel-&-serial conversion to arrange them sequentially along a time axis. With this provision, the data transfer rate to the exterior of the device can be improved without changing the operation speed of a core circuit.
- each column line is associated with a plurality of DQ pins, and a plurality of column lines are simultaneously activated that are equal in number to the number of data bits to be arranged along the time axis upon a single access, thereby reading the sequential data through parallel access.
- FIGS.1A and 1B are drawings showing data read operations in a case in which a column line is activated when each column line is associated with a plurality of DQ pins and in a case in which a plurality of column lines are activated when each column line is associated with a plurality of DQ pins.
- each column line is assigned to DQ 0 and DQ 1 , and a single column line is selectively activated to output data to the DQ 0 pad and the DQ 1 pad simultaneously.
- a column line C 1 is activated to output first data along the time axis.
- a column line C 2 is activated to output second data along the time axis.
- each column line is assigned to DQ 0 and DQ 1 , and a plurality of column lines are simultaneously activated to concurrently output respective data to the DQ 0 pad and the DQ 1 pad and sequentially output a plurality of data along the time axis.
- the column lines C 1 and C 2 are activated to output data of the column line C 1 at the first cycle and to output data of the column line C 2 at the second cycle.
- a parity bit is calculated with respect to a plurality of DQ data bits, and these DQ data bits are stored in memory together with the parity bit.
- the plurality of DQ data bits are stored in respective memory blocks, and the parity bit is stored in a parity-bit-storage-purpose memory block.
- the plurality of DQ data bits are read from the respective memory blocks, and the parity bit is read from the parity-bit-storage-purpose memory block.
- a parity check is carried out based on the retrieved DQ data bits and the parity bit. If a parity error is detected during a refresh operation, a data bit retrieved from the memory block that is currently being refreshed is corrected, and, then, the DQ data bits are output.
- a semiconductor memory device includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m>1) data pins, each of which continuously receives or outputs n (n>1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, m ⁇ n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, m address selection lines which are connected to m respective blocks of the memory blocks corresponding to the m respective data pins, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the m respective blocks and resulting in the n data pieces being input/output to/from the corresponding one of the m respective blocks, and a parity data comparison circuit which performs a parity check on m data pieces read from the m respective blocks
- the semiconductor memory device described above has a configuration in which each address selection line is responsible for a plurality of data pieces, and a plurality of address selection lines are simultaneously activated.
- the present invention performs a parity check on m data pieces read from the m respective blocks and a parity bit read from a parity-purpose memory block separately with respect to each of the n data pieces, thereby providing an error correction function for a refresh operation.
- the semiconductor memory device described above further includes a mask circuit which masks a specific one of the n data pieces with respect to all the m data pins at a time of data writing.
- a mask circuit which masks a specific one of the n data pieces with respect to all the m data pins at a time of data writing.
- a semiconductor memory device includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m>1) data pins, each of which continuously receives or outputs n (n>1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, m ⁇ n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, n address selection lines which are connected to n respective blocks of the memory blocks corresponding to the n respective data pieces, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the n respective blocks and resulting in m data pieces corresponding to the m respective data pins being input/output to/from the corresponding one of the n respective blocks, a parity data comparison circuit which performs a parity check on the n data pieces read from the n respective blocks and a parity bit read from a parity-purpose memory block,
- each address selection line is responsible for the m data pieces, and the n address selection lines correspond to the n respective data pieces, the parity check that is directed to the n data pieces can be performed properly even if one of the m data pieces is nonexistent.
- FIGS. 1A and 1B are drawings showing data read operations in a case in which a column line is activated when each column line is associated with a plurality of DQ pins and in a case in which a plurality of column lines are activated when each column line is associated with a plurality of DQ pins;
- FIG. 2 is a block diagram showing an example of a configuration of a semiconductor memory device according to the present invention
- FIG. 3 is a circuit diagram showing an example of a memory cell array of FIG. 2;
- FIG. 4 is a timing chart showing the operation of data writing with respect to the configuration of FIG. 3;
- FIG. 5 is a timing chart showing an operation of masking a first data in relation to the operation of FIG. 4;
- FIG. 6 is a circuit diagram showing an example of a configuration of the memory cell array in the case of a data-pin-specific mask operation
- FIGS. 7A and 7B are illustrative drawings showing a bit-specific mask operation and a corresponding circuit configuration of the memory cell array
- FIGS. 8A and 8B are illustrative drawings showing a data-pin-specific mask operation and a corresponding circuit configuration of the memory cell array
- FIG. 9 is a circuit diagram showing an example of a configuration relating to a memory core and data pins according to the present invention.
- FIG. 10 is a circuit diagram showing an example of a configuration of a parity generation circuit
- FIG. 11 is a circuit diagram showing an example of a configuration of a selector circuit
- FIG. 12 is a drawing for explaining data compression at the time of a test operation of a semiconductor memory device.
- FIGS. 13A and 13B are timing charts showing the way the data compression is made.
- FIG. 2 is a block diagram showing an example of a configuration of a semiconductor memory device according to the present invention.
- the semiconductor memory device of FIG. 2 includes a command input circuit 11 , an address input circuit 12 , a row decoder 13 , a column decoder 14 , a data I/O circuit 15 , a refresh signal generation circuit 2 , an internal address generation circuit 3 , a parity generation circuit 6 , a parity data comparison circuit 7 , a memory cell array 8 , a column driver 16 , a data bus amplifier units 17 including a write amplifier and a read amplifier, and a main-word-driver-&-sense-amplifier-driver circuit 18 .
- the refresh signal generation circuit 2 includes a refresh oscillator 21 and a divider 22 .
- the command input circuit 11 supplies a control signal to the address input circuit 12 for the purpose of capturing addresses according to a data read command and a data write command received from an external CPU or the like.
- the row decoder 13 and the column decoder 14 decode the captured addresses, and supply the decoded addresses to the main-word-driver-&-sense-amplifier-driver circuit 18 and the column driver 16 . Operation of each circuit/unit is controlled based on the command that is received by the command input circuit 11 from the exterior of the device. That is, the command input circuit 11 decodes a command to generate control signals, which are then supplied to respective circuit/units to control the operation of each circuit/unit.
- the refresh signal generation circuit 2 generates a refresh signal inside the semiconductor memory device, and a refresh operation is performed with respect to an address that is generated by the internal address generation circuit 3 in response to the refresh signal.
- the parity generation circuit 6 At the time of data writing, the parity generation circuit 6 generates a parity bit, which is then stored in the memory cell array 8 . Even when a refresh operation overlaps a routine data read operation or data write operation, the refresh operation will be performed. Since data read from the block that is currently being refreshed is not valid, this data is compared with the parity bit to perform a parity check. In the case of parity error, an error is corrected by reversing the data read from the block that is being refreshed. The comparison with the parity bit and the error correction are performed by the parity data comparison circuit 7 .
- FIG. 3 is a circuit diagram showing an example of the memory cell array 8 according to the present invention.
- the circuit of FIG. 3 corresponds to a portion of the memory cell array 8 in a case where two DQ pins DQ 0 and DQ 1 are provided.
- the circuit of FIG. 3 includes a plurality of cell gate transistors 30 , a plurality of memory cells 31 , a plurality of sense amplifiers 32 - 0 through 32 - 5 , a plurality of AND circuits 33 - 0 through 33 - 5 , a plurality of word lines WL 0 through WL 2 , a plurality of bit lines BL 0 through BL 5 , and a plurality of column lines CL 0 through CL 2 , and a data bus DB.
- the sense amplifiers 32 - 0 and 32 - 1 connected to the respective bit lines BL 0 and BL 1 correspond to the data pin DQ 0 .
- These sense amplifiers 32 - 0 and 32 - 1 are selected in response to the activation of the column line CL 0 corresponding to the data pin DQ 0 so as to be connected to the data bus DB.
- the data of the sense amplifiers 32 - 0 and 32 - 1 correspond to the first data Bit 1 and the second data Bit 2 , respectively, of the data pin DQ 0 along the time axis.
- the sense amplifiers 32 - 2 and 32 - 3 connected to the respective bit lines BL 2 and BL 3 correspond to the data pin DQ 1 .
- These sense amplifiers 32 - 2 and 32 - 3 are selected in response to the activation of the column line CL 1 corresponding to the data pin DQ 1 so as to be connected to the data bus DB.
- the data of the sense amplifiers 32 - 2 and 32 - 3 correspond to the first data Bit 1 and the second data Bit 2 , respectively, of the data pin DQ 1 along the time axis.
- the sense amplifiers 32 - 4 and 32 - 5 connected to the respective bit lines BL 4 and BL 5 correspond to the respective parity bits for the data pins DQ 0 and DQ 1 .
- These sense amplifiers 32 - 4 and 32 - 5 are selected in response to the activation of the column line CL 2 corresponding to the parity bit so as to be connected to the data bus DB.
- the data of the sense amplifiers 32 - 4 and 32 - 5 correspond to the parity bit for the first data Bit 1 and the parity bit for the second data Bit 2 , respectively, along the time axis.
- the parity bit is calculated through an XOR operation, so that it is designated as “XOR” in FIG. 3 .
- the word lines WL 0 through WL 2 are provided separately for the data pin DQ 0 , the data pin DQ 1 , and the parity bit, respectively. It is thus possible to perform a refresh operation independently with respect to each of the data pin DQ 0 , the data pin DQ 1 , and the parity bit. If data needs to be read while a refresh operation is being performed with respect to the data pin DQ 0 , the data of the data pin DQ 0 , the data of the data pin DQ 1 , and a parity bit are read, and a parity check is performed, followed by correcting the data of the data pin DQ 0 as necessary. The parity check and the error correction are carried out with respect to the first data Bit 1 and the second data Bit 2 separately along the time axis.
- the AND circuits 33 - 0 through 33 - 5 are each provided for the purpose of performing an AND operation between a column line signal and a mask signal to select a sense amplifier.
- the mask signal (MASK-Bit 1 and MASK-Bit 2 ) serves to prevent data from being written in the memory cells when data is masked at the time of data writing.
- FIG. 4 is a timing chart showing the operation of data writing with respect to the configuration of FIG. 3 .
- the first data Bit 1 and the second data Bit 2 are supplied to the data pin DQ 0 , and, also, the first data Bit 1 and the second data Bit 2 are supplied to the data pin DQ 1 .
- These data are subjected to serial-to-parallel conversion, and are stored in the sense amplifiers 32 - 0 through 32 - 5 as parallel data, as shown as “WRITE DATA” in FIG. 4 .
- the data of the sense amplifiers 32 - 0 through 32 - 5 are simultaneously stored in the memory cells 31 through the bit lines BL 0 through BL 5 , as shown as “MEMORY CELL” in FIG. 4 .
- FIG. 5 is a timing chart showing an operation of masking the first data in relation to the operation of FIG. 4 .
- the masked data Bit 1 is not stored in the sense amplifiers, and only the data Bit 2 that was not masked is stored in the sense amplifiers, as shown as “WRITE DATA”. Then, the data of the sense amplifiers are simultaneously stored in the memory cells 31 through the bit lines BL 0 through BL 5 , as shown as “MEMORY CELL” in FIG. 5 .
- the AND circuits 33 - 0 through 33 - 5 are provided for the purpose of performing an AND operation between a column line signal and a mask signal so as to select a sense amplifier.
- Turning the mask signal MASK-Bit 1 to LOW results in the outputs of the AND circuits 33 - 0 , 33 - 2 , and 33 - 4 being LOW, so that the sense amplifiers 32 - 0 , 32 - 2 , and 32 - 4 are not connected to the data bus DB even when the respective column lines are selected.
- the first data Bit 1 and the parity bit corresponding thereto supplied to the data bus DB are not supplied to the respective sense amplifiers 32 - 0 , 32 - 2 , and 32 - 4 .
- turning the mask signal MASK-Bit 1 to LOW will mask the first data Bit 1 .
- turning the mask signal MASK-Bit 2 to LOW will mask the second data Bit 2 .
- sense amplifiers connected to the same column line correspond to the data Bit 1 and the data Bit 2 , respectively, which are arranged along the time axis, and each column line corresponds to a different data pin DQ.
- This configuration is thus different from the configuration of FIG. 1B in which each column line is responsible for a plurality of DQ pins, and corresponds to a different one of data pieces arranged along the time axis.
- the configuration of FIG. 3 is necessary to achieve a bit-specific mask operation, i.e., to achieve a mask operation that masks a specified one of the data Bit 1 and Bit 2 arranged along the time axis. If sense amplifiers connected to a column line are associated with data pins DQ 0 and DQ 1 , and each column line corresponds to a different bit, data correction for a refresh operation cannot be attained when a bit-specific mask operation is carried out.
- the present invention makes each column line responsible for a plurality of data bits arranged along the time axis, and makes the plurality of column lines correspond to respective data pins DQ when a bit-specific mask operation is performed. Accordingly, even when the first bits Bit 1 are masked on a bit-specific basis, a parity check can be made with respect to the second bits Bit 2 .
- a plurality of column lines need to correspond to respective data bits arranged along the time axis, rather than correspond to respective data pins DQ as shown in FIG. 3 .
- FIG. 6 is a circuit diagram showing an example of a configuration of the memory cell array 8 according to the present invention in the case of a data-pin-specific mask operation.
- the circuit of FIG. 6 includes the plurality of cell gate transistors 30 , the plurality of memory cells 31 , a plurality of sense amplifiers 42 - 0 through 42 - 5 , a plurality of AND circuits 43 - 0 through 43 - 5 , a plurality of word lines WL 0 through WL 2 , a plurality of bit lines BL 0 or BL 5 , a plurality of column lines CL 0 through CL 2 , and a data bus DB.
- the sense amplifiers 42 - 0 and 42 - 1 both correspond to the first data bit Bit 1 , and are selected in response to the activation of the column line CL 0 so as to be connected to the data bus DB.
- the data of the sense amplifiers 42 - 0 and 42 - 1 correspond to the data pin DQ 0 and the data pin DQ 1 , respectively.
- the sense amplifiers 42 - 2 and 42 - 3 both correspond to the second data bit Bit 2 , and are selected in response to the activation of the column line CL 1 so as to be connected to the data bus DB.
- the data of the sense amplifiers 42 - 2 and 42 - 3 correspond to the data pin DQ 0 and the data pin DQ 1 , respectively.
- the sense amplifiers 42 - 4 and 42 - 5 correspond to the parity bit for the data of the data pin DQ 0 and the parity bit of the data of the data pin DQ 1 , respectively.
- the word lines WL 0 through WL 2 are provided separately for the data bit Bit 1 , the data bit Bit 2 , and the parity bit, respectively. It is thus possible to perform a refresh operation independently with respect to each of the data bit Bit 1 , the data bit Bit 2 , and the parity bit. If data needs to be read while a refresh operation is being performed with respect to the data bit Bit 1 , the data of the data bit Bit 1 , the data bit Bit 2 , and the parity bit are read, and a parity check is performed, followed by correcting the data of the data bit Bit 1 as necessary. The parity check and the error correction are carried out with respect to the data pin DQ 0 and the data pin DQ 1 separately.
- the AND circuits 43 - 0 through 43 - 5 are each provided for the purpose of performing an AND operation between a column line signal and a mask signal to select a sense amplifier.
- the circuit of FIG. 6 is configured in such a manner as to mask data on a data-pin-specific basis. Because of this, each column line does not correspond to a different data pin, but corresponds to a different one of data bits arranged along the time axis. Accordingly, a parity check for the data pin DQ 1 can be made even when the data of the data pin DQ 0 is masked on a data-pin-specific basis.
- the present invention changes the circuit configuration of the memory cell array as shown in FIG. 3 or FIG. 6 between the case of a bit-specific masking operation and the case of a data-pin-specific masking operation, thereby making it possible to make a parity check properly during a refresh operation.
- FIGS. 7A and 7B are illustrative drawings showing a bit-specific mask operation and a corresponding circuit configuration of the memory cell array.
- 4 data pins DQ are provided, and 4 data bits are arranged along the time axis.
- a masking operation is performed on a bit-specific basis.
- the memory cell array needs to be implemented to have the circuit arrangement of FIG. 7 B.
- the plurality of address selection lines e.g., column lines
- each address selection line is connected in parallel to the plurality of data bits arranged along the time axis.
- a parity check is performed between the plurality of data pins. With this provision, a parity check can be made with respect to each of the data bits Bit 2 through Bit 4 even if the data bit Bit 1 is masked on a bit-specific basis and thus nonexistent.
- FIGS. 8A and 8B are illustrative drawings showing a data-pin-specific mask operation and a corresponding circuit configuration of the memory cell array.
- 4 data pins DQ are provided, and 4 data bits are arranged along the time axis.
- a masking operation is performed on a data-pin-specific basis.
- the memory cell array needs to be implemented to have the circuit arrangement of FIG. 8 B.
- the plurality of address selection lines e.g., column lines
- each address selection line is connected in parallel to the plurality of data pins.
- a parity check is performed between the plurality of data bits arranged along the time axis.
- FIG. 9 is a circuit diagram showing an example of the configuration relating to the memory core and data pins according to the present invention.
- the configuration of FIG. 9 corresponds to the case of FIG. 3 in which a mask operation is performed on a bit-specific basis.
- This configuration is basically the same even in the case of FIG. 6 in which a mask operation is performed on a data-pin-specific basis, except for the relation between bits and data pins are interchanged.
- the circuit of FIG. 9 includes a plurality of memory blocks 51 , sense amplifiers 52 corresponding to the respective memory blocks 51 , word decoders 53 corresponding to the respective memory blocks 51 , a column decoder 54 - 0 corresponding to the data pin DQ 0 , a column decoder 54 - 1 corresponding to the data pin DQ 1 , a column decoder 54 - 2 corresponding to the parity bit, a parity generation circuit (XORA) 55 , an XOR circuit 56 , selector circuits (SEL) 57 , parallel-&-serial conversion circuits 58 , and data pins 59 corresponding to DQ 0 and DQ 1 .
- XORA parity generation circuit
- SEL selector circuits
- parallel-&-serial conversion circuits 58 parallel-&-serial conversion circuits 58
- data pins 59 corresponding to DQ 0 and DQ 1 .
- the plurality of memory blocks 51 corresponds to the memory cell array 8 , the word decoders 53 corresponding to the main-word-driver-&-sense-amplifier-driver circuit 18 , the column decoders 54 - 0 through 54 - 2 corresponding to the column decoder 14 , and the parity generation circuit 55 corresponding to the parity generation circuit 6 .
- the XOR circuit 56 and the selector circuits 57 are equivalent to the parity data comparison circuit 7 .
- the parallel-&-serial conversion circuit 58 corresponds to the data I/O circuit 15 .
- the data input to the data pins 59 are converted from serial data into parallel data by the parallel-&-serial conversion circuit 58 , and are supplied to the selector circuits 57 .
- the data supplied to the selector circuits 57 are supplied to the parity generation circuit 55 and to the sense amplifiers 52 through the data bus.
- the parity generation circuit 55 performs an XOR operation on a bit-specific basis, and generates parity bits. For example, an XOR operation between the first data bit Bit 1 of the data pin DQ 0 and the first data bit Bit 1 of the data pin DQ 1 is performed, thereby generating a parity bit for the data bits Bit 1 .
- the data of the data pin DQ 0 are supplied to the sense amplifiers 52 connected to the column decoder 54 - 0 .
- the data of the data pin DQ 1 are supplied to the sense amplifiers 52 connected to the column decoder 54 - 1 .
- the parity bits that are generated by the parity generation circuit 55 are supplied to the sense amplifiers 52 connected to the column decoder 54 - 2 .
- a selected mask signal (MASKBit 0 through MASKbit 3 ) may specify a masked bit, thereby prohibiting the specified bit from being stored in the sense amplifiers 52 .
- the word decoders 53 selectively activate a word line WL corresponding to the specified row address. In response, the data of the sense amplifiers 52 are stored in the memory cells of the memory blocks 51 .
- the word decoders 53 selectively activate a word line WL corresponding to the specified read row address.
- the data of memory cells are retrieved to the sense amplifiers 52 .
- the column decoders 54 - 0 through 54 - 2 selectively activate a column line corresponding to the specified read column address. This results in the data of the sense amplifiers 52 being read to the data bus.
- data that is retrieved from a memory block being refreshed and stored in the sense amplifiers 52 was being subjected the refresh operation, and, thus, such retrieved data may be affected by the refresh operation.
- the data read in this manner are supplied to the XOR circuit 56 , and are also supplied to the selector circuits 57 .
- the XOR circuit 56 performs an XOR operation on a bit-specific basis, thereby carrying out a parity check. For example, an XOR operation is performed between the first data bit Bit 1 retrieved for the data pin DQ 0 , the first data bit Bit 1 retrieved for the data pin DQ 1 , and the parity bit of the first data bit Bit 1 , thereby checking the parity of the data bits Bit 1 .
- a parity check result of “1” indicates an error
- a parity check result of “0” indicates no error.
- the selector circuits 57 attend to data correction on a bit-specific basis as necessary. For example, if the memory block corresponding to the data pin DQ 0 is being refreshed, and if the parity check of the first data bit Bit 1 indicates an error, this error is corrected by reversing the first data bit Bit 1 corresponding to the data pin DQ 0 .
- the retrieved data or retrieved and corrected data in this manner are converted from parallel data into serial data by the parallel-&-serial conversion circuits 58 , followed by being output from the data pins 59 .
- FIG. 10 is a circuit diagram showing an example of the configuration of the parity generation circuit 55 .
- the parity generation circuit 55 includes an XOR circuit 71 , an inverter 72 , and a transfer gate 73 comprised of a PMOS transistor and an NMOS transistor connected in parallel.
- the signal WR is LOW, so that the transfer gate 73 is closed, thereby suspending data output from the parity generation circuit 55 so as to avoid collision with parity bits read from the memory cells.
- FIG. 11 is a circuit diagram showing an example of the configuration of the selector circuit 57 .
- the selector circuit 57 includes a NAND circuit 81 , inverters 82 through 84 , and transfer gates 85 through 88 each comprised of a PMOS transistor and a NMOS transistor connected in parallel.
- the signal WR is HIGH, so that the transfer gate 87 is open and the transfer gate 88 is closed.
- the write data supplied from the parallel-&-serial conversion circuit 58 are supplied to the data bus.
- the signal WR is LOW, so that the transfer gate 87 is closed, and the transfer gate 88 is open.
- a signal XOR is the output of the corresponding XOR circuit 56 , and indicates a parity error when it is HIGH. If both the signal REFDy and the signal XOR are HIGH, the output of the NAND circuit 81 becomes LOW, thereby opening the transfer gate 85 .
- FIG. 12 is a drawing for explaining data compression at the time of a test operation of a semiconductor memory device.
- the test operation of a semiconductor memory device is provided with a test mode that activates a plurality of address selection lines and compresses data for the purpose of reducing a test time.
- a test mode that activates a plurality of address selection lines and compresses data for the purpose of reducing a test time.
- these data pieces can be compressed by the AND circuits 91 and 92 , thereby compressing the data in a time dimension.
- FIG. 3 In the related-art configurations, a plurality of data pins are connected to each address selection line (e.g., each of the column lines CL 0 and CL 1 ), so that data compression will results in a reduction of the number of data pins used for the test. In this case, however, data is not compressed in a time dimension.
- the configuration of FIG. 3 according to the present invention can thus reduce a test time compared to the related-art configuration.
- FIGS. 13A and 13B show the way the data compression is made.
- the related-art configuration can reduce the number of data pads by compressing data during the test operation.
- FIG. 13B on the other hand, the configuration of FIG. 3 according to the present invention can shorten the test time by reducing the number of operation cycles necessary for the test operation through data compression during the test operation.
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Abstract
Description
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2001-208069 | 2001-07-09 | ||
JP2001208069A JP3860436B2 (en) | 2001-07-09 | 2001-07-09 | Semiconductor memory device |
Publications (2)
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US20030007410A1 US20030007410A1 (en) | 2003-01-09 |
US6535452B2 true US6535452B2 (en) | 2003-03-18 |
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US10/097,621 Expired - Lifetime US6535452B2 (en) | 2001-07-09 | 2002-03-15 | Semiconductor memory device having error correction function for data reading during refresh operation |
Country Status (5)
Country | Link |
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US (1) | US6535452B2 (en) |
JP (1) | JP3860436B2 (en) |
KR (1) | KR100718518B1 (en) |
CN (1) | CN1396599B (en) |
TW (1) | TW550595B (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030074630A1 (en) * | 2001-10-16 | 2003-04-17 | Batson Kevin A. | Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM) |
US20040093465A1 (en) * | 2002-10-28 | 2004-05-13 | Quicksilver Technology, Inc. | Cache for instruction set architecture |
US7100097B2 (en) * | 2002-07-16 | 2006-08-29 | Hewlett-Packard Development Company, L.P. | Detection of bit errors in maskable content addressable memories |
US20060285409A1 (en) * | 2005-06-15 | 2006-12-21 | Klaus Hummler | Memory having parity generation circuit |
US7260673B1 (en) | 2001-07-20 | 2007-08-21 | Cisco Technology, Inc. | Method and apparatus for verifying the integrity of a content-addressable memory result |
US20080056025A1 (en) * | 2006-09-01 | 2008-03-06 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
US20080294934A1 (en) * | 2007-02-16 | 2008-11-27 | Bok-Gue Park | Semiconductor memory device having an error correction function and associated method |
US20120124449A1 (en) * | 2010-11-16 | 2012-05-17 | Micron Technology, Inc. | Method and apparatus to perform concurrent read and write memory operations |
US20150106678A1 (en) * | 2013-10-14 | 2015-04-16 | SK Hynix Inc. | Semiconductor device and semiconductor system including the same |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1771565B (en) * | 2003-08-18 | 2010-05-05 | 富士通微电子株式会社 | Semiconductor memory and operation method of semiconductor memory |
US7328304B2 (en) | 2004-02-27 | 2008-02-05 | Intel Corporation | Interface for a block addressable mass storage system |
KR100905712B1 (en) * | 2006-09-29 | 2009-07-01 | 삼성전자주식회사 | Parallel Bit Test device using Error Correct Code |
US20090013148A1 (en) * | 2007-07-03 | 2009-01-08 | Micron Technology, Inc. | Block addressing for parallel memory arrays |
US8327062B2 (en) * | 2008-12-09 | 2012-12-04 | Infineon Technologies Ag | Memory circuit and method for programming in parallel a number of bits within data blocks |
US9455020B2 (en) | 2014-06-05 | 2016-09-27 | Micron Technology, Inc. | Apparatuses and methods for performing an exclusive or operation using sensing circuitry |
US9704540B2 (en) | 2014-06-05 | 2017-07-11 | Micron Technology, Inc. | Apparatuses and methods for parity determination using sensing circuitry |
US9514800B1 (en) * | 2016-03-26 | 2016-12-06 | Bo Liu | DRAM and self-refresh method |
CN110740009B (en) * | 2018-07-20 | 2022-08-12 | 富联精密电子(天津)有限公司 | Data transmission checking device and method |
KR102717146B1 (en) * | 2018-11-19 | 2024-10-15 | 삼성전자주식회사 | Semiconductor memory device and memory system having the same |
US11152054B2 (en) * | 2019-08-28 | 2021-10-19 | Micron Technology, Inc. | Apparatuses and methods for performing background operations in memory using sensing circuitry |
CN115881206B (en) * | 2023-03-03 | 2023-07-18 | 长鑫存储技术有限公司 | Memory device |
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US5033050A (en) * | 1988-03-28 | 1991-07-16 | Kabushiki Kaisha Toshiba | Operation control system |
US5313425A (en) * | 1992-11-23 | 1994-05-17 | Samsung Electronics Co., Ltd. | Semiconductor memory device having an improved error correction capability |
US6421292B1 (en) * | 2000-12-04 | 2002-07-16 | Fujitsu Limited | Semiconductor memory, and memory access method |
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KR0168896B1 (en) * | 1993-09-20 | 1999-02-01 | 세키자와 다다시 | Semiconductor memory of xn type having error correcting circuit by parity |
EP1143443B1 (en) * | 1995-07-14 | 2003-09-17 | Sony Corporation | Method for transmitting digital data and record medium |
KR19980027610A (en) * | 1996-10-17 | 1998-07-15 | 문정환 | Error Correction Circuit in Flash Memory |
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2001
- 2001-07-09 JP JP2001208069A patent/JP3860436B2/en not_active Expired - Fee Related
-
2002
- 2002-03-15 US US10/097,621 patent/US6535452B2/en not_active Expired - Lifetime
- 2002-03-15 TW TW091104974A patent/TW550595B/en not_active IP Right Cessation
- 2002-03-25 KR KR1020020016119A patent/KR100718518B1/en not_active IP Right Cessation
- 2002-03-25 CN CN02108016XA patent/CN1396599B/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US5033050A (en) * | 1988-03-28 | 1991-07-16 | Kabushiki Kaisha Toshiba | Operation control system |
US5313425A (en) * | 1992-11-23 | 1994-05-17 | Samsung Electronics Co., Ltd. | Semiconductor memory device having an improved error correction capability |
US6421292B1 (en) * | 2000-12-04 | 2002-07-16 | Fujitsu Limited | Semiconductor memory, and memory access method |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7260673B1 (en) | 2001-07-20 | 2007-08-21 | Cisco Technology, Inc. | Method and apparatus for verifying the integrity of a content-addressable memory result |
US6760881B2 (en) * | 2001-10-16 | 2004-07-06 | International Business Machines Corporation | Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM) |
US20030074630A1 (en) * | 2001-10-16 | 2003-04-17 | Batson Kevin A. | Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM) |
US7100097B2 (en) * | 2002-07-16 | 2006-08-29 | Hewlett-Packard Development Company, L.P. | Detection of bit errors in maskable content addressable memories |
US7340562B2 (en) * | 2002-10-28 | 2008-03-04 | Nvidia Corporation | Cache for instruction set architecture |
US20040093465A1 (en) * | 2002-10-28 | 2004-05-13 | Quicksilver Technology, Inc. | Cache for instruction set architecture |
US7382673B2 (en) * | 2005-06-15 | 2008-06-03 | Infineon Technologies Ag | Memory having parity generation circuit |
US20060285409A1 (en) * | 2005-06-15 | 2006-12-21 | Klaus Hummler | Memory having parity generation circuit |
US20080056025A1 (en) * | 2006-09-01 | 2008-03-06 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
US8074144B2 (en) * | 2006-09-01 | 2011-12-06 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
US20080294934A1 (en) * | 2007-02-16 | 2008-11-27 | Bok-Gue Park | Semiconductor memory device having an error correction function and associated method |
US8225171B2 (en) | 2007-02-16 | 2012-07-17 | Samsung Electronics Co., Ltd. | Semiconductor memory device having an error correction function and associated method |
US20120124449A1 (en) * | 2010-11-16 | 2012-05-17 | Micron Technology, Inc. | Method and apparatus to perform concurrent read and write memory operations |
US8583987B2 (en) * | 2010-11-16 | 2013-11-12 | Micron Technology, Inc. | Method and apparatus to perform concurrent read and write memory operations |
US20140068380A1 (en) * | 2010-11-16 | 2014-03-06 | Micron Technology, Inc. | Method and apparatus to perform concurrent read and write memory operations |
US9208019B2 (en) * | 2010-11-16 | 2015-12-08 | Micron Technology, Inc. | Method and apparatus to perform concurrent read and write memory operations |
US9513992B2 (en) | 2010-11-16 | 2016-12-06 | Micron Technology, Inc. | Method and apparatus to perform concurrent read and write memory operations |
US20150106678A1 (en) * | 2013-10-14 | 2015-04-16 | SK Hynix Inc. | Semiconductor device and semiconductor system including the same |
US9239755B2 (en) * | 2013-10-14 | 2016-01-19 | SK Hynix Inc. | Semiconductor device and semiconductor system including the same |
Also Published As
Publication number | Publication date |
---|---|
US20030007410A1 (en) | 2003-01-09 |
TW550595B (en) | 2003-09-01 |
KR20030006933A (en) | 2003-01-23 |
KR100718518B1 (en) | 2007-05-16 |
CN1396599B (en) | 2010-04-14 |
CN1396599A (en) | 2003-02-12 |
JP3860436B2 (en) | 2006-12-20 |
JP2003022694A (en) | 2003-01-24 |
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