US6278323B1 - High gain, very wide common mode range, self-biased operational amplifier - Google Patents
High gain, very wide common mode range, self-biased operational amplifier Download PDFInfo
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- US6278323B1 US6278323B1 US09/547,748 US54774800A US6278323B1 US 6278323 B1 US6278323 B1 US 6278323B1 US 54774800 A US54774800 A US 54774800A US 6278323 B1 US6278323 B1 US 6278323B1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/4521—Complementary long tailed pairs having parallel inputs and being supplied in parallel
- H03F3/45219—Folded cascode stages
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- Embodiments of the present invention relate to analog circuits, and more particularly, to operational amplifiers.
- CMOS Complementary-Metal-Oxide-Semiconductor
- FET Field-Effect-Transistor
- external biasing may be sensitive to process technology, supply voltage, and temperature.
- the overall gain and output resistance of an operational amplifier may both be very high and difficult to accurately model, the output node voltages for zero differential input voltage is very difficult to predict. In general, these node voltages should be at or near V cc /2 for zero differential input voltage, where V cc is the supply voltage.
- FIG. 1 is a circuit for an embodiment of the present invention.
- FIG. 1 is a circuit for an embodiment of a high gain, very wide common mode range, self-biased operational amplifier.
- the operational amplifier of FIG. 1 may be considered a transconductance amplifier, in that a small-signal current is provided to a load in response to a differential voltage at input nodes 102 and 104 .
- the load in FIG. 1 may be taken as the output resistance of transistor 5 B in parallel with transistor 6 B.
- the operational amplifier of FIG. 1 is self-biasing because no external biasing is needed.
- Transistors 1 A and 1 B are pMOSFETs (p-Metal-Oxide-Semiconductor-Field-Effect-Transistor) arranged as a first differential pair of transistors having their sources connected to each other, and transistors 2 A and 2 B are nMOSFETs arranged as a second differential pair having their sources connected to each other.
- the two differential pairs are complementary to each other in that they comprise transistors having complementary carrier types, i.e., transistors 1 A and 1 B are of p-carrier type and transistors 2 A and 2 B are of n-carrier type.
- the gates of transistors 1 A and 2 A are connected to input node 102
- the gates of transistors 1 B and 2 B are connected to input node 104 .
- Transistor 3 sources bias current to the differential pair 1 A and 1 B.
- Transistors 8 A and 8 B comprise a current mirror.
- Transistor 8 A sinks bias currents from transistors 1 A and 6 A
- transistor 8 B sinks bias currents from transistors 1 B and 6 B.
- the bias current sourced by transistor 3 is equal in magnitude to the sum of the bias currents sunk by transistors 1 A and 1 B.
- transistors 8 A and 8 B sink equal bias currents.
- transistors 7 A and 7 B comprise a current mirror.
- Transistor 7 A sources bias currents to transistors 2 A and 5 A
- transistor 7 B sources bias currents to transistors 2 B and 5 B.
- Transistor 4 sinks bias current from the differential pair 2 A and 2 B. The bias current sunk by transistor 4 is equal in magnitude to the sum of the bias currents sourced by transistors 2 A and 2 B. When the voltage differential between nodes 102 and 104 is zero, transistors 7 A and 7 B source equal bias currents.
- the gate of transistor 7 A is connected to its drain, as well as to the gates of transistors 3 and 7 B. Because the gate of transistor 7 A is connected to its drain, it is biased in its saturation region as long as its gate-source voltage V GS is more negative than V TP , the pMOSFET threshold voltage. Consequently, transistors 3 and 7 B are also biased in their saturation regions within a margin of V TP .
- the gate of transistor 8 A is connected to its drain, as well as to the gates of transistors 4 and 8 B. Because the gate of transistor 8 A is connected to its drain, it is biased in its saturation region as long as its gate-source voltage V GS is more positive than V TN , the nMOSFET threshold voltage. Consequently, transistors 4 and 8 B are also biased in their saturation regions within a margin of V TN .
- Transistors 2 B and 5 B are arranged as a folded-cascode pair.
- Transistor 5 B is a pMOSFET, so that the folded-cascode pair 2 B and 5 B is comprised of transistors having complementary carrier types.
- Cascode transistor 5 B provides impedance translation. That is, the impedance at node 112 is very much smaller than the impedance at node 106 .
- transistors 1 B and 6 B are arranged as a folded-cascode pair with complementary carrier types, where the impedance at node 114 is much smaller than the impedance at node 106 .
- the use of cascode transistors 5 B and 6 B provides a high output impedance, which helps to provide a high amplifier gain because gain is determined by the product of the input transconductance and the output impedance.
- Transistors 5 A and 2 A, and transistors 6 A and 1 A are arranged as folded-cascode pairs having complementary carrier types.
- the gate of transistor 5 A is connected to its drain, and the gate of transistor 6 A is connected to its drain, so that transistors 5 A and 6 A are biased in their saturation regions.
- the gates and drains of transistors 5 A and 6 A which are at the same potential, are connected to the gates of transistors 5 B and 6 B and, thereby, bias them.
- the complementary arrangement of the amplifier of FIG. 1 provides for a very wide common mode range of operation, as reasoned as follows. If the common mode input voltage is low such that transistors 2 A and 2 B are in cut-off, then transistors 1 A and 1 B will still be ON and will continue to amplify. Conversely, if the common mode input voltage is high such that transistors 1 A and 1 B are in cut-off, then transistors 2 A and 2 B will still be ON and will continue to amplify. In this way, the amplifier of FIG. 1 will provide amplification over a wide common mode input voltage range.
- the self-biasing arrangement of the amplifier of FIG. 1 creates negative-feedback loops that stabilize the various bias voltages. Variations in processing parameters or operating conditions that shift the bias voltages away from their nominal values result in a shift in the bias voltages so as to be self-correcting.
- the self-biasing arrangement of the embodiment of FIG. 1 also contributes to its differential gain, which may be heuristically argued as follows.
- input node 102 goes HIGH and input node 104 goes LOW.
- Small-signal current is drawn from nodes 108 and 110 by transistors 2 A and lA, respectively, and small-signal current is injected into nodes 112 and 114 by transistors 2 B and 1 B, respectively.
- With small-signal current injected into nodes 112 and 114 more current will be sourced into transistor 5 B, and less current will be sunk from transistor 6 B, and as a result, node 106 will go HIGH.
- nodes 108 and 110 go LOW. Because the gates of transistors 3 and 7 B are connected to node 108 , they conduct more strongly, thereby causing the voltage at node 106 to go even higher. Furthermore, because the gates of transistors 4 and 8 B are connected to node 110 , these transistors conduct more weakly, thereby also causing the voltage at node 106 to go still even higher.
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Abstract
A high gain, very wide common mode range, self-biased operational amplifier comprising complementary differential transistor pairs biased by biasing transistors and current mirrors, and further comprising cascode transistors to provide a high amplifier output impedance, wherein the biasing transistors, current mirrors, and cascode transistors are all self-biased via negative feedback.
Description
Embodiments of the present invention relate to analog circuits, and more particularly, to operational amplifiers.
Many prior art CMOS (Complementary-Metal-Oxide-Semiconductor) operational amplifiers rely upon external biasing in order to bias in the saturation region various FETs (Field-Effect-Transistor) that serve as current sources (or active loads) in the operational amplifiers. However, external biasing may be sensitive to process technology, supply voltage, and temperature. Furthermore, because the overall gain and output resistance of an operational amplifier may both be very high and difficult to accurately model, the output node voltages for zero differential input voltage is very difficult to predict. In general, these node voltages should be at or near Vcc/2 for zero differential input voltage, where Vcc is the supply voltage.
Other prior art operational amplifiers have utilized various methods of self-biasing with negative feedback, so that the output node voltages are nominally at Vcc/2. However, for some of these prior art operational amplifiers, external biasing is not completely eliminated, and for others, some or all the FETs that serve as the current sources are biased in their linear region instead of their saturation region, resulting in reduced voltage gain. The present invention addresses these problems.
FIG. 1 is a circuit for an embodiment of the present invention.
FIG. 1 is a circuit for an embodiment of a high gain, very wide common mode range, self-biased operational amplifier. The operational amplifier of FIG. 1 may be considered a transconductance amplifier, in that a small-signal current is provided to a load in response to a differential voltage at input nodes 102 and 104. The load in FIG. 1 may be taken as the output resistance of transistor 5B in parallel with transistor 6B. The operational amplifier of FIG. 1 is self-biasing because no external biasing is needed.
Similarly, transistors 7A and 7B comprise a current mirror. Transistor 7A sources bias currents to transistors 2A and 5A, and transistor 7B sources bias currents to transistors 2B and 5B. Transistor 4 sinks bias current from the differential pair 2A and 2B. The bias current sunk by transistor 4 is equal in magnitude to the sum of the bias currents sourced by transistors 2A and 2B. When the voltage differential between nodes 102 and 104 is zero, transistors 7A and 7B source equal bias currents.
The gate of transistor 7A is connected to its drain, as well as to the gates of transistors 3 and 7B. Because the gate of transistor 7A is connected to its drain, it is biased in its saturation region as long as its gate-source voltage VGS is more negative than VTP, the pMOSFET threshold voltage. Consequently, transistors 3 and 7B are also biased in their saturation regions within a margin of VTP. Similarly, the gate of transistor 8A is connected to its drain, as well as to the gates of transistors 4 and 8B. Because the gate of transistor 8A is connected to its drain, it is biased in its saturation region as long as its gate-source voltage VGS is more positive than VTN, the nMOSFET threshold voltage. Consequently, transistors 4 and 8B are also biased in their saturation regions within a margin of VTN.
The complementary arrangement of the amplifier of FIG. 1 provides for a very wide common mode range of operation, as reasoned as follows. If the common mode input voltage is low such that transistors 2A and 2B are in cut-off, then transistors 1A and 1B will still be ON and will continue to amplify. Conversely, if the common mode input voltage is high such that transistors 1A and 1B are in cut-off, then transistors 2A and 2B will still be ON and will continue to amplify. In this way, the amplifier of FIG. 1 will provide amplification over a wide common mode input voltage range.
The self-biasing arrangement of the amplifier of FIG. 1 creates negative-feedback loops that stabilize the various bias voltages. Variations in processing parameters or operating conditions that shift the bias voltages away from their nominal values result in a shift in the bias voltages so as to be self-correcting.
Furthermore, the self-biasing arrangement of the embodiment of FIG. 1 also contributes to its differential gain, which may be heuristically argued as follows. Suppose input node 102 goes HIGH and input node 104 goes LOW. Small-signal current is drawn from nodes 108 and 110 by transistors 2A and lA, respectively, and small-signal current is injected into nodes 112 and 114 by transistors 2B and 1B, respectively. With small-signal current injected into nodes 112 and 114, more current will be sourced into transistor 5B, and less current will be sunk from transistor 6B, and as a result, node 106 will go HIGH. In addition, because small-signal current is drawn from nodes 108 and 110, these nodes go LOW. Because the gates of transistors 3 and 7B are connected to node 108, they conduct more strongly, thereby causing the voltage at node 106 to go even higher. Furthermore, because the gates of transistors 4 and 8B are connected to node 110, these transistors conduct more weakly, thereby also causing the voltage at node 106 to go still even higher.
Various modifications may be made to the described embodiments without departing from the scope of the invention as claimed below.
Claims (17)
1. An amplifier comprising:
a first differential pair comprising first and second transistors;
a first bias transistor to provide bias current to the first differential pair;
a first current mirror comprising first and second transistors to sink, respectively, currents from the first and second transistors of the first differential pair;
a second differential pair comprising first and second transistors;
a second bias transistor to sink current from the second differential pair; and
a second current mirror comprising first and second transistors to source, respectively, currents to the first and second transistors of the second differential pair;
wherein the second transistor of the second current mirror is coupled to be self-biased in its saturation region, and is coupled to bias the first transistor of the second current mirror and the first bias transistor.
2. The amplifier as set forth in claim 1, further comprising:
a first input node having a first input voltage; and
a second input node having a second input voltage; wherein
the second transistor of the second current mirror has a gate and a drain connected to each other, and the first transistor of the second current mirror and the first bias transistor have gates connected to the gate of the second transistor of the second current mirror;
the first and second transistors of the first differential pair are unipolar transistors of a first carrier type;
the first and second transistors of the second differential pair are unipolar transistors of a second carrier type complementary to the first carrier type;
the first transistors of the first and second differential pairs have gates coupled to the first input node to be responsive to the first input voltage; and
the second transistors of the first and second differential pairs have gates coupled to the second input node to be responsive to the second input voltage.
3. The amplifier as set forth in claim 1, wherein
the second transistor of the second current mirror has a gate and a drain connected to each other, and the first transistor of the second current mirror and the first bias transistor have gates connected to the gate of the second transistor of the second current mirror; and
the second transistor of the first current mirror has a gate and a drain connected to each other, and wherein the first transistor of the first current mirror and the second bias transistor have gates connected to the gate of the second transistor of the first current mirror.
4. The amplifier as set forth in claim 3, further comprising:
a first input node having a first input voltage; and
a second input node having a second input voltage; wherein
the first and second transistors of the first differential pair, the first bias transistor, and the first and second transistors of the second current mirror, are unipolar transistors of a first carrier type;
the first and second transistors of the second differential pair, the second bias transistor, and the first and second transistors of the first current mirror, are unipolar transistors of a second carrier type complementary to the first carrier type;
the first transistors of the first and second differential pairs have gates coupled to the first input node to be responsive to the first input voltage; and
the second transistors of the first and second differential pairs have gates coupled to the second input node to be responsive to the second input voltage.
5. The amplifier as set forth in claim 3, further comprising:
a first cascode transistor coupled to the first transistor of the first differential pair to form a folded-cascode pair;
a second cascode transistor coupled to the second transistor of the first differential pair to form a folded-cascode pair;
a third cascode transistor coupled to the first transistor of the second differential pair to form a folded-cascode pair; and
a fourth cascode transistor coupled to the second transistor of the second differential pair to form a folded-cascode pair, wherein
the fourth cascode transistor has a gate and a drain connected to each other;
the second cascode transistor has a gate and a drain connected to each other; and
the first, second, third, and fourth cascode transistors have their gates connected to each other.
6. The amplifier as set forth in claim 5, further comprising:
a first input node having a first input voltage;
a second input node having a second input voltage; and
an output node having an output voltage; wherein
the first and second transistors of the first differential pair, the first bias transistor, the first and second transistors of the second current mirror, and the third and fourth cascode transistors, are unipolar transistors of a first carrier type;
the first and second transistors of the second differential pair, the second bias transistor, the first and second transistors of the first current mirror, and the first and second cascode transistors, are unipolar transistors of a second carrier type complementary to the first carrier type;
the first transistors of the first and second differential pairs have gates coupled to the first input node to be responsive to the first input voltage;
the second transistors of the first and second differential pairs have gates coupled to the second input node to be responsive to the second input voltage; and
the first and third cascode transistors have drains coupled to the output node to provide the output voltage, wherein the output voltage is an amplified difference of the first and second input voltages.
7. An amplifier comprising:
a first differential pair comprising first and second transistors;
a first bias transistor to provide bias current to the first differential pair;
a first current mirror comprising first and second transistors to sink, respectively, drain currents from the first and second transistors of the first differential pair;
a second differential pair comprising first and second transistors;
a second bias transistor to sink current from the second differential pair; and
a second current mirror comprising first and second transistors to source, respectively, drain currents to the first and second transistors of the second differential pair;
wherein the second transistor of the second current mirror has a gate and a drain coupled to each other to be biased in its saturation region, and the first transistor of the second current mirror and the first bias transistor have gates coupled to the gate of the second transistor of the second current mirror to be biased in their saturation regions.
8. The amplifier as set forth in claim 7, further comprising:
a first input node having a first input voltage; and
a second input node having a second input voltage; wherein
the first and second transistors of the first differential pair are unipolar transistors of a first carrier type;
the first and second transistors of the second differential pair are unipolar transistors of a second carrier type complementary to the first carrier type;
the first transistors of the first and second differential pairs have gates coupled to the first input node to be responsive to the first input voltage; and
the second transistors of the first and second differential pairs have gates coupled to the second input node to be responsive to the second input voltage.
9. The amplifier as set forth in claim 7, wherein
the second transistor of the first current mirror has a gate and a drain coupled to each other to be biased in its saturation region, and wherein the first transistor of the first current mirror and the second bias transistor have gates coupled to the gate of the second transistor of the first current mirror to be biased in their saturation region.
10. The amplifier as set forth in claim 9, further comprising:
a first input node having a first input voltage; and
a second input node having a second input voltage; wherein
the first and second transistors of the first differential pair, the first bias transistor, and the first and second transistors of the second current mirror, are unipolar transistors of a first carrier type;
the first and second transistors of the second differential pair, the second bias transistor, and the first and second transistors of the first current mirror, are unipolar transistors of a second carrier type complementary to the first carrier type;
the first transistors of the first and second differential pairs have gates coupled to the first input node to be responsive to the first input voltage; and
the second transistors of the first and second differential pairs have gates coupled to the second input node to be responsive to the second input voltage.
11. The amplifier as set forth in claim 9, further comprising:
a first cascode transistor coupled to the first transistor of the first differential pair to form a folded-cascode pair;
a second cascode transistor coupled to the second transistor of the first differential pair to form a folded-cascode pair;
a third cascode transistor coupled to the first transistor of the second differential pair to form a folded-cascode pair; and
a fourth cascode transistor coupled to the second transistor of the second differential pair to form a folded-cascode pair; wherein
the fourth cascode transistor has a gate and a drain coupled to each other so as to be self-biased;
the second cascode transistor has a gate and a drain coupled to each other so as to be self-biased; and
the first, second, third, and fourth cascode transistors have their gates coupled to each other so as to be self-biased.
12. The amplifier as set forth in claim 11, further comprising:
a first input node having a first input voltage;
a second input node having a second input voltage; and
an output node having an output voltage; wherein
the first and second transistors of the first differential pair, the first bias transistor, the first and second transistors of the second current mirror, and the third and fourth cascode transistors, are unipolar transistors of a first carrier type;
the first and second transistors of the second differential pair, the second bias transistor, the first and second transistors of the first current mirror, and the first and second cascode transistors, are unipolar transistors of a second carrier type complementary to the first carrier type;
the first transistors of the first and second differential pairs have gates coupled to the first input node to be responsive to the first input voltage;
the second transistors of the first and second differential pairs have gates coupled to the second input node to be responsive to the second input voltage; and
the first and third cascode transistors have drains coupled to the output node to provide the output voltage, wherein the output voltage is an amplified difference of the first and second input voltages.
13. An amplifier comprising:
a first differential transistor pair;
a first bias transistor to source bias current to the first differential transistor pair;
a first current mirror comprising first and second transistors to sink bias current from the first differential transistor pair;
a first cascode transistor coupled to the first differential transistor pair to form a folded-cascode pair;
a second cascode transistor coupled to the first differential pair to form a folded-cascode pair;
a second differential transistor pair;
a second bias transistor to sink bias current from the second differential transistor pair;
a second current mirror comprising first and second transistors to source bias current to the second differential transistor pair;
a third cascode transistor coupled to the second differential transistor pair to form a folded-cascode pair; and
a fourth cascode transistor coupled to the second differential pair to form a folded-cascode pair; wherein
the second and fourth cascode transistors are coupled to be biased in saturation, and are coupled to bias the first and third cascode transistors;
the second transistor of the first current mirror is coupled to be biased in saturation, and is coupled to bias the first transistor of the first current mirror and the second bias transistor; and
the second transistor of the second current mirror is coupled to be biased in saturation, and is coupled to bias the first transistor of the second current mirror and the first bias transistor.
14. The amplifier as set forth in claim 13, wherein
the first differential pair comprises first and second transistors;
the second differential pair comprises first and second transistors;
the first and second transistors of the first differential pair, the first bias transistor, the first and second transistors of the second current mirror, and the third and fourth cascode transistors are field-effect-transistors having a first carrier type; and
the first and second transistors of the second differential pair, the second bias transistor, the first and second transistors of the first current mirror, and the first and second cascode transistors are field-effect-transistors having a second carrier type complementary to the first carrier type.
15. An operational amplifier to provide an output voltage as an amplified output of a differential of first and second input voltages, the operational amplifier comprising:
a first input node at the first input voltage;
a second input node at the second input voltage;
a first pFET comprising a source, a drain, and a gate coupled to the first input node to be responsive to the first input voltage;
a first nFET comprising a gate, and a drain coupled to the drain of the first pFET to sink current from the first pFET;
a second nFET comprising a source, a drain, and a gate coupled to the second input node to be responsive to the second input voltage;
a second pFET comprising a gate, and a drain coupled to the drain of the second nFET to source current to the second nFET, wherein the gate and drain of the second pFET are coupled to each other to have substantially the same voltage; and
a third pFET comprising a gate, and a drain coupled to the source of the first pFET to source current to the first pFET, wherein the gates of the third pFET and second pFET are coupled to each other to have substantially the same voltage.
16. The operational amplifier as set forth in claim 15, further comprising:
a third nFET comprising a source, a drain, and a gate coupled to the first input node to be responsive to the first input voltage;
a fourth pFET comprising a gate, wherein the gates of the fourth pFET and second pFET are coupled to each other to have substantially the same voltage, and comprising a drain coupled to the drain of the third nFET to source current to the third nFET;
a fifth pFET comprising a gate coupled to the second input node to be responsive to the second input voltage, a source coupled to the drain of the third pFET to sink current from the third pFET, and a drain;
a fourth nFET comprising a gate and a drain, wherein the gate and drain of the fourth nFET are coupled to each other to have substantially the same voltage, wherein the gates of the fourth nFET and first nFET are coupled to each other to have substantially the same voltage, and the drain of the fourth nFET is coupled to the drain of the fifth pFET to sink current from the fifth pFET; and
a fifth nFET comprising a gate, wherein the gates of the fifth nFET and fourth nFET are coupled to each other to have substantially the same voltage, and comprising a drain coupled to the sources of the second nFET and third nFET to sink current from the second nFET and third nFET.
17. The operational amplifier as set forth in claim 16, further comprising:
a sixth pFET comprising a source coupled to the drain of the second pFET to sink current from the second pFET, a gate, and a drain, wherein the gate and drain of the sixth pFET are coupled to each other to have substantially the same voltage;
a sixth nFET comprising a gate and a drain coupled to each other to have substantially the same voltage, wherein the gates of the sixth nFET and sixth pFET are coupled to each other to have substantially the same voltage, and comprising a drain coupled to the drain of the sixth pFET to sink current from the sixth pFET, and a source coupled to the drain of the fourth nFET to source current to the fourth nFET;
a seventh pFET comprising a source coupled to the drain of the fourth pFET to sink current from the fourth pFET, comprising a gate, wherein the gates of the seventh pFET and sixth pFET are coupled to each other to have substantially the same voltage, and comprising a drain coupled to the output node; and
a seventh nFET comprising a gate, wherein the gates of the seventh nFET and sixth pFET are coupled to each other to have substantially the same voltage, and comprising a drain coupled to the drain of the seventh pFET to sink current from the seventh pFET, and a source coupled to the drain of the first nFET to source current to the first nFET.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/547,748 US6278323B1 (en) | 2000-04-12 | 2000-04-12 | High gain, very wide common mode range, self-biased operational amplifier |
| CN01811059A CN1436400A (en) | 2000-04-12 | 2001-03-29 | High-gain, very wide common mode range, self biased operational amplifier |
| EP01924523A EP1275199A2 (en) | 2000-04-12 | 2001-03-29 | High-gain, very wide common mode range, self biased operational amplifier |
| PCT/US2001/010381 WO2001076346A2 (en) | 2000-04-12 | 2001-03-29 | High-gain, very wide common mode range, self biased operational amplifier |
| AU2001251171A AU2001251171A1 (en) | 2000-04-12 | 2001-03-29 | High-gain, very wide common mode range, self biased operational amplifier |
| HK03102195.6A HK1050085A1 (en) | 2000-04-12 | 2003-03-26 | High-gain, very wide common mode range, self biased operational amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/547,748 US6278323B1 (en) | 2000-04-12 | 2000-04-12 | High gain, very wide common mode range, self-biased operational amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US6278323B1 true US6278323B1 (en) | 2001-08-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/547,748 Expired - Lifetime US6278323B1 (en) | 2000-04-12 | 2000-04-12 | High gain, very wide common mode range, self-biased operational amplifier |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6278323B1 (en) |
| EP (1) | EP1275199A2 (en) |
| CN (1) | CN1436400A (en) |
| AU (1) | AU2001251171A1 (en) |
| HK (1) | HK1050085A1 (en) |
| WO (1) | WO2001076346A2 (en) |
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|---|---|---|---|---|
| US6525608B2 (en) * | 2001-03-27 | 2003-02-25 | Intel Corporation | High gain, high bandwidth, fully differential amplifier |
| US20040006041A1 (en) * | 2002-05-24 | 2004-01-08 | Dorla Mirejovsky | Aqueous fludarabine phosphate composition |
| US6822513B1 (en) | 2003-05-28 | 2004-11-23 | Ami Semiconductor, Inc. | Symmetric and complementary differential amplifier |
| US6930550B1 (en) | 2004-04-26 | 2005-08-16 | Pericom Semiconductor Corp. | Self-biasing differential buffer with transmission-gate bias generator |
| US20060014514A1 (en) * | 2004-07-13 | 2006-01-19 | Chiung-Ting Ou | Self-biased high-speed receiver |
| US20060139066A1 (en) * | 2004-12-28 | 2006-06-29 | Samsung Electronics Co., Ltd. | Input buffer circuit having a differential amplifier structure |
| CN103825559A (en) * | 2014-03-03 | 2014-05-28 | 西安华芯半导体有限公司 | High-speed RCV biasing system |
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| JP4761458B2 (en) * | 2006-03-27 | 2011-08-31 | セイコーインスツル株式会社 | Cascode circuit and semiconductor device |
| US9306509B2 (en) * | 2012-07-27 | 2016-04-05 | Xilinx, Inc. | Receiver having a wide common mode input range |
| CN103618506A (en) * | 2013-11-27 | 2014-03-05 | 苏州贝克微电子有限公司 | Common-emitter amplifier operating in multiple power supplies |
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| US5337008A (en) * | 1993-02-25 | 1994-08-09 | Hewlett-Packard Corporation | High gain rail-to-rail CMOS amplifier |
| US5963053A (en) * | 1997-10-09 | 1999-10-05 | Pericom Semiconductor Corp. | Self-biasing CMOS PECL receiver with wide common-mode range and multi-level-transmit to binary decoder |
| US6052025A (en) * | 1997-07-29 | 2000-04-18 | Samsung Electronics Co., Ltd. | CMOS operational amplifiers having reduced power consumption requirements and improved phase margin characteristics |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4284959A (en) * | 1979-11-13 | 1981-08-18 | Rca Corporation | Folded-cascode amplifier arrangement with cascode load means |
-
2000
- 2000-04-12 US US09/547,748 patent/US6278323B1/en not_active Expired - Lifetime
-
2001
- 2001-03-29 CN CN01811059A patent/CN1436400A/en active Pending
- 2001-03-29 EP EP01924523A patent/EP1275199A2/en not_active Withdrawn
- 2001-03-29 WO PCT/US2001/010381 patent/WO2001076346A2/en not_active Application Discontinuation
- 2001-03-29 AU AU2001251171A patent/AU2001251171A1/en not_active Abandoned
-
2003
- 2003-03-26 HK HK03102195.6A patent/HK1050085A1/en unknown
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| US6052025A (en) * | 1997-07-29 | 2000-04-18 | Samsung Electronics Co., Ltd. | CMOS operational amplifiers having reduced power consumption requirements and improved phase margin characteristics |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6525608B2 (en) * | 2001-03-27 | 2003-02-25 | Intel Corporation | High gain, high bandwidth, fully differential amplifier |
| US20040006041A1 (en) * | 2002-05-24 | 2004-01-08 | Dorla Mirejovsky | Aqueous fludarabine phosphate composition |
| US6822513B1 (en) | 2003-05-28 | 2004-11-23 | Ami Semiconductor, Inc. | Symmetric and complementary differential amplifier |
| US6930550B1 (en) | 2004-04-26 | 2005-08-16 | Pericom Semiconductor Corp. | Self-biasing differential buffer with transmission-gate bias generator |
| US20060014514A1 (en) * | 2004-07-13 | 2006-01-19 | Chiung-Ting Ou | Self-biased high-speed receiver |
| US7349681B2 (en) | 2004-07-13 | 2008-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-biased high-speed receiver |
| US20060139066A1 (en) * | 2004-12-28 | 2006-06-29 | Samsung Electronics Co., Ltd. | Input buffer circuit having a differential amplifier structure |
| JP2006191572A (en) * | 2004-12-28 | 2006-07-20 | Samsung Electronics Co Ltd | Input buffer circuit |
| US7262651B2 (en) * | 2004-12-28 | 2007-08-28 | Samsung Electronics Co., Ltd. | Differential input buffer circuit with rail-to-rail input range |
| CN103825559A (en) * | 2014-03-03 | 2014-05-28 | 西安华芯半导体有限公司 | High-speed RCV biasing system |
Also Published As
| Publication number | Publication date |
|---|---|
| HK1050085A1 (en) | 2003-06-06 |
| WO2001076346A2 (en) | 2001-10-18 |
| EP1275199A2 (en) | 2003-01-15 |
| CN1436400A (en) | 2003-08-13 |
| AU2001251171A1 (en) | 2001-10-23 |
| WO2001076346A3 (en) | 2002-05-23 |
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