[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

US6245682B1 - Removal of SiON ARC film after poly photo and etch - Google Patents

Removal of SiON ARC film after poly photo and etch Download PDF

Info

Publication number
US6245682B1
US6245682B1 US09/266,374 US26637499A US6245682B1 US 6245682 B1 US6245682 B1 US 6245682B1 US 26637499 A US26637499 A US 26637499A US 6245682 B1 US6245682 B1 US 6245682B1
Authority
US
United States
Prior art keywords
layer
polysilicon
sion
angstroms
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/266,374
Inventor
Chu-Yun Fu
Syun-Ming Jang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US09/266,374 priority Critical patent/US6245682B1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FU, CHU-YUN, JANG, SYUN-MING
Application granted granted Critical
Publication of US6245682B1 publication Critical patent/US6245682B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/952—Utilizing antireflective layer

Definitions

  • This invention relates to the fabrication of integrated circuit devices and more particularly to a method for using a wet etch process to remove an anti-reflective coating (ARC), made from silicon oxynitride (S i ON), after the ARC has been used to enhance the photolithograpic definition of sub-micron polysilicon gate structures.
  • ARC anti-reflective coating
  • S i ON silicon oxynitride
  • the main problem addressed by this invention is the need to avoid severe polysilicon attack from the wet etch step, when hot phosphoric acid (H 3 P 0 4 ) is used as the etchant.
  • anti-reflective coatings can be a very effective means of minimizing photoresist exposure problems that would, otherwise, be aggravated by the high reflectivity of underlying wafer surfaces.
  • photons that are reflected back up into the resist layer, at angles other than 90 degrees can lead to distorted images.
  • Scattered photons from rough underlying surfaces can lead to a general reduction in image contrast.
  • scattered photons from underlying steps can lead to notched images.
  • Even for the more ideal case of 90 degree reflection from a smooth flat underlying surface the resultant standing wave pattern in the resist layer can also lead to a reduction in image contrast.
  • ARC anti-reflective coating
  • the ARC may be in the form of a highly absorbing layer, such as a polymer, or a thin layer of titanium (Ti) or silicon oxynitride (SiON), for example.
  • Ti titanium
  • SiON silicon oxynitride
  • the optical properties of ARCs should be optically optimized with any underlying layers, the overlying photoresist layer and the wavelength of the exposure source. Consequently, S i ON layers, by virtue of having process controllable optical properties, have become particularly attractive as ARCs.
  • ARCs have been used in the form of localized as well as blanket layers which may or may not be deliberatly removed during subsequent processing.
  • a method is taught for the removal of a blanket SiON layer after it has been used as an ARC for improving the image control of sub-micron polysilicon gates.
  • SiON is not totally devoid of its own problems, as addressed in the following patent by Tsukamoto, et. al.
  • U.S. Pat. No. 5,600,165 to Tsukamoto, et. al. teaches a method for using SiON as an ARC while also avoiding a device degradation problem associated With the hydrogen that is contained within the SiON film.
  • SiON is used as an ARC to improve the image definition of a sub-micron polysilicon gate, for example, and then allowed to remain during subsequent hot processing
  • hydrogen in the SiON film can diffuse down through the underlying polysilicon and gate oxide. Once the hydrogen reaches the gate oxide, its resistance to hot carrier damage can be reduced and this can, in turn, lead to unacceptable device threshold voltage instability.
  • This invention addresses the formation of via holes down to the underlying conductive regions of devices, while avoiding the problem of damaging the conductive regions, such as aluminum or titanium silicide, for example.
  • the etching means includes a fluoride-containing gas, along with a passivating gas (such as nitrogen), which is used to suppress sputtering damage of the underlying conductive regions.
  • a passivating gas such as nitrogen
  • a principle object of the present invention is to provide an effective and manufacturable method to photolithographically define sub-micron polysilicon gate features, over a semiconductor substrate.
  • Another object of the present invention is to provide an improved method for using anti-reflective coatings (ARCs), as an improved means of avoiding the problem of distorted photoresist images due to spurious reflections from the underlying semiconductor substrate, during the photolithographic definition of sub-micron polysilicon gates.
  • ARCs anti-reflective coatings
  • a further object of the invention is to provide a method for: (1) Using silicon oxynitride (SiON) layers as ARCs on blanket polysilicon layers, to be formed into sub-micron gate features, and (2) Subsequently, removing the remaining SON without imparting any associated etching damage to the surface of the newly formed polysilicon gate features.
  • SiON silicon oxynitride
  • a still further and primary object of the present invention is to provide a method for using hot H 3 PO 4 acid as the means of removing the S i ON based, ARC, while preventing the serious etching damage that can occur when polysilicon is exposed to hot H 3 PO 4 .
  • a fabrication method which uses thin oxide layers to the protect the top surface and side wall regions of the polysilicon gates from being severely attacked by hot H 3 PO 4 , comprising the steps of: (a) forming a thin protective layer of thermal silicon oxide over a blanket polysilicon layer for the purpose of protecting the polysilicon surface from direct exposure to the hot H 3 PO 4 , which will be used during an eventual S i ON, ARC removal step; (b) forming a thin SION ARC over the thin protective thermal oxide layer; (c) using a photolithography and dry etching process to form sub-micron polysilicon gate features; (d) forming a second thin thermal oxide layer on the exposed side walls of the newly formed polysilicon gate features for the purpose of protecting the polysilicon side walls from eventual direct exposure to hot H 3 PO 4 etching step; (e) removal of the S i ON ARC on the top surface of the polysilicon gates, by means of a hot H 3 PO 4 wet etch process; and (f) removal of the thin oxide layers to the
  • the present invention solves the above problems by, primarily, using thin oxide layers to protect the top and side wall surfaces of polysilicon gates, before a hot H 3 PO 3 etching process is used to subsequently remove a SiON ARC.
  • This is accomplished by a new method to fabricate polysilicon gate structures.
  • This new method features: (1) A thin protective thermal oxide layer between the SiON ARC and the polysilicon surface, (2) A subsequent second thin protective oxide layer that is grown on the side walls of newly formed polysilicon gates and (3) The ability to tailor the combination of the composition and thickness of the SiON layer and the thickness of the underlying protective thin thermal oxide layer, in order to minimize the undesired high optical reflectivity of the underlying polysilicon surface.
  • FIGS. 1 to 5 schematically illustrate in cross-sectional representation the preferred embodiments of the process of the present invention.
  • Hot H 3 PO 4 etching is a very effective means for the removal of S i ON on the surface of newly formed polysilicon gates.
  • the undesired etching of any exposed thermal gate oxide (S i O 2 ) around the side walls of the gates, will be at least ⁇ 100 ⁇ slower than that of S i ON.
  • hot H 3 PO 4 can severely attack any exposed polysilicon surfaces, such as the top surface and side wall areas.
  • SiON layers can be rich in hydrogen that can subsequently diffuse down into gate oxide regions and, thereby, result in reduced resistance to hot carrier induced device degradation. Therefore, a solution is still needed for how to use hot H 3 PO 4 to remove S i ON layers from the surface of newly formed sub-micron polysilicon gate features, after the SiON layers have served their temporary purpose as ARCs.
  • FIG. 1 there is shown a portion of a partially completed integrated circuit.
  • a semiconductor substrate 2 intended to represent a conventional ion implanted N well or P well region, in which an eventual CMOS narrow channel FET will be formed.
  • an overlying stack consisting of a gate oxide layer 4 , an overlying polysilicon layer 6 .
  • Said gate oxide 4 is a thin thermal oxide, with a typical thickness range of about 20 to 60 Angstroms.
  • a preferred gate oxide thickness of about 32 angstroms is grown in a steam ambient at temperature of about 700 to 1000 degrees Centigrade for a duration of about 10 to 40 mins.
  • said polysilicon layer 6 is preferably deposited, by means of Low Pressure Chemical Vapor Deposition, LPCVD, to a typical thickness range of about 1500 to 2500 Angstroms, with a preferred thickness of about 2000 Angstroms.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • said overlying SiON ARC layer 10 is typically grown to a thickness of about 250 to 350 Angstroms, with a preferred thickness of about 300 Angstroms.
  • Said SiON ARC layer 10 is typically formed by means of a PECVD process.
  • Such SiON ARC films have been characterized, for a deep ultraviolet, DUV, wavelength of about 320 A, and found to exhibit a complex refractive index having a real part, n, equal to about 2.12 and an imaginary part, k, equal to about 0.65.
  • photoresist island 12 is formed from a conventional DUV process, consisting of organic polymeric materials and resulting in typical photoresist layer thickness values of about 4000 to 6000 Angstroms.
  • conventional plasma etching such as Cl 2 /HBr. based chemistry, is now performed on the stack, consisting of said S i ON ARC layer 10 , said underlying thermal oxide layer 8 and said further underlying polysilicon layer 6 , in order to define polysilicon gate feature 14 .
  • photoresist island 12 is removed by a conventional photoresist stripping means, such as H 2 SO 4 +H 2 O 2 .
  • the still further underlying gate oxide layer 4 acts as an etch stop for said plasma etching process.
  • a second thin protective thermal oxide 16 is now formed on the side walls of newly formed polysilicon gate feature 14 .
  • Said oxide layer 16 in concert with said first protective oxide layer 8 , will be used to protect the, otherwise, exposed top and side wall surfaces of said polysilicon gate feature 14 from being attacked during a subsequent hot H 3 PO 3 etching step for the removal of said S i ON ARC layer 10 .
  • These two aforementioned thin protective oxide layers ( 8 and 16 ) are the key to this invention.
  • Said second protective oxide layer 16 is thermally grown to a thickness of about 20 to 50 angstroms, with a preferred thickness of about 30 Angstroms.
  • said S i ON ARC layer 10 is now removed by means of a hot H 3 PO 3 etching process.
  • the solution is maintained at a bath temperature of about 100 to 150 degrees, Fahrenheit, and an etching time of about 600 seconds is used to remove a typical S i ON ARC layer thickness of about 320 Angstroms.
  • etching time of about 600 seconds is used to remove a typical S i ON ARC layer thickness of about 320 Angstroms.
  • conventional dilute hydrofluoric acid (50:1) etching is now used to remove said first protective oxide layer 8 and said second protective oxide layer 16 , in preparation for silicidation of the resultant polysilicon gate 6 feature 18 and other subsequent conventional process steps that may be needed for the completion of a given sub-micron FET device.
  • the typical etching time is about one minute. This relatively short etching time results in minimal removal of the gate oxide 4 under the polysilicon gate 6 , as shown in FIG. 5 .
  • a critical dimension (CD) control problem has been solved by using a S i ON ARC as a means of minimizing spurious reflected photons from leading to distorted photoresist images, during the photolithographic exposure step used for defining sub-micron polysilicon gates.
  • the key to this invention is a solution to the consequent problem, that was created, after having choosen hot H 3 PO 4 as the etchant for the removal of S i ON, with regard to how to subsequently remove the SiON ARC in a manner that would not result in unacceptable attack of the gate oxide or of the polysilicon gate surfaces.
  • hot H 3 PO 4 instead of a hydrofluoric acid solution

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

This invention relates to the fabrication of integrated circuit devices and more particularly to a method for forming and then later removing a silicon oxynitride, SiON, anti-reflection coating (ARC) over a semiconductor substrate, for the purpose of enhancing the resolution of photolithographically defined sub-micron polysilicon gates. The problem addressed by this invention is that the SiON ARC must first be used to reduce optical reflection from a blanket polysilicon surface, during the photolithography exposure step that defines the sub-micron polysilicon gate features, and then the ARC must be removed by a wet etch process that will not chemically attack the gate oxide under the polysilicon gate features or any exposed polysilicon surfaces. This is accomplished with a fabrication method that uses hot phosphoric acid (H3PO4) to preferentially etch the SiON ARC, relative to the thermal gate oxide, while also using thin thermal oxide layers to protect the polysilicon gate surfaces from being severely attacked by the hot H3PO4. This new method also features the ability to tailor the combination of the composition and thickness of the SiON layer and the thickness of the underlying protective thin thermal oxide layer, in order to minimize the undesired high optical reflectivity of the underlying polysilicon surface.

Description

FIELD OF THE INVENTION
This invention relates to the fabrication of integrated circuit devices and more particularly to a method for using a wet etch process to remove an anti-reflective coating (ARC), made from silicon oxynitride (SiON), after the ARC has been used to enhance the photolithograpic definition of sub-micron polysilicon gate structures. The main problem addressed by this invention is the need to avoid severe polysilicon attack from the wet etch step, when hot phosphoric acid (H3P0 4) is used as the etchant.
BACKGROUND OF THE INVENTION AND PRIOR ART
As the demand to push semiconductor device features deeper into the sub-micron range has increased, numerous techniques have been developed for extending the ability of photolithograpic processes to define increasingly smaller image sizes. Since the 1970's the resolution limits of optical lithography have been reduced from about 1.5 microns down to about 0.2 microns and lower. Advancements, such as shorter exposure wavelengths, variable numerical aperture exposure lenses and phase shift masks, have contributed greatly to the progress that has occurred. In concert, anti-reflective coatings (ARC) have increasingly been incorporated into semiconductor process sequences, as a means of further enhancing critical dimension (CD) control during sub-micron photolithography steps. The use of such anti-reflective coatings can be a very effective means of minimizing photoresist exposure problems that would, otherwise, be aggravated by the high reflectivity of underlying wafer surfaces. During a photoresist exposure operation, photons that are reflected back up into the resist layer, at angles other than 90 degrees, can lead to distorted images. Scattered photons from rough underlying surfaces can lead to a general reduction in image contrast. Furthermore, scattered photons from underlying steps can lead to notched images. Even for the more ideal case of 90 degree reflection from a smooth flat underlying surface, the resultant standing wave pattern in the resist layer can also lead to a reduction in image contrast. These image control problems can occur when photoresist layers are exposed over reflective surfaces such as aluminum and polysilicon, for example. These problems can be greatly minimized by first depositing an anti-reflective coating, (ARC) prior to the application of the photoresist layer. The ARC may be in the form of a highly absorbing layer, such as a polymer, or a thin layer of titanium (Ti) or silicon oxynitride (SiON), for example. Ideally, to help minimize reflectivity, the optical properties of ARCs should be optically optimized with any underlying layers, the overlying photoresist layer and the wavelength of the exposure source. Consequently, SiON layers, by virtue of having process controllable optical properties, have become particularly attractive as ARCs.
When SiON is deposited by CVD, for example, its optical properties can be adjusted by changing the atomic composition of the film.
There are numerous methodologies used for employing ARCs. ARCs have been used in the form of localized as well as blanket layers which may or may not be deliberatly removed during subsequent processing. In the case of the present invention, a method is taught for the removal of a blanket SiON layer after it has been used as an ARC for improving the image control of sub-micron polysilicon gates. Although quite advantageous from the standpoint of having adjustable optical properties, SiON as an ARC, however, is not totally devoid of its own problems, as addressed in the following patent by Tsukamoto, et. al.
U.S. Pat. No. 5,600,165 to Tsukamoto, et. al., teaches a method for using SiON as an ARC while also avoiding a device degradation problem associated With the hydrogen that is contained within the SiON film. When SiON is used as an ARC to improve the image definition of a sub-micron polysilicon gate, for example, and then allowed to remain during subsequent hot processing, hydrogen in the SiON film can diffuse down through the underlying polysilicon and gate oxide. Once the hydrogen reaches the gate oxide, its resistance to hot carrier damage can be reduced and this can, in turn, lead to unacceptable device threshold voltage instability. The patent of Tsukamoto et.al., teaches several methods to solve this potential hydrogen related problem, by means of creating hydrogen diffusion barriers (such as thin layers of silicon nitride of titanium silicide) between the SiON ARC and the gate oxide region of active devices. However, since the inventors deliberately left the SiON layer on after it was used as an ARC, no method was taught for how to remove it.
There have been prior publications that do discuss methods for the removal of SiON layers. U.S. Pat. No. 5,741,396, to Loewenstein, teaches dry isotropic etching methods for the removal of nitride, oxynitride and polysilicon layers, while not removing thin pad oxide layers that are used to protect underlying silicon regions from being attacked at the same time. The invention also discusses the use of hot phosphoric acid (H3PO4), as a wet etching means of removing nitride and oxynitride films, in conjunction with thin pad oxides to protect underlying silicon regions. However, a method for the formation and wet etch removal of a SiON film and thin pad oxide combination that have been optimized as an ARC for the photolithographic definition of polysilicon gates is not addressed.
U.S. Pat. No. 5,269,879, to Rhoades, et. al., also teaches methodologies for the dry etching of insulating films, such as silicon dioxide, silicon nitride and silicon oxynitride. This invention addresses the formation of via holes down to the underlying conductive regions of devices, while avoiding the problem of damaging the conductive regions, such as aluminum or titanium silicide, for example. The etching means includes a fluoride-containing gas, along with a passivating gas (such as nitrogen), which is used to suppress sputtering damage of the underlying conductive regions. However, similar to the above prior art, a method for the formation and wet etch removal of a SiON film and thin pad oxide combination that have been optimized as an ARC, for the photolithographic definition of polysilicon gates, is not addressed.
SUMMARY OF THE INVENTION
A principle object of the present invention is to provide an effective and manufacturable method to photolithographically define sub-micron polysilicon gate features, over a semiconductor substrate.
Another object of the present invention is to provide an improved method for using anti-reflective coatings (ARCs), as an improved means of avoiding the problem of distorted photoresist images due to spurious reflections from the underlying semiconductor substrate, during the photolithographic definition of sub-micron polysilicon gates.
A further object of the invention is to provide a method for: (1) Using silicon oxynitride (SiON) layers as ARCs on blanket polysilicon layers, to be formed into sub-micron gate features, and (2) Subsequently, removing the remaining SON without imparting any associated etching damage to the surface of the newly formed polysilicon gate features.
A still further and primary object of the present invention is to provide a method for using hot H3PO4 acid as the means of removing the SiON based, ARC, while preventing the serious etching damage that can occur when polysilicon is exposed to hot H3PO4.
These objects are achieved by a fabrication method which uses thin oxide layers to the protect the top surface and side wall regions of the polysilicon gates from being severely attacked by hot H3PO4, comprising the steps of: (a) forming a thin protective layer of thermal silicon oxide over a blanket polysilicon layer for the purpose of protecting the polysilicon surface from direct exposure to the hot H3PO4, which will be used during an eventual SiON, ARC removal step; (b) forming a thin SION ARC over the thin protective thermal oxide layer; (c) using a photolithography and dry etching process to form sub-micron polysilicon gate features; (d) forming a second thin thermal oxide layer on the exposed side walls of the newly formed polysilicon gate features for the purpose of protecting the polysilicon side walls from eventual direct exposure to hot H3PO4 etching step; (e) removal of the SiON ARC on the top surface of the polysilicon gates, by means of a hot H3PO4 wet etch process; and (f) removal of the thin protective oxide layers on the top surface and side wall areas of the polysilicon gates, by means of a dilute hydrofluoric acid wet etch process, followed by completion of sub-micron field effect devices.
The present invention solves the above problems by, primarily, using thin oxide layers to protect the top and side wall surfaces of polysilicon gates, before a hot H3PO3 etching process is used to subsequently remove a SiON ARC. This is accomplished by a new method to fabricate polysilicon gate structures. This new method features: (1) A thin protective thermal oxide layer between the SiON ARC and the polysilicon surface, (2) A subsequent second thin protective oxide layer that is grown on the side walls of newly formed polysilicon gates and (3) The ability to tailor the combination of the composition and thickness of the SiON layer and the thickness of the underlying protective thin thermal oxide layer, in order to minimize the undesired high optical reflectivity of the underlying polysilicon surface.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings for a material part of this description, there is shown:
FIGS. 1 to 5 schematically illustrate in cross-sectional representation the preferred embodiments of the process of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
This invention provides a method for solving the problem of using hot H3PO4 to remove SiON ARCs after they have been used to improve the critical dimension (CD) control of sub-micron polysilicon gates. Hot H3PO4 etching is a very effective means for the removal of SiON on the surface of newly formed polysilicon gates. The undesired etching of any exposed thermal gate oxide (SiO2) around the side walls of the gates, will be at least ˜100× slower than that of SiON. However, hot H3PO4can severely attack any exposed polysilicon surfaces, such as the top surface and side wall areas. Consequently, if an ARC of SiON has been directly deposited on a blanket polysilicon surface, prior to defining polysilicon gate features, both the top surface and the side walls of the eventual polysilicon gate features will be exposed to severe attack by the subsequent hot H3PO4 etching process that is used for the removal of the remaining SiON layer. In some cases, one may be able to avoid this problem by simply allowing the SiON layer to permanently remain on the polysilicon surface. However, leaving the SiON layer in place is not always a viable solution. For example, this would not allow for the subsequent silicidation of the polysilicon gates, in order to meet device performance (switching speed) requirements. In addition, SiON layers can be rich in hydrogen that can subsequently diffuse down into gate oxide regions and, thereby, result in reduced resistance to hot carrier induced device degradation. Therefore, a solution is still needed for how to use hot H3PO4 to remove SiON layers from the surface of newly formed sub-micron polysilicon gate features, after the SiON layers have served their temporary purpose as ARCs.
It is noted that the following preferred embodiments and associated figures will be presented in a way that can be generically applied to the fabrication of a variety of N channel and/or the P channel device technologies that could employ sub-micron polysilicon gates. Referring now more particularly to FIG. 1, there is shown a portion of a partially completed integrated circuit. There is shown a semiconductor substrate 2 intended to represent a conventional ion implanted N well or P well region, in which an eventual CMOS narrow channel FET will be formed. Also shown is an overlying stack consisting of a gate oxide layer 4, an overlying polysilicon layer 6. a further overlying thermal SiO2 layer 8, a still further overlying SiON ARC layer 10 and, finally, a photoresist island 12 that will be used to define a sub-micron polysilicon gate feature. It is noted that the image control of said photoresist island 12, has been enhanced by using said underlying ARC layer 10, in order to reduce the intensity of photons, reflected from said polysilicon layer 6, that would have, otherwise, tended to distort the desired sub-micron geometry of said resist layer 12. Such distortions would tend to be increasingly worse for desired gate dimensions of 0.25 microns or less.
Said gate oxide 4 is a thin thermal oxide, with a typical thickness range of about 20 to 60 Angstroms. A preferred gate oxide thickness of about 32 angstroms is grown in a steam ambient at temperature of about 700 to 1000 degrees Centigrade for a duration of about 10 to 40 mins.
Still referring to FIG. 1, said polysilicon layer 6 is preferably deposited, by means of Low Pressure Chemical Vapor Deposition, LPCVD, to a typical thickness range of about 1500 to 2500 Angstroms, with a preferred thickness of about 2000 Angstroms.
Continuing to refer to FIG. 1, said overlying SiON ARC layer 10 is typically grown to a thickness of about 250 to 350 Angstroms, with a preferred thickness of about 300 Angstroms. Said SiON ARC layer 10 is typically formed by means of a PECVD process. Such SiON ARC films have been characterized, for a deep ultraviolet, DUV, wavelength of about 320 A, and found to exhibit a complex refractive index having a real part, n, equal to about 2.12 and an imaginary part, k, equal to about 0.65.
Continuing to refer to FIG. 1, photoresist island 12 is formed from a conventional DUV process, consisting of organic polymeric materials and resulting in typical photoresist layer thickness values of about 4000 to 6000 Angstroms. Referring now more particularly to FIG. 2, conventional plasma etching, such as Cl2/HBr. based chemistry, is now performed on the stack, consisting of said Si ON ARC layer 10, said underlying thermal oxide layer 8 and said further underlying polysilicon layer 6, in order to define polysilicon gate feature 14. Following said plasma etching, for defining polysilicon gate feature 14, photoresist island 12 is removed by a conventional photoresist stripping means, such as H2SO4+H2O2. As also shown in FIG. 2, the still further underlying gate oxide layer 4, acts as an etch stop for said plasma etching process.
Referring now more particularly to FIG. 3, a second thin protective thermal oxide 16, is now formed on the side walls of newly formed polysilicon gate feature 14. Said oxide layer 16, in concert with said first protective oxide layer 8, will be used to protect the, otherwise, exposed top and side wall surfaces of said polysilicon gate feature 14 from being attacked during a subsequent hot H3PO3 etching step for the removal of said Si ON ARC layer 10. These two aforementioned thin protective oxide layers (8 and 16), are the key to this invention. Said second protective oxide layer 16, is thermally grown to a thickness of about 20 to 50 angstroms, with a preferred thickness of about 30 Angstroms.
Referring now more particularly to FIG. 4, said Si ON ARC layer 10 is now removed by means of a hot H3PO3 etching process. For the hot H3PO3 process, the solution is maintained at a bath temperature of about 100 to 150 degrees, Fahrenheit, and an etching time of about 600 seconds is used to remove a typical SiON ARC layer thickness of about 320 Angstroms. These conditions yield typical etch rates, for SiON, of about 50 angstroms/min, in contrast to SiO2 etch rates of ˜0 angstroms/min.
During the above hot H3PO4 etching process to remove said Si ON ARC layer 10, the top and side wall surfaces of polysilicon gate feature 14, were protected by said first and second protective oxide layers, 8 and 16. Without this protection, there would have been chemical attack of the, otherwise exposed, polysilicon surfaces by the hot H3PO3 solution. The main objective of this invention has now been accomplished. Namely, the SiON ARC layer has been removed by a hot H3PO4 process, while also avoiding chemical attack of polysilicon gate features.
Referring now more particularly to FIG. 5, conventional dilute hydrofluoric acid (50:1) etching is now used to remove said first protective oxide layer 8 and said second protective oxide layer 16, in preparation for silicidation of the resultant polysilicon gate 6 feature 18 and other subsequent conventional process steps that may be needed for the completion of a given sub-micron FET device. For the removal of said oxide layers 8 and 16, the typical etching time is about one minute. This relatively short etching time results in minimal removal of the gate oxide 4 under the polysilicon gate 6, as shown in FIG. 5. In contrast, if a hydrofluoric acid solution would have been used in place of hot H3PO4, in order to remove the SiON ARC layer 10, the longer required etching time (about 1.2× longer) would have resulted in unacceptable removal of the gate oxide 4 under the polysilicon gate. That is why this invention exploited the faster etch rate of hot H3PO4, for SiON removal, while also solving the problem of the hot H3PO4 solution being able to attack any exposed polysilicon surfaces.
The objects of the invention have now been accomplished. A critical dimension (CD) control problem has been solved by using a SiON ARC as a means of minimizing spurious reflected photons from leading to distorted photoresist images, during the photolithographic exposure step used for defining sub-micron polysilicon gates.
The key to this invention is a solution to the consequent problem, that was created, after having choosen hot H3PO4 as the etchant for the removal of SiON, with regard to how to subsequently remove the SiON ARC in a manner that would not result in unacceptable attack of the gate oxide or of the polysilicon gate surfaces. As discussed, above, this was accomplished by using hot H3PO4 (instead of a hydrofluoric acid solution), to selectively etch the ARC relatively faster than the gate oxide, while also using thin thermal oxide layers to the protect polysilicon surfaces from being attacked at the same time.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Claims (19)

What is claimed is:
1. A method for removing SiON layers from polysilicon gate features, while also protecting said polysilicon features and underlying gate oxides from being appreciably attacked or etched at the same time, comprising the steps of:
(a) forming a first insulating oxide layer over a polysilicon layer, over a semiconductor substrate, to be used as an eventual selective etch stopping layer;
(b) forming a SiON layer over said first insulating layer
(c) forming sub-micron polysilicon gate features by etching said SiON, insulating oxide and polysilicon layers;
(d) forming a second insulating oxide layer on the side walls of said polysilicon features; and
(e) selectively wet etching said SiON layer, by means of H3PO4 which etches SiON relatively faster than silicon oxide, whereby said first and second insulating oxide layers will protect said polysilicon layer from chemical attack and said underlying gate oxide layer will also remain in tact.
2. The method of claim 1 wherein the thickness of said first insulating oxide layer is between about 20 to 50 Angstroms.
3. The method of claim 1 wherein the thickness of said SiON layer is between about 250 and 350 Angstroms.
4. The method of claim 1 wherein the thickness of said second insulating oxide layer is between about 20 and 50 Angstroms.
5. The method of claim 1 wherein the thickness of said gate oxide layer is between about 20 to 60 Angstroms.
6. The method of claim 1 wherein the thickness of said polysilicon layer is between about 1500 to 2500 Angstroms.
7. The method of claim 1 wherein said hot H3PO4 etching step exhibits an etch rate of about 50 angstroms/min. for SiON, along with a much slower etch rate of about 0 Angstroms/min. for the case of thermal silicon oxide.
8. A fabrication method for selectively removing SiON layers from polysilicon gate features, after said layers have been used as anti-reflective coatings (ARCs), for the purpose of enhancing the photolithographic definition of sub-micron polysilicon gate features, comprising the steps of:
(a) forming blanket gate oxide layer and an overlying blanket polysilicon layer over a semiconductor substate;
(b) forming a first insulating oxide layer over said polysilicon layer;
(c) forming a SiON based layer over said first insulating layer;
(d) patterning the stack, consisting of said polysilicon layer, said thermal oxide layer and said ARC layer, into sub-micron polysilicon gate features;
(e) forming a second protective insulating oxide layer on the side walls of said polysilicon features; and
(f) selectively wet etching said SiON based layer from the top surface of said polysilicon gate features, by means of hot H3PO4 whereby said first and second protective insulating oxide layers are not appreciably etched.
9. The method of claim 8 where removal of said first and second protective insulating oxide layers from the top and side wall surfaces of said polysilicon features, by means of a rapid hydrofluoric acid etching step that will not appreciably remove said underlying gate oxide layer.
10. The method of claim 8 wherein the thickness of said first insulating oxide layer is between about 20 to 50 Angstroms.
11. The method of claim 8 wherein the thickness of said SiON layer is between about 250 and 350 Angstroms.
12. The method of claim 8 wherein the thickness of said second insulating oxide layer is between about 20 and 50 Angstroms.
13. The method of claim 8 wherein the thickness of said gate oxide layer is between about 20 to 60 Angstroms.
14. The method of claim 8 wherein the thickness of said polysilicon layer is between about 1500 to 2500 Angstroms.
15. The method of claim 8 wherein said hot H3PO4 etching step exhibits an etch rate of about 50 Angstroms/min. for SiON and a much slower etch rate of about 0 angstroms/min. for the case of thermal silicon oxide.
16. The method of claim 8 wherein the thickness values and the optical constants of said first insulating layer and said SiON ARC layer are approximately optimized for minimal optical reflectivity from the surface of said underlying polysilicon surface.
17. The method of claim 16 wherein said first insulating layer is a thermal oxide with a thickness range of about 20 to 50 angstroms and where the thickness of said SiON layer is between about 250 to 350 Angstroms, for case of the optical constants for said SiON layer being about 2.12 for n and about 0.65 for the value of k.
18. The method of claim 8 wherein said hydrofluoric acid, HF, solution is a 50:1 mixture of water and HF and having an approximate etch rate of about 55 Angstroms/min. for thermal oxide and an approximate etch rate of about 40 Angstroms/min. for said SiON layer.
19. The method of claim 8 wherein said SiON ARC layer is formed by means of a PECVD deposition process.
US09/266,374 1999-03-11 1999-03-11 Removal of SiON ARC film after poly photo and etch Expired - Lifetime US6245682B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/266,374 US6245682B1 (en) 1999-03-11 1999-03-11 Removal of SiON ARC film after poly photo and etch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/266,374 US6245682B1 (en) 1999-03-11 1999-03-11 Removal of SiON ARC film after poly photo and etch

Publications (1)

Publication Number Publication Date
US6245682B1 true US6245682B1 (en) 2001-06-12

Family

ID=23014308

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/266,374 Expired - Lifetime US6245682B1 (en) 1999-03-11 1999-03-11 Removal of SiON ARC film after poly photo and etch

Country Status (1)

Country Link
US (1) US6245682B1 (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573193B2 (en) * 2001-08-13 2003-06-03 Taiwan Semiconductor Manufacturing Co., Ltd Ozone-enhanced oxidation for high-k dielectric semiconductor devices
WO2003081660A1 (en) * 2002-03-19 2003-10-02 Freescale Semiconductor, Inc. Integrated circuit device and method therefor
US20030205785A1 (en) * 2001-11-30 2003-11-06 Micron Technology, Inc. Low k film application for interlevel dielectric and method of cleaning etched features
EP1418613A1 (en) * 2002-11-08 2004-05-12 Interuniversitair Microelektronica Centrum ( Imec) Etching method for manufacturing a semiconductor device
US20050156229A1 (en) * 2003-12-16 2005-07-21 Yeap Geoffrey C. Integrated circuit device and method therefor
US6924196B1 (en) * 1999-08-06 2005-08-02 Newport Fab, Llc Anti-reflective coating and process using an anti-reflective coating
US20050215038A1 (en) * 2004-03-26 2005-09-29 Texas Instruments, Incorporated Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same
US6964929B1 (en) 2002-05-02 2005-11-15 Cypress Semiconductor Corporation Method of forming a narrow gate, and product produced thereby
US7268029B2 (en) 2003-11-21 2007-09-11 Samsung Electronics Co., Ltd. Method of fabricating CMOS transistor that prevents gate thinning
US20090170322A1 (en) * 2007-12-31 2009-07-02 Hynix Semiconductor Inc. Method for Manufacturing Semiconductor Device Including Vertical Transistor
EP2336828A2 (en) 2009-12-15 2011-06-22 Rohm and Haas Electronic Materials LLC Photoresists and methods for use thereof
EP2336829A1 (en) 2009-12-15 2011-06-22 Rohm and Haas Electronic Materials LLC Photoresists and methods for use thereof
EP2472327A1 (en) 2010-12-30 2012-07-04 Rohm and Haas Electronic Materials LLC Photoresists and methods for use thereof
CN104465367A (en) * 2013-09-16 2015-03-25 北大方正集团有限公司 Method and application for processing field oxide layer
CN108231778A (en) * 2016-12-09 2018-06-29 联华电子股份有限公司 Semiconductor element and preparation method thereof
US11411009B2 (en) 2018-04-12 2022-08-09 United Microelectronics Corp. Semiconductor device and method for fabricating the same

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4657630A (en) * 1983-01-31 1987-04-14 Hitachi, Ltd. Method for manufacturing semiconductor device having isolating groove
US5269879A (en) 1991-10-16 1993-12-14 Lam Research Corporation Method of etching vias without sputtering of underlying electrically conductive layer
US5472827A (en) * 1991-12-30 1995-12-05 Sony Corporation Method of forming a resist pattern using an anti-reflective layer
US5600165A (en) 1994-07-27 1997-02-04 Sony Corporation Semiconductor device with antireflection film
US5674356A (en) * 1994-04-05 1997-10-07 Sony Corporation Method for forming a semiconductor device in which an anti reflective layer is formed by varying the composition thereof
US5741396A (en) 1994-04-29 1998-04-21 Texas Instruments Incorporated Isotropic nitride stripping
US5904564A (en) * 1996-12-27 1999-05-18 Hyundai Electronics Industries Co., Ltd. Method for fabricating MOSFET having cobalt silicide film
US5937319A (en) * 1997-10-31 1999-08-10 Advanced Micro Devices, Inc. Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching
US6074905A (en) * 1998-12-28 2000-06-13 Taiwan Semiconductor Manufacturing Company Formation of a thin oxide protection layer at poly sidewall and area surface
US6083852A (en) * 1997-05-07 2000-07-04 Applied Materials, Inc. Method for applying films using reduced deposition rates
US6103632A (en) * 1997-10-22 2000-08-15 Applied Material Inc. In situ Etching of inorganic dielectric anti-reflective coating from a substrate

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4657630A (en) * 1983-01-31 1987-04-14 Hitachi, Ltd. Method for manufacturing semiconductor device having isolating groove
US5269879A (en) 1991-10-16 1993-12-14 Lam Research Corporation Method of etching vias without sputtering of underlying electrically conductive layer
US5472827A (en) * 1991-12-30 1995-12-05 Sony Corporation Method of forming a resist pattern using an anti-reflective layer
US5674356A (en) * 1994-04-05 1997-10-07 Sony Corporation Method for forming a semiconductor device in which an anti reflective layer is formed by varying the composition thereof
US5741396A (en) 1994-04-29 1998-04-21 Texas Instruments Incorporated Isotropic nitride stripping
US5600165A (en) 1994-07-27 1997-02-04 Sony Corporation Semiconductor device with antireflection film
US5904564A (en) * 1996-12-27 1999-05-18 Hyundai Electronics Industries Co., Ltd. Method for fabricating MOSFET having cobalt silicide film
US6083852A (en) * 1997-05-07 2000-07-04 Applied Materials, Inc. Method for applying films using reduced deposition rates
US6103632A (en) * 1997-10-22 2000-08-15 Applied Material Inc. In situ Etching of inorganic dielectric anti-reflective coating from a substrate
US5937319A (en) * 1997-10-31 1999-08-10 Advanced Micro Devices, Inc. Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching
US6074905A (en) * 1998-12-28 2000-06-13 Taiwan Semiconductor Manufacturing Company Formation of a thin oxide protection layer at poly sidewall and area surface

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Chen, I., et al., "Microelectronic Device and Multilevel Interconnection Technology II", SPIE vol. 2875, pp. 188-200 (1996). *
Wu, J., et al., "Comparing Inorganic and Organic BARC for a Deep Sub-Micron Gate Patterning & Etch", Proc. SPIE vol. 3332, pp.696-709 (1998).*

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6924196B1 (en) * 1999-08-06 2005-08-02 Newport Fab, Llc Anti-reflective coating and process using an anti-reflective coating
US6573193B2 (en) * 2001-08-13 2003-06-03 Taiwan Semiconductor Manufacturing Co., Ltd Ozone-enhanced oxidation for high-k dielectric semiconductor devices
US20030205785A1 (en) * 2001-11-30 2003-11-06 Micron Technology, Inc. Low k film application for interlevel dielectric and method of cleaning etched features
US20040245644A1 (en) * 2001-11-30 2004-12-09 Micron Technology, Inc. Low K film application for interlevel dielectric and method of cleaning etched features
WO2003081660A1 (en) * 2002-03-19 2003-10-02 Freescale Semiconductor, Inc. Integrated circuit device and method therefor
US6753242B2 (en) 2002-03-19 2004-06-22 Motorola, Inc. Integrated circuit device and method therefor
US20040124450A1 (en) * 2002-03-19 2004-07-01 Yeap Geoffrey C-F Integrated circuit device and method therefor
US6846716B2 (en) 2002-03-19 2005-01-25 Freescale Semiconductor, Inc. Integrated circuit device and method therefor
US6964929B1 (en) 2002-05-02 2005-11-15 Cypress Semiconductor Corporation Method of forming a narrow gate, and product produced thereby
EP1418613A1 (en) * 2002-11-08 2004-05-12 Interuniversitair Microelektronica Centrum ( Imec) Etching method for manufacturing a semiconductor device
US7268029B2 (en) 2003-11-21 2007-09-11 Samsung Electronics Co., Ltd. Method of fabricating CMOS transistor that prevents gate thinning
US20050156229A1 (en) * 2003-12-16 2005-07-21 Yeap Geoffrey C. Integrated circuit device and method therefor
US20050215038A1 (en) * 2004-03-26 2005-09-29 Texas Instruments, Incorporated Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same
US7157358B2 (en) * 2004-03-26 2007-01-02 Texas Instruments Incorporated Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same
US20090170322A1 (en) * 2007-12-31 2009-07-02 Hynix Semiconductor Inc. Method for Manufacturing Semiconductor Device Including Vertical Transistor
EP2336828A2 (en) 2009-12-15 2011-06-22 Rohm and Haas Electronic Materials LLC Photoresists and methods for use thereof
EP2336829A1 (en) 2009-12-15 2011-06-22 Rohm and Haas Electronic Materials LLC Photoresists and methods for use thereof
EP2472327A1 (en) 2010-12-30 2012-07-04 Rohm and Haas Electronic Materials LLC Photoresists and methods for use thereof
CN104465367A (en) * 2013-09-16 2015-03-25 北大方正集团有限公司 Method and application for processing field oxide layer
CN104465367B (en) * 2013-09-16 2018-06-05 北大方正集团有限公司 A kind of method handled field oxide and application
CN108231778A (en) * 2016-12-09 2018-06-29 联华电子股份有限公司 Semiconductor element and preparation method thereof
US11411009B2 (en) 2018-04-12 2022-08-09 United Microelectronics Corp. Semiconductor device and method for fabricating the same

Similar Documents

Publication Publication Date Title
US6245682B1 (en) Removal of SiON ARC film after poly photo and etch
KR100300258B1 (en) Method and structure for forming integrated circuit pattern on semiconductor substrate
US5674356A (en) Method for forming a semiconductor device in which an anti reflective layer is formed by varying the composition thereof
US6004850A (en) Tantalum oxide anti-reflective coating (ARC) integrated with a metallic transistor gate electrode and method of formation
US7482280B2 (en) Method for forming a lithography pattern
US20060270230A1 (en) Critical dimension control for integrated circuits
JPH08255752A (en) Semiconductor element with low reflectance coating and its preparation
KR101164690B1 (en) A semiconductor device having an organic anti-reflective coatingarc and method therefor
KR100243266B1 (en) (Ge, Si)Nx antireflective layer and fabricating method of semiconductor device pattern using the same
US5332653A (en) Process for forming a conductive region without photoresist-related reflective notching damage
EP1292969B1 (en) Patterning method using a removable inorganic antireflection coating
KR100219550B1 (en) Anti-reflective coating layer and pattern forming method using the same
JPH1098029A (en) Processing method for etching anti-reflection organic coating from substrate
KR20160117818A (en) Method for manufacturing semiconductor device
US20190385903A1 (en) Method of Patterning Low-K Materials Using Thermal Decomposition Materials
US7163880B2 (en) Gate stack and gate stack etch sequence for metal gate integration
US6924196B1 (en) Anti-reflective coating and process using an anti-reflective coating
US5422312A (en) Method for forming metal via
US6806154B1 (en) Method for forming a salicided MOSFET structure with tunable oxynitride spacer
CN108597991B (en) Photoresist back etching process
KR100555622B1 (en) Method for forming antireflective layer of semiconductor devices
KR101692119B1 (en) Improved etching process
KR20020027503A (en) Method of dry etching an antireflection coating in semiconductor devices
KR100816687B1 (en) A forming method of pattern
KR100744089B1 (en) Method for fabricating semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FU, CHU-YUN;JANG, SYUN-MING;REEL/FRAME:009822/0533

Effective date: 19981231

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12