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US5708550A - ESD protection for overvoltage friendly input/output circuits - Google Patents

ESD protection for overvoltage friendly input/output circuits Download PDF

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Publication number
US5708550A
US5708550A US08/736,113 US73611396A US5708550A US 5708550 A US5708550 A US 5708550A US 73611396 A US73611396 A US 73611396A US 5708550 A US5708550 A US 5708550A
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Prior art keywords
esd protection
voltage
clamping
input terminal
circuit
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Expired - Fee Related
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US08/736,113
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Leslie Ronald Avery
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Sarnoff Corp
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David Sarnoff Research Center Inc
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Priority to US08/736,113 priority Critical patent/US5708550A/en
Assigned to DAVID SARNOFF RESEARCH CENTER, INC. reassignment DAVID SARNOFF RESEARCH CENTER, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AVERY, LESLIE RONALD
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Publication of US5708550A publication Critical patent/US5708550A/en
Assigned to SARNOFF CORPORATION reassignment SARNOFF CORPORATION MERGER (SEE DOCUMENT FOR DETAILS). Assignors: DAVID SARNOFF RESEARCH CENTER, INC.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/20—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage
    • H02H3/22—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage of short duration, e.g. lightning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Definitions

  • the present invention is directed to an electrostatic discharge (ESD) protection circuit, and, more particularly to an ESD protection circuit for overvoltage friendly input/output circuits.
  • ESD electrostatic discharge
  • the input and bidirectional input/output (I/O) circuits have to withstand an input voltage which can exceed the IC supply voltage.
  • the IC may operated from 3.3 volts, but must have the ability to interface with other circuits having 5 volt logic swings. This ability is commonly called 5 volt friendly.
  • Electrostatic discharge (ESD) protection for these circuits is more difficult as a simple diode protection to the supply line clamps the signal at the terminal to a diode drop above the supply line voltage, or 4 volts in the case of 3.3 volt supplies.
  • ESD Electrostatic discharge
  • An ESD protection circuit includes an input terminal, a power supply line for providing a power supply voltage, and a source of reference potential.
  • a Schottky varrier diode is between the input terminal and the power supply line for blocking voltages from the input terminal which are greater than the power supply voltage.
  • a clamping circuit is provided for clamping excess positive voltage at a higher voltage than the power voltage.
  • a first clamping means is between the input terminal and the clamping circuit, and a second clamping means is provided for clamping negative voltages at the input terminal to the source of reference potential.
  • FIGURE of the drawings is a schematic diagram of an I/O circuit with ESD protection in accordance with the present invention.
  • FIG. 1 there is shown a schematic diagram of an I/O circuit 10 which includes NMOS transistor 18 and PMOS transistor 19.
  • the drains of the transistors 18 and 19 are connected to an I/O terminal pad 11.
  • the source of the NMOS transistor 18 is connected to a source of reference potential 12.
  • the source of the PMOS transistor 19 is connected to the cathode of a Schottky diode 20.
  • the anode of the Schottky diode 20 is connected to a power supply line 13.
  • Power supply protection structure 14 is connected between the power supply line 13 and the source of reference potential 12.
  • a diode 16 is connected between the pad 11 and the source of reference potential 12, with the anode of the diode 16 being connected to the source of reference potential 12, and the cathode of the diode 16 being connected to the terminal pad 11.
  • a diode 17 is connected between the terminal pad 11 and a dummy supply line 15. The anode of diode 17 is connected to the terminal pad 11, and the cathode of the diode 17 is connected to the dummy supply line 15.
  • a power supply protection structure 21 is connected between the source of reference potential 12 and the dummy supply line 15.
  • a diode 22 is shown connected between the source and drain of the PMOS transistor 19.
  • the diode 22 is a parasitic diode present in a bulk CMOS device, and is formed by the drain of PMOS transistor 19 and an N-well or bulk silicon body in which the circuit is formed.
  • ESD protection structures 14 and 21 can be those commonly used in the art, such as high holding voltage SCRs, lateral npn transistors, vertical npn transistors, shunt regulators, etc., which are designed to clamp the ESD transient to a safe level once the structure is triggered.
  • the ESD protection structure 14 is of the type which will trigger within two or three volts above the maximum allowable supply voltage, and snap-back to a holding voltage which is only one or two volts above the maximum allowable supply voltage.
  • the ESD protection structure 21 should be of a structure which will trigger about one diode forward drop below the maximum logic level, normally about 5.5 volts, and clamp at that voltage.
  • NMOS transistor 18 provides the pull down capability, sinking current to the source of reference potential.
  • PMOS transistor 19 provides the pull up capability, sourcing current through the Schottky diode 20 from the power line 13 into the external load and raising the potential on terminal pad 11.
  • the potential on terminal pad 11 reaches a value slightly below the potential of the power line 13 due to the forward voltage drop of the Schottky diode 20. This voltage drop depends on the metal used to form the Schottky diode 20, but is normally less than about 0.4 volts.
  • NMOS transistor 18 and PMOS transistor 19 are switched to the off state by internal logic control signals, and terminal pad 11 acts an in input terminal.
  • the I/O pad 11 is connected to the gates of input transistors via resistor/protection networks well known in the art. For logic signal within a range from the source of reference potential minus one diode drop (nominally about -0.6 volts) to the trigger potential of ESD protection structure 21 plus the forward voltage of diode 17, all protection elements and MOS devices appear to be open circuit.
  • diode 16 If the input signal or a transient causes the potential at terminal pad 11 to fall more than one forward diode voltage below the source of reference potential, diode 16 conducts, clamping the signal or transient to the source of reference potential. Diode 16 turns off when the signal or transient rises above the forward voltage drop of diode 16.
  • the Schottky diode 20 becomes reversed biased and turns off, thereby preventing current from flowing through the parasitic diode 22 to the power supply line 13. If the voltage at terminal pad 11 continues to rise, a point is reached where diode 17 becomes forward biased and protection structure 21 is triggered. The input is then clamped to the clamping voltage of protection structure 21 plus the forward voltage drop of diode 17. Protection structure 21 and diode 17 turn off when the input signal or transient fall below the combined clamping voltage of structure 21 and diode 17.
  • PMOS transistor 19 could still be turned on by having the gate voltage held at a fixed potential while the drain, which is connected to terminal pad 11, is taken to a higher potential than the gate. Under these bias conditions, the drain and source of the PMOS transistor 19 are reversed and current could flow from the terminal pad 11 into power supply line 13. The presence of The Schottky diode 20 prevents this flow of current.
  • the invention is an ESD protection circuit whereby any potential source of current flow from an input terminal into the power supply line by voltages exceeding the power supply voltage is blocked by a Schottky diode.
  • a first clamping means is introduced between the input terminal and a clamp circuit enables excess positive voltage to be clamped at a higher voltage than the power supply voltage.
  • a second clamping means is provided whereby negative voltages at the input terminal are clamped to a source of reference potential.
  • the first and second clamping means are semiconductor diodes, but any other types of structures can be used which turn on above a certain voltage to connect the signal line to a dummy supply line.
  • the clamp circuit of the present invention may be shared between one or more input circuits or input/output circuits connected with a dummy supply line.
  • the Schottky diode is typically formed by introducing a metal or metal-silicide contact into an N-well.
  • a dummy supply line with distributed ESD protection structures designed to accommodate signal levels, e.g., above about 5 volts, greater than the power supply voltage, e.g., about 3.3 volts, with ESD protection and with diodes from each input or I/O circuit to this dummy supply line is disclosed.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

An electrostatic discharge (ESD) protection circuit includes an input terminal, a power supply line and a source of reference potential. The circuit also includes a dummy supply line. A Schottky barrier diode is connected between the input terminal and the power supply line for blocking voltages from the input terminal which are greater than the power supply voltage. A first clamping structure is connected between the dummy supply line and the source of reference potential, and a second clamping structure is connected between the power supply line and the source of reference potential. A first clamping diode is connected between the input terminal and the dummy supply line and a second clamping diode is connected between the input terminal and the source of reference potential.

Description

RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional application Ser. No. 60/007,069, filed Oct. 25, 1995 abandoned.
FIELD OF THE INVENTION
The present invention is directed to an electrostatic discharge (ESD) protection circuit, and, more particularly to an ESD protection circuit for overvoltage friendly input/output circuits.
BACKGROUND
For an integrated circuit (IC) fabricated using geometries below about 0.5 micrometers, the input and bidirectional input/output (I/O) circuits have to withstand an input voltage which can exceed the IC supply voltage. For example, the IC may operated from 3.3 volts, but must have the ability to interface with other circuits having 5 volt logic swings. This ability is commonly called 5 volt friendly. Electrostatic discharge (ESD) protection for these circuits is more difficult as a simple diode protection to the supply line clamps the signal at the terminal to a diode drop above the supply line voltage, or 4 volts in the case of 3.3 volt supplies. The use of a single protection structure to the common reference potential is undesirable since it requires a large silicon area as the structure must absorb all the ESD energy.
SUMMARY OF THE INVENTION
An ESD protection circuit includes an input terminal, a power supply line for providing a power supply voltage, and a source of reference potential. A Schottky varrier diode is between the input terminal and the power supply line for blocking voltages from the input terminal which are greater than the power supply voltage. A clamping circuit is provided for clamping excess positive voltage at a higher voltage than the power voltage. A first clamping means is between the input terminal and the clamping circuit, and a second clamping means is provided for clamping negative voltages at the input terminal to the source of reference potential.
BRIEF DESCRIPTION OF THE DRAWING
The FIGURE of the drawings is a schematic diagram of an I/O circuit with ESD protection in accordance with the present invention.
DETAILED DESCRIPTION
Referring to the FIGURE of the drawings there is shown a schematic diagram of an I/O circuit 10 which includes NMOS transistor 18 and PMOS transistor 19. The drains of the transistors 18 and 19 are connected to an I/O terminal pad 11. The source of the NMOS transistor 18 is connected to a source of reference potential 12. The source of the PMOS transistor 19 is connected to the cathode of a Schottky diode 20. The anode of the Schottky diode 20 is connected to a power supply line 13. Power supply protection structure 14 is connected between the power supply line 13 and the source of reference potential 12. A diode 16 is connected between the pad 11 and the source of reference potential 12, with the anode of the diode 16 being connected to the source of reference potential 12, and the cathode of the diode 16 being connected to the terminal pad 11. A diode 17 is connected between the terminal pad 11 and a dummy supply line 15. The anode of diode 17 is connected to the terminal pad 11, and the cathode of the diode 17 is connected to the dummy supply line 15. A power supply protection structure 21 is connected between the source of reference potential 12 and the dummy supply line 15. A diode 22 is shown connected between the source and drain of the PMOS transistor 19. The diode 22 is a parasitic diode present in a bulk CMOS device, and is formed by the drain of PMOS transistor 19 and an N-well or bulk silicon body in which the circuit is formed.
ESD protection structures 14 and 21 can be those commonly used in the art, such as high holding voltage SCRs, lateral npn transistors, vertical npn transistors, shunt regulators, etc., which are designed to clamp the ESD transient to a safe level once the structure is triggered. Ideally, the ESD protection structure 14 is of the type which will trigger within two or three volts above the maximum allowable supply voltage, and snap-back to a holding voltage which is only one or two volts above the maximum allowable supply voltage. The ESD protection structure 21 should be of a structure which will trigger about one diode forward drop below the maximum logic level, normally about 5.5 volts, and clamp at that voltage. My U.S. Pat. No. 5,043,782, my U.S. Pat. No. 5,343,053 and my U.S. Pat. No. 5,600,525, each of which is incorporated herein by reference, disclose applicable power supply protection structures.
In normal operation as an output circuit, NMOS transistor 18 provides the pull down capability, sinking current to the source of reference potential. PMOS transistor 19 provides the pull up capability, sourcing current through the Schottky diode 20 from the power line 13 into the external load and raising the potential on terminal pad 11. The potential on terminal pad 11 reaches a value slightly below the potential of the power line 13 due to the forward voltage drop of the Schottky diode 20. This voltage drop depends on the metal used to form the Schottky diode 20, but is normally less than about 0.4 volts.
When operating as an input circuit receiving signals from an external source, NMOS transistor 18 and PMOS transistor 19 are switched to the off state by internal logic control signals, and terminal pad 11 acts an in input terminal. The I/O pad 11 is connected to the gates of input transistors via resistor/protection networks well known in the art. For logic signal within a range from the source of reference potential minus one diode drop (nominally about -0.6 volts) to the trigger potential of ESD protection structure 21 plus the forward voltage of diode 17, all protection elements and MOS devices appear to be open circuit.
If the input signal or a transient causes the potential at terminal pad 11 to fall more than one forward diode voltage below the source of reference potential, diode 16 conducts, clamping the signal or transient to the source of reference potential. Diode 16 turns off when the signal or transient rises above the forward voltage drop of diode 16.
If the input signal rises a forward diode voltage drop above the voltage on power supply line 13, the Schottky diode 20 becomes reversed biased and turns off, thereby preventing current from flowing through the parasitic diode 22 to the power supply line 13. If the voltage at terminal pad 11 continues to rise, a point is reached where diode 17 becomes forward biased and protection structure 21 is triggered. The input is then clamped to the clamping voltage of protection structure 21 plus the forward voltage drop of diode 17. Protection structure 21 and diode 17 turn off when the input signal or transient fall below the combined clamping voltage of structure 21 and diode 17.
This arrangement can be used for both bulk silicon and oxide isolated processes in which diode 22 does not exist. However, PMOS transistor 19 could still be turned on by having the gate voltage held at a fixed potential while the drain, which is connected to terminal pad 11, is taken to a higher potential than the gate. Under these bias conditions, the drain and source of the PMOS transistor 19 are reversed and current could flow from the terminal pad 11 into power supply line 13. The presence of The Schottky diode 20 prevents this flow of current.
It is to be understood that the apparatus and method of operation taught herein are illustrative of the invention. Modifications may readily be devised by those skilled in the art without departing from the spirit or scope of the invention. The invention is an ESD protection circuit whereby any potential source of current flow from an input terminal into the power supply line by voltages exceeding the power supply voltage is blocked by a Schottky diode. A first clamping means is introduced between the input terminal and a clamp circuit enables excess positive voltage to be clamped at a higher voltage than the power supply voltage. A second clamping means is provided whereby negative voltages at the input terminal are clamped to a source of reference potential. The first and second clamping means are semiconductor diodes, but any other types of structures can be used which turn on above a certain voltage to connect the signal line to a dummy supply line. The clamp circuit of the present invention may be shared between one or more input circuits or input/output circuits connected with a dummy supply line. The Schottky diode is typically formed by introducing a metal or metal-silicide contact into an N-well.
The use of a dummy supply line with distributed ESD protection structures designed to accommodate signal levels, e.g., above about 5 volts, greater than the power supply voltage, e.g., about 3.3 volts, with ESD protection and with diodes from each input or I/O circuit to this dummy supply line is disclosed.

Claims (8)

What is claimed is:
1. An ESD protection circuit comprising:
an input terminal;
power supply line for providing a power supply voltage;
a source of reference potential;
a Schottky barrier diode between the input terminal and the power supply line for blocking voltages from the input terminal which are greater than the power supply voltage;
a clamping circuit for clamping excess positive voltage at a higher voltage than the power voltage;
first clamping means between the input terminal and the clamping circuit; and
second clamping means for clamping negative voltages at the input terminal to the source of reference potential.
2. An ESD protection circuit in accordance with claim 1 including a dummy supply line and a first portion of the clamping circuit is connected between the dummy supply line and the source of reference potential.
3. An ESD protection circuit in accordance with claim 2 in which a second portion of the clamping circuit is connected between the power supply line and the source of reference potential.
4. An ESD protection circuit in accordance with claim 3 in which the first clamping means is a semiconductor diode connected between the input terminal and the dummy line.
5. An ESD protection circuit in accordance with claim 4 in which the second clamping means is a semiconductor diode connected between the input terminal and the source of reference potential.
6. The ESD protection circuit in accordance with claim 5 in which each portion of the clamping circuit is a separate ESD protection structure.
7. The ESD protection circuit in accordance with claim 6 in which the first portion of the clamping circuit is an ESD protection structure which will trigger within two to three volts above the maximum allowable supply voltage and will snap-back to a holding voltage which is only one to two volts above the maximum allowable supply voltage.
8. The ESD protection circuit in accordance with claim 7 in which the second portion of the clamping circuit is an ESD protection structure which triggers at about one diode forward voltage drop below the maximum logic level and clamps at that voltage.
US08/736,113 1995-10-25 1996-10-24 ESD protection for overvoltage friendly input/output circuits Expired - Fee Related US5708550A (en)

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Cited By (18)

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EP0982776A2 (en) * 1998-08-25 2000-03-01 Sharp Kabushiki Kaisha ESD protection thyristor with trigger diode
US6281735B1 (en) * 1999-09-09 2001-08-28 National Semiconductor Corporation Voltage clamping circuits for limiting the voltage range of an input signal
US6344385B1 (en) 2000-03-27 2002-02-05 Chartered Semiconductor Manufacturing Ltd. Dummy layer diode structures for ESD protection
US6583972B2 (en) 2000-06-15 2003-06-24 Sarnoff Corporation Multi-finger current ballasting ESD protection circuit and interleaved ballasting for ESD-sensitive circuits
US6700763B2 (en) 2002-06-14 2004-03-02 Thomson Licensing S.A. Protected dual-voltage microcircuit power arrangement
US6727554B1 (en) 1999-03-18 2004-04-27 Hyundai Electronics Industries Co., Ltd. ESD protection circuit and method for fabricating the same
US6747857B1 (en) 2002-02-01 2004-06-08 Taiwan Semiconductor Manufacturing Company Clamping circuit for stacked NMOS ESD protection
US20050073348A1 (en) * 2003-10-01 2005-04-07 Hinterscher Eugene B. Dynamic receiver clamp that is enabled during periods in which overshoot is likely
US20050269659A1 (en) * 2004-06-08 2005-12-08 Shao-Chang Huang Esd performance using separate diode groups
US20070007545A1 (en) * 2005-07-07 2007-01-11 Intersil Americas Inc. Devices with adjustable dual-polarity trigger- and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated circuits
US7719806B1 (en) 2006-02-07 2010-05-18 Pmc-Sierra, Inc. Systems and methods for ESD protection
US20100165524A1 (en) * 2008-12-31 2010-07-01 Dong-Ju Lim Integrated circuit
US20100308472A1 (en) * 2007-11-06 2010-12-09 Silicon Works Co., Ltd Semiconductor chip having power supply line with minimized voltage drop
US8022498B1 (en) * 2007-03-26 2011-09-20 Synopsys, Inc. Electrostatic discharge management apparatus, systems, and methods
US20150207312A1 (en) * 2014-01-17 2015-07-23 Silergy Semiconductor Technology (Hangzhou) Ltd Low Capacitance Transient Voltage Suppressor
CN112397499A (en) * 2019-08-12 2021-02-23 创意电子股份有限公司 Electrostatic discharge protection device and method
US20210327871A1 (en) * 2019-01-24 2021-10-21 Western Digital Technologies, Inc. High voltage protection for high-speed data interface
US11569220B2 (en) * 2019-08-12 2023-01-31 Global Unichip Corporation Electrostatic discharge protection device and method

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TW200739872A (en) 2006-04-04 2007-10-16 Univ Nat Chiao Tung Power line electrostatic discharge protection circuit featuring triple voltage tolerance

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Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6696730B2 (en) 1998-08-25 2004-02-24 Sharp Kabushiki Kaisha Electrostatic discharge protection device for semiconductor integrated circuit, method for producing the same, and electrostatic discharge protection circuit using the same
EP0982776A3 (en) * 1998-08-25 2000-11-02 Sharp Kabushiki Kaisha ESD protection thyristor with trigger diode
US6338986B1 (en) 1998-08-25 2002-01-15 Sharp Kabushiki Kaisha Electrostatic discharge protection device for semiconductor integrated circuit method for producing the same and electrostatic discharge protection circuit using the same
EP0982776A2 (en) * 1998-08-25 2000-03-01 Sharp Kabushiki Kaisha ESD protection thyristor with trigger diode
US6524893B2 (en) 1998-08-25 2003-02-25 Sharp Kabushiki Kaisha Electrostatic discharge protection device for semiconductor integrated circuit, method for producing the same, and electrostatic discharge protection circuit using the same
US6727554B1 (en) 1999-03-18 2004-04-27 Hyundai Electronics Industries Co., Ltd. ESD protection circuit and method for fabricating the same
US6281735B1 (en) * 1999-09-09 2001-08-28 National Semiconductor Corporation Voltage clamping circuits for limiting the voltage range of an input signal
US6344385B1 (en) 2000-03-27 2002-02-05 Chartered Semiconductor Manufacturing Ltd. Dummy layer diode structures for ESD protection
US6552399B2 (en) 2000-03-27 2003-04-22 Chartered Semiconductor Manufacturing Ltd. Dummy layer diode structures for ESD protection
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EP0858688A4 (en) 1999-07-07
KR19990064296A (en) 1999-07-26
EP0858688A1 (en) 1998-08-19
JPH11513879A (en) 1999-11-24
WO1997015975A1 (en) 1997-05-01

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