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US5475583A - Programmable control system including a logic module and a method for programming - Google Patents

Programmable control system including a logic module and a method for programming Download PDF

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Publication number
US5475583A
US5475583A US07/840,326 US84032692A US5475583A US 5475583 A US5475583 A US 5475583A US 84032692 A US84032692 A US 84032692A US 5475583 A US5475583 A US 5475583A
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United States
Prior art keywords
logic
internal electrical
connections
performance characteristics
subfunctions
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US07/840,326
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English (en)
Inventor
Genther Bock
Helmut Macht
Christof Wombacher
Manfred Prechtl
Andre Lengemann
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Callahan Cellular LLC
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Siemens AG
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/056—Programming the PLC
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1174—Input activates directly output and vice versa
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1176—I-O signal processing, adaption, conditioning, conversion of signal levels
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1185—Feedback of output status to input module and compare with command
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13007—Program hardwired logic, pld, fpga when out of machine, or inactive
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13071—Non time critical program by processor, time critical program by hardware
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13109—Pld programmable logic device software for plc
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15057—FPGA field programmable gate array
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15074—Modules on bus and direct connection between them for additional logic
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15078—Modules, construction of system
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15105—Hardwired logic to accelerate, speed up execution of instructions

Definitions

  • the present invention relates to a storage-programmable control system having several inputs and outputs for linking process control elements, for example sensors or final controlling elements.
  • the present invention also relates to a method for operating a storage-programmable control system and a method for the computer-controlled, internal electrical connection of a field-programmable gate array.
  • the present invention provides a storage-programmable control system which can handle extremely fast control operations. Furthermore, the present invention provides a method which enables such a storage-programmable control system, containing a logic module with a field-programmable gate array, to be programmed quickly and simply.
  • control system of the present invention By providing the control system of the present invention with at least one logic module having an internal interconnection connecting at least one output to its corresponding input, extremely fast control operations can be handled. In this manner, the output signal from this output is constantly adapted to the value of the corresponding input, so that a costly alarm response system, which would otherwise be necessary at this input, is no longer needed.
  • the logic module of the present invention is advantageously designed to operate in parallel, so that several inputs and outputs are connected to one another..As a result, the output signals from these outputs are not subject to- beat frequencies and fluctuations caused by the processing time and can therefore be stably reproduced.
  • control system can be easily adapted to altered requirements.
  • the logic module By providing the logic module with a static storage device for storing the conditions which stipulate its internal interconnection, programming the logic module is quite simple.
  • the logic module can be a field-programmable gate array (FPGA).
  • the logic module is advantageously configured in an input/output subassembly, since the control system's system bus would no longer be needed for data transfer.
  • the logic module is also advantageous.
  • control system of the present invention enables at least one input signal to be read into a logic module and processed there, so that the logic module is capable of outputting an output signal corresponding to the input signal.
  • the present invention provides the following method which enables a storage-programmable control system to be programmed quickly and simply:
  • the determined internal electrical configuration including the connections and possibly the logic functions, are applied to the logic array;
  • the logic array is then programmed by
  • Programming the logic array is particularly simple for the user when the total functional performance characteristics are specified in a programming language for storage-programmable control systems, especially in a graphic programming language.
  • FIG 1 depicts several subassemblies of a modular storage-programmable control system
  • FIG. 2 depicts the internal structure of an input/output subassembly
  • FIG. 3 depicts the connections between inputs and outputs
  • FIG. 4 depicts the structural design of an input/output subassembly
  • FIG. 5 depicts the inner structure of a field-programmable gate array
  • FIG. 6 depicts the design of a logic block
  • FIG. 7 depicts an example of solving a traffic-signal installation problem
  • FIGS. 8a-8n depicts the corresponding solution realized by circuit engineering of the traffic-signal-installation control
  • FIG. 9 depicts the preliminary establishment of the internal electrical connections
  • FIG. 10 depicts an example of an internal electrical standard connection
  • FIG. 11 depicts the specified total performance characteristics realized in the field-programmable gate array.
  • FIG. 12 depicts schematically depicts the communication between the logic module and the processor.
  • a modular storage-programmable control system comprises a current supply 1, a central processing unit 2, the input/output subassemblies 3, 3', as well as additional peripheral units 4.
  • the subassemblies 2, 3, 3', 4 are interconnected via a bus 5.
  • the central processing unit 2 has at least one processor 6 for executing a program, as well as an interface 7 for exchanging data with a programming unit.
  • the subassembly 3 has a logic module 10, which can be a field-programmable gate array (FPGA), for example.
  • the logic module 10 is connected via processor 11 to the bus 5 and, consequently, to the central processing unit 2.
  • FPGA field-programmable gate array
  • the user sets up two program parts using the above-mentioned programming unit: a non-time critical part; and a time-critical part. Both parts are transferred by the programming unit to the processor 6 of the central processing unit 2.
  • the non-time critical part is stored in the central processing unit 2, as is customary for storage-programmable control systems, and is executed sequentially.
  • the time-critical part is transferred further by the processor 6 to the logic modules 10, 10', and is converted by these modules into a logical interconnection.
  • the two program parts operate independent of one another. However, by using special commands, the processor 6 and the logic modules 10, 10' can exchange information.
  • the logical conditions, which establish the interconnection of the logic module 10, are advantageously transferred to a static storage device 12 of the logic module 10, such that the interconnection of the logic module 10 is determined based on the contents of the storage device 12.
  • the subassembly 3' likewise has a logic module 10' with a static storage device 12'. However, the logic module 10' is programmed via a user storage module 13'. When the interconnection of the logic module 10' is to be altered, the user storage module 13' must be replaced or reprogrammed since the logical conditions which determine the interconnection of the logic module 10' are stored in the user storage module 13'.
  • FIG. 2 shows the electrical design of the subassembly 3.
  • the inputs 8 are connected via input filters 14 to the logic module 10, and the outputs 9 are connected from the logic module 10 via output drivers 15 thereby ensuring that the logic module 10 is not damaged by an unintentionally defective circuit wiring, a short circuit, or similar malfunctions.
  • the input signals can be debounced by the input filters 14.
  • signal levels can be adapted to by the filters 14 and the drivers 15, for example from 20 mA to 5 V.
  • the logic module 10 is connected, via bus 16 and control lines 17, to the processor 11, and thus also to the processor 6. Therefore, monitoring the correct function of the logic module 10 is possible, even during operation.
  • the values of corresponding inputs 8 and outputs 9 can be transmitted simultaneously to the processor 11 and, in addition, to the processor 6 for processing in the logic module 10.
  • intermediate states of the logic module 10 for example a flag or a counter content, can be signalled to the processor 6.
  • New control parameters for example new time constants, can also be transferred to the logic module 10.
  • the control lines 17 depicted in FIG. 2 are used, for example, to transmit a reset signal, with which the internal flags can be reset, and to allow the logic module 10 to provide the processor 6 with its present programming state, for example, "programming logic module altered".
  • the programming of the logic module 10 can only be altered when the logic module 10 is inactive, i.e., when the logic module 10 is not linked to the control of a process.
  • the logic module 10 comprises several independent operative parts, deactivating only one part, to alter that part's programming, is possible.
  • the logic module 10 has an input latch 20 and an output latch 21, clocked, for example, with a clock pulse of 1 MHz.
  • the inputs 8 provide the inputs of the input latch 20.
  • the outputs of the output latch 21 provide the outputs 9.
  • the actual, parallel processing of the signals takes place between the latches 20, 21.
  • an elementary logical gating of the inputs E0 and E1 is carried out, for example, in the logic switch 22, possibly also including interim results, as is indicated through the line 23.
  • the result of the logic switch 22 can be further processed or directly supplied to one of the output latch's input pins.
  • the result of the logic switch 22 is provided to the output A0.
  • the logic switches 22 can carry out any elementary, logical gatings, for example, EQV, AND, OR, NAND, NOR.
  • the logic module 10 advantageously has storing elements 24, from which counters, timing devices or edge trigger flags, for example, can then be set up.
  • FIG. 4 depicts a preferred structural design of the input/output subassembly 3.
  • the subassembly 3 is preferably an encapsulated, pluggable, printed-board assembly, connected to a modular mounting rack 25.
  • the subassembly 3 has a module slot 26 to accommodate, for example, the user module 13' depicted in FIG. 1 and has an interface 27 for linking a programming unit. Programming the logic module 10 contained in the subassembly 3 directly (i.e., not via the processor 6) is possible via the user module 13' and the interface 27.
  • the subassembly 3 includes two sub-D plug-in contacts 28a and 28b, whereby the contacts 28a are used for connecting sensors and the contacts 28b are used for connecting final controlling elements.
  • the present invention maps a conventional, sequential, user program for a storage-programmable control system, to the extent possible, onto the structures known from contactor relaying (i.e., to directly wire up the corresponding inputs and outputs via logic elements).
  • contactor relaying i.e., to directly wire up the corresponding inputs and outputs via logic elements.
  • the logical conditions of a user program produced in a programming language for storage-programmable control systems are converted into a connection list and filed in a data field. These data are then loaded into the logic module 10 and provide the data necessary for a corresponding internal interconnection of the logic module 10.
  • FIG. 1 interconnecting several of these logic modules 10, 10' serially and/or in parallel to one another is possible such that the program to be run is divided between the central processing unit 2 and the subassemblies 3,3'.
  • the logic module was used in a modular programmable controller. This application of the logic module is also possible in a programmable controller capable of stand-alone operation. In the most basic version of this programmable controller, the programmable controller no longer has a processor, but still has the logic module, so that the program to be executed is carried out solely by the logic module. In such a version, programming the logic module takes place either via an interface to a programming unit or via a storage module previously programmed by the user.
  • FIG. 5 depicts a portion of the inner structure of such a logic arrays.
  • the inner structure shows a two-dimensional matrix of, for example, 12 ⁇ 12 logic blocks 31. This matrix is surrounded by a ring of input/output blocks. Two input/output blocks are assigned to both the beginning as well as the end of each row and each column. The input/output blocks are not depicted for clarity.
  • two non-interruptible connections 32 are assigned to each row of logic blocks 31; and three connections 33, two of which can be interrupted once in the middle of each column are assigned to each column.
  • This configuration of logic blocks 31 and input/output blocks is penetrated by a network with 13 ⁇ 13 switching matrices 34, whereby adjacent switching matrices 34 are each interconnected via five short connections 35.
  • the logic blocks 31 each comprise a combination block 310, which determines two output variables 312 from a maximum of five input variables 311. Further, the logic block 31 has two flipflops 313, 314, having input signals consisting either of one of the output variables 312 of the combination block 310 or of a variable input directly through the input 315. The output signals from the flipflops 313, 314 can either be fed back into the combination block 310 or be output as one of the output signals 316 from the logic block 31. Thus, programming the logic block 31 can be directed towards those logic and/or storage functions to be carried out.
  • the two output functions of the logic block 31 are independent of one another. However, here they are always selected to be the same, since each of the two outputs 316 can be directly connected to two of the four closest neighbors of its logic module. Because the two functions are identical, the output signal of each logic block 31 can be made available as an input signal to its four closest neighbors (see FIG. 5). Therefore, a more structured topology results.
  • outputs 316 can be connected to the short connections 35 surrounding them, as well as to the long connections 32, 33 surrounding them.
  • electrical connections still can be programmed among the points of intersection between the long connections 32, 33, as well as between the long connections 32, 33 and the short connections 35.
  • the switching matrices 34 are likewise programmable. They can realize a multitude of the theoretically conceivable interconnections, for example, horizontal and/or perpendicular through-connections, the contacting of horizontal with perpendicular short connections 35, and dividing up one connection into two or three.
  • the input/output blocks are connected to a chip connection pin and can optionally either input or output a signal, whereby this signal can be optionally clocked or not.
  • each logic block 31, each switching matrix 34, and each input/output block are each stored locally in these elements.
  • each is provided with a small static storage device 12 (SRAM).
  • SRAM static storage device 12
  • Manufacturers' manuals, such as manuals covering the XC 3000 logic cell array family by Xilinx may be referred to, to provide any further details concerning field-programmable gate array modules.
  • ASIC application specific integrated circuit
  • Programs exist for converting the desired programming into internal interconnections of the logic module 10.
  • the running time of these programs that is, the time required to transform the desired total performance characteristics into an internal interconnection of the logic arrays, amounts to quite a few minutes, hours, sometimes even days.
  • the long running time of these programs is particularly due to the diverse connecting possibilities.
  • the example is drawn from the task collector, Simatic S5 of Siemens AG, order no. E 80850-C 345-X-A1, and is clarified referring to FIG. 7.
  • traffic on a street must be directed over a traffic lane due to construction work.
  • an optional traffic-signal installation is installed. When the installation is switched on, both traffic lights show red. If an initiator is actuated, then a corresponding light switches after 10 seconds to green. The green phase is supposed to last for at least 20 seconds, until both signal lamps show red again as the result of possible actuation of the other initiator. After 10 seconds, the other traffic lane is switched to green. If there is no status signal from an initiator, then the traffic-signal installation remains in its current state. The installation is only supposed to be able to be switched off after the green phase of a traffic lane. When the control system is switched on, the initial state (M0) must be unconditionally set.
  • the corresponding interconnection is represented in the programming language for storage programmable controllers FUP (function diagram), as depicted in FIGS. 8a-8n.
  • FUP function diagram
  • FIGS. 8a-8n A typical user of storage programmable controllers is familiar with this type of programming.
  • the present invention converts the specified total performance characteristics, formulated in a programming language for storage programmable controllers, quickly and simply into an FPGA structure, such that the user of storage programmable controllers can program the logic module 10.
  • the program converted into the corresponding internal interconnection of the logic module 10 by the user program only takes advantage of a small fraction of the theoretically complex possibilities of the logic module 10 because a portion of the connections freely selectable in principle, for example the internal interconnection of the switching matrices 34, is firmly stipulated in the conversion program, and thus cannot be influenced by the programmer of the user program.
  • the interconnections of the switching matrices 34 of each of the thirteen perpendicular columns are explicitly specified such that, first of all, the top-most, the bottom-most, as well as the middle three switching matrices 34 of one column connect through the horizontally running short connections 35 and, for the moment, do not yet connect the other short connections 35, and secondly, the remaining switching matrices 34 only connect through the perpendicular (i.e., vertical) short connections 35 and block the horizontal short connections 35.
  • a structure as depicted in FIG. 9 is formed as follows: groups 36 are formed, each containing five logic blocks 31, arranged one below the other, and surrounded in the front and back by five short connections 37 which extend over the length of a "half column".
  • the circuit arrangement of FIG. 8 is mapped onto these groups 36 in a manner described below.
  • the two horizontal middle rows of logic blocks 31 are used to generate clock signals in a manner described below.
  • the groups 36 formed in this manner are of a manageable size. On the one hand, they are not so complex as to be incomprehensible so that estimating if a subnetwork of the total circuit arrangement to be realized can be achieved by one of the groups 36 is easy. On the other hand, the groups are large enough so that breaking up the entire circuit arrangement of FIG. 8 into subnetworks which are too small is not necessary.
  • the available connection resources and the available logical capacity of the groups 36 are used as a criterion for selecting the subnetworks. Each subnetwork is designed such that:
  • the AND-gate 82 can be realized in the same logic block 31 is immediately recognizable, since combining these two functions also only results in a combination function with three inputs and one output.
  • a separate logic block 31 is assigned to the RS-flipflop 83, since each of the logic blocks 31 can either only execute a combination function or only detect a storage function due to a compiler directive. Therefore, the subnetwork 84 (see FIG. 8a) can be realized in one group 36, since altogether only four input signals (of a maximum of 5); one output signal (of a maximum of 5) and two logic blocks 31 (of a maximum of 5) are needed.
  • the other networks 91 through 100 (see FIGS. 8g-8n) of the entire circuit arrangement are divided up analogously, but are not yet assigned to specific groups 36.
  • timing elements 99 and 100 cause a certain difficulty when the individual networks are divided up, since no corresponding counterpart in the "world of field programmable gate arrays" corresponds to a timing element in the "world of storage programmable controllers". Nevertheless, to allow the user of storage programmable controllers to easily program timing elements, this function, often required for storage-programmable control systems, is made available to the user as a function macro.
  • the compiler recognizes that a function macro exists and converts this macro into an internal standard connection movable within the logic arrays.
  • the internal standard connection was first determined thereby by the compiler manufacturer or rather by the ASIC designer. In this manner, the compiler is not burdened with determining the connections which realize the function macro.
  • FIG. 10 shows an example of such a standard connection for a timer, which can count up to 2 10 cycle times.
  • the actual countable time of course, still depends on the clocking of the counting unit.
  • FIG. 10 requires three side-by-side groups 36 of logic blocks 31.
  • the exact mapping of the logic on FPGA structures depicted in FIG. 10 is irrelevant for the user of storage programmable controllers.
  • the compiler manufacturer, or rather the ASIC designer must be careful that only local connections, in other words direct connections and short connections 35, are used rather than global long connections 32, 33. This enables these macros to not only be easily moved (thus relocated) and also to be placed independently of the networks or macros surrounding them.
  • subnetworks 84 through 98 After the-entire circuit arrangement is broken down into subnetworks 84 through 98, these subnetworks are combined, in so far as the combination also fulfills the above described criteria a) through d).
  • the subnetworks 87 (see FIG. 8d) and 94 (see FIG. 8j), as well as the subnetworks 93 (see FIG. 8i) and 97 (see FIG. 8m) are combinable. This combination is not absolutely necessary, but does increase the utilization factor of the logic arrays.
  • the individual subnetworks 84 through 100 are assigned now to the individual groups 36, as depicted in FIG. 11.
  • the subnetworks 84 through 100 are allocated to the individual groups 36 by their sequence. This is the simplest way to allocate the subnetworks. More complex solutions which already consider the connections of the subnetworks 84 through 100 among themselves are also conceivable.
  • the outermost groups 36 are not occupied, since the external, lengthened, short connections 37 are not available to tie up these groups, but are needed elsewhere. This use for a different purpose shall be described below.
  • the internal electrical connections are established.
  • the direct connections between the logic blocks 31 are utilized initially.
  • only the flag output of the subnetworks 84 through 91 can be put through further into the next network in each case.
  • this is not useful, since the output signals from the individual subnetworks are also needed elsewhere and, therefore, more global connections must be used.
  • the input and output signals to and from the process to be controlled are put through, thus the input signals E0 through E2 and the output signals A1 through A4.
  • the input and output signals are fed directly via the horizontal long connections 32 to the outermost of the lengthened short connections 37. If the horizontal long connections 32 are already occupied, for example because three signals have to be put through, but only two horizontal long connections 32 are available, the signals are initially applied to perpendicular long connections 33 or to the perpendicular short connections 37. They are then fed via a long connection 32, which is assigned to another row of logic blocks 31, to the edge of the logic arrays. At the edges of the logic arrays, the input and output signals are put through further by the lengthened short connections 37 such that, for example, the logical input signal E0 is put through to the physical process input E0.
  • the five lengthened short connections 37 between the subnetworks 84 through 100 always suffice to network the inputs and outputs of the subnetworks 84 through 100 perpendicularly to one another. Should more than five lines be required, the perpendicular long connections 33 would be used to effect a complete connection, preferably initially the interruptible long connections 33.
  • the three internal output signals still to be put through are applied to three of the horizontal long connections 32, so that they are likewise able to be tapped off where they are needed. If one of these three signals is produced in the top row of the groups 36 as an output signal, but is needed in the bottom row of groups 36 the specific internal output signal is applied to one of the horizontal long connections 32 in the top half of the logic arrays.
  • This horizontal long connection 32 is connected to a perpendicular long connection 33, and the perpendicular long connection 33 is connected to a horizontal long connection 32, arranged in the bottom half of the logic arrays so that this signal is also available in the bottom half of the logic arrays.
  • the three internal signals mentioned above are produced only once as an output signal, namely in the subnetworks 90, 93 and 94, and are also needed only once as input signals, namely by the subnetworks 89, 99 and 100.
  • these signals can be connected among themselves directly via closest-neighbor connections of the logic blocks 31.
  • a connection is also possible via the lengthened short connection 37 situated between the prevailing subnetwork pairs. In both cases, no horizontal connections 32, 41, 42, 43 are needed Consequently, these connections are available elsewhere.
  • clock pulses of 1 ms, 10 ms, 100 ms and 1 second are made available within the logic arrays in the following manner:
  • Divider steps are set up by the compiler manufacturer using ASIC design tools. These steps divide any applied clock pulse down to 1/10, 1/100 and 1/1000 of its original frequency. This divider macro, is created thereby such that it only requires the two middle, previously unused rows of logic blocks 31, as well as the direct connections between these logic blocks. This portion of the system- programming of the FPGAs is fixed and does not change. A clock pulse of 1 ms is applied directly into this divider macro from outside of the logic module 10, via one of the input/output buffers.
  • the logic modules 10, 10' and the central processing unit 2 must also exchange data with one another during operation.
  • the parameterization of the logic module 10 may need to be changed during operation.
  • the central processing unit 2 should be informed, at least from time to time, about the actual state of the logic module 10 (or 10').
  • the processor 6 and the logic modules 10, 10' are not synchronized with one another. Therefore, the problem of data consistency arises. As a result, the problem is further magnified because the processor 6 and the logic modules 10, 10' communicate data to each other serially. The serial data communication is necessary., otherwise too many of the pins of the logic modules 10, 10' would be needed to communicate with the processor 6.
  • the problem is solved by providing the user with other function macros.
  • These function macros realize shift registers used for temporarily storing or buffering input or output data, and realizing working storages.
  • the new data to be input are first written thereby by the processor 6 into the write buffer storage, for example of the logic module 10.
  • the values stored in the buffer storages are indeed available in the logic module 10, but are not yet used since they have not yet been released.
  • the new values written into the logic module 10 are then retrieved by the buffer storages into the working storages by a separate command.
  • the values read out of the logic module 10 are read into other, so-called read buffer storages.
  • the data are then serially read out of these read buffer storages into the processor 6.
  • FIG. 12 shows an example of such a data cycle.
  • five lines are needed to transmit all the required signals.
  • the following information is transmitted on those lines:
  • CLK is a clock pulse.
  • CLK binary one (1)
  • the buffer storage addressed at any one time reads a new bit in or out.
  • DATA is the data line, on which the information is transmitted. In the present example, nothing but binary ones (Is) are transmitted (purely coincidentally).
  • At least four lines namely the lines RW, CLK, data, as well as at least one address line, are needed to read from or write to the buffer storages.
  • These four signals are applied to the middle one of the three short, previously unused, connection strips 43 (see FIG. 9). As a result, these four signals are available across the entire logic module 10. When no parameters at all have to be read in or out, the middle one of the three short connection strips 43 is available for internally connecting the groups 36.
  • additional address signals PA3, PA4, etc. are applied to the logic module 10. These additional address signals are normally applied to two horizontal long connections 32 (see FIG. 5), whereby one of the long connections 32 is configured in the top half of the logic field, and the other in the bottom half of the logic arrays.
  • the signal-light control selected in the present case as an exemplified embodiment is of course not as time-critical as other control operations.
  • the signal-light control example was selected because the principle procedure was able to be easily explained on the basis of this simple example.

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US7822881B2 (en) 1996-12-27 2010-10-26 Martin Vorbach Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
US6088795A (en) * 1996-12-27 2000-07-11 Pact Gmbh Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)
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CA2061599A1 (en) 1992-08-23
EP0642094A3 (de) 1995-05-10
EP0499695A2 (de) 1992-08-26
EP0642094B1 (de) 1998-09-02
EP0642094A2 (de) 1995-03-08
DE4205524A1 (de) 1992-08-27
DE4205524C2 (de) 1999-04-29
DE59107764D1 (de) 1996-06-05

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