[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

US5391257A - Method of transferring a thin film to an alternate substrate - Google Patents

Method of transferring a thin film to an alternate substrate Download PDF

Info

Publication number
US5391257A
US5391257A US08/165,050 US16505093A US5391257A US 5391257 A US5391257 A US 5391257A US 16505093 A US16505093 A US 16505093A US 5391257 A US5391257 A US 5391257A
Authority
US
United States
Prior art keywords
substrate
thin film
bonding
layer
epitaxial thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/165,050
Inventor
Gerard J. Sullivan
Mary K. Szwed
Mau-Chung F. Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Skyworks Solutions Inc
Original Assignee
Rockwell International Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rockwell International Corp filed Critical Rockwell International Corp
Priority to US08/165,050 priority Critical patent/US5391257A/en
Assigned to ROCKWELL INTERNATIONAL CORPORATION reassignment ROCKWELL INTERNATIONAL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, MAU-CHUNG F., SULLIVAN, GERARD J., SZWED, MARY K.
Application granted granted Critical
Publication of US5391257A publication Critical patent/US5391257A/en
Assigned to ROCKWELL SCIENTIFIC COMPANY, LLC reassignment ROCKWELL SCIENTIFIC COMPANY, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CONEXANT SYSTEMS, INC.
Assigned to TELEDYNE SCIENTIFIC & IMAGING, LLC reassignment TELEDYNE SCIENTIFIC & IMAGING, LLC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: ROCKWELL SCIENTIFIC COMPANY, LLC
Assigned to ROCKWELL SCIENCE CENTER, INC. reassignment ROCKWELL SCIENCE CENTER, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ROCKWELL INTERNATIONAL CORPORATION
Assigned to ROCKWELL SCIENCE CENTER, LLC reassignment ROCKWELL SCIENCE CENTER, LLC MERGER (SEE DOCUMENT FOR DETAILS). Assignors: ROCKWELL SCIENCE CENTER, INC.
Assigned to CONEXANT SYSTEMS, INC. reassignment CONEXANT SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ROCKWELL SCIENCE CENTER, LLC
Assigned to SKYWORKS SOLUTIONS, INC. reassignment SKYWORKS SOLUTIONS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TELEDYNE SCIENTIFIC & IMAGING, LLC
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/915—Separating from substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Definitions

  • the present invention relates to the fabrication of thin film devices and, in particular, to a method of transferring a thin film to an alternate substrate.
  • lattice-matched epitaxial growth may require a substrate of a certain material that has other characteristics, such a thermal, mechanical, and/or electromagnetic properties, that produce less than optimal performance in the final device or system.
  • performance may be substantially improved by transferring the thin epitaxial layer from the growth substrate to another substrate that has the desired thermal, mechanical, and/or electromagnetic properties.
  • Epitaxial films can be separated from their original growth substrates using known materials processing techniques generally referred to as epitaxial liftoff (ELO).
  • ELO epitaxial liftoff
  • One such process uses east films of "black wax" (Apiezon W) atop the epitaxial layer to provide support after separation from the original substrate. Bonding to a new substrate can be achieved through Van der Waals attraction to the new surface or metallurgical interactions with a gold or palladium coating. Black wax, however, is not easily manipulated, and the method of casting is not part of a normal microelectronics fabrication process. The total area that can be lifted using black wax is small, unless the epitaxial layer and wax are bent away from the substrate to allow the etching agent to get deeper under the layer. Bending of a thin epitaxial layer, however, is not desirable because it can damage the materials or structures of the layer. Furthermore, post processing of the lifted film suffers from the fragility, opacity, and low tolerance of black wax to solvents and elevated temperatures.
  • Another known ELO process uses polyimide films to support both continuous and patterned epitaxial structures.
  • Use of transparent polyimide as a membrane material facilitates vacuum deposition on the back surface of the epitaxial material after liftoff and before grafting. Perforation of the polyimide membrane allows visibility through the membrane to the host substrate, even after metal film deposition on the underside. These attributes facilitate manipulation and alignment of arrays of previously fabricated devices without the need for transfer from the primary temporary support membrane to a secondary membrane.
  • the flexibility of polyimide membranes can cause damage to thin film circuit devices as a result of bending.
  • the thin film to be transferred is held by a rigid temporary substrate, a problem may be encountered releasing the film from the temporary substrate after the film has been attached to the host substrate.
  • dissolving a glue bond with solvents is effective only for small sections since the rate of dissolution drops exponentially with distance from an edge.
  • One approach to this problem has been to glue the thin film to a temporary substrate of silicon that has had many holes etched through it. This allows solvents better access to the bonding glue, but fragile circuit films can be damaged where they bridge the relatively large holes etched in the silicon substrate.
  • the present invention comprises a method of transferring a thin film, such as a semiconductor epitaxial layer, from an original substrate to an alternate host substrate.
  • a thin film such as a semiconductor epitaxial layer
  • an etch stop layer is provided below an epitaxial layer grown on a semiconductor substrate.
  • the epitaxial layer is bonded, using metallic solder, for example, to a rigid host substrate having desirable thermal, electromagnetic, and/or mechanical properties.
  • the original growth substrate is then separated from the transferred epitaxial layer using the etch stop layer.
  • the epitaxial layer is first bonded to a rigid, porous, temporary support substrate using a thermally or chemically releasable resin, for example.
  • the original growth substrate is removed using the etch stop layer so that the side of the epitaxial layer originally abutting the growth substrate can be bonded to the rigid host substrate, as described above.
  • the temporary substrate is then removed using the releasable resin, leaving the transferred epitaxial layer attached to the host substrate.
  • a principal object of the invention is a method of transferring thin films to alternate substrates.
  • a feature of the invention is use of a temporary substrate that is rigid, porous with uniform small pores, and easily releasable from transferred thin films.
  • An advantage of the invention is the use of rigid substrates to support transferred thin films having large areas.
  • FIGS. 1A-F are schematic cross-sections illustrating the transfer of a thin film to an alternate substrate using a single transfer process of the present invention.
  • FIGS. 2A-F are schematic cross-sections illustrating the transfer of a thin film to an alternate substrate using a double transfer process of the present invention.
  • Lattice-matched epitaxial growth may require a substrate of a certain material, for example a III-V semiconductor such as gallium arsenide or indium phosphide, that has less than optimal thermal, mechanical, and/or electromagnetic characteristics with respect to performance of finished devices or systems, such as light emitting diodes, lasers, and high power heterojunction bipolar transistor (HBT) amplifiers.
  • a substrate of a certain material for example a III-V semiconductor such as gallium arsenide or indium phosphide
  • HBT heterojunction bipolar transistor
  • performance can be significantly improved by transferring the thin epitaxial layer (or layers) from the growth substrate to another substrate, such as diamond or aluminum nitride, for example, that has the desired thermal, mechanical, and/or electromagnetic properties.
  • the actual thin film to be transferred may comprise unprocessed epitaxial layers, functional circuits, microelectromechanical devices, or other thin film structures.
  • FIGS. 1A-F A single transfer process is illustrated schematically in FIGS. 1A-F.
  • a GaAs substrate 10 is prepared with an etch-stop layer 12, that may comprise AlAs or AlGaAs, for example.
  • An epitaxial layer 14 is then grown atop the etch-stop layer 12.
  • Epitaxial layer 14 may comprise one or more epitaxial growths or thin layers, such as GaAs, InGaAs, and AlGaAs for fabricating HBTs, for example.
  • epitaxial layer 14 is bonded to a host substrate 16, comprising a material such as diamond or aluminum nitride (AlN), for example, that has desirable thermal, mechanical, and/or electromagnetic properties. Bonding of layer 14 to host substrate 16 may be accomplished using a resin or glue, a metallic solder for good thermal conductivity, or chemical bonds that would form if host substrate 16 were deposited directly on top of layer 14. In the process illustrated in FIGS. 1A-F, epitaxial layer 14 and host substrate 16 are coated with metal adhesion and barrier layers 18, which may comprise Ti/Pd barrier metal, for example.
  • metal adhesion and barrier layers 18 which may comprise Ti/Pd barrier metal, for example.
  • Metal layers 18 can then be bonded using a bonding layer 19 of indium (In) or tin (Sn) conductive metal, for example, applied to either or both of metal barrier layers 18.
  • the layers of FIG. 1B are brought together and heated so that bonding layer 19 solders metal barrier layers 18 together to form a solid, thermally conductive bond as shown in FIG. 1C.
  • original substrate 10 can be lapped and then reactive ion etched up to etch-stop layer 12, as shown in FIG. 1D.
  • Etch-stop layer 12 can then be removed by selective etching and the whole structure inverted, as shown in FIG. 1E, for conventional fabrication of circuit devices, as illustrated in FIG. 1F.
  • epitaxial layer 14 (which may comprise a plurality of thin layers as described above) is now inverted from its original growth sequence.
  • FIGS. 2A-F A double (or multiple) transfer process of the present invention is illustrated in FIGS. 2A-F.
  • FIG. 2A which is similar to FIG. 1A, shows a GaAs substrate 20, an AlAs or AlGaAs etch-stop layer 22, and an epitaxial layer 24 grown atop layer 22.
  • Epitaxial layer 24 may comprise one or more epitaxial growths or thin layers, such as GaAs, InGaAs, and AlGaAs for fabricating HBTs, as in the example above.
  • the top of epitaxial layer 24 is then bonded to a rigid, temporary substrate 26 using a releasable bonding material 25.
  • Bonding material 25 may comprise a glue or resin that can be released, for example, with a thermal, chemical, or photoactivated process.
  • temporary substrate 26 comprises a rigid, porous material such as porous alumina (Al 2 O 3 ), for example.
  • Porous alumina has a coefficient of thermal expansion that is a good match for GaAs and InP substrates so that strain on the thin film is reduced during the transfer process.
  • a porous material provides a good temporary substrate 26 because the surface hole size can be small enough not to damage the fragile thin film to be transferred but still allow resin releasing solvents to penetrate substrate 26 for fast release of the temporary bond.
  • Porous materials suitable for temporary substrate 26 are typically made by taking a powder form of the desired material (perhaps combined with a binder material to improve bonding), pressing it into a desired shape, and sintering it to strengthen the bonds.
  • the material is generally chosen to optimize a certain characteristic, such as coefficient of thermal expansion, for example.
  • the pore size of the final material is largely determined by the particulate size of the forming powder.
  • the density, or porosity, of the final material is a function of the force used to press the powder into the desired shape.
  • the pressed and sintered porous material can be made into a suitable temporary substrate 26 using well known shaping and polishing methods.
  • porous substrate 26 There are many materials that can be prepared as porous substrate 26.
  • Aluminum oxide pressed powder disks for example, are commercially available and have a fairly good match to the coefficient of thermal expansion of GaAs.
  • a variety of glasses can be prepared as porous substrate 26, some of which have a good match to the coefficient of thermal expansion of silicon. In theory, it should be possible, although probably not always practical, to prepare any chemically stable solid, including diamond and most metals, as porous substrate 26.
  • the pore size of temporary substrate 26 should be large enough to allow for rapid transport of resin releasing agents through the substrate, but small enough that layer 24 is supported effectively by the releasable bonding agent 25 where layer 24 traverses a pore of the porous material of substrate 26. Therefore, the pore size of substrate 26 should be a fraction of the average thickness of the releasable resin 25. For typical resin thicknesses of 15 to 30 microns, for example, the pore size should be in the 5 to 20 micron range.
  • a host substrate 30, as described above, may then be bonded to the bottom surface of epitaxial layer 24.
  • bonding of layer 24 to host substrate 30 may be accomplished using a resin or glue, a metallic solder for good thermal conductivity, or chemical bonds that would form if host substrate 30 were deposited directly on layer 24.
  • epitaxial layer 24 and host substrate 30 are coated with metal adhesion and barrier layers 28, which may comprise Ti/Pd barrier metal, for example.
  • Metal layers 28 can then be bonded together using a bonding layer 29 of indium (In) or tin (Sn) conductive metal, for example, applied to either or both of metal barrier layers 28.
  • the layers of FIG. 2D are brought together and heated so that bonding layer 29 solders metal barrier layers 28 together to form a solid, thermally conductive bond.
  • epitaxial layer 24 After epitaxial layer 24 has been bonded to host substrate 30, releasable bonding layer 25 is dissolved or otherwise released, as shown in FIG. 2E, using a chemical, thermal, or ultraviolet process, for example. After cleaning as necessary to remove residual temporary bonding material 25, epitaxial layer 24, now bonded to host substrate 30, is ready for conventional fabrication of circuit devices as illustrated in FIG. 1F.
  • the final orientation of epitaxial layer 24 (which may comprise a plurality of thin layers as described above) is its original growth order. As can be seen, transferred layer 24 will end up in a face up or face down orientation depending on the number of transfers (i.e., even or odd) in the overall process.
  • the method of the present invention has be described with reference to HBT epitaxial layers grown on a GaAs substrate.
  • the process is applicable to the transfer of any thin film to an alternate, rigid substrate.
  • Prior art transfer processes that use flexible membranes can damage delicate films and circuits by bending the layers during transfer. Transfer processes that rely on chemical attack of a bonding layer exposed along the edge of a wafer severely limit the size of the thin film patch that can be released and transferred.
  • the present invention is most applicable to the transfer of a thin film, such as an epitaxial layer (or layers) or a complete semiconductor circuit, for example, from a growth substrate to a host substrate having more desirable performance characteristics.
  • the host substrate may comprise any suitable material, such as diamond, polycrystalline AlN, sapphire, or silicon, for example.
  • Temporary substrate 26 may comprise any rigid material that can be released after it is temporarily bonded to the thin film being transferred.
  • porous ceramic materials used as temporary substrate 26 have advantages in allowing a chemical solvent to reach and dissolve the glue or resin 25 used for the temporary bond.
  • the temporary bonding material 25 my comprise a material that can be released using a thermal, chemical, or photochemical process, for example. Selected portions of a thin film can be released and/or transferred by using a photosensitive glue and an optical mask to expose and release selected regions of the thin film layer onto specific spots of the new substrate. Likewise, if the glue is thermally releasable, certain regions can be heated while others are not to release and/or transfer only selected regions.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

A method is described for transferring a thin film of arbitrarily large area from an original substrate to an alternate substrate. An etch stop layer is provided below an epitaxial layer, for example, grown on a semiconductor substrate. In a single transfer process, the epitaxial layer is bonded to a rigid host substrate having desirable thermal, electromagnetic, and/or mechanical properties. The original growth substrate is then removed from the transferred epitaxial layer using the etch stop layer. In a double transfer process, the epitaxial layer is first bonded to a rigid and porous temporary substrate using a thermally or chemically releasable resin, for example. The original growth substrate is removed using the etch stop layer so that the original substrate side of the epitaxial layer can be bonded to a rigid host substrate, as described above. The temporary substrate is then removed using the releasable resin to leave the transferred thin film attached to the host substrate.

Description

TECHNICAL FIELD
The present invention relates to the fabrication of thin film devices and, in particular, to a method of transferring a thin film to an alternate substrate.
BACKGROUND OF THE INVENTION
During fabrication of thin film devices, such as semiconductor devices having epitaxial layers, it is sometimes desirable to transfer a thin layer from one supporting substrate to another. For example, lattice-matched epitaxial growth may require a substrate of a certain material that has other characteristics, such a thermal, mechanical, and/or electromagnetic properties, that produce less than optimal performance in the final device or system. In such a case, performance may be substantially improved by transferring the thin epitaxial layer from the growth substrate to another substrate that has the desired thermal, mechanical, and/or electromagnetic properties.
Epitaxial films can be separated from their original growth substrates using known materials processing techniques generally referred to as epitaxial liftoff (ELO). One such process uses east films of "black wax" (Apiezon W) atop the epitaxial layer to provide support after separation from the original substrate. Bonding to a new substrate can be achieved through Van der Waals attraction to the new surface or metallurgical interactions with a gold or palladium coating. Black wax, however, is not easily manipulated, and the method of casting is not part of a normal microelectronics fabrication process. The total area that can be lifted using black wax is small, unless the epitaxial layer and wax are bent away from the substrate to allow the etching agent to get deeper under the layer. Bending of a thin epitaxial layer, however, is not desirable because it can damage the materials or structures of the layer. Furthermore, post processing of the lifted film suffers from the fragility, opacity, and low tolerance of black wax to solvents and elevated temperatures.
Another known ELO process uses polyimide films to support both continuous and patterned epitaxial structures. Use of transparent polyimide as a membrane material facilitates vacuum deposition on the back surface of the epitaxial material after liftoff and before grafting. Perforation of the polyimide membrane allows visibility through the membrane to the host substrate, even after metal film deposition on the underside. These attributes facilitate manipulation and alignment of arrays of previously fabricated devices without the need for transfer from the primary temporary support membrane to a secondary membrane. The flexibility of polyimide membranes, however, can cause damage to thin film circuit devices as a result of bending.
If the thin film to be transferred is held by a rigid temporary substrate, a problem may be encountered releasing the film from the temporary substrate after the film has been attached to the host substrate. For example, dissolving a glue bond with solvents is effective only for small sections since the rate of dissolution drops exponentially with distance from an edge. One approach to this problem has been to glue the thin film to a temporary substrate of silicon that has had many holes etched through it. This allows solvents better access to the bonding glue, but fragile circuit films can be damaged where they bridge the relatively large holes etched in the silicon substrate.
Because of the deficiencies in the known methods of transferring thin films to alternate substrates, there has been a need for a method of transferring thin films that is effective, does not damage fragile films, can transfer entire wafers reliably, and is compatible with established semiconductor fabrication processes.
SUMMARY OF THE INVENTION
The present invention comprises a method of transferring a thin film, such as a semiconductor epitaxial layer, from an original substrate to an alternate host substrate. In the preferred embodiment, an etch stop layer is provided below an epitaxial layer grown on a semiconductor substrate. In a single transfer process, the epitaxial layer is bonded, using metallic solder, for example, to a rigid host substrate having desirable thermal, electromagnetic, and/or mechanical properties. The original growth substrate is then separated from the transferred epitaxial layer using the etch stop layer. In a double (or multiple) transfer process, the epitaxial layer is first bonded to a rigid, porous, temporary support substrate using a thermally or chemically releasable resin, for example. The original growth substrate is removed using the etch stop layer so that the side of the epitaxial layer originally abutting the growth substrate can be bonded to the rigid host substrate, as described above. The temporary substrate is then removed using the releasable resin, leaving the transferred epitaxial layer attached to the host substrate.
A principal object of the invention is a method of transferring thin films to alternate substrates. A feature of the invention is use of a temporary substrate that is rigid, porous with uniform small pores, and easily releasable from transferred thin films. An advantage of the invention is the use of rigid substrates to support transferred thin films having large areas.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and for further advantages thereof, the following Detailed Description of the Preferred Embodiment makes reference to the accompanying Drawings, in which:
FIGS. 1A-F are schematic cross-sections illustrating the transfer of a thin film to an alternate substrate using a single transfer process of the present invention; and
FIGS. 2A-F are schematic cross-sections illustrating the transfer of a thin film to an alternate substrate using a double transfer process of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
During fabrication of some types of semiconductor devices, it may be desirable to transfer thin epitaxial layers from the growth substrate to another supporting substrate. Lattice-matched epitaxial growth may require a substrate of a certain material, for example a III-V semiconductor such as gallium arsenide or indium phosphide, that has less than optimal thermal, mechanical, and/or electromagnetic characteristics with respect to performance of finished devices or systems, such as light emitting diodes, lasers, and high power heterojunction bipolar transistor (HBT) amplifiers. In such devices, performance can be significantly improved by transferring the thin epitaxial layer (or layers) from the growth substrate to another substrate, such as diamond or aluminum nitride, for example, that has the desired thermal, mechanical, and/or electromagnetic properties. The actual thin film to be transferred may comprise unprocessed epitaxial layers, functional circuits, microelectromechanical devices, or other thin film structures.
The method of the present invention is particularly useful for fabricating high power HBT amplifiers. A single transfer process is illustrated schematically in FIGS. 1A-F. A GaAs substrate 10 is prepared with an etch-stop layer 12, that may comprise AlAs or AlGaAs, for example. An epitaxial layer 14 is then grown atop the etch-stop layer 12. Epitaxial layer 14 may comprise one or more epitaxial growths or thin layers, such as GaAs, InGaAs, and AlGaAs for fabricating HBTs, for example.
After substram 10 has been prepared with etch-stop layer 12 and epitaxial layer 14, the top of epitaxial layer 14 is bonded to a host substrate 16, comprising a material such as diamond or aluminum nitride (AlN), for example, that has desirable thermal, mechanical, and/or electromagnetic properties. Bonding of layer 14 to host substrate 16 may be accomplished using a resin or glue, a metallic solder for good thermal conductivity, or chemical bonds that would form if host substrate 16 were deposited directly on top of layer 14. In the process illustrated in FIGS. 1A-F, epitaxial layer 14 and host substrate 16 are coated with metal adhesion and barrier layers 18, which may comprise Ti/Pd barrier metal, for example. Metal layers 18 can then be bonded using a bonding layer 19 of indium (In) or tin (Sn) conductive metal, for example, applied to either or both of metal barrier layers 18. The layers of FIG. 1B are brought together and heated so that bonding layer 19 solders metal barrier layers 18 together to form a solid, thermally conductive bond as shown in FIG. 1C.
After bonding to form the structure of FIG. 1C, original substrate 10 can be lapped and then reactive ion etched up to etch-stop layer 12, as shown in FIG. 1D. Etch-stop layer 12 can then be removed by selective etching and the whole structure inverted, as shown in FIG. 1E, for conventional fabrication of circuit devices, as illustrated in FIG. 1F. In this single transfer process, epitaxial layer 14 (which may comprise a plurality of thin layers as described above) is now inverted from its original growth sequence.
A double (or multiple) transfer process of the present invention is illustrated in FIGS. 2A-F. FIG. 2A, which is similar to FIG. 1A, shows a GaAs substrate 20, an AlAs or AlGaAs etch-stop layer 22, and an epitaxial layer 24 grown atop layer 22. Epitaxial layer 24 may comprise one or more epitaxial growths or thin layers, such as GaAs, InGaAs, and AlGaAs for fabricating HBTs, as in the example above. The top of epitaxial layer 24 is then bonded to a rigid, temporary substrate 26 using a releasable bonding material 25. Bonding material 25 may comprise a glue or resin that can be released, for example, with a thermal, chemical, or photoactivated process. Preferably, temporary substrate 26 comprises a rigid, porous material such as porous alumina (Al2 O3), for example. Porous alumina has a coefficient of thermal expansion that is a good match for GaAs and InP substrates so that strain on the thin film is reduced during the transfer process. A porous material provides a good temporary substrate 26 because the surface hole size can be small enough not to damage the fragile thin film to be transferred but still allow resin releasing solvents to penetrate substrate 26 for fast release of the temporary bond.
Porous materials suitable for temporary substrate 26 are typically made by taking a powder form of the desired material (perhaps combined with a binder material to improve bonding), pressing it into a desired shape, and sintering it to strengthen the bonds. The material is generally chosen to optimize a certain characteristic, such as coefficient of thermal expansion, for example. The pore size of the final material is largely determined by the particulate size of the forming powder. The density, or porosity, of the final material is a function of the force used to press the powder into the desired shape. The pressed and sintered porous material can be made into a suitable temporary substrate 26 using well known shaping and polishing methods.
There are many materials that can be prepared as porous substrate 26. Aluminum oxide pressed powder disks, for example, are commercially available and have a fairly good match to the coefficient of thermal expansion of GaAs. Also, a variety of glasses can be prepared as porous substrate 26, some of which have a good match to the coefficient of thermal expansion of silicon. In theory, it should be possible, although probably not always practical, to prepare any chemically stable solid, including diamond and most metals, as porous substrate 26.
The pore size of temporary substrate 26 should be large enough to allow for rapid transport of resin releasing agents through the substrate, but small enough that layer 24 is supported effectively by the releasable bonding agent 25 where layer 24 traverses a pore of the porous material of substrate 26. Therefore, the pore size of substrate 26 should be a fraction of the average thickness of the releasable resin 25. For typical resin thicknesses of 15 to 30 microns, for example, the pore size should be in the 5 to 20 micron range.
After temporary substrate 26 has been bonded to epitaxial layer 24, as illustrated in FIG. 2B, original substrate 20 and etch-stop layer 22 are removed as described above, resulting in the structure shown in FIG. 2C. A host substrate 30, as described above, may then be bonded to the bottom surface of epitaxial layer 24. As stated above, bonding of layer 24 to host substrate 30 may be accomplished using a resin or glue, a metallic solder for good thermal conductivity, or chemical bonds that would form if host substrate 30 were deposited directly on layer 24. In the process illustrated in FIGS. 2D-F, epitaxial layer 24 and host substrate 30 are coated with metal adhesion and barrier layers 28, which may comprise Ti/Pd barrier metal, for example. Metal layers 28 can then be bonded together using a bonding layer 29 of indium (In) or tin (Sn) conductive metal, for example, applied to either or both of metal barrier layers 28. The layers of FIG. 2D are brought together and heated so that bonding layer 29 solders metal barrier layers 28 together to form a solid, thermally conductive bond.
After epitaxial layer 24 has been bonded to host substrate 30, releasable bonding layer 25 is dissolved or otherwise released, as shown in FIG. 2E, using a chemical, thermal, or ultraviolet process, for example. After cleaning as necessary to remove residual temporary bonding material 25, epitaxial layer 24, now bonded to host substrate 30, is ready for conventional fabrication of circuit devices as illustrated in FIG. 1F. In this double transfer process, the final orientation of epitaxial layer 24 (which may comprise a plurality of thin layers as described above) is its original growth order. As can be seen, transferred layer 24 will end up in a face up or face down orientation depending on the number of transfers (i.e., even or odd) in the overall process.
The method of the present invention has be described with reference to HBT epitaxial layers grown on a GaAs substrate. The process, however, is applicable to the transfer of any thin film to an alternate, rigid substrate. Prior art transfer processes that use flexible membranes can damage delicate films and circuits by bending the layers during transfer. Transfer processes that rely on chemical attack of a bonding layer exposed along the edge of a wafer severely limit the size of the thin film patch that can be released and transferred. The present invention is most applicable to the transfer of a thin film, such as an epitaxial layer (or layers) or a complete semiconductor circuit, for example, from a growth substrate to a host substrate having more desirable performance characteristics. In addition to the example described above, it is useful to transfer III-V semiconductor optoelectronic devices onto silicon chips to form hybrid devices. The host substrate may comprise any suitable material, such as diamond, polycrystalline AlN, sapphire, or silicon, for example.
Temporary substrate 26 may comprise any rigid material that can be released after it is temporarily bonded to the thin film being transferred. As stated above, porous ceramic materials used as temporary substrate 26 have advantages in allowing a chemical solvent to reach and dissolve the glue or resin 25 used for the temporary bond. The temporary bonding material 25 my comprise a material that can be released using a thermal, chemical, or photochemical process, for example. Selected portions of a thin film can be released and/or transferred by using a photosensitive glue and an optical mask to expose and release selected regions of the thin film layer onto specific spots of the new substrate. Likewise, if the glue is thermally releasable, certain regions can be heated while others are not to release and/or transfer only selected regions.
Although the present invention has been described with respect to specific embodiments thereof, various changes and modifications can be carried out by those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.

Claims (17)

We claim:
1. A method of transferring a thin film to an alternate substrate, comprising the steps of:
providing a first semiconductor substrate;
forming an etch-stop layer atop said first substrate;
depositing said thin film atop said etch stop layer, said thin film comprising at least one layer of deposited material;
providing a rigid host substrate;
coating said thin film and said host substrate with respective layers of adhesive barrier metal;
applying a layer of bonding metal to at least one of said layers of adhesive barrier metal:
bringing said coated thin film and said coated host substrate together with said bonding metal in between; and
heating said layers so that said bonding metal solders said adhesive barrier metal layers to form a thermally conductive bond between said thin film and said host substrate; and
removing said first substrate and said etch-stop layer from said thin film.
2. The method of claim 1, wherein said coating step comprises coating said thin film and said rigid host substrate with respective layers of Ti/Pd barrier metal, and said step of applying a layer of bonding metal further comprises selecting said bonding metal from the group consisting of indium and tin.
3. The method of claim 1, wherein the step of removing said first substrate comprises reactive ion etching said first substrate up to said etch-stop layer.
4. A method of transferring an epitaxial thin film to an alternate substrate, comprising the steps of:
providing a first semiconductor substrate;
forming an etch-stop layer atop said first substrate;
growing said epitaxial thin film atop said etch stop layer, said epitaxial thin film comprising at least one layer of epitaxially grown material;
releasably bonding a temporary substrate comprising a rigid, porous material atop said epitaxial thin film;
removing said first substrate and said etch-stop layer from said epitaxial thin film;
bonding said epitaxial thin film to a rigid host substrate; and
releasing said temporary substrate from atop said epitaxial thin film.
5. The method of claim 4, wherein said providing and forming steps comprise providing said first substrate of III-V semiconductor material and forming said etch-stop layer with a material selected from the group consisting of AlAs and AlGaAs.
6. The method of claim 4, wherein said growing step comprises growing said epitaxial thin film to have at least one layer of material selected from the group consisting of GaAs, AlGaAs, and InGaAs.
7. The method of claim 4, wherein said step of releasably bonding comprises bonding said temporary substrate atop said epitaxial thin film using a material selected from the group consisting of thermally, chemically, and photochemically releasable glues and resins.
8. The method of claim 4, wherein the step of removing said first substrate comprises reactive ion etching said first substrate up to said etch-stop layer.
9. The method of claim 4, wherein bonding said epitaxial thin film further comprises the steps of:
coating said epitaxial thin film and said rigid host substrate with respective layers of adhesive barrier metal;
applying a layer of bonding metal to at least one of said layers of adhesive barrier metal;
bringing said coated epitaxial layer and said coated host substrate together with said bonding metal in between; and
heating said layers so that said bonding metal solders said adhesive barrier metal layers to form a thermally conductive bond between said epitaxial thin film and said host substrate.
10. The method of claim 9, wherein said coating step comprises coating said epitaxial thin film and said rigid host substrate with respective layers of Ti/Pd barrier metal, and said step of applying a layer of bonding metal further comprises selecting said bonding metal from the group consisting of indium and tin.
11. The method of claim 4, wherein said step of bonding said epitaxial thin film comprises applying an adhesive between said epitaxial layer and said host substrate.
12. The method of claim 4, wherein the step of bonding said epitaxial thin film comprises depositing said host substrate directly atop said epitaxial thin film.
13. A method of transferring an epitaxial thin film to an alternate substrate, comprising the steps of:
providing a first substrate comprising a III-V semiconductor material;
forming an etch-stop layer atop said first substrate;
growing said epitaxial thin film atop said etch stop layer, said epitaxial thin film comprising at least one layer of epitaxially grown material;
releasably bonding a temporary substrate comprising a rigid, porous material atop said epitaxial thin film;
removing said first substrate and said etch-stop layer from said epitaxial thin film;
bonding said epitaxial thin film to a rigid host substrate comprising a material selected from the group consisting of diamond, aluminum nitride, sapphire, and silicon; and
releasing said temporary substrate from atop said epitaxial thin film.
14. The method of claim 13, wherein bonding said epitaxial thin film further comprises the steps of:
coating said epitaxial thin film and said rigid host substrate with respective layers of Ti/Pd barrier metal;
applying a layer of bonding metal to at least one of said layers of Ti/Pd barrier metal, said bonding metal selected from the group consisting of indium and tin;
bringing said coated epitaxial layer and said coated host substrate together with said bonding metal in between; and
heating said layers so that said bonding metal solders said adhesive barrier metal layers to form a thermally conductive bond between said epitaxial thin film and said host substrate.
15. The method of claim 13, wherein said step of releasably bonding comprises bonding said temporary substrate atop said epitaxial thin film using a material selected from the group consisting of thermally, chemically, and photochemically releasable glues and resins.
16. The method of claim 13, wherein said etch-stop forming step comprises forming said etch-stop layer with a material selected from the group consisting of AlAs and AlGaAs, and said growing step comprises growing said epitaxial thin film to have at least one layer of material selected from the group consisting of GaAs, AlGaAs, and InGaAs.
17. The method of claim 13, wherein said step of releasably bonding comprises bonding a temporary substrate of porous alumina atop said epitaxial thin film.
US08/165,050 1993-12-10 1993-12-10 Method of transferring a thin film to an alternate substrate Expired - Lifetime US5391257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/165,050 US5391257A (en) 1993-12-10 1993-12-10 Method of transferring a thin film to an alternate substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/165,050 US5391257A (en) 1993-12-10 1993-12-10 Method of transferring a thin film to an alternate substrate

Publications (1)

Publication Number Publication Date
US5391257A true US5391257A (en) 1995-02-21

Family

ID=22597213

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/165,050 Expired - Lifetime US5391257A (en) 1993-12-10 1993-12-10 Method of transferring a thin film to an alternate substrate

Country Status (1)

Country Link
US (1) US5391257A (en)

Cited By (167)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5476810A (en) * 1994-01-31 1995-12-19 U.S. Philips Corporation Manufacture of electronic devices comprising thin-film circuits using a metal foil as a temporary support
US5563084A (en) * 1994-09-22 1996-10-08 Fraunhofer-Gesellschaft zur F orderung der angewandten Forschung e.V. Method of making a three-dimensional integrated circuit
WO1997039481A1 (en) * 1996-04-12 1997-10-23 Northeastern University An integrated complex-transition metal oxide device and a method of fabricating such a device
EP0867918A2 (en) * 1997-03-27 1998-09-30 Canon Kabushiki Kaisha Process for producing semiconductor substrate
US5846844A (en) * 1993-11-29 1998-12-08 Toyoda Gosei Co., Ltd. Method for producing group III nitride compound semiconductor substrates using ZnO release layers
EP0924769A1 (en) * 1997-07-03 1999-06-23 Seiko Epson Corporation Method of transferring thin film devices, thin film device, thin film integrated circuit device, active matrix substrate, liquid crystal display, and electronic apparatus
US5943563A (en) * 1994-08-03 1999-08-24 Siemens Aktiengesellschaft Method for producing a three-dimensional circuit arrangement
US5966622A (en) * 1997-10-08 1999-10-12 Lucent Technologies Inc. Process for bonding crystalline substrates with different crystal lattices
US5993677A (en) * 1996-01-25 1999-11-30 Commissariat A L'energie Atomique Process for transferring a thin film from an initial substrate onto a final substrate
US6004865A (en) * 1993-09-06 1999-12-21 Hitachi, Ltd. Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator
US6027958A (en) * 1996-07-11 2000-02-22 Kopin Corporation Transferred flexible integrated circuit
EP1014452A1 (en) * 1998-02-25 2000-06-28 Seiko Epson Corporation Method of detaching thin-film device, method of transferring thin-film device, thin-film device, active matrix substrate, and liquid crystal display
US6100166A (en) * 1996-12-18 2000-08-08 Canon Kabushiki Kaisha Process for producing semiconductor article
US6114188A (en) * 1996-04-12 2000-09-05 Northeastern University Method of fabricating an integrated complex-transition metal oxide device
US6114256A (en) * 1995-08-18 2000-09-05 California Institute Of Technology Stable metallization for diamond and other materials
US6136667A (en) * 1997-10-08 2000-10-24 Lucent Technologies Inc. Method for bonding two crystalline substrates together
JP2000332270A (en) * 1999-05-21 2000-11-30 Canon Inc Method of manufacturing photoelectric conversion device and photoelectric conversion device manufactured by the method
US6190937B1 (en) * 1996-12-27 2001-02-20 Canon Kabushiki Kaisha Method of producing semiconductor member and method of producing solar cell
US6214733B1 (en) * 1999-11-17 2001-04-10 Elo Technologies, Inc. Process for lift off and handling of thin film materials
US6291314B1 (en) * 1998-06-23 2001-09-18 Silicon Genesis Corporation Controlled cleavage process and device for patterned films using a release layer
WO2001078132A2 (en) * 2000-04-05 2001-10-18 Hrl Laboratories, Llc. Method for transferring semiconductor device layers to different substrates
US6328796B1 (en) * 1999-02-01 2001-12-11 The United States Of America As Represented By The Secretary Of The Navy Single-crystal material on non-single-crystalline substrate
US6339010B2 (en) * 1997-09-16 2002-01-15 President Of Tokyo University Of Agriculture & Technology Semiconductor element forming process having a step of separating film structure from substrate
US6375738B1 (en) * 1999-03-26 2002-04-23 Canon Kabushiki Kaisha Process of producing semiconductor article
FR2816445A1 (en) * 2000-11-06 2002-05-10 Commissariat Energie Atomique METHOD FOR MANUFACTURING A STACKED STRUCTURE COMPRISING A THIN FILM ADHERING TO A TARGET SUBSTRATE
US6436614B1 (en) 2000-10-20 2002-08-20 Feng Zhou Method for the formation of a thin optical crystal layer overlying a low dielectric constant substrate
FR2823012A1 (en) * 2001-04-03 2002-10-04 Commissariat Energie Atomique METHOD FOR THE SELECTIVE TRANSFER OF AT LEAST ONE ELEMENT FROM AN INITIAL MEDIUM TO A FINAL MEDIUM
US6468824B2 (en) * 2001-03-22 2002-10-22 Uni Light Technology Inc. Method for forming a semiconductor device having a metallic substrate
US6498073B2 (en) * 2001-01-02 2002-12-24 Honeywell International Inc. Back illuminated imager with enhanced UV to near IR sensitivity
US20030047280A1 (en) * 2001-08-22 2003-03-13 Toru Takayama Peeling method and method of manufacturing semiconductor device
US6555451B1 (en) 2001-09-28 2003-04-29 The United States Of America As Represented By The Secretary Of The Navy Method for making shallow diffusion junctions in semiconductors using elemental doping
US6562648B1 (en) * 2000-08-23 2003-05-13 Xerox Corporation Structure and method for separation and transfer of semiconductor thin films onto dissimilar substrate materials
US6562127B1 (en) 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates
US6593212B1 (en) 2001-10-29 2003-07-15 The United States Of America As Represented By The Secretary Of The Navy Method for making electro-optical devices using a hydrogenion splitting technique
US6607969B1 (en) 2002-03-18 2003-08-19 The United States Of America As Represented By The Secretary Of The Navy Method for making pyroelectric, electro-optical and decoupling capacitors using thin film transfer and hydrogen ion splitting techniques
US20030170965A1 (en) * 2001-12-27 2003-09-11 Seiko Epson Corporation Semiconductor integrated circuit and method for manufacturing semiconductor integrated circuit
US20030170946A1 (en) * 2001-12-28 2003-09-11 Seiko Epson Corporation Semiconductor integrated circuit and method for manufacturing semiconductor integrated circuit
US6624050B2 (en) * 1998-10-21 2003-09-23 Sony Corporation Method of manufacturing semiconductor device
EP1363319A2 (en) * 2002-05-17 2003-11-19 Semiconductor Energy Laboratory Co., Ltd. Method of transferring a laminate and method of manufacturing a semiconductor device
US6656271B2 (en) * 1998-12-04 2003-12-02 Canon Kabushiki Kaisha Method of manufacturing semiconductor wafer method of using and utilizing the same
US6677249B2 (en) * 1998-01-27 2004-01-13 Robert Bosch Gmbh Method for manufacturing breakaway layers for detaching deposited layer systems
US20040007709A1 (en) * 2002-06-10 2004-01-15 Seiko Epson Corporation Semiconductor integrated circuit, signal transmitting device, electro-optical device, and electronic apparatus
EP1385200A2 (en) * 2002-07-24 2004-01-28 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Method for making thin film devices intended for solar cells or SOI applications
US20040016932A1 (en) * 2002-05-30 2004-01-29 Seiko Epson Corporation Semiconductor unit, semiconductor apparatus, and method for making the same, electrooptic apparatus, and electronic apparatus
US20040036074A1 (en) * 2002-06-18 2004-02-26 Seiko Epson Corporation Optical interconnection integrated circuit, method of manufacturing optical interconnection integrated circuit, electro-optical apparatus, and electronic apparatus
US20040036078A1 (en) * 2002-06-20 2004-02-26 Seiko Epson Corporation Semiconductor device, method of manufacturing the same, electro-optic device and electronic apparatus
US20040100677A1 (en) * 2000-12-07 2004-05-27 Reflectivity, Inc., A California Corporation Spatial light modulators with light blocking/absorbing areas
US6743697B2 (en) * 2000-06-30 2004-06-01 Intel Corporation Thin silicon circuits and method for making the same
US20040109629A1 (en) * 2002-10-01 2004-06-10 Seiko Epson Corporation Optical interconnection circuit, manufacturing method thereof, electro-optical device and electronic equipment
US6756289B1 (en) 1996-12-27 2004-06-29 Canon Kabushiki Kaisha Method of producing semiconductor member and method of producing solar cell
US20040126994A1 (en) * 2002-12-31 2004-07-01 Rafael Reif Method of forming a multi-layer semiconductor structure having a seamless bonding interface
US20040135158A1 (en) * 2003-01-03 2004-07-15 Supernova Optoelectronics Corp. Method for manufacturing of a vertical light emitting device structure
US20040136639A1 (en) * 2002-11-20 2004-07-15 Seiko Epson Corporation Optical interconnection circuit between chips, electrooptical device and electronic equipment
WO2004061953A2 (en) * 2002-12-31 2004-07-22 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure incorporating a processing handle member
US6767749B2 (en) 2002-04-22 2004-07-27 The United States Of America As Represented By The Secretary Of The Navy Method for making piezoelectric resonator and surface acoustic wave device using hydrogen implant layer splitting
US20040149810A1 (en) * 2003-02-04 2004-08-05 Kuang-Neng Yang Led stack manufacturing method and its structure thereof
US20040166649A1 (en) * 2003-01-24 2004-08-26 Soitec & Cea Layer transfer method
US6797604B2 (en) * 2000-05-08 2004-09-28 International Business Machines Corporation Method for manufacturing device substrate with metal back-gate and structure formed thereby
US20040206444A1 (en) * 2003-03-14 2004-10-21 Fabrice Letertre Methods for forming an assembly for transfer of a useful layer
US20040214434A1 (en) * 2001-04-17 2004-10-28 Atwater Harry A. Wafer bonded virtual substrate and method for forming the same
US20040218874A1 (en) * 2003-02-28 2004-11-04 Seiko Epson Corporation Fiber optic transceiver module, manufacturing method thereof, and electronic equipment
US20040239827A1 (en) * 2003-01-15 2004-12-02 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method for manufacturing display device using the peeling method
US20040253795A1 (en) * 2003-06-11 2004-12-16 Muriel Martinez Methods of producing a heterogeneous semiconductor structure
US20050020032A1 (en) * 2002-07-24 2005-01-27 Solanki Chetan Singh Method for making thin film devices intended for solar cells or silicon-on-insulator (SOI) applications
US20050026432A1 (en) * 2001-04-17 2005-02-03 Atwater Harry A. Wafer bonded epitaxial templates for silicon heterostructures
US20050048736A1 (en) * 2003-09-02 2005-03-03 Sebastien Kerdiles Methods for adhesive transfer of a layer
US20050104083A1 (en) * 2000-08-31 2005-05-19 Osram Opto Semiconductors Gmbh Method for fabricating a radiation-emitting semiconductor chip based on Ill-V nitride semiconductor
US20050227455A1 (en) * 2004-03-29 2005-10-13 Jongkook Park Method of separating layers of material
US20050282357A1 (en) * 2001-08-10 2005-12-22 Semiconductor Energy Laboratory Co., Ltd. Method of peeling off and method of manufacturing semiconductor device
US20060021565A1 (en) * 2004-07-30 2006-02-02 Aonex Technologies, Inc. GaInP / GaAs / Si triple junction solar cell enabled by wafer bonding and layer transfer
US7019339B2 (en) 2001-04-17 2006-03-28 California Institute Of Technology Method of using a germanium layer transfer to Si for photovoltaic applications and heterostructure made thereby
US20060112986A1 (en) * 2004-10-21 2006-06-01 Aonex Technologies, Inc. Multi-junction solar cells and methods of making same using layer transfer and bonding techniques
FR2880189A1 (en) * 2004-12-24 2006-06-30 Tracit Technologies Sa Semi-conductor structure manufacturing method, involves forming bonding layer on electrically conductive or grounding plane forming layer, where binding layer has specific thickness
US20060185582A1 (en) * 2005-02-18 2006-08-24 Atwater Harry A Jr High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
US20060255341A1 (en) * 2005-04-21 2006-11-16 Aonex Technologies, Inc. Bonded intermediate substrate and method of making same
US20060273319A1 (en) * 2005-06-03 2006-12-07 Semiconductor Energy Laboratory Co., Ltd. Integrated circuit device and manufacturing method thereof
SG127711A1 (en) * 2003-02-25 2006-12-29 Sony Corp Process for the fabrication of thin-film device and thin-film device
US20070015349A1 (en) * 2003-10-07 2007-01-18 Patrice Aublanc Method of producing a composite multilayer
US20070020884A1 (en) * 2005-07-25 2007-01-25 Qi Wang Semiconductor structures formed on substrates and methods of manufacturing the same
US20070087644A1 (en) * 2000-07-18 2007-04-19 Sony Corporation Method of producing image display unit
US20070117289A1 (en) * 2002-04-24 2007-05-24 Yoshikazu Akiyama thin film apparatus, a manufacturing method of the thin film apparatus, an active matrix substrate, a manufacturing method of the active matrix substrate, and an electro-optical apparatus having the active matrix substrate
US20070243703A1 (en) * 2006-04-14 2007-10-18 Aonex Technololgies, Inc. Processes and structures for epitaxial growth on laminate substrates
US20070269960A1 (en) * 2000-11-27 2007-11-22 S.O.I.Tec Silicon On Insulator Technologies Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US20080128751A1 (en) * 2002-06-07 2008-06-05 Amberwave Systems Corporation Methods for forming iii-v semiconductor device structures
US20080211061A1 (en) * 2004-04-21 2008-09-04 California Institute Of Technology Method For the Fabrication of GaAs/Si and Related Wafer Bonded Virtual Substrates
DE102007016995A1 (en) * 2007-04-11 2008-10-16 Beyer, André Method for transferring a nanolayer
US20090179259A1 (en) * 2007-09-27 2009-07-16 Qi Wang Semiconductor device with (110)-oriented silicon
US20090200550A1 (en) * 2008-02-08 2009-08-13 Roger Stanley Kerr Method for forming an electronic device on a flexible substrate supported by a detachable carrier
US20090199401A1 (en) * 2008-02-08 2009-08-13 Roger Stanley Kerr Method for forming cast flexible substrate and resultant substrate and electronic device
US20090239320A1 (en) * 2001-07-16 2009-09-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
WO2009138138A2 (en) * 2008-05-14 2009-11-19 Robert Bosch Gmbh Method for producing chips
US7656002B1 (en) * 2007-11-30 2010-02-02 Rf Micro Devices, Inc. Integrated bipolar transistor and field effect transistor
EP2151852A1 (en) * 2008-08-06 2010-02-10 S.O.I. TEC Silicon Relaxation and transfer of strained layers
US20100035418A1 (en) * 2008-08-06 2010-02-11 Bruce Faure Passivation of semiconductor structures having strained layers
US20100032805A1 (en) * 2008-08-06 2010-02-11 Fabrice Letertre Methods and structures for relaxation of strained layers
WO2010025218A2 (en) * 2008-08-28 2010-03-04 The Regents Of The University Of California Composite semiconductor substrates for thin-film device layer transfer
US20100059797A1 (en) * 2008-09-09 2010-03-11 Tat Ngai (110)-oriented p-channel trench mosfet having high-k gate dielectric
US20100066683A1 (en) * 2008-09-17 2010-03-18 Shih-Chang Chang Method for Transferring Thin Film to Substrate
US7732301B1 (en) 2007-04-20 2010-06-08 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US20100176490A1 (en) * 2008-09-24 2010-07-15 Fabrice Letertre Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same
US7820495B2 (en) 2005-06-30 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20110127640A1 (en) * 2008-08-25 2011-06-02 Bruce Faure Stiffening layers for the relaxation of strained layers
US20110217825A1 (en) * 2003-02-28 2011-09-08 S.O.I.Tec Silicon On Insulator Technologies Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
US8252664B2 (en) 2000-11-27 2012-08-28 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US8481408B2 (en) 2008-08-06 2013-07-09 Soitec Relaxation of strained layers
US20140014977A1 (en) * 2011-02-24 2014-01-16 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor device and method for producing an optoelectronic semiconductor device
US8637383B2 (en) 2010-12-23 2014-01-28 Soitec Strain relaxation using metal materials and related structures
US8836081B2 (en) 2008-10-30 2014-09-16 Soitec Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain
TWI462316B (en) * 2008-03-03 2014-11-21 Univ Nat Chunghsing Solar cell having a thermal conductive substrate and a method for manufacturing the same
US9214337B2 (en) 2013-03-06 2015-12-15 Rf Micro Devices, Inc. Patterned silicon-on-plastic (SOP) technology and methods of manufacturing the same
US20160126196A1 (en) 2014-11-03 2016-05-05 Rf Micro Devices, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
WO2016073460A1 (en) * 2014-11-04 2016-05-12 The Regents Of The University Of California Solid-state wafer bonding of functional materials on substrates and self-aligned contacts
EP1699091B1 (en) * 2005-03-02 2017-01-25 Oki Data Corporation Semiconductor composite LED apparatus
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US20170194194A1 (en) * 2015-12-31 2017-07-06 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US9824951B2 (en) 2014-09-12 2017-11-21 Qorvo Us, Inc. Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
US20170358511A1 (en) 2016-06-10 2017-12-14 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US20180019184A1 (en) 2016-07-18 2018-01-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US20180044177A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US9919515B2 (en) 2016-01-28 2018-03-20 Tracer Imaging Llc Product alignment using a printed relief
US9947568B2 (en) 2013-02-20 2018-04-17 Semiconductor Energy Laboratory Co., Ltd. Peeling method, semiconductor device, and peeling apparatus
US9960145B2 (en) 2015-03-25 2018-05-01 Qorvo Us, Inc. Flip chip module with enhanced properties
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
US10032943B2 (en) 2015-12-18 2018-07-24 International Business Machines Corporation Device layer thin-film transfer to thermally conductive substrate
US10038055B2 (en) 2015-05-22 2018-07-31 Qorvo Us, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US20180228030A1 (en) 2014-10-01 2018-08-09 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10062583B2 (en) 2016-05-09 2018-08-28 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US10109550B2 (en) 2016-08-12 2018-10-23 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US20190013255A1 (en) 2017-07-06 2019-01-10 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10189048B2 (en) 2013-12-12 2019-01-29 Semiconductor Energy Laboratory Co., Ltd. Peeling method and peeling apparatus
US20190074271A1 (en) 2017-09-05 2019-03-07 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US20190074263A1 (en) 2017-09-05 2019-03-07 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
CN110050335A (en) * 2016-11-08 2019-07-23 麻省理工学院 Dislocation filtration system and method for layer transfer
US10486963B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
WO2019226711A1 (en) * 2018-05-22 2019-11-28 Etx Corporation Method and apparatus for transfer of two-dimensional materials
CN110970340A (en) * 2019-10-31 2020-04-07 中国电子科技集团公司第五十五研究所 A kind of flexible InP HBT device and preparation method thereof
US20200235054A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US20210296199A1 (en) 2018-11-29 2021-09-23 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
CN113764968A (en) * 2021-09-07 2021-12-07 中国科学院半导体研究所 A kind of method of removing epitaxial wafer substrate
US20220108938A1 (en) 2019-01-23 2022-04-07 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US20220139862A1 (en) 2019-01-23 2022-05-05 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US12046535B2 (en) 2018-07-02 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12062701B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12062571B2 (en) 2021-03-05 2024-08-13 Qorvo Us, Inc. Selective etching process for SiGe and doped epitaxial silicon
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
DE112013000499B4 (en) 2012-01-05 2024-10-10 Commissariat à l'énergie atomique et aux énergies alternatives Backscattering device and light emitting device and manufacturing method thereof
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3959045A (en) * 1974-11-18 1976-05-25 Varian Associates Process for making III-V devices
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5073230A (en) * 1990-04-17 1991-12-17 Arizona Board Of Regents Acting On Behalf Of Arizona State University Means and methods of lifting and relocating an epitaxial device layer
US5261999A (en) * 1991-05-08 1993-11-16 North American Philips Corporation Process for making strain-compensated bonded silicon-on-insulator material free of dislocations

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3959045A (en) * 1974-11-18 1976-05-25 Varian Associates Process for making III-V devices
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5073230A (en) * 1990-04-17 1991-12-17 Arizona Board Of Regents Acting On Behalf Of Arizona State University Means and methods of lifting and relocating an epitaxial device layer
US5261999A (en) * 1991-05-08 1993-11-16 North American Philips Corporation Process for making strain-compensated bonded silicon-on-insulator material free of dislocations

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
C. Camperi Binestet et al., Alignable Epitaxial Liftoff of GaAs Materials with Selective Deposition Using Polyimide Diaphragms , IEEE Transactions Photonics Technology Letters , vol. 3, No. 12, pp. 1123 1126, Dec. 1991. *
C. Camperi-Binestet et al., "Alignable Epitaxial Liftoff of GaAs Materials with Selective Deposition Using Polyimide Diaphragms", IEEE Transactions Photonics Technology Letters, vol. 3, No. 12, pp. 1123-1126, Dec. 1991.
E. Yablonovitch et al., "Extreme selectivity in the lift-off of epitaxial GaAs films," Appl. Phys. Lett., vol. 51, No. 26, pp. 2222-2224, Dec. 28, 1987.
E. Yablonovitch et al., "Van der Waals bonding of GaAs on Pd leads to a permanent, solid-phase-topotaxial, metallurgical bond," Appl. Phys. Lett., vol. 59, No. 24, pp. 3159-3161, Dec. 9, 1991.
E. Yablonovitch et al., Extreme selectivity in the lift off of epitaxial GaAs films, Appl. Phys. Lett. , vol. 51, No. 26, pp. 2222 2224, Dec. 28, 1987. *
E. Yablonovitch et al., Van der Waals bonding of GaAs on Pd leads to a permanent, solid phase topotaxial, metallurgical bond, Appl. Phys. Lett. , vol. 59, No. 24, pp. 3159 3161, Dec. 9, 1991. *
J. Callahan et al., "Alignable Liftoff Transfer of Device Arrays via a Single Polymeric Carrier Membrane," Electronics Letters, vol. 29, No. 11, pp. 951-953, May 27, 1993.
J. Callahan et al., Alignable Liftoff Transfer of Device Arrays via a Single Polymeric Carrier Membrane, Electronics Letters , vol. 29, No. 11, pp. 951 953, May 27, 1993. *

Cited By (365)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6004865A (en) * 1993-09-06 1999-12-21 Hitachi, Ltd. Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator
US5846844A (en) * 1993-11-29 1998-12-08 Toyoda Gosei Co., Ltd. Method for producing group III nitride compound semiconductor substrates using ZnO release layers
US5476810A (en) * 1994-01-31 1995-12-19 U.S. Philips Corporation Manufacture of electronic devices comprising thin-film circuits using a metal foil as a temporary support
US5943563A (en) * 1994-08-03 1999-08-24 Siemens Aktiengesellschaft Method for producing a three-dimensional circuit arrangement
US5563084A (en) * 1994-09-22 1996-10-08 Fraunhofer-Gesellschaft zur F orderung der angewandten Forschung e.V. Method of making a three-dimensional integrated circuit
US6114256A (en) * 1995-08-18 2000-09-05 California Institute Of Technology Stable metallization for diamond and other materials
US5993677A (en) * 1996-01-25 1999-11-30 Commissariat A L'energie Atomique Process for transferring a thin film from an initial substrate onto a final substrate
WO1997039481A1 (en) * 1996-04-12 1997-10-23 Northeastern University An integrated complex-transition metal oxide device and a method of fabricating such a device
US6114188A (en) * 1996-04-12 2000-09-05 Northeastern University Method of fabricating an integrated complex-transition metal oxide device
US6027958A (en) * 1996-07-11 2000-02-22 Kopin Corporation Transferred flexible integrated circuit
US6534382B1 (en) 1996-12-18 2003-03-18 Canon Kabushiki Kaisha Process for producing semiconductor article
US6100166A (en) * 1996-12-18 2000-08-08 Canon Kabushiki Kaisha Process for producing semiconductor article
US6190937B1 (en) * 1996-12-27 2001-02-20 Canon Kabushiki Kaisha Method of producing semiconductor member and method of producing solar cell
US6756289B1 (en) 1996-12-27 2004-06-29 Canon Kabushiki Kaisha Method of producing semiconductor member and method of producing solar cell
EP0867918A3 (en) * 1997-03-27 1998-12-16 Canon Kabushiki Kaisha Process for producing semiconductor substrate
EP0867918A2 (en) * 1997-03-27 1998-09-30 Canon Kabushiki Kaisha Process for producing semiconductor substrate
US6258698B1 (en) 1997-03-27 2001-07-10 Canon Kabushiki Kaisha Process for producing semiconductor substrate
US6521511B1 (en) 1997-07-03 2003-02-18 Seiko Epson Corporation Thin film device transfer method, thin film device, thin film integrated circuit device, active matrix board, liquid crystal display, and electronic apparatus
EP0924769A1 (en) * 1997-07-03 1999-06-23 Seiko Epson Corporation Method of transferring thin film devices, thin film device, thin film integrated circuit device, active matrix substrate, liquid crystal display, and electronic apparatus
US6878607B2 (en) 1997-07-03 2005-04-12 Seiko Epson Corporation Thin film device transfer method, thin film device, thin film integrated circuit device, active matrix board, liquid crystal display, and electronic apparatus
KR100494479B1 (en) * 1997-07-03 2005-06-10 세이코 엡슨 가부시키가이샤 Method for manufacturing an active matrix substrate
EP0924769A4 (en) * 1997-07-03 2001-11-14 Seiko Epson Corp METHOD FOR TRANSFERING THIN-LAYER COMPONENTS, THIN-LAYER COMPONENT, THIN-LAYER INTEGRATED CIRCUIT COMPONENT, ACTIVE MATRIX SUBSTRATE, LIQUID CRYSTAL DISPLAY AND ELECTRONIC DEVICE
US6339010B2 (en) * 1997-09-16 2002-01-15 President Of Tokyo University Of Agriculture & Technology Semiconductor element forming process having a step of separating film structure from substrate
DE19842419B4 (en) * 1997-09-16 2005-03-03 President Of Tokyo University Of Agriculture & Technology Method for forming a semiconductor element
US6136667A (en) * 1997-10-08 2000-10-24 Lucent Technologies Inc. Method for bonding two crystalline substrates together
US5966622A (en) * 1997-10-08 1999-10-12 Lucent Technologies Inc. Process for bonding crystalline substrates with different crystal lattices
US6677249B2 (en) * 1998-01-27 2004-01-13 Robert Bosch Gmbh Method for manufacturing breakaway layers for detaching deposited layer systems
EP1014452A4 (en) * 1998-02-25 2001-11-14 Seiko Epson Corp METHOD TO SEPARATE A THIN-LAYER COMPONENT, METHOD TO TRANSFER A THIN-LAYER COMPONENT, THIN-LAYER COMPONENT, ACTIVE MATRIX SUBSTRATE, AND LIQUID CRYSTAL DISPLAY
US6885389B2 (en) 1998-02-25 2005-04-26 Seiko Epson Corporation Method of separating thin film device, method of transferring thin film device, thin film device, active matrix substrate and liquid crystal display device
US6700631B1 (en) 1998-02-25 2004-03-02 Seiko Epson Corporation Method of separating thin-film device, method of transferring thin-film device, thin-film device, active matrix substrate, and liquid crystal display device
US20030008437A1 (en) * 1998-02-25 2003-01-09 Seiko Epson Corporation Method of separating thin film device, method of transferring thin film device, thin film device, active matrix substrate and liquid crystal display device
EP1014452A1 (en) * 1998-02-25 2000-06-28 Seiko Epson Corporation Method of detaching thin-film device, method of transferring thin-film device, thin-film device, active matrix substrate, and liquid crystal display
US6291314B1 (en) * 1998-06-23 2001-09-18 Silicon Genesis Corporation Controlled cleavage process and device for patterned films using a release layer
US6624050B2 (en) * 1998-10-21 2003-09-23 Sony Corporation Method of manufacturing semiconductor device
US6656271B2 (en) * 1998-12-04 2003-12-02 Canon Kabushiki Kaisha Method of manufacturing semiconductor wafer method of using and utilizing the same
US6328796B1 (en) * 1999-02-01 2001-12-11 The United States Of America As Represented By The Secretary Of The Navy Single-crystal material on non-single-crystalline substrate
US6375738B1 (en) * 1999-03-26 2002-04-23 Canon Kabushiki Kaisha Process of producing semiconductor article
JP2000332270A (en) * 1999-05-21 2000-11-30 Canon Inc Method of manufacturing photoelectric conversion device and photoelectric conversion device manufactured by the method
US6214733B1 (en) * 1999-11-17 2001-04-10 Elo Technologies, Inc. Process for lift off and handling of thin film materials
US6589811B2 (en) 2000-04-05 2003-07-08 Hrl Laboratories, Llc Method for transferring semiconductor device layers to different substrates
WO2001078132A3 (en) * 2000-04-05 2002-02-14 Hrl Lab Llc Method for transferring semiconductor device layers to different substrates
WO2001078132A2 (en) * 2000-04-05 2001-10-18 Hrl Laboratories, Llc. Method for transferring semiconductor device layers to different substrates
US6797604B2 (en) * 2000-05-08 2004-09-28 International Business Machines Corporation Method for manufacturing device substrate with metal back-gate and structure formed thereby
US7145212B2 (en) 2000-05-08 2006-12-05 International Business Machines Corporation Method for manufacturing device substrate with metal back-gate and structure formed thereby
US20040188686A1 (en) * 2000-06-30 2004-09-30 Ravi Kramadhati V. Thin silicon circuits and method for making the same
US6743697B2 (en) * 2000-06-30 2004-06-01 Intel Corporation Thin silicon circuits and method for making the same
US8409886B2 (en) * 2000-07-18 2013-04-02 Sony Corporation Method of producing image display unit
US20070087644A1 (en) * 2000-07-18 2007-04-19 Sony Corporation Method of producing image display unit
US6562648B1 (en) * 2000-08-23 2003-05-13 Xerox Corporation Structure and method for separation and transfer of semiconductor thin films onto dissimilar substrate materials
US7105370B2 (en) * 2000-08-31 2006-09-12 Osram Gmbh Method for fabricating a radiation-emitting semiconductor chip based on III-V nitride semiconductor
US20050104083A1 (en) * 2000-08-31 2005-05-19 Osram Opto Semiconductors Gmbh Method for fabricating a radiation-emitting semiconductor chip based on Ill-V nitride semiconductor
US6436614B1 (en) 2000-10-20 2002-08-20 Feng Zhou Method for the formation of a thin optical crystal layer overlying a low dielectric constant substrate
US6974759B2 (en) * 2000-11-06 2005-12-13 Commissariat A L'energie Atomique Method for making a stacked comprising a thin film adhering to a target substrate
KR100855083B1 (en) * 2000-11-06 2008-08-29 꼼미사리아 아 레네르지 아토미끄 Method of manufacturing a laminated structure having a thin film bonded to a target substrate
FR2816445A1 (en) * 2000-11-06 2002-05-10 Commissariat Energie Atomique METHOD FOR MANUFACTURING A STACKED STRUCTURE COMPRISING A THIN FILM ADHERING TO A TARGET SUBSTRATE
US20040014299A1 (en) * 2000-11-06 2004-01-22 Hubert Moriceau Method for making a stacked structure comprising a thin film adhering to a target substrate
WO2002037556A1 (en) * 2000-11-06 2002-05-10 Commissariat A L'energie Atomique Method for making a stacked structure comprising a thin film adhering to a target substrate
US8679946B2 (en) 2000-11-06 2014-03-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate
US8481409B2 (en) 2000-11-06 2013-07-09 Commissariat A L'energie Atomique Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate
CN1327505C (en) * 2000-11-06 2007-07-18 法国原子能委员会 Method for making stacked structure comprising thin film adhering to target substrate
US20060079071A1 (en) * 2000-11-06 2006-04-13 Hubert Moriceau Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate
JP2004513517A (en) * 2000-11-06 2004-04-30 コミツサリア　タ　レネルジー　アトミーク Method of making a laminated structure with at least one thin layer bonded to a target substrate
US7888235B2 (en) * 2000-11-27 2011-02-15 S.O.I.Tec Silicon On Insulator Technologies Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US8252664B2 (en) 2000-11-27 2012-08-28 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US20070269960A1 (en) * 2000-11-27 2007-11-22 S.O.I.Tec Silicon On Insulator Technologies Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US8507361B2 (en) 2000-11-27 2013-08-13 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US10002763B2 (en) 2000-11-27 2018-06-19 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US20040100677A1 (en) * 2000-12-07 2004-05-27 Reflectivity, Inc., A California Corporation Spatial light modulators with light blocking/absorbing areas
US6498073B2 (en) * 2001-01-02 2002-12-24 Honeywell International Inc. Back illuminated imager with enhanced UV to near IR sensitivity
US6468824B2 (en) * 2001-03-22 2002-10-22 Uni Light Technology Inc. Method for forming a semiconductor device having a metallic substrate
FR2823012A1 (en) * 2001-04-03 2002-10-04 Commissariat Energie Atomique METHOD FOR THE SELECTIVE TRANSFER OF AT LEAST ONE ELEMENT FROM AN INITIAL MEDIUM TO A FINAL MEDIUM
US20040104272A1 (en) * 2001-04-03 2004-06-03 Christophe Figuet Method for selectively transferring at least an element from an initial support onto a final support
WO2002082502A2 (en) * 2001-04-03 2002-10-17 Commissariat A L'energie Atomique Method for selectively transferring at least an element from an initial support onto a final support
US6959863B2 (en) 2001-04-03 2005-11-01 Commissariat A L'engergie Atomique Method for selectively transferring at least an element from an initial support onto a final support
CN1322575C (en) * 2001-04-03 2007-06-20 法国原子能委员会 Method for selectively transferring at least an element for initial support onto a final support
WO2002082502A3 (en) * 2001-04-03 2003-11-06 Commissariat Energie Atomique Method for selectively transferring at least an element from an initial support onto a final support
US7238622B2 (en) 2001-04-17 2007-07-03 California Institute Of Technology Wafer bonded virtual substrate and method for forming the same
US7019339B2 (en) 2001-04-17 2006-03-28 California Institute Of Technology Method of using a germanium layer transfer to Si for photovoltaic applications and heterostructure made thereby
US20040214434A1 (en) * 2001-04-17 2004-10-28 Atwater Harry A. Wafer bonded virtual substrate and method for forming the same
US20050142879A1 (en) * 2001-04-17 2005-06-30 California Institute Of Technology Wafer bonded epitaxial templates for silicon heterostructures
US7141834B2 (en) 2001-04-17 2006-11-28 California Institute Of Technology Method of using a germanium layer transfer to Si for photovoltaic applications and heterostructure made thereby
US20050085049A1 (en) * 2001-04-17 2005-04-21 California Institute Of Technology Wafer bonded virtual substrate and method for forming the same
US7341927B2 (en) 2001-04-17 2008-03-11 California Institute Of Technology Wafer bonded epitaxial templates for silicon heterostructures
US20050026432A1 (en) * 2001-04-17 2005-02-03 Atwater Harry A. Wafer bonded epitaxial templates for silicon heterostructures
US8367440B2 (en) 2001-07-16 2013-02-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US20090239320A1 (en) * 2001-07-16 2009-09-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US9608004B2 (en) 2001-07-16 2017-03-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US10586816B2 (en) 2001-07-16 2020-03-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US8415208B2 (en) 2001-07-16 2013-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US9202987B2 (en) 2001-07-16 2015-12-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US7361573B2 (en) 2001-08-10 2008-04-22 Semiconductor Energy Laboratory Co., Ltd. Method of peeling off and method of manufacturing semiconductor device
US20050282357A1 (en) * 2001-08-10 2005-12-22 Semiconductor Energy Laboratory Co., Ltd. Method of peeling off and method of manufacturing semiconductor device
US10529748B2 (en) 2001-08-22 2020-01-07 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method of manufacturing semiconductor device
US9755148B2 (en) 2001-08-22 2017-09-05 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method of manufacturing semiconductor device
US9842994B2 (en) 2001-08-22 2017-12-12 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method of manufacturing semiconductor device
US8674364B2 (en) 2001-08-22 2014-03-18 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method of manufacturing semiconductor device
US8338198B2 (en) 2001-08-22 2012-12-25 Semiconductor Energy Laboratory Co., Ltd. Method of peeling thin film device and method of manufacturing semiconductor device using peeled thin film device
US7825002B2 (en) 2001-08-22 2010-11-02 Semiconductor Energy Laboratory Co., Ltd. Method of peeling thin film device and method of manufacturing semiconductor device using peeled thin film device
US9281403B2 (en) 2001-08-22 2016-03-08 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method of manufacturing semiconductor device
US20090042356A1 (en) * 2001-08-22 2009-02-12 Semiconductor Energy Laboratory Co., Ltd. Peeling Method and Method of Manufacturing Semiconductor Device
US11296131B2 (en) 2001-08-22 2022-04-05 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method of manufacturing semiconductor device
US20030047280A1 (en) * 2001-08-22 2003-03-13 Toru Takayama Peeling method and method of manufacturing semiconductor device
US7351300B2 (en) 2001-08-22 2008-04-01 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method of manufacturing semiconductor device
US6555451B1 (en) 2001-09-28 2003-04-29 The United States Of America As Represented By The Secretary Of The Navy Method for making shallow diffusion junctions in semiconductors using elemental doping
US6593212B1 (en) 2001-10-29 2003-07-15 The United States Of America As Represented By The Secretary Of The Navy Method for making electro-optical devices using a hydrogenion splitting technique
US20030170965A1 (en) * 2001-12-27 2003-09-11 Seiko Epson Corporation Semiconductor integrated circuit and method for manufacturing semiconductor integrated circuit
US7244662B2 (en) 2001-12-27 2007-07-17 Seiko Epson Corporation Method for manufacturing semiconductor integrated circuit
US6858518B2 (en) 2001-12-28 2005-02-22 Seiko Epson Corporation Method for manufacturing semiconductor integrated circuit
US20030170946A1 (en) * 2001-12-28 2003-09-11 Seiko Epson Corporation Semiconductor integrated circuit and method for manufacturing semiconductor integrated circuit
US6562127B1 (en) 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates
US6607969B1 (en) 2002-03-18 2003-08-19 The United States Of America As Represented By The Secretary Of The Navy Method for making pyroelectric, electro-optical and decoupling capacitors using thin film transfer and hydrogen ion splitting techniques
US6767749B2 (en) 2002-04-22 2004-07-27 The United States Of America As Represented By The Secretary Of The Navy Method for making piezoelectric resonator and surface acoustic wave device using hydrogen implant layer splitting
US7422964B2 (en) * 2002-04-24 2008-09-09 Ricoh Company, Ltd. Manufacturing method of the active matrix substrate, and an electro-optical apparatus having the active matrix substrate
US20070117289A1 (en) * 2002-04-24 2007-05-24 Yoshikazu Akiyama thin film apparatus, a manufacturing method of the thin film apparatus, an active matrix substrate, a manufacturing method of the active matrix substrate, and an electro-optical apparatus having the active matrix substrate
US20070243352A1 (en) * 2002-05-17 2007-10-18 Semiconductor Energy Laboratory Co., Ltd. Method of transferring a laminate and method of manufacturing a semiconductor device
EP1363319A2 (en) * 2002-05-17 2003-11-19 Semiconductor Energy Laboratory Co., Ltd. Method of transferring a laminate and method of manufacturing a semiconductor device
US7147740B2 (en) 2002-05-17 2006-12-12 Semiconductor Energy Laboratory Co., Ltd. Method of transferring a laminate and method of manufacturing a semiconductor device
US20030217805A1 (en) * 2002-05-17 2003-11-27 Semiconductor Energy Laboratory Co. , Ltd. Method of transferring a laminate and method of manufacturig a semiconductor device
EP1363319A3 (en) * 2002-05-17 2005-01-26 Semiconductor Energy Laboratory Co., Ltd. Method of transferring a laminate and method of manufacturing a semiconductor device
US8945331B2 (en) 2002-05-17 2015-02-03 Semiconductor Energy Laboratory Co., Ltd. Method of transferring a laminate and method of manufacturing a semiconductor device
US20040016932A1 (en) * 2002-05-30 2004-01-29 Seiko Epson Corporation Semiconductor unit, semiconductor apparatus, and method for making the same, electrooptic apparatus, and electronic apparatus
US7180924B2 (en) 2002-05-30 2007-02-20 Seiko Epson Corporation Semiconductor apparatus and a semiconductor unit, the semiconductor unit including a functional layer including a semiconductor element, and a highly conductive layer
US7838392B2 (en) 2002-06-07 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming III-V semiconductor device structures
US20080128751A1 (en) * 2002-06-07 2008-06-05 Amberwave Systems Corporation Methods for forming iii-v semiconductor device structures
US20040007709A1 (en) * 2002-06-10 2004-01-15 Seiko Epson Corporation Semiconductor integrated circuit, signal transmitting device, electro-optical device, and electronic apparatus
US7368754B2 (en) 2002-06-10 2008-05-06 Seiko Epson Corporation Semiconductor integrated circuit, signal transmitting device, electro-optical device, and electronic apparatus
US6858872B2 (en) 2002-06-18 2005-02-22 Seiko Epson Corporation Optical interconnection integrated circuit, method of manufacturing optical interconnection integrated circuit, electro-optical apparatus, and electronic apparatus
US20040036074A1 (en) * 2002-06-18 2004-02-26 Seiko Epson Corporation Optical interconnection integrated circuit, method of manufacturing optical interconnection integrated circuit, electro-optical apparatus, and electronic apparatus
US7709283B2 (en) 2002-06-20 2010-05-04 Seiko Epson Corporation Method of manufacturing a semiconductor device having an insulating protective film covering at least a portion of a tile-shaped element
US20080277671A1 (en) * 2002-06-20 2008-11-13 Seiko Epson Corporation Semiconductor device, method of manufacturing the same, electro-optic device and electronic apparatus
US7435998B2 (en) 2002-06-20 2008-10-14 Seiko Epson Corporation Semiconductor device, method of manufacturing the same, electro-optic device and electronic apparatus with a protective film
US20040036078A1 (en) * 2002-06-20 2004-02-26 Seiko Epson Corporation Semiconductor device, method of manufacturing the same, electro-optic device and electronic apparatus
US20060184266A1 (en) * 2002-07-24 2006-08-17 Solanki Chetan S Method for making thin film devices intended for solar cells or silicon-on-insulator (SOI) applications
EP1385200A3 (en) * 2002-07-24 2005-03-09 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Method for making thin film devices intended for solar cells or SOI applications
US20050020032A1 (en) * 2002-07-24 2005-01-27 Solanki Chetan Singh Method for making thin film devices intended for solar cells or silicon-on-insulator (SOI) applications
EP1385200A2 (en) * 2002-07-24 2004-01-28 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Method for making thin film devices intended for solar cells or SOI applications
US7022585B2 (en) 2002-07-24 2006-04-04 Interuniversitair Microelektronica Centrum (Imec) Method for making thin film devices intended for solar cells or silicon-on-insulator (SOI) applications
US20040109629A1 (en) * 2002-10-01 2004-06-10 Seiko Epson Corporation Optical interconnection circuit, manufacturing method thereof, electro-optical device and electronic equipment
US7228018B2 (en) 2002-10-01 2007-06-05 Seiko Epson Corporation Optical interconnection circuit, manufacturing method thereof, electro-optical device and electronic equipment
US7092588B2 (en) 2002-11-20 2006-08-15 Seiko Epson Corporation Optical interconnection circuit between chips, electrooptical device and electronic equipment
US20040136639A1 (en) * 2002-11-20 2004-07-15 Seiko Epson Corporation Optical interconnection circuit between chips, electrooptical device and electronic equipment
US7067909B2 (en) 2002-12-31 2006-06-27 Massachusetts Institute Of Technology Multi-layer integrated semiconductor structure having an electrical shielding portion
WO2004061953A3 (en) * 2002-12-31 2005-06-23 Massachusetts Inst Technology Method of forming a multi-layer semiconductor structure incorporating a processing handle member
US20040219765A1 (en) * 2002-12-31 2004-11-04 Rafael Reif Method of forming a multi-layer semiconductor structure incorporating a processing handle member
WO2004061953A2 (en) * 2002-12-31 2004-07-22 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure incorporating a processing handle member
US20040126994A1 (en) * 2002-12-31 2004-07-01 Rafael Reif Method of forming a multi-layer semiconductor structure having a seamless bonding interface
US20060087019A1 (en) * 2002-12-31 2006-04-27 Rafael Reif Multi-layer integrated semiconductor structure having an electrical shielding portion
US20060099796A1 (en) * 2002-12-31 2006-05-11 Rafael Reif Method of forming a multi-layer semiconductor structure having a seam-less bonding interface
US7307003B2 (en) 2002-12-31 2007-12-11 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure incorporating a processing handle member
US7064055B2 (en) 2002-12-31 2006-06-20 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure having a seamless bonding interface
US6933160B2 (en) * 2003-01-03 2005-08-23 Supernova Optoelectronics Corp. Method for manufacturing of a vertical light emitting device structure
US20040135158A1 (en) * 2003-01-03 2004-07-15 Supernova Optoelectronics Corp. Method for manufacturing of a vertical light emitting device structure
US7714950B2 (en) 2003-01-15 2010-05-11 Semiconductor Energy Laboratory Co., Ltd Peeling method and method for manufacturing display device using the peeling method
US20070211189A1 (en) * 2003-01-15 2007-09-13 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method for manufacturing display device using the peeling method
US9299879B2 (en) 2003-01-15 2016-03-29 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method for manufacturing display device using the peeling method
US8228454B2 (en) 2003-01-15 2012-07-24 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method for manufacturing display device using the peeling method
US20040239827A1 (en) * 2003-01-15 2004-12-02 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method for manufacturing display device using the peeling method
US7245331B2 (en) 2003-01-15 2007-07-17 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method for manufacturing display device using the peeling method
US8508682B2 (en) 2003-01-15 2013-08-13 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method for manufacturing display device using the peeling method
US9013650B2 (en) 2003-01-15 2015-04-21 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method for manufacturing display device using the peeling method
US8830413B2 (en) 2003-01-15 2014-09-09 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method for manufacturing display device using the peeling method
US7060590B2 (en) 2003-01-24 2006-06-13 S.O.I. Tec Silicon On Insulator Technologies S.A. Layer transfer method
US20040166649A1 (en) * 2003-01-24 2004-08-26 Soitec & Cea Layer transfer method
US6786390B2 (en) * 2003-02-04 2004-09-07 United Epitaxy Company Ltd. LED stack manufacturing method and its structure thereof
US20040149810A1 (en) * 2003-02-04 2004-08-05 Kuang-Neng Yang Led stack manufacturing method and its structure thereof
US7172708B2 (en) 2003-02-25 2007-02-06 Sony Corporation Process for the fabrication of thin-film device and thin-film device
SG127711A1 (en) * 2003-02-25 2006-12-29 Sony Corp Process for the fabrication of thin-film device and thin-film device
US20110217825A1 (en) * 2003-02-28 2011-09-08 S.O.I.Tec Silicon On Insulator Technologies Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
US20070041685A1 (en) * 2003-02-28 2007-02-22 Seiko Epson Corporation Fiber optic transceiver module, manufacturing method thereof, and electronic equipment
US20040218874A1 (en) * 2003-02-28 2004-11-04 Seiko Epson Corporation Fiber optic transceiver module, manufacturing method thereof, and electronic equipment
US8173512B2 (en) 2003-02-28 2012-05-08 Soitec Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
US20080258265A1 (en) * 2003-03-14 2008-10-23 S.O.I.Tec Silicon On Insulator Technologies Methods for forming an assembly for transfer of a useful layer
US7404870B2 (en) 2003-03-14 2008-07-29 S.O.I.Tec Silicon On Insulator Technologies Methods for forming an assembly for transfer of a useful layer
US20060231203A1 (en) * 2003-03-14 2006-10-19 S.O.I.Tec Silicon on Insulator Technologies S.A., a French company Methods for forming an assembly for transfer of a useful layer
US8093687B2 (en) 2003-03-14 2012-01-10 S.O.I.Tec Silicon On Insulator Technologies Methods for forming an assembly for transfer of a useful layer using a peripheral recess area to facilitate transfer
US20040206444A1 (en) * 2003-03-14 2004-10-21 Fabrice Letertre Methods for forming an assembly for transfer of a useful layer
US7122095B2 (en) 2003-03-14 2006-10-17 S.O.I.Tec Silicon On Insulator Technologies S.A. Methods for forming an assembly for transfer of a useful layer
US20040253795A1 (en) * 2003-06-11 2004-12-16 Muriel Martinez Methods of producing a heterogeneous semiconductor structure
US6858517B2 (en) * 2003-06-11 2005-02-22 S.O.I. Tec Silicon On Insulator Technologies S.A. Methods of producing a heterogeneous semiconductor structure
US20050048736A1 (en) * 2003-09-02 2005-03-03 Sebastien Kerdiles Methods for adhesive transfer of a layer
US20070015349A1 (en) * 2003-10-07 2007-01-18 Patrice Aublanc Method of producing a composite multilayer
US20050227455A1 (en) * 2004-03-29 2005-10-13 Jongkook Park Method of separating layers of material
US20060003553A1 (en) * 2004-03-29 2006-01-05 Jongkook Park Method of separating layers of material
US7202141B2 (en) 2004-03-29 2007-04-10 J.P. Sercel Associates, Inc. Method of separating layers of material
US7241667B2 (en) 2004-03-29 2007-07-10 J.P. Sercel Associates, Inc. Method of separating layers of material
US20080211061A1 (en) * 2004-04-21 2008-09-04 California Institute Of Technology Method For the Fabrication of GaAs/Si and Related Wafer Bonded Virtual Substrates
US20060021565A1 (en) * 2004-07-30 2006-02-02 Aonex Technologies, Inc. GaInP / GaAs / Si triple junction solar cell enabled by wafer bonding and layer transfer
US7846759B2 (en) 2004-10-21 2010-12-07 Aonex Technologies, Inc. Multi-junction solar cells and methods of making same using layer transfer and bonding techniques
US20060112986A1 (en) * 2004-10-21 2006-06-01 Aonex Technologies, Inc. Multi-junction solar cells and methods of making same using layer transfer and bonding techniques
US20080128868A1 (en) * 2004-12-24 2008-06-05 Tracit Technologies Method of Transferring a Circuit Onto a Ground Plane
FR2880189A1 (en) * 2004-12-24 2006-06-30 Tracit Technologies Sa Semi-conductor structure manufacturing method, involves forming bonding layer on electrically conductive or grounding plane forming layer, where binding layer has specific thickness
US8298915B2 (en) 2004-12-24 2012-10-30 S.O.I. Tec Silicon On Insulator Technologies Method of transferring a circuit onto a ground plane
WO2006070167A1 (en) * 2004-12-24 2006-07-06 Tracit Technologies Method for transferring a circuit to a grounding plane
US20060185582A1 (en) * 2005-02-18 2006-08-24 Atwater Harry A Jr High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
US10374120B2 (en) 2005-02-18 2019-08-06 Koninklijke Philips N.V. High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
EP1699091B1 (en) * 2005-03-02 2017-01-25 Oki Data Corporation Semiconductor composite LED apparatus
US8101498B2 (en) 2005-04-21 2012-01-24 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US20060255341A1 (en) * 2005-04-21 2006-11-16 Aonex Technologies, Inc. Bonded intermediate substrate and method of making same
US20060273319A1 (en) * 2005-06-03 2006-12-07 Semiconductor Energy Laboratory Co., Ltd. Integrated circuit device and manufacturing method thereof
US8492246B2 (en) 2005-06-03 2013-07-23 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing integrated circuit device
US7972910B2 (en) 2005-06-03 2011-07-05 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of integrated circuit device including thin film transistor
US8361845B2 (en) 2005-06-30 2013-01-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20110033987A1 (en) * 2005-06-30 2011-02-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7820495B2 (en) 2005-06-30 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
WO2007015951A3 (en) * 2005-07-25 2007-08-16 Fairchild Semiconductor Semiconductor structures formed on substrates and methods of manufacturing the same
US20100052046A1 (en) * 2005-07-25 2010-03-04 Fairchild Semiconductor Corporation Semiconductor structures formed on substrates and methods of manufacturing the same
WO2007015951A2 (en) * 2005-07-25 2007-02-08 Fairchild Semiconductor Corporation Semiconductor structures formed on substrates and methods of manufacturing the same
US20070020884A1 (en) * 2005-07-25 2007-01-25 Qi Wang Semiconductor structures formed on substrates and methods of manufacturing the same
US7635637B2 (en) * 2005-07-25 2009-12-22 Fairchild Semiconductor Corporation Semiconductor structures formed on substrates and methods of manufacturing the same
US20070243703A1 (en) * 2006-04-14 2007-10-18 Aonex Technololgies, Inc. Processes and structures for epitaxial growth on laminate substrates
DE102007016995A1 (en) * 2007-04-11 2008-10-16 Beyer, André Method for transferring a nanolayer
US7732301B1 (en) 2007-04-20 2010-06-08 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US8101500B2 (en) 2007-09-27 2012-01-24 Fairchild Semiconductor Corporation Semiconductor device with (110)-oriented silicon
US20090179259A1 (en) * 2007-09-27 2009-07-16 Qi Wang Semiconductor device with (110)-oriented silicon
US8338886B2 (en) 2007-09-27 2012-12-25 Fairchild Semiconductor Corporation Semiconductor device with (110)-oriented silicon
US7656002B1 (en) * 2007-11-30 2010-02-02 Rf Micro Devices, Inc. Integrated bipolar transistor and field effect transistor
US20090200550A1 (en) * 2008-02-08 2009-08-13 Roger Stanley Kerr Method for forming an electronic device on a flexible substrate supported by a detachable carrier
US9627420B2 (en) * 2008-02-08 2017-04-18 Carestream Health, Inc. Method for forming an electronic device on a flexible substrate supported by a detachable carrier
US7743492B2 (en) * 2008-02-08 2010-06-29 Carestream Health, Inc. Method for forming cast flexible substrate and resultant substrate and electronic device
US20090199401A1 (en) * 2008-02-08 2009-08-13 Roger Stanley Kerr Method for forming cast flexible substrate and resultant substrate and electronic device
TWI462316B (en) * 2008-03-03 2014-11-21 Univ Nat Chunghsing Solar cell having a thermal conductive substrate and a method for manufacturing the same
CN102026909B (en) * 2008-05-14 2013-11-20 罗伯特·博世有限公司 Method for producing chips
US20110151620A1 (en) * 2008-05-14 2011-06-23 Torsten Kramer Method for manufacturing chips
WO2009138138A3 (en) * 2008-05-14 2010-05-27 Robert Bosch Gmbh Method for producing chips
US8389327B2 (en) 2008-05-14 2013-03-05 Robert Bosch Gmbh Method for manufacturing chips
WO2009138138A2 (en) * 2008-05-14 2009-11-19 Robert Bosch Gmbh Method for producing chips
US20100032793A1 (en) * 2008-08-06 2010-02-11 Pascal Guenard Methods for relaxation and transfer of strained layers and structures fabricated thereby
TWI456660B (en) * 2008-08-06 2014-10-11 Soitec Silicon On Insulator Strain relaxation and transfer
US8048693B2 (en) 2008-08-06 2011-11-01 S.O.I. Tec Silicon On Insulator Technologies Methods and structures for relaxation of strained layers
US20100032805A1 (en) * 2008-08-06 2010-02-11 Fabrice Letertre Methods and structures for relaxation of strained layers
WO2010015302A3 (en) * 2008-08-06 2010-05-14 S.O.I. Tec Silicon On Insulator Technologies Relaxation and transfer of strained layers
EP2151852A1 (en) * 2008-08-06 2010-02-10 S.O.I. TEC Silicon Relaxation and transfer of strained layers
WO2010015302A2 (en) * 2008-08-06 2010-02-11 S.O.I. Tec Silicon On Insulator Technologies Relaxation and transfer of strained layers
US8492244B2 (en) 2008-08-06 2013-07-23 Soitec Methods for relaxation and transfer of strained layers and structures fabricated thereby
US7981767B2 (en) 2008-08-06 2011-07-19 S.O.I.Tec Silicon On Insulator Technologies Methods for relaxation and transfer of strained layers and structures fabricated thereby
CN102113090B (en) * 2008-08-06 2013-12-18 硅绝缘体技术有限公司 Relaxation and transfer of strained layers
US20100035418A1 (en) * 2008-08-06 2010-02-11 Bruce Faure Passivation of semiconductor structures having strained layers
US8481408B2 (en) 2008-08-06 2013-07-09 Soitec Relaxation of strained layers
US7736935B2 (en) 2008-08-06 2010-06-15 S.O.I.Tec Silicon On Insulator Technologies Passivation of semiconductor structures having strained layers
US8912081B2 (en) 2008-08-25 2014-12-16 Soitec Stiffening layers for the relaxation of strained layers
US20110127640A1 (en) * 2008-08-25 2011-06-02 Bruce Faure Stiffening layers for the relaxation of strained layers
WO2010025218A3 (en) * 2008-08-28 2010-05-06 The Regents Of The University Of California Composite semiconductor substrates for thin-film device layer transfer
US8624357B2 (en) 2008-08-28 2014-01-07 The Regents Of The University Of California Composite semiconductor substrates for thin-film device layer transfer
WO2010025218A2 (en) * 2008-08-28 2010-03-04 The Regents Of The University Of California Composite semiconductor substrates for thin-film device layer transfer
US20110221040A1 (en) * 2008-08-28 2011-09-15 The Regents Of The University Of California Composite Semiconductor Substrates for Thin-Film Device Layer Transfer
US20100059797A1 (en) * 2008-09-09 2010-03-11 Tat Ngai (110)-oriented p-channel trench mosfet having high-k gate dielectric
US8039877B2 (en) 2008-09-09 2011-10-18 Fairchild Semiconductor Corporation (110)-oriented p-channel trench MOSFET having high-K gate dielectric
US20100066683A1 (en) * 2008-09-17 2010-03-18 Shih-Chang Chang Method for Transferring Thin Film to Substrate
US20100176490A1 (en) * 2008-09-24 2010-07-15 Fabrice Letertre Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same
US8486771B2 (en) 2008-09-24 2013-07-16 Soitec Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same
US9368344B2 (en) 2008-10-30 2016-06-14 Soitec Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain
US8836081B2 (en) 2008-10-30 2014-09-16 Soitec Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain
US8637383B2 (en) 2010-12-23 2014-01-28 Soitec Strain relaxation using metal materials and related structures
US9312339B2 (en) 2010-12-23 2016-04-12 Soitec Strain relaxation using metal materials and related structures
US9076897B2 (en) * 2011-02-24 2015-07-07 Osram Opto Semiconductor Gmbh Optoelectronic semiconductor device and method for producing an optoelectronic semiconductor device
US20140014977A1 (en) * 2011-02-24 2014-01-16 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor device and method for producing an optoelectronic semiconductor device
DE112013000499B4 (en) 2012-01-05 2024-10-10 Commissariat à l'énergie atomique et aux énergies alternatives Backscattering device and light emitting device and manufacturing method thereof
US9947568B2 (en) 2013-02-20 2018-04-17 Semiconductor Energy Laboratory Co., Ltd. Peeling method, semiconductor device, and peeling apparatus
US11355382B2 (en) 2013-02-20 2022-06-07 Semiconductor Energy Laboratory Co., Ltd. Peeling method, semiconductor device, and peeling apparatus
US10636692B2 (en) 2013-02-20 2020-04-28 Semiconductor Energy Laboratory Co., Ltd. Peeling method, semiconductor device, and peeling apparatus
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US10134627B2 (en) 2013-03-06 2018-11-20 Qorvo Us, Inc. Silicon-on-plastic semiconductor device with interfacial adhesion layer
US9214337B2 (en) 2013-03-06 2015-12-15 Rf Micro Devices, Inc. Patterned silicon-on-plastic (SOP) technology and methods of manufacturing the same
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US10062637B2 (en) 2013-10-31 2018-08-28 Qorvo Us, Inc. Method of manufacture for a semiconductor device
US10189048B2 (en) 2013-12-12 2019-01-29 Semiconductor Energy Laboratory Co., Ltd. Peeling method and peeling apparatus
US9824951B2 (en) 2014-09-12 2017-11-21 Qorvo Us, Inc. Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
US20180228030A1 (en) 2014-10-01 2018-08-09 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10492301B2 (en) 2014-10-01 2019-11-26 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10121718B2 (en) 2014-11-03 2018-11-06 Qorvo Us, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US10199301B2 (en) 2014-11-03 2019-02-05 Qorvo Us, Inc. Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US20160126196A1 (en) 2014-11-03 2016-05-05 Rf Micro Devices, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US10109548B2 (en) 2014-11-03 2018-10-23 Qorvo Us, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
WO2016073460A1 (en) * 2014-11-04 2016-05-12 The Regents Of The University Of California Solid-state wafer bonding of functional materials on substrates and self-aligned contacts
US10679964B2 (en) 2014-11-04 2020-06-09 The Regents Of The University Of California Solid-state wafer bonding of functional materials on substrates and self-aligned contacts
US9960145B2 (en) 2015-03-25 2018-05-01 Qorvo Us, Inc. Flip chip module with enhanced properties
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US10020206B2 (en) 2015-03-25 2018-07-10 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US10038055B2 (en) 2015-05-22 2018-07-31 Qorvo Us, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US10396220B2 (en) 2015-12-18 2019-08-27 International Business Machines Corporation Device layer thin-film transfer to thermally conductive substrate
US10243091B2 (en) 2015-12-18 2019-03-26 International Business Machines Corporation Device layer thin-film transfer to thermally conductive substrate
US10032943B2 (en) 2015-12-18 2018-07-24 International Business Machines Corporation Device layer thin-film transfer to thermally conductive substrate
US10867834B2 (en) * 2015-12-31 2020-12-15 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN107017197A (en) * 2015-12-31 2017-08-04 台湾积体电路制造股份有限公司 Semiconductor structure and method of manufacturing the same
US10930547B2 (en) 2015-12-31 2021-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
DE102016117028B4 (en) 2015-12-31 2022-03-03 Taiwan Semiconductor Manufacturing Co. Ltd. Semiconductor structure and manufacturing method therefor
US20170194194A1 (en) * 2015-12-31 2017-07-06 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN107017197B (en) * 2015-12-31 2020-08-07 台湾积体电路制造股份有限公司 Semiconductor structure and method of making the same
US12191191B2 (en) 2015-12-31 2025-01-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
US10245825B2 (en) 2016-01-28 2019-04-02 Tracer Imaging Llc Product alignment using a printed relief
US10889107B2 (en) 2016-01-28 2021-01-12 Tracer Imaging Llc Product alignment using a printed relief
US9919515B2 (en) 2016-01-28 2018-03-20 Tracer Imaging Llc Product alignment using a printed relief
US10062583B2 (en) 2016-05-09 2018-08-28 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10090262B2 (en) 2016-05-09 2018-10-02 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10882740B2 (en) 2016-05-20 2021-01-05 Qorvo Us, Inc. Wafer-level package with enhanced performance and manufacturing method thereof
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US20180197803A1 (en) 2016-06-10 2018-07-12 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US10262915B2 (en) 2016-06-10 2019-04-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US20170358511A1 (en) 2016-06-10 2017-12-14 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US10468329B2 (en) 2016-07-18 2019-11-05 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US20180019184A1 (en) 2016-07-18 2018-01-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10079196B2 (en) 2016-07-18 2018-09-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10486965B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10804179B2 (en) 2016-08-12 2020-10-13 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10486963B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
US20180044177A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10109550B2 (en) 2016-08-12 2018-10-23 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10985033B2 (en) 2016-09-12 2021-04-20 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
CN110050335A (en) * 2016-11-08 2019-07-23 麻省理工学院 Dislocation filtration system and method for layer transfer
US10903073B2 (en) * 2016-11-08 2021-01-26 Massachusetts Institute Of Technology Systems and methods of dislocation filtering for layer transfer
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10790216B2 (en) 2016-12-09 2020-09-29 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US20180342439A1 (en) 2016-12-09 2018-11-29 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US20190013255A1 (en) 2017-07-06 2019-01-10 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10490471B2 (en) 2017-07-06 2019-11-26 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US20190074271A1 (en) 2017-09-05 2019-03-07 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US20190074263A1 (en) 2017-09-05 2019-03-07 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US12062701B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12062700B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12125739B2 (en) 2018-04-20 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
WO2019226711A1 (en) * 2018-05-22 2019-11-28 Etx Corporation Method and apparatus for transfer of two-dimensional materials
US10995409B2 (en) 2018-05-22 2021-05-04 Etx Corporation Method and apparatus for transfer of two-dimensional materials
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US11063021B2 (en) 2018-06-11 2021-07-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US12165951B2 (en) 2018-07-02 2024-12-10 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046535B2 (en) 2018-07-02 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11942389B2 (en) 2018-11-29 2024-03-26 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US20210296199A1 (en) 2018-11-29 2021-09-23 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US20220108938A1 (en) 2019-01-23 2022-04-07 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11961813B2 (en) 2019-01-23 2024-04-16 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US20200235054A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11710680B2 (en) 2019-01-23 2023-07-25 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923313B2 (en) 2019-01-23 2024-03-05 Qorvo Us, Inc. RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same
US20220139862A1 (en) 2019-01-23 2022-05-05 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US12062623B2 (en) 2019-01-23 2024-08-13 Qorvo Us, Inc. RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same
US12112999B2 (en) 2019-01-23 2024-10-08 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
CN110970340A (en) * 2019-10-31 2020-04-07 中国电子科技集团公司第五十五研究所 A kind of flexible InP HBT device and preparation method thereof
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
US12062571B2 (en) 2021-03-05 2024-08-13 Qorvo Us, Inc. Selective etching process for SiGe and doped epitaxial silicon
CN113764968A (en) * 2021-09-07 2021-12-07 中国科学院半导体研究所 A kind of method of removing epitaxial wafer substrate

Similar Documents

Publication Publication Date Title
US5391257A (en) Method of transferring a thin film to an alternate substrate
US5286335A (en) Processes for lift-off and deposition of thin film materials
US6335263B1 (en) Method of forming a low temperature metal bond for use in the transfer of bulk and thin film materials
US5465009A (en) Processes and apparatus for lift-off and bonding of materials and devices
US5641381A (en) Preferentially etched epitaxial liftoff of InP material
US5244818A (en) Processes for lift-off of thin film materials and for the fabrication of three dimensional integrated circuits
US7709353B2 (en) Method for producing semiconductor device
CN100444318C (en) Processes for the preparation of separable semiconductor components, especially substrates for the manufacture of electronic, optoelectronic and optical devices
US20030122141A1 (en) Structure and method for separation and transfer of semiconductor thin films onto dissimilar substrate materials
US11152216B2 (en) Method for manufacturing semiconductor device
KR102533932B1 (en) Strain relief epitaxial lift-off with pre-patterned mesas
US8330036B1 (en) Method of fabrication and structure for multi-junction solar cell formed upon separable substrate
US6974721B2 (en) Method for manufacturing thin semiconductor chip
US20220148921A1 (en) Semiconductor device manufacturing method and semiconductor device manufacturing system
US20050048736A1 (en) Methods for adhesive transfer of a layer
JP3307186B2 (en) Jig for semiconductor surface treatment
KR102656505B1 (en) Die-to-wafer bonding utilizing micro-transfer printing
US5376229A (en) Method of fabrication of adjacent coplanar semiconductor devices
US8033011B2 (en) Method for mounting a thinned semiconductor wafer on a carrier substrate
JP7635838B2 (en) Method for manufacturing compound semiconductor junction substrate
WO2020095610A1 (en) Method for manufacturing semiconductor substrate for light-emitting element, and method for manufacturing light-emitting element
WO2022249675A1 (en) Method for manufacturing compound semiconductor junction substrate, and compound semiconductor junction substrate
JP6836022B2 (en) Semiconductor substrate, semiconductor substrate manufacturing method and semiconductor element manufacturing method
JP4168460B2 (en) Method for manufacturing optoelectronic semiconductor integrated circuit device
JP2021077909A5 (en)

Legal Events

Date Code Title Description
AS Assignment

Owner name: ROCKWELL INTERNATIONAL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SULLIVAN, GERARD J.;SZWED, MARY K.;CHANG, MAU-CHUNG F.;REEL/FRAME:006824/0556;SIGNING DATES FROM 19931207 TO 19931210

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: TELEDYNE SCIENTIFIC & IMAGING, LLC, CALIFORNIA

Free format text: CHANGE OF NAME;ASSIGNOR:ROCKWELL SCIENTIFIC COMPANY, LLC;REEL/FRAME:018855/0939

Effective date: 20060918

Owner name: ROCKWELL SCIENTIFIC COMPANY, LLC, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CONEXANT SYSTEMS, INC.;REEL/FRAME:018855/0931

Effective date: 20011031

AS Assignment

Owner name: ROCKWELL SCIENCE CENTER, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ROCKWELL INTERNATIONAL CORPORATION;REEL/FRAME:019795/0862

Effective date: 19961115

Owner name: ROCKWELL SCIENCE CENTER, LLC, CALIFORNIA

Free format text: MERGER;ASSIGNOR:ROCKWELL SCIENCE CENTER, INC.;REEL/FRAME:019795/0892

Effective date: 19970827

AS Assignment

Owner name: CONEXANT SYSTEMS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ROCKWELL SCIENCE CENTER, LLC;REEL/FRAME:019892/0269

Effective date: 19981210

AS Assignment

Owner name: SKYWORKS SOLUTIONS, INC., MASSACHUSETTS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TELEDYNE SCIENTIFIC & IMAGING, LLC;REEL/FRAME:020035/0776

Effective date: 20071029