US3708874A - Method of making a batch fabricated magnetic memory - Google Patents
Method of making a batch fabricated magnetic memory Download PDFInfo
- Publication number
- US3708874A US3708874A US00176411A US3708874DA US3708874A US 3708874 A US3708874 A US 3708874A US 00176411 A US00176411 A US 00176411A US 3708874D A US3708874D A US 3708874DA US 3708874 A US3708874 A US 3708874A
- Authority
- US
- United States
- Prior art keywords
- channels
- conductors
- memory
- planar member
- planar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015654 memory Effects 0.000 title claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims description 32
- 239000003989 dielectric material Substances 0.000 claims description 5
- 238000003486 chemical etching Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 11
- 238000010276 construction Methods 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000010408 film Substances 0.000 description 3
- DMFGNRRURHSENX-UHFFFAOYSA-N beryllium copper Chemical compound [Be].[Cu] DMFGNRRURHSENX-UHFFFAOYSA-N 0.000 description 2
- 229910000889 permalloy Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 230000005389 magnetism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000012815 thermoplastic material Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/04—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using storage elements having cylindrical form, e.g. rod, wire
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
- Y10T29/49069—Data storage inductor or core
Definitions
- the sheets have channels formed therein using precision batch fabricated metal sculpturing techniques, with certain of the channels being filled with insulative material.
- the dimensions and locations of the channels are chosen so that precisely located memory wire receiving tunnels and corresponding insulated drive line strips perpendicular thereto are formed whenthe sheets are placed together in opposed relation.
- Memory wire elements are inserted into the tunnels which protect and shield the elements and maintain them accurately positioned with respect to one another and to the drive line strips so as to permit achieving a memory of increased density and speed of operation.
- the present invention is directed to a magnetic wire memory construction and fabrication method therefor which makes possible the provision of an improved magnetic wire memory which significantly reduces the problems heretofore associated with such memories.
- a basic feature of the present invention resides in the use of precision batch fabricated metal sculpturing techniques on metal sheets for forming memory planes having tunnels and insulated conductive drive line strips at predetermined locations whereby, after stacking of the planes, a modular magnetic wire memory structure is obtained in which the magnetic wire elements are uniformly and symmetrically retained with respect to each other and to the memory drive lines with an accuracy and shielding significantly greater than would be possible using other known types of memory constructions.
- noise cancellation can be achieved to a much higher degree than was heretofore possible so as to permit achieving a significantly greater packing density aswell as an increased speed of operation.
- the use of sculptured metal sheets provides the memory with a much greater heat dissipation capability than would. otherwise be possible.
- FIGS. 1-4 are fragmentary cross-sectional and pictorial views illustrating stages in the fabrication of a memory plane in accordance with the invention
- FIG. 5 is a fragmentary cross-sectional and pictorial view of a memory plane in accordance with the inven? tion;
- FIG. 5A is a fragmentary cross-sectional view of a modified form of the structure of FIG. 5;
- FIG. 6 is a cross-sectional view illustrating the structure of an exemplary plated wire memory element which may be employed in the memory of the invention.
- a rigid self-supporting conductive metal plate or sheet 10 which may, for example, be beryllium copper has a first plurality of spaced parallel channels 12 chemically etched in one surface, thereof.
- the channels 12 are filled with dielectric material 14 which is ground flush with the surface.
- the other surface of the sheet 10 is chemically etched to form second and third pluralities of spaced parallel channels 16 and 18 respectively perpendicular and parallel to the channels 12.
- the channels 18 are also located opposite respective channels 12 and have a width and depth with respect thereto so as to form spaced conductive strips 15 insulated from one another and from the sheet 10, and supported by the dielectric material I 14. It is to be understood that well known precision chemical etching techniques, such as photolithograph, may be employed for etching the channels 12,16, and 18.
- each memory element 25 is completely surrounded by contacting metal portions of the sheets 10, and that the drive line strips 15 alternate with contacting metal portions 10A of the sheets 10, thereby providing good shielding for each memory element 25 as well as for each opposed pair of drive lines 15.
- a construction as illustrated in FIG. 5A could be provided in which the drive line strips 15 are recessed from the outer surfaces and the recesses 21 filled with dielectric material ground flush with the outer surfaces.
- An adjacent contacting conductive layer 29 is then provided over the surface such as by plating or by the provision'of a metal sheet fused theretoto complete the conductive encirclement of each pair of opposed drive lines 15.
- a high permeability magnetic layer 30 of, for example, conetic or permalloy may also be provided on one or both of the outer sides of each plane in order to reduce memory cell disturbance by the earths magnetic field.
- An insulation layer 31 is" additionally provided in the embodiment of FIG. 5 to prevent the magnetic layer 30 from shorting the insulated strips 15.
- FIG. 6 illustrates an exemplary type of memory element which may be employed for each of the memory elements 25 in FIG. 5.
- the memory element 25 illustrated in FIG. 6 comprises a beryllium copper inner wire 26 having, for example, a diameter of 0.005 inch and on which is plated an essentially single domain thin .film 27 of magnetic material such as permalloy having a thickness of, for example, 10,000 Angstroms. The plating is done in a circumferential magnetic field produced by current flowing in the inner wire 26 so that the resultingfilm 27 is magnetically anisotropic, displaying remanent magnetism in the circumferential direction (commonly referred to 'as the "easy direction),but not in the longitudinal direction (commonly referred to as the hard" direction).
- a final insulative coating 28 of, for example, 0.0001 inch of a thermoplastic material is applied over the-magnetic film 27, such as by dipping, so as to prevent shorting of the drive line conductive strips when the memory wire elements are inserted in the tunnels 22 as shown in FIG. 5.
- FIGS. 7-9 illustrate how a plurality of the memory planes of FIG. 5 may be stacked and peripherally interconnected to form a multi-plane three-dimensional memory.
- FIG. 7 is a cross-section taken longitudinally through the center of a wire memory element 25 and perpendicular to the drive line strips 15, while FIG. 8 is across-section taken longitudinally through the center of a drive line strip 15 and perpendicular to the wire memory elements 25, as indicated byv the line 8-8 in FIG. 7, the line7-7 in FIG. 8, and the lines 7--7 and 8-'-8in FIG. 9.
- the peripheral sections and 42 in FIGS. 7-9 contain circuitry whichprovides appropriate interconnections for the inner conductors 26 of the memory wire elements 25 and the drive line strips 15. These peripheral sections 40 and 42 may also advantageously contain the sensing, selecting and driving circuitry required forthe memory.
- the circuitry in the sections 40 and 42 is preferably provided using the coaxial packaging techniques disclosed in the commonly as- 'signedU.S.'Pat.- No. 3,351,816 andin the commonly assigned copending'. patent applications Ser. No. 613,652, filed Feb. 2, 1967, and Ser. No. 819,888, filed Apr. 28, 1969.
- the resulting memory will then comprise a stack of wafers containing memory wire elements and drive lines as well as the peripheral sensing, driving, selecting, and interconnectin g circuitry therefor.
- the lower sheet 10 of each memory plane extends into the peripheral sections 40 in order to feed thereto the memory wire connecting strips 51 to which are soldered the ends of the inner conductors of the memory elements 25.
- the solder is indicated by the numeral 154.
- Insulative material 53 is provided to insulate the connecting strips 51 from each other and from the sheet 10.
- both of the sheets 10 extend-into the peripheral sections 42 in order to feed the drive lin'e strips 15 thereto.
- the memory sheets 10 may conveniently be incorporated with the circuitry of the peripheral wafers to provide the resulting structure shown in FIG. 9. I
- a memoryconst'ructed as described herein may be operated in various known types of operating modes in either a destructive or nondestructive manner.
- One skilled in the art will readily be able to provide the required driving, sensing, selecting, and interconnecting circuitry for this purpose.
- certain of. the wires 25 may be provided without a magnetic film 27 (FIG. 6) thereon so that they may serve as dummies to provide for noise cancellation.
- dielectric-filled spaced parallel channels in one surface of each planar-memberand a' plurality of spaced parallel memory element channels in the other surface of at least one planarmember extending in a direction so as to cross said dielectricfilled channels
- each'planar member parallelito said dielectric-filled channels and. having a location, width, and depth relative thereto so as to, electrically isolate spaced parallel conductive portions of each planar member to thereby form a plurality of spaced, electrically isolated conductors parallelto saiddielectric-filled channels and located, in a common plane perpendicularly spaced from said other surface, and
- planar members disposing said planar members inopposed relation to and parallel to respective conductors of the other planar member and so that the memory element channels form memory element receiving tunnels crossed by conductors on opposite sides thereof.
- said method includes the additional step of inserting wire-like memory elements into said tunnels.
- channels are formed using precision chemical etching techniques.
- each isolating channel is formed opposite a respective conductor if its planar member with a width extending at least beyond the nearest side of each of the dielectric-filled channels forming the conductor and with a depth extending to the conductor 6.
- said method includes the additional steps of recessing the conductors of each planar member from said one surface thereof,
- said method includes the additional step of providing a magnetic layer adjacent at least one of the surfaces of said planar members containing said dielectric-filled channels.
- said method includes the additional step of stacking a plurality of opposed pairs of planar members to form a three-dimensional memory.
- each wire-like memory element has a conductive inner wire and a magnetic thin film thereon
- said method includes forming insulated connecting conductors in one of said planar members and electrically connecting said connecting conductors to respective conductive inner wires of said memory elements.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (9)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17641171A | 1971-08-23 | 1971-08-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
US3708874A true US3708874A (en) | 1973-01-09 |
Family
ID=22644252
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US00176411A Expired - Lifetime US3708874A (en) | 1971-08-23 | 1971-08-23 | Method of making a batch fabricated magnetic memory |
Country Status (1)
Country | Link |
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US (1) | US3708874A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3771220A (en) * | 1972-05-05 | 1973-11-13 | Goodyear Aerospace Corp | Method of making a plated wire array |
US5071359A (en) * | 1990-04-27 | 1991-12-10 | Rogers Corporation | Array connector |
US5245751A (en) * | 1990-04-27 | 1993-09-21 | Circuit Components, Incorporated | Array connector |
US20050039331A1 (en) * | 2000-06-19 | 2005-02-24 | Smith Douglas W. | Electrically shielded connector |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3665428A (en) * | 1970-10-16 | 1972-05-23 | Minnesota Mining & Mfg | Keepered plated-wire memory |
-
1971
- 1971-08-23 US US00176411A patent/US3708874A/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3665428A (en) * | 1970-10-16 | 1972-05-23 | Minnesota Mining & Mfg | Keepered plated-wire memory |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3771220A (en) * | 1972-05-05 | 1973-11-13 | Goodyear Aerospace Corp | Method of making a plated wire array |
US5071359A (en) * | 1990-04-27 | 1991-12-10 | Rogers Corporation | Array connector |
US5245751A (en) * | 1990-04-27 | 1993-09-21 | Circuit Components, Incorporated | Array connector |
US20050039331A1 (en) * | 2000-06-19 | 2005-02-24 | Smith Douglas W. | Electrically shielded connector |
US7155818B2 (en) * | 2000-06-19 | 2007-01-02 | Intest Ip Corp | Method of fabricating a connector |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ALLIED CORPORATION COLUMBIA ROAD AND PARK AVENUE, Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:BUNKER RAMO CORPORATION A CORP. OF DE;REEL/FRAME:004149/0365 Effective date: 19820922 |
|
AS | Assignment |
Owner name: EATON CORPORATION AN OH CORP Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:ALLIED CORPORATION A NY CORP;REEL/FRAME:004261/0983 Effective date: 19840426 |
|
AS | Assignment |
Owner name: CONTEL FEDERAL SYSTEMS, INC., A DE CORP.,VIRGINIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:EATON CORPORATION, A OH CORP.;REEL/FRAME:004941/0693 Effective date: 19880831 Owner name: CONTEL FEDERAL SYSTEMS, INC., CONTEL PLAZA BUILDIN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:EATON CORPORATION, A OH CORP.;REEL/FRAME:004941/0693 Effective date: 19880831 |