US3617722A

US3617722A - Multiple-character generator

Info

Publication number: US3617722A
Application number: US864765A
Authority: US
Inventors: Stephen A Grosky
Original assignee: Bunker Ramo Corp
Current assignee: Bunker Ramo Corp; Allied Corp
Priority date: 1969-10-08
Filing date: 1969-10-08
Publication date: 1971-11-02
Anticipated expiration: 1988-11-02
Also published as: GB1285288A; DE2042596A1; JPS511369B1

Abstract

A circuit for converting a single coded input character into a plurality of coded output characters by applying a portion of the coded input character to a character generator device and deriving the remaining inputs to the character generator device from a counter which is incremented each time an output character is generated. The multiple character sequence is terminated when a predetermined output is obtained from the character generator.

Description

United States Patent [72] Inventor Stephen A.Grosky 3,413,610 11/1968 Botzer 340/3241 Monroe, Conn. 3,422,420 1/1969 Clark 340/324.1 [21] Appl. No. 864,765 3,440,638 4/1969 Vaikenburg... 340/3241 [22] Filed Oct.8, 1969 3,483,547 12/1969 Henderson 340/3241 [45] 1971 Primary Examiner-Maynard R. Wilbur [73] Ass'gnee The uunker'Ramo 9' Assistant Examiner-Jeremiah Giassman Stamford Conn Attorney-Frederick M. Arbuckle [54] MULTIPLE-CHARACTER GENERATOR 10 Claims, 2 Drawing Figs. [52] U.S.C1 235/154,

340/324'1 ABSTRACT: A circuit for converting a single coded input [51] Int. Cl 0413/02 character i a l i y of coded output characters by app|y [50] Field ofSearch 235/154; ing a portion f the coded input character to a character 3403413241 154 generator device and deriving the remaining inputs to the R f C" d character generator device from a counter which is incre- [56] e fences e mented each time an output character is generated. The multi- UNITED STATES PATENTS ple character sequence is terminated when a predetermined 3,396,377 8/1968 Strout 340/324.1 output is obtained from the charactergenerator.

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$2? 7 q ocutnnon 9 40 j o 52 52 a W 14 s so I run or seoucucz unscrew o I lust m" M l 107% an! a. I I -50 ENABLE MULTIPLE-CHARACTER GENERATOR MULTIPLE CHARACTER GENERATOR This invention relates to a circuit for generating a plurality of coded output characters in response to the receipt of a single input character, and more particularly to a circuit for generating a plurality of output characters as a result of the depression of a single key on a keyboard.

In most applications where a keyboard is being utilized to enter information into a data processing system, there are character combinations, such as words or short phrases, which frequently appear. For exampleflwords such as "buy" sell, and "cancel might appear frequently in a sales-orientated application. Editing or other instruction characters, such as tab,

skip, and the like, may, in some application be included in the multiple character sequences. In such applications, substantial operator time can be saved if these words are generated as a result of a single key depression. However, the multiple character combination required .for each application generally differ, and even the words or other character combinations required within a single application may differ with time. Also, the number of characters in the sequences will vary both within a single application and from application to application.

l-ieretofore, multiple character generation has been accomplished by hard wiring the multiple character sequences into the control logic of the system. Thus, special logic design was required for each application of the system, and a rewiring of the system logic was required for any change in a system's multiple character sequences.

A problem similar to that described above also arises in applications where the information is to be transmitted over lines. If frequently used character combinations could be transmitted as a single character, significant savings in transmission time and bandwidth would be obtained..I-Iowever, a capability must be provided for-converting the transmitted characters into the desired multiple character sequence at the receiving station. Again, flexibility in design and ease in making alterations are desirable. I,

t It is, therefore, aprimary object of this invention to provide as improved circuit for converting a single coded input character into a plurality of coded output characters.

A more specific object of this invention is to provide a circuit for generating a plurality .of output characters as a result of a single key depression on a keyboard.

A still more specific object of this invention is to provide a circuit of the type indicated above which permits the output character sequences to be easily modified.

A further object of this invention is to provide a circuit of the type indicated above which provides flexibility over a wide range in the length of the character sequences which may be obtained.

In accordance with these objects, this invention provides a circuit for converting a single coded input character into a plurality of coded output characters. The circuit includes a character generator means adapted to generate a predetermined coded output character in'response to the application thereto of a selected combination of input bits. A counter means is provided, with at least a portion of an input character being applied as part of the inputto the character generator, and the output from the counter means being applied as the remaining input to the character generator. Each time an out put is generated by the charactergenerator, the output from the counter is altered. When a predetermined output is obtained from the character generator, the generating of new characters by the character means is terminated. The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descrip tion of preferred embodiments of the invention as illustrated in the accompanying drawings.

In the drawings: drawings.

In FIG. 1 is a schematic block diagram of an illustrative embodiment of the invention.

FIG. 2 is a schematic block diagram of an alternative embodiment of the invention.

Referring now to FIG. 1, it is seen that an input code is derived on lines 10 from a keyboard 12. Forpurposes of the following discussion it will be assumed that either the circuit operates quickly enough so that the multiple character generation can be completed during the minimum time that a key is depressed, as would normally be the case, or that the keyboard is of a locking variety in which a key is not released until a release signal is received. Thus, signals remain on lines 10 until all required characters have been generated.

For the illustrated embodiment of the invention, it has been assumed that there are seven lines 10 and that the coded output from keyboard 12 is in the seven bit ASCII code. From the discussion to follow, it will be apparent that, while in FIG. 1, a keyboard has been shown for applying signals to lines 10, ASCII codes could be applied to these lines from some other source such as, for example a transmission line or a radio receiver. With such an input, a buffer register might be required in order to hold the input code until the completion of the multiple-character generation operation.

Multiple-character (MC) flip-flop 14 is normally in its ZERO state generating an output signal on line 16 which isapplied to condition gates 18 to pass on lines 10 through lines 20, OR gates 22, and lines 24 to be stored in memory 26. Thus, as long as MC flip-flop 14 is in its ZERO state, input characters on lines 10 are stored directly in memory 26. These characters may be stored in parallel, or may be serialized before being stored. Memory 26 may, for example, be standard recirculatingdelay line, drum or disk.

However, when detector 28 generates an output on line 30, indicating that the character code on lines 10 is one of the special codes which appears in column, or stick, 6, in ASCII code, MC flip-flop 14 is set to its ONE state. This deconditions gates 18, preventing the character on line 10 from being stored in memory 26. As a practical matter, a short delay may be required in the circuit prior to gate 18 in order to permit the detection operation in circuit 28, and the setting of flip-flop 14, to be completed before the character reaches this gate.

The four least significant, or row, lines of the lines 10 are connected as four of the inputs to character generator 32. Generator 32 may be any of a variety of known circuits which are capable of accepting coded inputs on a first selected number of lines and of generating, through the use of "matrix combinations of gates, diodes and/or the like, a unique output on a second selected number of lines. A read-only memory might also be'utilized for the generator 32. While the particular generator utilized is not a critical part of the present invention, a generator suitable for this purpose will be described later. The remaining N inputs to the character generator matrix are the N output lines 34 from counter 36. The number of lines 34, and therefore the size of the counter 36, depends on the maximum number of characters which is required in an output multiple character sequence. Thus, if N is three, no more than eight characters are obtainable in an output sequence. Generally, the number of characters obtainable will be equal to (2").

In operation, counter 36 is initially reset to a count of zero. The manner in which this is accomplished will be described later. Thus, the initial code applied to matrix 32 is the row code of the input character on lines 10, plus all zeros on lines 34. This input code is converted, by known encoding techniques, into the seven bit ASCII code for the first character of the desired output. This character, appearing on lines 38 is applied as the information input to gates 40. Since MC flip-flop 14 is now in its ONE state, a signal appears on ONE-side output line 42 partially conditioning AND gate 44. At character clock time, a signal appears on enable line 46, fully conditioning AND gate 44 to generate an output on line 48 which is applied to condition gate 40 to pass the character code on lines 38 through lines 50, OR gates 22, and lines 24 to be stored in memory 26. The signal on line 46 may be derived from memory 26 when it is in a condition to receive a new character. The first character of the desired multiplecharacter sequence is in this manner obtained and stored.

The character on lines 38 is also applied to end-of-sequence detector 52. Detector 52 may, for example, be an AND gate, the inputs to which are selected such that it generates an output signal on end-of-sequence line 54 only when the selected end-of-sequence code, such as all zeros, appears on lines 38. Line 54 is connected through inverter 56 and line 58 to one input of AND gate 60. ONE-side output line 42 from MC flipflop I4 is a second input to this AND gate with enable line 46 being its final input. Thus, if the character code which was stored in memory is not the end-of-sequence code, AND gate 60 is fully conditioned to generate an output signal on line 62, which signal is applied to step counter 36. This increments the value appearing on line 34. Matrix 32 is arranged so that the code appearing on the first four of the lines plus the incremented value on lines 34 results in the ASCII code for the second desired character of the character sequence appearing on lines 38.

The above sequence of operations is repeated with a new character of the desired sequence being generated each time counter 36 is incremented. It should be noted that the same output character may be generated as a result of several different inputs. Thus, for the word sell,".lthe code of the letter 1" is generated both when an output of 2 is generated by the counter and when 3 output of 3 is generated.

When the last of the characters which it is desired to generate has been stored in memory 26, the next incrementing of counter 36 results in matrix 32 generating the end-ofsequence code on lines 38. In a preferred embodiment of the invention, this is accomplished by providing no output from generator 32 for the input code which appears after the last character of a desired sequence has been generated. The resulting all-zeros input to detector 52 causes a signal on line 54 which is applied to reset counter 36 to a count of zero and to reset MC flip-flop 14 to its ZERO state. If a locking keyboard is utilized, the signal of line 54 may also be applied to release keyboard 12. The circuit is thus reset in preparation of the next input code. It should be noted that no means has been shown in the circuit for suppressing the storage of the end-of-sequence code in memory 26. If desired, this may be accomplished by utilizing line 58 as an additional input to AND gate 44.

A circuit has thus been described which is capable of storing either a single character or a plurality of characters in response to a single code input. The number of characters which appear in each sequence may be varied over a wide range depending on the size of the counter 36 utilized, and single character sequences are possible. It can also be seen that the multiple-character sequences generated may be changed merely by changing character generator matrix 32. Since this matrix may be formed on a single printed circuit card, changes in the character sequences become a relatively simple matter. If an ROM character generator is utilized, changes may be even more easily effected by merely reprogramming the ROM.

For the illustrative embodiment of the invention, the characters stored in memory 26 are utilized to control the display on a cathode-ray tube (CRT) display device. Thus, the contents of memory 26 are applied through line 64 to video code character generator 66. As will be seen shortly, this generator may be of the same general form as the generator 32, thus simplifying design and reducing total system cost. The video code output on line 68 from generator 66 is applied to control and refresh the display on display device 70.

Since character generator 32 is the most expensive element of the circuit in FIG. I, the cost of a system having multiple inputs may be reduced by having this element shared by a number of keyboards. FIG. 2 shows such a multiplexed system and also shows in more detail a selected embodiment for character generator matrix 32 and counter 36.

Referring now to FIG. 2 it is see that there are three keyboards l2A-l2C each of which is adapted to generate outputs in a selected code, such as ASCII, on corresponding output lines 10. These outputs would normally be applied through gates 18, such as that shown in FIG. '1, to be stored in a memory 26. The particular keyboard which has access to memory at any given time is determined by input assignment logic 76. This logic accepts inputs from a system master clock (not shown) and generates outputs on one of three lines, designated C1, C2, C3, to indicate which of the three input keyboards is to have access to the memory at a given time.

When a column 6 character is detected in one of the keyboards 12, it generates an output on the corresponding line 78 to cause the corresponding MC flip-flop of the MC flipfiops 14 to be set to its ONE STATE. This results in a signal on the corresponding one of the three MC lines 42.

The four least significant bits, or row bits, of the code appearing on a set of lines 10 are applied to the appropriate gate of input assignment logic circuit 80. This circuit would consist of three sets of gates, one for each of the sets of lines 10, with corresponding outputs from each of the sets being ORed together. Each set of gates is conditioned by a corresponding one of the clocklines C1-C3. When a signal appears on the appropriate clock line, the signals on lines 10 are passed through circuit 80 and lines 82 to form one set of inputs to character generator matrix 84.

Character generator matrix 84 is the same as the front end of the character generator 66 (FIG. 1) used for converting ASCII code to video code. This circuit accepts the seven-bit ASCII input and generates the equivalent 35-bit video output. These 35 bits on lines 86 are applied to a second character encoder 88 which gates these bits, seven bits at a time, to the display device under control of a stroke counter. Thus, the seven bits for the first stroke would be applied to the display device during stroke one time, followed by the seven bits of the second stroke during stroke two time, as so on until all five strokes of the five by seven character have been generated. A code generator of this general type is shown in U.S. Pat. No. 3,440,646 entitled CODE CONVERSION MEANS which issued to E. M. Dean on Apr. 22, 1969 and is assigned to the assignee of the instant application. The discussion to follow will show how this character generator may be utilized as the character generator matrix 32.

As was indicated previously, in addition to the 35 lines 86, matrix 88 also has as inputs five lines 90 only one of which has a signal on it at any time. These lines would normally indicate the stroke of the character which is being generated. However, in this invention, they are merely used as additional code inputs. Thus, the circuit has three stroke substitute character counters (SSCCs) 92 each of which is normally set to generate an output on the first of its five output lines 94. The lines 94 are connected through a gating circuit designated SSCC selector 96 to the five lines 90. Thus at C1 time lines 94A will be connected to the lines 90, at C2 time lines 94B will be connected, and at C1 time lines 94C will be connected.

Matrix 84 is adapted to receive seven inputs only four of which are supplied by the lines 82. The remaining three inputs are output lines 98 from sequence counter (SC) selector 100. Selector 100 is a gating circuit which connects one of the three sets of output lines 102 from a sequence counter 104 to line 98 under control of the assignment logic clock lines. All of the sequence counters are initially set to zero.

While matrix 88 generates outputs on its seven output lines 105 at each character time, these outputs are not utilized until one of the MC flip-flops 14 is set to its ONE state. This results in a signal on one of the lines 42 which is applied as an input to a corresponding AND gate 106. The other inputs to each of the AND gates 106 are enable line 46 and the corresponding assignment logic clock line, output lines 108 from AND gates 106 are applied to gate the signals on generator matrix output lines 105 to a memory (such as memory 76 shown in FIG. 1) and are also applied as a step input to the corresponding SSCC. Thus, during the first character time that a signal appears on a line 42, the character resulting from the input code on line 82, plus an all zero code on lines 98, plus a signal on the first of the lines 90, is applied through lines 105, loadmemory selector circuit 109, and line 111 to be stored in memory. The appropriate SSCC is also incremented. During the next character time the character which results from the same combination of inputs on lines, but from a signal on the second of the lines 90, appears on the circuit output line. The appropriate SSCC is again incremented. This process continues until the fifth character of the sequence is generated at which time the SSCC is incremented back to its initial condition and an overflow signal appears on the appropriate line 110 causing the corresponding sequence counter to be incremented. Additional characters may now be generated, with a new input now appearing on lines 98, as the appropriate SSCC is again stepped through its five conditions. This sequence of operation may be repeated two more times until a count of three appears on lines 98. Thus, the circuit is capable of generating five character codes as a result of the SSCC counter for each of four possible outputs from the corresponding sequence counter for a total of 20'p0ssible characters.

After the generation of any character, the character sequence may be terminated by providing no code output for matrix 88 for the combination of inputs applied to it on

lines

86 and 90. The detection of this all zeros code results in an endmf-sequence signal on line 54 which is applied to reset the appropriate MC flip-flop l4 and to reset the SSCC and SC counters. The circuit is thus reset in preparation for the next input, and, as with the general embodiment of the invention shown in FIG. 1, characters are again permitted to flow directly from keyboard to memory.

While the invention has been particularly shown and described with reference to preferred -embodiments thereof, it will be understood by those skilled in the art that the various changes in form and details previously discussed, as well as others, may be made therein without departing from the spirit and scope of the invention. What is claimed is: 1. A circuit for converting a single coded input character into a plurality of coded output characters comprising:

character generator means adapted to generate a predetermined coded output character in response to the application thereto of a selected combination of input bits;

means for applying at least a portion of an input character as input bits to said character generator means; counter means; means for applying the output from said counter means as the remaining input bits to said character generator means;

means operative only at times when an output character is be generated by said character generator means for altering the output from said counter means; and

means responsive to a predetermined output from said character generator means for terminating the generating of characters by said character generator means.

2. A circuit of the type described in claim 1 wherein the count in said counter means is incremented each time an output character is generated.

3. A circuit of the type described in claim 2 wherein there are a plurality of said counter means, wherein the count in a first of said counter means is incremented each time an output character is generated; and

wherein the counts in said remaining counter means are incremented each time an overflow occurs from the preceding counter means.

4. A circuit of the type described in claim 1 wherein said coded input character is derived from the depression of a single key on a keyboard.

5. A circuit of the type described in claim 1 including means for indicating that an input character may represent a plurality of output characters; I

a character storage means;

means for normally passing input characters directly to said character storage means; and

means responsive to an output from said indicating means for applying an input character to said converting circuit and for applying the output from said converting circuit to said character storage means. 6. A circuit of the type described in claim 5 wherein said input characters are coded in ASCII; and

wherein said indicating means is energized when a character in a selected stick of said ASCII code is applied to said circuit.

7. A circuit of the type described in claim 1 wherein said character generator means does not have a coded output which corresponds to the coded input applied to said character generator after the last character of a desired sequence has been generated whereby said predetermined output is an all zeros code.

8. A circuit of the type described in claim 1 including a plurality of different sources for said coded input characters;

a separate counter means for each of said sources;

means for indicating the input character source which is to have access to said character generator at any given time; and

means responsive to said indicating means for gating the outputs from the indicated source and its corresponding counter means to said character generator.

9. A circuit of the type described in claim 1 wherein said character generator is in two parts;

wherein said counter means is in two parts;

wherein the first part of said character generator accepts the portion of the input character and the output from one of said counter means and generates as an output an intermediate code; and

wherein the second of said character generator means accepts said intermediate code and the output from the other said counter means to generate the desired coded output character.

10. A circuit of the type described in claim 9 wherein said second counter is a stroke substitute counter which is incremented after each character is generated and wherein said first counter means is incremented when an overflow occurs from said stroke substitute counter.

Claims

1. A circuit for converting a single coded input character into a plurality of coded output characters comprising: character generator means adapted to generate a predetermined coded output character in response to the application thereto of a selected combination of input bits; means for applying at least a portion of an input character as input bits to said character generator means; counter means; means for applying the output from said counter means as the remaining input bits to said character generator means; means operative only at times when an output character is be generated by said character generator means for altering the output from said counter means; and means responsive to a predetermined output from said character generator means for terminating the generating of characters by said character generator means.

3. A circuit of the type described in claim 2 wherein there are a plurality of said counter means, wherein the count in a first of said counter means is incremented each time an output character is generated; and wherein the counts in said remaining counter means are incremented each time an overflow occurs from the preceding counter means.

5. A circuit of the type described in claim 1 including means for indicating that an input character may represent a plurality of output characters; a character storage means; means for normally passing input characters directly to said character storage means; and means responsive to an output from said indicating means for applying an input character to said converting circuit and for applying the output from said converting circuit to said character storage means.

6. A circuit of the type described in claim 5 wherein said input characters are coded in ASCII; and wherein said indicating means is energized when a character in a selected stick of said ASCII code is applied to said circuit.

8. A circuit of the type described in claim 1 including a plurality of different sources for said coded input characters; a separate counter means for each of said sources; means for indicating the input character source which is to have access to said character generator at any given time; and means responsive to said indicating means for gating the outputs from the indicated source and its corresponding counter means to said character generator.

9. A circuit of the type described in claim 1 wherein said character generator is in two parts; wherein said counter means is in two parts; wherein the first part of said character generator accepts the portion of the input character and the output from one of said counter means and generates as an output an intermediate code; and wherein the second of said character generator means accepts said intermediate code and the output from the other said counter means to generate the desired coded output character.