US3660729A

US3660729A - Electronic combination lock system

Info

Publication number: US3660729A
Authority: US
Inventors: Charles Fitzhugh James; Ralston Hodges Robertson Jr; Merville Lee Warnock
Original assignee: Bell Telephone Laboratories Inc
Current assignee: AT&T Corp
Priority date: 1971-01-11
Filing date: 1971-01-11
Publication date: 1972-05-02
Anticipated expiration: 1989-05-02
Also published as: CA948296A

Abstract

An electronic combination lock system comprises a decoder unit having a built-in combination. An external combination generator transmits a combination into the decoder unit to energize a lock operating means which operates a locking bar to lock or unlock the enclosure. The decoder recognizes a combination only if it has the correct number, sequence, and spacings of digits.

Description

United States Patent James et al.

154] ELECTRONIC COMBINATION LOCK SYSTEM [72] Inventors: Charles Fitzhugh James; Ralston Hodges Robertson, Jr.; Merville Lee Warnock, all of Indianapolis, 1nd.

Bell Telephone Laboratories, Incorporated, Murray Hill, NJ.

22 Filed: Jan.l1, 1971 21 Appl. No.5 105,406

[73] Assignee:

[52] U.S. Cl... ..317/134, 70/277 [51] Int. Cl ..E05b 49/00 [58] Field of Search ..317/134; 70/277 [56] References Cited 5 I UNITED STATES PATENTS 3,587,950 6/1971 Haigh etal ..317/134 51 May 2, 1972 3,587,051 6/1971 Hovey ..317/134 3,411,046 11/1968 Swannick ..317/134 3,513,357 5/1970 Dittmore ..317/134 Primary Examiner-J. D. Miller Assistant Examiner-Harry E. Moose, Jr. Att0rneyR. J. Guenther and Edwin B. Cave 57 ABSTRACT An electronic combination lock system comprises a decoder unit having a built-in combination. An external combination generator transmits a combination into'the decoder unit to energize a lock operating means which operates a locking bar to lock or unlock the enclosure. The decoder recognizes a combination only if it has the correct number, sequence, and spacings of digits.

24 Claims, 5 Drawing Figures DECODER' UNIT 4 ,BINARY-DECIMAL' CONVERTER COUNTER] INTERFACE COMBINATION GENERATOR 52 SINGLE SHOT MULTIVIBRATOR 72 32 comm; MATRIX 4 United States Patent v 1 3,660,729 James et al. [451 May 2, 1972 DECODER UNIT 4 6 MECHANICAL LOCKING MEANS COUNTER I J BINARY DECIMAL 34 CONVERTER COUNTER Patented May 2, 1972 3 Sheets-Sheet 3 f Tn Tn+ FIG. 2A

fF/Gj3 5 TIME IN YEARS ELECTRONIC COMBINATION LOCK SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to lock systems and, more particularly, to an electronic lock system for coin telephone cash vaults.

2. Description of the Prior Art Presently, coin telephones utilize various types of mechanical locks which may be opened by keys or dials. Such locks provide less than full security because key openings offer access to the locking mechanism which often can be operated by a skilled lockpicker. Also, the mechanical movement of dial locks often may be audibly detected to enable unauthorized persons to operate the lock system. Furthermore, the more secure mechanical locks are complex and, therefore, expensive to manufacture.

Electronic lock systems are known and used in such applications as safes, filing cabinets and like enclosures. However, none of the disclosed electronic lock systems appears satisfactory for use in coin telephones.

Accordingly, it is an object of this invention to provide an electronic lock system for coin telephones which furnishes more security than mechanical locks.

Another object is to provide a lock system having no mechanical openings therein and few moving parts to thereby prevent unauthorized operation of the lock system.

SUMMARY OF THE INVENTION The foregoing objects and others are achieved in accordance with the principles of this invention by an improved electronic lock system which utilizes electronic circuits to control the operation of mechanical locking means. The lock system comprises a decoder unit having a coding matrix with a preset code or combination. A combination generator transmits to the decoder unit a first type of control signal, or initializing signal, to initialize the decoder unit. A series of digit signals, which are interspersed with a second type of control signal or spacing signal, is subsequently transmitted to the decoder unit. Each digit signal is compared with the digit having the corresponding sequential position in the preset code. When the number of correct consecutive digit signals equals the number of digits in the preset code, the decoder unit produces an output which activates the mechanical'locking means. The decoder unit automatically produces an initializing signal after the number of digit signals transmitted to it equals the number of digits in the preset code. This insures that only the exact combination of digits, rather than just the correct sequence of digits, will produce an output. The duration of the spacing signal is required to be greater than a builtin time delay before the decoder circuit will function. Thus, operation of the lock system by use of a random digit generator in any reasonable period of time is prevented.

DESCRIPTION OF THE DRAWING The invention will be more fully comprehended from the following detailed description and the accompanying drawing in which:

FIG. 1A and 18 comprise a schematic block diagram of an electronic combination lock system embodying the invention;

FIG. 2A and 2B are, respectively, a schematic representation of the toggle flip-flop circuit used in FIG. 1A and 1B and a truth table therefor; and

FIG. 3 is a graphic representation of the probability of operating the lock system versus the length of time of using a random number generator for various built-in time delays.

DETAILED DESCRIPTION FlG. 1A and 18 comprise a schematic block diagram of an electronic lock system according to this invention. The major parts of the system are a combination generator 2 which generates the signals or digits required to operate the system; a

decoder unit 4 which compares the digits from generator 2 with an internal preset code and generates an output only when the combination presented by generator 2 matches the preset combination; and a mechanical locking means 6 which responds to the output decoder unit 4 to open the secured enclosure. Decoder unit 4 and locking mean 6 advantageously are contained within the secured enclosure, e.g., a coin telephone, while combination generator 2 is exterior to such enclosure.

Decoder unit 4 comprises an interface 8 which receives signals from generator 2 and produces initializing signals or pulses on connection 22, spacing signals on connection 24, and digit signals representing a combination on connection 26. Power for operating the decoder unit 4 and locking means 6 can also be transmitted from generator 2 through interface 8. Alternatively, such power may be furnished directly to these units from a power source such as the telephone central office.

The first signal from interface 8 is an initializing signal appearing on connection 22. This initializing signal is connected to the reset terminal r of toggle flip-flop 40 and to an input terminal of a 2-input OR gate 42. Consequently, whenever an initializing pulse appears at the input of OR gate 42, the gate produces an output which is connected through connection 50 to the reset terminals r of toggle flip-

flops

44 and 46, which comprise

counters

12 and 14, respectively. The operation of flip-

flops

44 and 46 can be readily understood by reference to FIG. 2A and 2B, which show a schematic representation of a toggle flip-f1op and a truth table of its operation, respectively. The appearance of a signal at the reset terminal r of the flipflop sets the state of the flip-flop to 0, i.e., the output Q is low. Thus, the appearance of a signal from OR gate 42 on connection 50 resets both counters I2 and 14 to the 0000" state.

Following the resetting or initializing of counters l2 and 14 by the initializing pulse, interface 8 next transmits a spacing signal pulse on connection 24 which is connected to the respective inputs of a single-shot multivibrator 28 and a 2- input OR gate 32. The outputs of multivibrator 28 and OR gate 32 are respectively connected to the reset terminals r of flip-flops 30 which comprise counter 10 and the input terminal T of the initial flip-flop 44 of counter 12 by

connections

52 and 54, respectively. The output of gate 32 is also connected to an input terminal of a series of AND gates Bl-Bl0 through connection 54. When the spacing pulse on connection 24 goes from high to low, i.e., from a logical l to a logical 0," multivibrator 28 produces an output on connection 52 which initializes counter 10 by resetting it to state 0000. Simultaneously, the output from OR gate 32 goes from high to low, thereby advancing counter 12 from the initial 0000 state to the 0001 state in accordance with FIG. 2A and 2B. Decoder unit 4 can now compare the digits of a transmitted combination with corresponding digits of the preset combination, as will subsequently be explained.

The preset combination or code in decoder unit 4 is determined by the interconnections made in coding matrix 20. Matrix 20 is, in essence, an X-Y or crosspoint matrix which interconnects AND gates A1-A10 of binary-decimal converter 16 with AND gates 81-810 of binary-decimal converter 18. The A connection in matrix 20 represents the numerical value of the respective digit of the preset code, while the 8 connection represent the sequential position of the respective digit in the code. For example, if the desired preset code is "7, 4, l0, 6, 3, 8, 9, 5, l, 2, then A7, A4, A10, A6, A3, A8, A9, A5, A1 and A2 would be connected with B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, respectively, in matrix 20. Digits can be used more than once in a combination by connecting the output of an A gate to the input of more than one "B gate. The interconnections between AND gates A1-A10 and 81-810 can be made by hard wiring, printed circuit techniques, or by other means which will be apparent to those skilled in the art. Matrix 20 can be made in the fonn of a plug-in unit to permit rapid changing of the combination. Although a ten digit code has been illustrated, it is apparent that codes having a different number of digits can be readily obtained by changing the number of AND gates, the interconnections in matrix 20, etc.

Following the removal of the spacing pulse from connection 24, interface 8 transmits a digit signal representing the first digit of a proposed combination on connection 26 which is connected to the input terminal T of the initial flip-flop 30 of counter 10. The digit signals are transmitted in serial form. Thus, if the first digit of the proposed combination is seven, seven pulses will be transmitted on connection 26. These seven pulses advance counter 10 to the l 1 1 state. Binarydecimal converter 16 interconnects AND gates A1-Al0 with counter such that when counter 10 registers seven, i.e., O1 1 l"state, all inputs to AND gate A7 are high and thus gate A7 produces a high output. Likewise, the output of any gate An will be high when counter 10 is registering the number nJ Thus, counter 10 specifies the value of the particular digit signal According to the illustrative combination, the output of AND gate A7 is connected by matrix 20 to one input of AND gate B1. In addition to the input from gates A1-A10, gates Bl-Bl0 each have five additional inputs, four of which are connected to counter 12 by binary-decimal converter 18. Counter 12 specifies the sequential position of the digit signal in the proposed sequence of signals. Thus the four inputs from counter 12 to gate Bm will be high when counter 12 is registering the number m. Consequently, since counter 12 was placed in the 0001" state by the first spacing pulse, the four inputs to gate Bl will be high in this particular situation because this digit signal is the first digit signal being considered.

The digit signals on connection 26 from interface 8 are interspersed by spacing signals on connection 24. Thus, after the seven pulses, i.e., the first digit signal, representing the first digit of the proposed combination have been transmitted, a second spacing signal is transmitted on connection 24. This second spacing signal causes the output of OR gate 32 to go high and provide the final required high input to gate Bl through connection 54, thereby causing the output of gate B1 to go high and provide a high input to OR gate 34 through connection 56. If the value of the initial digit signal does not equal the value of the initial digit of the preset combination, no output from any AND gate 131-1310 is high.

The high input to OR gate 34 produces a high output therefrom which is connected to respective inputs of time delay 36 and AND gate 38 through connection 58. The output from time delay 36 is connected to a second input of gate 38 through connection 62. If the spacing pulse from interface 8 has a duration greater than the period of time delay 36, the two inputs to gate 38 will be high simultaneously and gate 38 will produce a high output. This high output is connected to the input terminal T of the initial flip-flop 46 of counter 14 through connection 60. When the spacing pulse goes from high to low, the output from gate 38 goes from high to low and advances counter 14 to the 0001 state. Counter 14 represents the number of correct sequential digit signals which have been received from combination generator 2. Simultaneous with the advancement of counter 14, counter 12 is also advanced to the 0010 state and counter 10 is reset to the 0000state. Decoder 4 is now ready to compare the second transmitted digit signal with the second digit of the preset code.

The comparison of the transmitted digit signals with the corresponding digits of the preset code continues by the same process as that described for the first digit with counter 14 advancing one counter each time the transmitted digit signal compares in value and sequential position with the corresponding digit of the preset code. Counter 14 is connected to an AND gate 48 by connections 64 in such a manner that all inputs to gate 48 are high when counter 14 registers the same number as the number of digits in the preset code. ln the example, all inputs to gate 48 from counter 14 will be high when counter 14 registers l0, i.e., 1010 state, signifying that ten correct digit signals have been transmitted by interface 8. This number of correct digit signals equals the number of digits in the preset code.

AND gate 48 produces an output when all of its inputs are high. This output is connected to a mechanical locking means 6 by a connection 66. The high output energizes locking means 6 to open the secured enclosure. For example, locking means can comprise a solenoid and a locking bar responsive to the solenoid. The output from gate 48 can switch energy to such a solenoid, causing it to operate the locking bar and unlock or lock the enclosure. Various other locking means and methods of utilizing the output of gate 48 to control such locking means will be apparent to those skilled in the art.

The lock system of this invention contains additional features to prevent fraudulent operation thereof. As has been previously mentioned, the duration of the spacing pulse must be greater than the delay time of time delay 36 if counter 14 is to register a correct digit. Thus, time delay 36 determines the minimum time for operation of the lock system. This time can be set sufficiently long to prevent the operation of the lock system in any reasonable period of time by the use of a random digit generator in lieu of the combination generator 2. FIG. 3 graphically shows the probability of operating the lock system versus time for difi'erent values of time delay and for a given combination by use of a random number generator. For example, if the delay time I introduced by time delay 36 is 5 milliseconds and the number of digits in the combination is 10, approximately 19 months of random digit generation would be required to have a 10 percent probability of operating the lock system.

A second antifraud feature insures that the decoder 4 will only consider a sequence of digit signals equal to the number of digits in the preset code. Thus, in order to operate the system, the transmitted digit signals must be the exact combination rather than just the correct sequence of digits. This feature is provided by an AND gate B11 and the flip-flop 40. Gate B11 is connected to counter 12 in such a way as to produce an output when counter 12 advances beyond the number of digits in the preset code. In the illustrative example, when the number of digits in the preset code is 10, gate B11 produces an output when an eleventh digit signal is transmitted causing counter 12 to register lOl I." This output from gate B11 triggers flipflop 40 through connection 68 and produces a high output which is connected to OR gate 42 through connection 70. The output from gate 42 subsequently resets or initializes

counters

12 and 14 as described earlier.

Another antifraud circuit comprises AND gate All which provides a high input to OR gate 32 through connection 72 to prevent the lock system from responding to digit signals having values greater than the value of the largest digit in the preset code. For example, if one digit in the preset code was 2, transmitted digit signals having values such as 18,34, 50, etc., could be interpreted by decoder unit 4 as correct digits because counter 10 would be in the same state for all of these digit signals. However, when counter 10 advances beyond the value of the largest digit in the preset code, i.e., 10 in the illustrative example, gate A11 produces a high output which causes OR gate 32 to also produce a high output, thereby advancing counter 12 without registering a correct digit on counter 14.

The spacing and digit signals advantageously can be transmitted from combinations generator 2 to interface 8 as positive and negative pulses on a signal conductor. These signals can then be separated in interface 8 by polarity separators known in the art. Under such conditions, the spacing and digit signals cannot exist simultaneously. However, when these signals can exist simultaneously, such as by being transmitted over separate conductors, a correct digit reading on counter 14 could be obtained by keeping the spacing signal high and by transmitting a sequence of well-spaced digit signals and then removing the spacing signal. This procedure could be repeated until the correct reading for operating locking means 6 is obtained on counter 14. Such fraudulent operation can be prevented by connecting the spacing and digit signals as the inputs of a 2-input AND gate whose output resets counters 12 and 14 when both signals appear simultaneously.

As previously mentioned, the spacing and digit signals can be transmitted from generator 2 to interface 8 over wire con ductors. The initializing signal, power, and ground can likewise be transmitted. Interface 8 can include a plug and jack arrangement, contact plate, or various other methods of making connection which would be apparent to those skilled in the art. Further, the signals can be transmitted by radio or like methods, and the power can be furnished from the central office, if desired.

The combination generator 2 also can take many forms. For example, if the combination generator 2 is to be used on a collection route for coin telephones, it can comprise a magnetic tape having the combinations of numerous coin telephone locks written thereon by a computer in a prescribed sequence which corresponds with the collection route. The tape can be sealed into the generator 2 such that a combination will be transmitted only when the generator 2 is properly connected to a telephone. Numerous other features for increasing the security of combination generator 2 will be apparent to those skilled in the art.

While the invention has been described with respect to a specific embodiment, it is to be understood that various modifications thereto might be made by those skilled in the art without departing from the spirit and scope of the foregoing description and the following claims.

What is claimed is:

1. A electronic combination lock system comprising, in combination:

input means for providing control signals for said system, said control signals including a sequence of digit signals representing a combination;

a decoder including coding means for establishing a predetermined combination of digits for said system, means for comparing said digit signals with respective digits of said predetermined combination and producing an output signal in response thereto, said comparing means r slsdissfi st me s r .sistsnsis s ses each of said digit signals and second means for determining the sequential position of each of said digit signals such that each of said digit signals can be compared to the corresponding digit in said predetermined combination; and

locking means responsive to said output signal for moving between locked and unlocked positions.

2. Apparatus in accordance with claim 1 wherein said first and second determining means comprise first and second counters, respectively.

3. Apparatus in accordance with claim 2 including a first series of AND gates connected to said first counter, one of said first series of gates responding to said first counter according to said value of said digit signal, a second series of AND gates connected to said second counter, one of said second series of gates responding to said second counter according to said sequential position.

4. Apparatus in accordance with claim 3 wherein said coding means interconnects said first and second series of AND gates such that said predetermined combination of digits is established, said one of said second series of AND gates produces an output when said digit signal compares with said respective digit of said predetermined combination.

5. Apparatus in accordance with claim .4 including third means for determining the number of said outputs from said second series of AND gates and producing said output signal when said number of outputs equals the number of digits in said predetermined combination.

6. Apparatus in accordance with claim 5 wherein said third determining means comprises a third counter for counting said number of outputs and an AND gate responsive to said counter for producing said output signal.

7. Apparatus in accordance with claim 6 wherein said first, second, and third counters comprise flip-flop circuits.

8. Apparatus in accordance with claim 6 including means for resetting said second and third counters to respective initial sets whenever the number of said digit signals exceeds said number of digits in said predetermined combination.

9. Apparatus in accordance with claim 8 wherein said resetting means includes a gate of said second series which produces a trigger output in response to said second counter whenever said second counter registers a number greater than said number of digits in said predetermined combination, and a flip-flop circuit which produces a pulse in response to said trigger output to reset said second and third counters.

10. Apparatus in accordance with claim 6 wherein said control signals include an initializing signal for setting said second and third counters to respective initial sets before and after said sequence of digit signals is provided.

11. Apparatus in accordance with claim 6 wherein said control signals include a spacing signal interspersed between each of said digit signals, said spacing signal resetting said first counter to an initial state and advancing said second counter one count after each digit signal of said sequence is provided.

12. Apparatus in accordance with claim 5 including means for delaying said outputs from said second series of gates, said third determining means selectively responding to said outputs which have a duration greater than the delay time of said delaying means such that a minumum time for operating said lock system is established.

13. Apparatus in accordance with claim 1 including means for rejecting any digit signals having a value greater than the value of the largest of said digits in said predetermined combination.

14. Apparatus in accordance with claim 13 wherein said rejecting means comprises an AND gate responsive to said first determining means for producing an output vvhenever said first determining means indicates a value greater than said value of said largest of said digits, said second determining means being responsive to said output to change said sequential position.

15. Apparatus in accordance with claim 1 wherein said locking means comprises a locking bar movable between said 'locked and unlocked positions, and power means for moving said bar.

16. Apparatus in accordance with claim 15 wherein said power means comprises a solenoid.

17. Apparatus in accordance with claim 1 wherein said control signals include an initializing signal for setting said decoder to an initial state before and after said sequence of digits is provided.

18. Apparatus in accordance with claim 17 wherein said initializing signal sets said second determining means to an initial state.

19. Apparatus in accordance with claim 1 wherein said con trol signals include a spacing signal interspersed between each digit signal of said sequence, said spacing signal resetting said first determining means to an initial state and causing said second determining means to indicate a different sequential position after each digit signal is provided.

20. Apparatus in accordance with claim 19 wherein said spacing signals and said digit signals comprise respective positive and negative pulses on a single conductor from said input means, said decoder including an interface connected to said input means for separating said spacing and said digit signals.

21. Apparatus in accordance with claim 19 wherein said decoder includes an AND gate for producing an initializing signal whenever said spacing signal and said digit signal coincide, said initializing signal operating to reset said decoder to an initial state.

22. An electronic combination lock system comprising, in combination:

a coding matrix for establishing a predetermined combination of digits for said system;

input means for providing a sequence of digit signals for comparison with said digits of said predetermined combination;

a first counter including a series of flip-flop circuits for determining the value of each of said digit signals;

a second counter including a series of flip-flop circuits for determining the sequential position of each of said digit signals;

comparing means including first and second series of AND gates connected to said first and second counters, respectively, for sequentially comparing said digit signals with respective digits of said predetermined combination and producing an output whenever a digit signal equals said respective digit;

a third counter comprising a series of flip-flop circuits for counting said outputs;

an AND gate responsive to said third counter for producing an output signal when said third counter registers a value equal to the number of digits in said predetermined combination; and

23. Apparatus in accordance with claim 22 wherein said input means provides a first control signal for setting said second and third counters to respective initial states before and after each sequence of digit signals is provided, and a second control signal for resetting said first counter to an initial state after each of said digit signals is provided.

24. Apparatus in accordance with claim 22 wherein said input means provides power for operating said lock system.

Claims

1. A electronic combination lock system comprising, in combination: input means for providing control signals for said system, said control signals including a sequence of digit signals representing a combination; a decoder including coding means for establisHing a predetermined combination of digits for said system, means for comparing said digit signals with respective digits of said predetermined combination and producing an output signal in response thereto, said comparing means including first means for determining the value of each of said digit signals and second means for determining the sequential position of each of said digit signals such that each of said digit signals can be compared to the corresponding digit in said predetermined combination; and locking means responsive to said output signal for moving between locked and unlocked positions.

5. Apparatus in accordance with claim 4 including third means for determining the number of said outputs from said second series of AND gates and producing said output signal when said number of outputs equals the number of digits in said predetermined combination.

14. Apparatus in accordance with claim 13 wherein said rejecting means comprises an AND gate responsive to said first determining means for producing an output whenever said first determiniNg means indicates a value greater than said value of said largest of said digits, said second determining means being responsive to said output to change said sequential position.

15. Apparatus in accordance with claim 1 wherein said locking means comprises a locking bar movable between said locked and unlocked positions, and power means for moving said bar.

19. Apparatus in accordance with claim 1 wherein said control signals include a spacing signal interspersed between each digit signal of said sequence, said spacing signal resetting said first determining means to an initial state and causing said second determining means to indicate a different sequential position after each digit signal is provided.

22. An electronic combination lock system comprising, in combination: a coding matrix for establishing a predetermined combination of digits for said system; input means for providing a sequence of digit signals for comparison with said digits of said predetermined combination; a first counter including a series of flip-flop circuits for determining the value of each of said digit signals; a second counter including a series of flip-flop circuits for determining the sequential position of each of said digit signals; comparing means including first and second series of AND gates connected to said first and second counters, respectively, for sequentially comparing said digit signals with respective digits of said predetermined combination and producing an output whenever a digit signal equals said respective digit; a third counter comprising a series of flip-flop circuits for counting said outputs; an AND gate responsive to said third counter for producing an output signal when said third counter registers a value equal to the number of digits in said predetermined combination; and locking means responsive to said output signal for moving between locked and unlocked positions.