US3300582A - Solid state identification keyer - Google Patents

Description

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DON H/MES ROBERT M. AdG/ISV ATTORNEY United States Patent O 3,300,582 SOLID STATE IDENTIFICATION KEYER Don I. Himes, Nutley, and Robert M. Aughey, Dover,

NJ., assignors to International Telephone and Telegraph Corporation, Nutley, NJ., a corporation of Maryland Filed .lune 10, 1963, Ser. No. 286,528 7 Claims. (Cl. 178-79) This invention relates to keyers and more particularly to a solid state identification keyer.

In certain radio navigation systems, such as Tacan, the radio beacon periodically transmits its identifying call in international Morse code, thus enabling the aircraft to determine which radio beacon it is in contact with. In Tacan, the characters of the code consist of a train of pulse pairs generated at a fixed rate of 1350 cycles per second. A mechanical keyer comprising a coding wheel cam and a switching arrangement cooperating therewith accomplishes the coding. The coding wheel cam consists of peripheral segments which can be adjusted into or out of contact with the switching arrangement as required by the code. However, mechanical keyers such as the one described, have demonstrated rather poor reliability in operation particularly under severe environmental conditions. Further, the time required to change the code is long and the procedure complicated.

It is, therefore, an object of this invention to provide a keyer with substantially improved reliability over the mechanical keyers with improved code changing characteristics.

Another object is to provide a solid state keyer with no moving parts.

A feature of this invention is an automatic keying apparatus comprising clock means to generate a starting pulse and another clock means to generate shift pulses which are coupled to a shift register having a plurality of outputs. A plurality of switching means is coupled to each output of the shift register and the switching means connect the output of the shift register to a dot symbol and dash symbol generating means. The outputs of the shift register are then coupled to dash symbol and dot symbol generating means by virtue of the switching position according to the desired code configuration.

The above-mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawings, in which:

FIGURE 1 is a block diagram of an embodiment of this invention;

FIGURE 2 is a graph of waveforms useful in describing the operation of this invention;

FIGURE 3 is an expanded block diagram of this invention; and

FIGURE 4 is a block diagram of the magnetic shift register used in this invention.

This invention is based on a completely solid state device with no moving parts and is designed to operate continuously in any ambient temperature from -55 C. to |100 C. In addition, the code can be changed in less than one minute; and no adjustments are required before or after the code is changed. Referring now to FIG- URE 1, the basic unit of the keyer of this invention is a 21 bit magnetic core shift register and switching network 1 with serial input and parallel output. The shift or clock rate of the register 1 is determined by a .250 second multivibrator or clock 2. This clock pulse rate is required because a Morse code dot length is .125 second and a dot is always followed by .125 second space. Similarly, a Morse code dash is .375 second and is always followed by a .125 second space. This specified spacing very con- ICC veniently fits the .250 second clock rate for the keyer. The output of the clock 2 is fed via an inhibit gate 3 to trigger a two microsecond, one shot multivibrator 4 which generates a shift pulse. The output of the two microsecond, one shot multivibrator 4 is fed to a core driver S which has suicient capacity to drive the cores of the magnetic shift register in the magnetic shift register and switching network 1. It is required that a series of four Morse code characters (3 letters and 1 number) be keyed once every 3() seconds. The 30 second timing interval is generated by a 30 second multivibrator 6 whose outputs set a flip-flop once every 30 seconds. The output of this flip-flop is gated via an AND gate 7 to an initial pulse gate 8 with a pulse from the clocking circuit of clock 2 to assure proper timing of the 1 insertion in the first core of the register. The output of the initial pulse gate 8 triggers a 15 microsecond, one shot multivibrator or initial pulse generator 9 which is used to inseit a l in the first core of the register. This output is also used to reset the initial pulse gate 8 by way of gate 7. The l in the first core is now shifted serially down the magnetic core register and out of the 21st core. As will be shown later, each of the 21 core parallel outputs is connected via an OR gate to the arms of 2l single pole, double throw switches, the outputs of which are connected to a dot line 10 or a dash line 11. Each switch can be used to generate either a dot, a dash or a space making a total of 21 combinations. The dot line 10 triggers a dot generator 12 which is a .125 second one shot multivibrator which generates the specified dot timing and this output is fed via a nor gate 13 to the keyer output which may be a transistor switch. The dash line 11 is identical to the dot line except that due to the .375 second timing of the dash, the clock shift pulse must be inhibited during the dash interval. This is accomplished by feeding the output of the .375 second multivibrator dash generator via an RC delay (not shown) to the inhibit gate 3 in the clocking circuit. It is apparent that the number of cores in the magnetic shift register can be increased to any desired code length or that the clock rate can be increased to any desired speed.

Referring now to FIGURE 3, the clock generator 2 is composed of a bistable flip-flop multivibrator and a unijunction transistor triggering circuit. This combination provides once each 250 milliseconds, a square wave of millisecond duration. The timing of this circuit can be adjusted by a variable resistance (not shown). This clock output is inverted and fed to one input of the inhibit gate 3. The other input to the inhibit gate 3 receives the inverted and delayed output from the dash generator 11 by way of a delay circuit 15. The delay input to the inhibit gate 3 permits an inhibit gate output during the generation of a dot and at the beginning of the generation of a dash. It inhibits an output during the remainder of the generation of the dash. Since the output of the inhibit gate is used in the generation of the shift pulse and the suppression pulse, these pulses are supplied to the magnetic shift register 14 at the clock rate except during the generation of a dash which insures that the next shift register output is delayed until the dash has been generated. The inhibit gate output triggers the shift pulse generator 4 which is a monostable multivibrator that provides a retimed and reshaped output consisting of a train of essentially square pulses of approximately 5 mircroseconds in duration. These pulses occur at a 250 millisecond rate except when inhibited by the output from the delay circuit 15. The output of the shift pulse generator 4 is supplied to both a shift pulse inverter 16 and to the core driver 5 Where it is amplified, inverted and passed to the magnetic shift register 14. The output from the first stage of the core driver 5 is reshaped, am-

plified and inverted in the suppression pulse generator 20 and the output of the suppression pulse generator 20V is also passed to the magnetic shift register 14.

The multivibrator 6 is triggered by a unijunction transistor circuit (not shown), the time constant of which is determined by a circuit that is adjustable. It provides an output pulse of 15 seconds duration once each 30 seconds. This output is used to trigger the gate control 7 which provides an output once each 30 seconds that is fed to the initial pulse gate 8. The initial pulse gate 8 passes the gate control 7 signal to the initial pulse generator 9 unless it is in coincidence with the inverted shift pulse output. If the two pulses are in coincidence, the output of the initial pulse gate 8 is delayed for the duration of the initial pulse microseconds), after which time a pulse is passed to the initial pulse generator 9. The initial pulse gate 8 is required in order to insure that the initial pulse and shift pulse do not occur simultaneously in the magnetic shift register causing a possible cancellation of input signals and a lack of output. The initial pulse generator 9 is a one shot multivibrator which provides an output pulse of microsecond duration once each 30 seconds. The initial pulse is supplied to the first core of the magnetic shift register and is also used as a feedback via line 21 to turn off the output of the gate control 7. Since the 30 second generator 6 produces one pulse of l5 second duration each 30 seconds, the gate control 7 ip-op circuitry is required in order to reduce the pulse duration to approximately 50 microseconds. This insures that only one initial pulse is generated in each 30 second period. If the 15 second pulse output of generator 6 were permitted to pass directly to the initial pulse gate 8, the initial pulses would be generated at the clock rate during the 15 second pulse duration of the 30 second generator period.

It is now seen that the 30 second generator 6 through the gate control flip-tiop 7, the initial pulse gate 8 and the initial pulse generator 9 provides the initial pulse to the magnetic shift register 14. The clock generator 2 through the inhibit gate 3, shift pulse generator 4 and core driver 5 provides both the shift pulse and the suppression pulse to the magnetic shift register 14. The shift pulse reacts with the initial pulse and the magnetic properties of the cores in the magnetic shift register to provide consecutive outputs at the 1 through 21 switches shown in FIGURE 4. The suppression pulse insures the transfer of the output of one core to the input of the next core. The delay circuit insures that a dash output is completed before the next output is generated. The initial pulse gate 8 insures that the initial pulse and the shift pulse do not occur simultaneously. This eliminates the possibility of a cancellation of input signals to the cores and the consequent lack of output from the cores.

In FIGURE 4, there is shown the magnetic shift register 14 and switching network 25 of the keyer of this invention. The initial pulse from the initial pulse generator 9, the shift pulses at the clock rate from the core driver 5, and the suppression pulses at the clock rate from the suppression pulse generator are supplied to the magnetic shift register 14. The outputs of the magnetic shift register are shown as numbered A1 to A21, inclusive. These outputs are fed respectively to diode gates 26 and the output of each diode gate 26 is fed to the center connection 27 of a single pole double throw switch 28. There is one switch for each diode gate 26 and for each output of the magnetic shift register 14. One side of each switch 28 is connected to a dot bus 30 and the other side of the switch is connected to a dash bus 31. As outputs appear consecutively at the magnetic shift register output A1 through A21, the signal is passed to either the dot bus or to the dash bus depending upon the position of the switch 28 associated with the particular magnetic shift register output. The dot bus is connected to the input of a dot buffer amplifier 32 and the dash bus is connected to the input of a dash buffer amplifier 33. Assuming an output to the dot bus, the dot buffer amplifier 32 serves to amplify the signal received from the magnetic shift register 14. It provides a negative trigger pulse which turns on the dot generator 35. The dot generator 35 consists of a monostable multivibrator circuit and a unijunction transistor trigger circuit (not shown in detail). The negative trigger from the dot buffer amplifier 32 turns on the dot generator monostable multivibrator causing an output which as well as being applied to one input of the keyer gate 40 is also used to initiate the charging sequence within the circuitry associated with the unijunction transistor. After a prescribed time interval (0.125 second) has passed the unijunction transistor fires providing a pulse which turns on the off side of the monostable dot multivibrator thereby cutting off the circuit output.

A magnetic shift register output to the dash bus 31 causes the dash buffer amplifier 33 to trigger the dash monostable multivibrator generator 11 providing an output. The unijunction timing circuit (not shown) of the dash generator provides a time constant of approximately 0.375 second. The functioning of the circuitry is the same as for the dot generator with the exception of the time constant. In addition to supplying an output to one input of the keyer gate 40, the dash generator also supplies an input to the delay circuit 15 which delays and inverts the dash output for use as an input to the inhibit gate 3which was described above. The keyer gate 40 provides isolation for the dot and dash outputs and passes them to the solid state switch 41.. The output of the switch is then fed to the beacon transmitter.

While we have described above the principles of our invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of our invention as set forth in the objects thereof and in the accompanying claims.

We claim:

1. An automatic keying apparatus comprising:

first clock means to generate starting pulses;

second clock `means to generate shift pulses;

a shift register having a plurality of outputs;

first coupling means coupling the outputs of said first clock :means and said second clock means t0 said shift register;

a plurality of switching means adapted to be set according to a preselected code;

second coupling means coupling each said output of said shift register to a corresponding one of said plurality of switching means; dash symbol generating means; dot symbol generating means; said first coupling means including an inhibiting means coupled between said second clock means and said shift register and responsive to signals from said dash generator for inhibiting the application of shift pulses from said second clock means to said shift register during the generation of a dash symbol; and

third coupling means coupling the outputs of each of said switching means to said dash symbol generating means or to said dot symbol generating means according lto said preselected code.

2. An automatic keying apparatus according to claim 1 wherein said first clock means comprises:

a first multivibrator generating a pulse at the repetition rate of said preselected coded message,

a gate control,

an initial pulse gate,

a lbistable multivibrator coupling said first multivibrator to said initial pulse gate,

an initial pulse generator, and

means coupling said initial pulse gate to said initial pulse generator.

3. An automatic keying apparatus according to claim 2, wherein said second clock means comprises:

a clock generator,

a shift pulse generator,

an inhibit gate coupling said clock generator to said shift pulse generator,

a shift pulse inventer,

a core driver,

means coupling the output of said shift pulse generator to said shift pulse inverter and said core driver,

a suppression pulse generator, and

means coupling the output of said core driver to said suppression pulse generator.

4. An automatic keying apparatus according to claim 3 further comprising means coupling the output of said shift pulse inverter to said initial pulse gate whereby no output from said initial pulse gate occurs if there is a coincidence in time of the outputs of said shift pulse inverter and said gate control bistable multivibrator.

5. An automatic keying apparatus according to claim 4 wherein said dash generating means comprises:

a dash generator, and

a dash buffer coupling the dash output of said magnetic shift register to said dash generator.

6. An automatic keying apparatus according to claim 5 wherein said dot generating means comprises:

a dot generator, and

References Cited by the Examiner UNITED STATES PATENTS Dorfman 178-79 Lee 178-79 Zahner 178-79 Schierhorst 178-79 NEIL C. READ, Primary Examiner.

ROBERT H. ROSE, Examiner.

A. J. DUNN, T. A. ROBINSON, Assistant Examiners.

Claims (1)

1. AN AUTOMATIC KEYING APPARATUS COMPRISING: FIRST CLOCK MEANS TO GENERATE STARTING PULSES; SECOND CLOCK MEANS TO GENERATE SHIFT PULSES; A SHIFT REGISTER HAVING A PLURALITY OF OUTPUTS; FIRST COUPLING MEANS COUPLING THE OUTPUTS OF SAID FIRST CLOCK MEANS AND SAID SECOND CLOCK MEANS TO SAID SHIFT REGISTER; A PLURALITY OF SWITCHING MEANS ADAPTED TO BE SET ACCORD ING TO A PRESELECTED CODE; SECOND COUPLING MEANS COUPLING EACH SAID OUTPUT OF SAID SHIFT REGISTER TO A CORRESPONDING ONE OF SAID PLURALITY OF SWITCHING MEANS; DASH SYMBOL GENERATING MEANS; DOT SYMBOL GENERATING MEANS; SAID FIRST COUPLING MEANS INCLUDING AN INHIBITING MEANS COUPLED BETWEEN SAID SECOND CLOCK MEANS AND SAID

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