US3343119A

US3343119A - Auxiliary plugboard control panel

Info

Publication number: US3343119A
Application number: US445331A
Authority: US
Inventors: Donald O Neddenriep
Original assignee: Sperry Rand Corp
Current assignee: Sperry Corp
Priority date: 1965-04-05
Filing date: 1965-04-05
Publication date: 1967-09-19
Anticipated expiration: 1984-09-19

Description

P 1967 D. o. NEDDENRIEP 3,343,119

I AUXILIARY PLUGBOARD CONTROL PANEL Filed April 5, 1965 FIG. 1

31 m 26 30 55 l 35 F|G.'2 I I 1 g -11 54 25 i i? i INVENTOR DONALD 0. NEDDENRIEP ATTORNEY United States Patent M 3,343,119 AUXILIARY PLUGBOARD CONTROL PANEL Donald 0. Nedd-enriep, Maple Glen, Pa., assignor to Sperry Rand Corporation, New York, N.Y., a corporation of Delaware Filed Apr. 5, 1965, Ser. No. 445,331 5 Claims. (Cl. 339-18) ABSTRACT OF THE DISCLOSURE The present device provides a means to selectively obtain information from the memory means of a data processor that employs a plugboard control device, without having to relocate, or replug, the plug wires normally used with such a data processor, when seeking information at a change of address in the memory.

This invention relates to plugboard type control panels and more particularly to a second level switching means which operates in conjunction with a first level or principal plugboard device.

In certain plugboard controlled data processing systems, the addresses of information words, which can be held in the memory means thereof, are designated on the plugboard control panel. In such data processing systems when the data storage locations of the memory are arranged according to rows and columns or according to X and Y coordinates, the address designations on the plugboard device accordingly are designated as the most significant row and column positions and the least significant row and column positions. Very often because the address designations are available on a plugboard control device the system can handle a variable length word, although obviously other system requisites are necessary to handle variable length words.

When in the use of data processing system of the type described above, it becomes necessary to repeatedly change the address of the information being handled, it can be done in a number of ways. Assuming that there are a suflicient number of selectors in the machine, the system can be wired on the control panel to select particular selectors which will enable the proper program steps to choose the various address locations which are necessary for any particular operation. As an alternative if there is an insufficient number of selectors to handle all the possibilities for any particular data processing operation, then a number of different control panels may be wired.

The price that is paid in either of the foregoing alternatives is that the additional selectors become costly and possibly circuitry-wise impossible. In a similar manner the additional number of plugboards become costly and in addition present a storage problem.

The present invention provides a means which allows the operator to easily change the desired addresses but which works in conjunction with signal collector devices so that a number of addresses may be set up at any particular time.

Accordingly it is an object of the present invention to provide an improved plugboard control panel arrangement.

It is a further object of the present invention to provide an improved plugboard control panel arrangement which will enable the operator to set up a plurality of memory addresses for transferring information within a data processing system in compliance with the use of a particular set of cards.

In accordance with a feature of the present invention a secondary switching means is mounted on a principal 3,343,119 Patented Sept. 19, 1967 plugboard whereby the control features of the plugboard are readily switched.

In accordance with another feature of the present invention a plurality of control positions are provided to effect similar controls in general but which are selectively chosen to effect different controls in particular.

The above mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawings wherein:

FIGURE 1 is a top view of the plugboard arrangement including a cutaway to show the relationship between the address plug hubs of the primary level control panel and the second level control panel;

FIGURE 2 is a side view showing the wiring arrangement between the second level member and the primary control panel.

The present plugboard arrangement finds great use with the Univac Card Controlled Device which is a device that handles cards in both a collating and a sorting principal fashion. In addition the Univac Card Controlled data processes both information from said cards (which information may be transmitted to some auxiliary data processor) and information received from some auxiliary data processor. In the normal collating operation, it is very often customary to merge two decks of cards and to sequence check the fields of merger as each of the decks is processed through its own read station and transport mechanism. Hence, basically there are three facets to a collating operation, although there may be more. Accordingly, the present invention provides for handling three sets of addresses but as will be perfectly obvious, the device might handle many addresses by simply expanding it.

Examine FIGURE 1 which shows the plan, or top, view of the pegboard arrangement with portions cut away to show the relationship between the primary plugboard and the secondary level plugboard. In FIGURE 1 there are no plug wires shown connecting the various plug hubs for purposes of simple explanation. However, it is to be understood that such plug wires will he used when the plugboard control panel is in operation.

In FIGURE 1 there is shown the secondary level switch board 11 which is mounted on the principal plugboard 13 by virtue of four

supports

15, 16, 1 7 and 18. (The fourth support 18 being located at the upper left hand cutaway section of secondary plugboard 11.) Actually the secondary level pugboard 11 is hinged on the

supports

15 and 16 and is able to move away from the upper supports 17 and 18 (the support not shown in FIGURE 1) in order to enable the operator to get at the rear side of the secondary level plugboard. The cover means 19 fits over the plugboard after the primary plugboard has been wired and leaves simply a secondary plugboard exposed. The principal plugboard 13 is designed to fit into a frame which meshes the contacts thereof with the controls on the data processor. The processing circuitry within the data processor is connected to the contacts into which the plugboard 13 is meshed.

The upper cutaway of FIGURE 1 is cut into the secondary level plugboard 1-1 as well as the cover 19 and shows one of the step change plug hubs, a pair of the step plug hubs 21, five of the operand 1 plug hubs, five of the operand 2 plug hubs, and some collector plug hubs. A plug hub as described herein is the aperture in the control panel into which fits a control wire contact plug. Actually there are many change plug hubs and many step plug hubs, many operand 1 and operand 2 plug hubs which are not shown but are located under the cover 19. When the system, with which the present invention is employed, normally operates, the program sign-a1 from a previous step is wired into the change plug hub which causes the program to move to the step of the program represented by the change plug hub. A plug wire from the step plug hub 21 would be wired to some other change plug hub to advance the program.

While the system is operating on the step represented by the step plug hub 21, a wire from operand 1 would be wired to a collector such as collector plug hub 24. Another wire from the selector output hub 23 would be connected to possibly the secondary level control plug hub 25 shown in phantom. This last mentioned connection would be located at the rearward, or lower, side of the secondary level plug board 11. As can be seen in phantom, the plug hub 25 of the secondary level plugboard is connected to a strap which runs horizontal and is connected to each of the external plug hubs such as plug hubs 26. In a similar manner (although the strap connections are not shown in order to eliminate confusion in the drawing), the under plug hubs 28 are connected by straps in common with the other rows of external plug hubs which are counterparts of the plug hubs 26.

It will also be noted that there is a row of under plug hubs that connect by straps in common to columns of external plug hubs. For instance, the under plug hub 30 connects with the external column of plug hubs 29. In a similar manner, each of the under plug hubs 33 in the row lying to the right of 30 connects via a vertical strap to a column of plug hubs which are the counterparts of the plug hubs 29.

Now the vertical straps that connect the column plug hubs in common are insulated from the horizontal straps that connect the row external plug hubs in common, and these horizontal and vertical straps may be joined with one another by inserting a connector pin through the common plug hu'bs of the straps, thereby providing a short circuit between the straps. For instance, a pin connector 31 through the first row and column external plug hub 26 (FIG. 2) would connect the under plug hub 25 to the under plug hub 30.

The under plug hubs 33 are connected to the most significant row positions of the memory address. In the lower breakaway 34 of FIGURE 1 the first level plugboard row and column plug hubs can be seen and these plug hubs are wired internally to a transfer register which selects the particular location in memory to which information is transferred or from which information is extracted. While only four of the address positions on the primary plugboard are shown for the sake of simplicity, it should be understood that the second level plugboard device has as many plug hub positions as there are in the principal plugboard. It will be noted in the lower breakaway 34 that the upper set of plug hubs is labeled Row and the lower set is labeled Column. In the same area of the plugboard, but not shown, there are labels MSL standing for most significant location and LSL standing for least significant location. The least significant level addresses are found to the right of the section shown by the cutaway 34. v

The most significant location row of plug hubs 33 of the secondary plugboard are connected to the MSLR plug hubs of the principal plugboard, while the most significant location columns 35 of the second level plugboard are connected to the MSLC plug hubs of the primary plugboard.

In a similar fashion, the under

plug hubs

37 and 38 are connected to output plug hubs of collectors such as output plug hub 23, while the under

plug hubs

43 and 47 are connected to the least significant location row and column plug hubs according to their proper designation. Now the foregoing described arrangement enables the operator to simply locate the pins in the second level plugboard so that when the machine requires operand 1 from a certain location, its address may be simply designated by locating the pins in the upper three rows and operand 2 may be located by inserting pins in the lower three rows of any section. The step which would use these operands is wired through a selector to the proper row of under plug hubs (such as one of the plug hubs 28).

FIGURE 2 is a side view showing the principal plugboard 13 with the secondary level plugboard 11 mounted thereon by virtue of the

supports

15 and 18. The common external plug hub 26 with the pin 31 therein enables the strap 54 to be connected to the strap 55, and hence a signal being transmitted from the output plug hub of a selector along line 56 would pass through the under plug hub 25, along the strap 54, through the pin 31, along the strap 55 along the line 57 into an address plug hub 58 of the primary plugboard 13. In FIGURE 2 only three pins are shown connected into the board, in order to keep the drawing clear. However, it is to be understood that actually there will be pins in each of the rows and in some particular columns thereof so that these pins will enable the user of the present invention to readily select the addresses.

While I have described above the principles of my invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of my invention as set forth in the objects thereof and the accompanying claims.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A plugboard device to control a card-handling, data processor which has a memory means whose memory 10- cations are arranged according to rows and columns, comprising in combination:

(a) principal plugboard means having a plurality of aperture means therein to receive jack-like connectors of plugboard wires;

(b) said principal plugboard means constructed to fit with matching connectors on said card-handling, data processor;

(c) certain of said aperture means having means which designate them as memory address apertures and thus cause them to be used to select information words which are stored in said memory locations of said data processor, each of said information words in memory capable of being addressed by a four point address designation as follows, most significant column, most significant row, least significant column, and least significant row;

(d) certain others of said aperture means having means which group them as collector apertures and which further designate them as input and output collector apertures said aperture means enable an address selection signal to enter said input collector apertures and then be transmitted from at least one of said output collector apertures;

(e) second level plugboard means having first groups and second groups of apertures therein, means externally mounting said second level plugboard means on said principal plugboard means, each of said first groups of apertures intersecting each of said second groups of apertures at a different common aperture, each one of a plurality of said collector output apertures being respectively connected to a diflerent one of said first groups of apertures of said second level plugboard means and each of said memory address apertures being respectively connected to a different one of said second groups of apertures of said secand level plugboard means; and

(f) a plurality of connector pin means to fit into said first and second group of apertures of said second level plugboard means to connect particular ones of said collector device output apertures with particular ones of said memory address apertures by virtue of installing a proper number of said pins in said common apertures thereby providing a simple external means of changing the addresses of information to be extracted from or inserted into the memory of said card-handling, data processor.

2. A plugboard device to control a card-handling, data processor which has a memory means whose memory cations are addressable, comprising in combination:

(a) a principal plugboard means having a plurality of aperture means therein to receive jack-like connectors of plugboard Wires;

(c) certain of said aperture means having means which designate them as memory address apertures and thus cause them to be used to select information Words which are stored in said memory locations;

((1) certain others of said aperture means having means which designate them as controlled signal apertures and which provide output control signals in response to input signals;

(e) second level plugboard means having first groups and second groups of apertures therein, means externally mounting said second level plugboard means upon said principal plugboard means, each of said first groups of apertures intersecting each of said second groups of apertures at a different common aperture, means respectively connecting each one of said apertures of said first group of apertures of said second level plugboard means to a ditferent one of said control signal apertures and means respectively connecting each of said memory address apertures to a difierent one of said second groups of apertures of said second level plugboard means;

(f) a plurality of connector pin means to fit into said common apertures to connect particular ones of said control signal apertures with particular ones of said memory address apertures thereby providing a simple external means of changing the addresses of information to be extracted from or inserted into said memory of said card-handling, data processor.

3. A plugboard device to control a card-handling, data processor which has a memory means whose memory locations are arranged according to 'rows and columns, comprising in combination:

('b) said principal plugboard means constructed to fit matching connectors on said card-handling, data processor;

(c) certain of said aperture means having means which designate them as memory address apertures and thus cause them to he used to select information Words which are stored in said memory of said data processor, each of said information words in memory being capable of being addressed by a four point address designation as follows, most significant column, most significant row, least significant column'and least significant row;

(d) certain others of said aperture means having means which designate them as control signal apertures and which provide output control signals in response to input signals thereto;

(e) second level plugboard means having first groups and second groups of apertures therein, means externally mounting said second level plugboard means on said principal plugboard means, means which designate said first groups of apertures as representing the rows of said memory and said second groups of apertures as representing the columns of said memory, means electrically connecting each aperture in one of said first groups to each other aperture in that row and means electrically connecting each aperture in one of said second groups with each other aperture in that column, each of said row apertures formed to provide a different common aperture with each of said column apertures;

(f) each row aperture of said second level plugboard means being respectively connected to a different one of said control signal apertures to receive an output signal therefrom and each of said memory address apertures being respectively connected to a different one of said column aperture of said second level plugboard means;

(g) a plurality of connector 'pin means to fit into said common apertures to connect particular ones of said control signal apertures with particular ones of said memory address apertures thereby providing a simple external means for changing the addresses of information to be extracted from or inserted into said memory of said card-handling data processor.

4. A plugboard device according to claim 3 wherein said control signal apertures comprise groups of connector apertures each of which group has an input aperture and a plurality of output apertures to enable an address selection signal to enter said input collector aperture and then be transmitted from at least one of said output collector apertures to predetermine the ones of said rows of apertures of said second level plugboard.

5. A plugboard device according to claim 3 wherein said second level plugboard means is rotatably secured to said principal plugboard means thereby enabling said second level plugboard means to the rotated away from said principal plugboard means in order to arrange connector means on the side of said second level plugboard means away from said connector pin means.

References Cited UNITED STATES PATENTS 2,874,313 2/1959 Githens 339-18 X 2,901,736 8/1959 Sylvester 339-17 X 2,926,340 2/1960 Blain et a1 339-252 X 2,963,626 12/1960 Du Val et al. 339-18 X 2,967,285 1/1961 'Freitas 339-18 3,045,077 7/1962 Knanishu 339-18 3,065,439 11/1962 Krause 339-18 3,085,220 4/1963 'Sitz 339-18 3,175,179 3/1965 Trump 339-18 3,241,000 3/1966 Roslyn 339-18 X 3,274,327 9/1966 Schnitzler 339-18 X MARVIN A. CHAMPION, Primary Examiner.

P. TEITELBAUM, Assistant Examiner.

Claims

2. A PLUGBOARD DEVICE TO CONTROL A CARD-HANDLING, DATA PROCESSOR WHICH HAS A MEMORY MEANS WHOSE MEMORY LOCATIONS ARE ADDRESSABLE, COMPRISING IN COMBINATION: (A) A PRINCIPAL PLUGBOARD MEANS HAVING A PLURALTIY OF APERTURE MEANS THEREIN TO RECEIVE JACK-LIKE CONNECTORS OF PLUGBOARD WIRES; (B) SAID PRINCIPAL PLUGBOARD MEANS CONSTRUCTED TO FIT WITH MATCHING CONNECTORS ON SAID CARD-HANDLING, DATA PROCESSOR; (C) CERTAIN OF SAID APERTURE MEANS HAVING MEANS WHICH DESIGNATE THEM AS MEMORY APERTURES AND THUS CAUSE THEM TO BE USED TO SELECT INFORMATION WORDS WHICH ARE STORED IN SAID MEMORY LOCATIONS; (D) CERTAIN OTHERS OF SAID APERTURE MEANS HAVING MEANS WHICH DESIGNATE THEM AS CONTROLLED SIGNAL APERTURES AND WHICH PROVIDE OUTPUT CONTROL SIGNALS IN RESPONSE TO INPUT SIGNALS; (E) SECOND LEVEL PLUGBOARD MEANS HAVING FIRST GROUP AND SECOND GROUPS OF APERTURES THEREIN, MEANS EXTERNALLY MOUNTING SAID SECOND LEVEL PLUGBOARD MEANS UPON SAID PRINCIPAL PLUGBOARD MEANS, EACH OF SAID FIRST GROUPS OF APERTURES INTERSECTING EACH OF SAID SECOND GROUPS OF APERTURES AT A DIFFERENT COMMON APERTURE, MEANS RESPECTIVELY CONNECTING EACH ONE OF SAID APERTURES OF SAID FIRST GROUP OF APERTURES OF SAID SECOND LEVEL PLUGBOARD MEANS TO A DIFFERENT ONE OF SAID CONTROL SIGNAL APERTURES AND MEANS RESPECTIVELY CONNECTING EACH OF SAID MEMORY ADDRESS APERTURES TO A DIFFERENT ONE OF SAID SECOND GROUPS OF APERTURES OF SAID SECOND LEVEL PLUGBOARD MEANS; (F) A PLURALITY OF CONNECTOR PIN MENS TO FIT INTO SAID COMMON APERTURES TO CONNECT PARTICULAR ONE''S OF SAID CONTROL SIGNAL APERTURES WITH PARTICULAR ONE''S OF SAID MEMORY ADDRESS APERTURES THEREBY PROVIDING A SIMPLE EXTERNAL MEANS OF CHANGING THE ADDRESSES OF INFORMATION TO BE EXTRACTED FROM OR INSERTED INTO SAID MEMORY OF SAID CARD-HANDLING, DATA PROCESSOR.