US20210233890A1

US20210233890A1 - Packaging structures

Info

Publication number: US20210233890A1
Application number: US17/232,786
Authority: US
Inventors: Lei Shi
Original assignee: Tongfu Microelectronics Co Ltd
Current assignee: Tongfu Microelectronics Co Ltd
Priority date: 2018-07-19
Filing date: 2021-04-16
Publication date: 2021-07-29
Also published as: CN109037082A; CN109037082B; US10998289B2; US20200027858A1

Abstract

Packaging structure includes a substrate; a bonding layer on the substrate; and an improvement layer on the bonding layer. The improvement layer contains openings exposing surface portions of the bonding layer at bottoms of the openings. Chips are located in the openings. The chips include functional surfaces that bond to the bonding layer, and top surfaces of the chips are lower than or flush with a top surface of the improvement layer. Another packaging structure includes chips and an improvement layer. The chips are interspersed in the improvement layer. Each chip includes a functional surface coplanar with a first surface of the improvement layer, and another surface lower than or flush with a second surface of the improvement layer. A gap is formed between each sidewall of the chips and the improvement layer. An encapsulation layer is formed in the gap between each chip and the improvement layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 16/393,632, filed on Apr. 24, 2019, which claims priority to Chinese Patent Application No. 201810796603.5, filed on Jul. 19, 2018, the entire content of which is hereby incorporated by reference.

FIELD OF THE INVENTION

The present disclosure generally relates to the field of packaging and, more particularly, relates to semiconductor structures including packaging structures.

BACKGROUND

With rapid development of integrated circuit manufacturing industry, requirements for packaging technologies of integrated circuits are increasing. Existing packaging technologies mainly include ball grid array packaging (BGA), chip-size packaging (CSP), wafer-level packaging (WLP), three-dimensional packaging (3D), and system in package (SiP). Among them, the wafer-level packaging (WLP) is gradually adopted by most semiconductor manufacturers due to its advantages. All or most of processing steps of the wafer-level packaging (WLP) may be completed on a silicon wafer whose pre-processes have been completed, and finally the wafer is directly cut into independent devices.
The wafer-level packaging has the following advantages. The wafer-level packaging may have a high packaging efficiency. Multiple wafers may be processed at a same time. The wafer-level packaging may have advantages of flip-chip packaging. That is, packaging structures formed by the wafer-level packaging may be light, thin, short, and small. Compared with previous processing steps, the wafer-level packaging only adds two processing steps including pin rewiring (RDL) and bump making, and all other processing steps are conventional processing steps. Further, the wafer-level packaging may reduce multiple tests in conventional packaging. Accordingly, major IC packaging companies in the world invested in the research, development and production of the wafer-level packaging.
However, many problems of existing wafer-level packaging technologies are still to be solved, and thus performances of packaging structures formed by existing wafer-level packaging technologies may be still undesirable. The disclosed methods and structures are directed to solve one or more problems set forth above and other problems in the art.

BRIEF SUMMARY OF THE DISCLOSURE

One aspect of the present disclosure provides a packaging structure. The packaging structure includes a substrate; a bonding layer on the substrate; and an improvement layer on the bonding layer. The improvement layer contains openings exposing surface portions of the bonding layer at bottoms of the openings. Chips are located in the openings. The chips include functional surfaces that bond to the bonding layer, and top surfaces of the chips are lower than or flush with a top surface of the improvement layer.
Another aspect of the present disclosure provides a packaging structure. The packaging structure includes chips and an improvement layer. The chips are interspersed in the improvement layer. Each chip includes a functional surface coplanar with a first surface of the improvement layer, and another surface lower than or flush with a second surface of the improvement layer. A gap is formed between each sidewall of the chips and the improvement layer. An encapsulation layer is formed in the gap between each chip and the improvement layer.
Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present disclosure.

FIG. 1 illustrates a packaging structure;

FIG. 2 illustrates an exemplary forming process of a packaging structure consistent with the disclosed embodiments;

FIGS. 3 to 14 illustrate structures corresponding to certain stages of an exemplary forming process of a packaging structure consistent with the disclosed embodiments;

FIG. 14 illustrates another exemplary packaging structure consistent with the disclosed embodiments;

FIGS. 15 to 18 illustrate structures corresponding to certain stages of another exemplary forming process of a packaging structure consistent with the disclosed embodiments.

DETAILED DESCRIPTION

To make the objectives, technical solutions and advantages of the present invention more clear and explicit, the present invention is described in further detail with accompanying drawings and embodiments. It should be understood that the specific exemplary embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.
Reference will now be made in detail to exemplary embodiments of the present invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
FIG. 1 illustrates a packaging structure. As shown in FIG. 1, a substrate 100 is provided, and a bonding layer 101 is disposed on a surface of the substrate 100. Chips 102 are provided, and each of the chips 102 includes a functional surface 1. Each of the chips 102 has pads 102 a at the functional surface 1. Each of the chips 102 is mounted on the substrate 100 through the bonding layer 101 such that the functional surface 1 is bonded to the bonding layer 101.
In the packaging structure shown in FIG. 1, a material of the chips 102 includes silicon that has a small thermal expansion coefficient. A thermal expansion coefficient of a material of the bonding layer 101 is much larger than a thermal expansion coefficient of the material of the chips 102. Accordingly, in a subsequent high temperature process, degrees of thermal expansions of the bonding layer 101 and the chips 102 may be different. Thus relative displacements between the chips 102 and the bonding layer 101 may occur, and thus performances of the packaging structure may not be improved.
To solve the above technical problems, the present disclosure provides a method of forming a packaging structure. In the method, an improvement layer is formed on top of the bonding layer, and the improvement layer contains openings. The openings may have a strong ability in defining chip positions. Thus, chips may not be prone to relative displacements and performances of the packaging structure may thus be improved.
FIG. 2 illustrates an exemplary process of forming a packaging structure consistent with the disclosed embodiments; and FIGS. 3 to 14 illustrate structures corresponding to certain stages of an exemplary process of forming a packaging structure consistent with the disclosed embodiments.
As shown in FIG. 2, at the beginning of the forming process, a substrate is provided, and a bonding layer is formed on the substrate (S201). FIG. 3 illustrates a corresponding structure.
As shown in FIG. 3, a substrate 200 is provided, and a bonding layer 201 is disposed on a surface the substrate 200. A material of the substrate 200 includes glass, ceramic, metal, or polymer. A shape of the substrate 200 includes a circle, a rectangle, or a triangle. The bonding layer 201 may make subsequent chips adhere to the surface of the substrate 200.
In one embodiment, a material of the bonding layer 201 is an ultraviolet adhesive. The ultraviolet adhesive may have a high viscosity when it is not irradiated by ultraviolet light. Cross-linking chemical bonds in the ultraviolet adhesive may be broken after being irradiated by ultraviolet light, and the viscosity of the ultraviolet adhesive may thus decrease or disappear. Accordingly, the bonding layer 201 and the substrate 200 may be peeled off in a subsequent process.
In some other embodiments, the material of the bonding layer may include an acrylic pressure sensitive adhesive or an epoxy pressure sensitive adhesive.
A forming process of the bonding layer 201 includes a spin coating process, a spray coating process, a rolling process, a printing process, a non-rotating coating process, a hot pressing process, a vacuum pressing process, or a pressure pressing process.
The material of the bonding layer 201 has a first thermal expansion coefficient, and the first thermal expansion coefficient may be high.
Returning to FIG. 2, after providing the substrate and forming the bonding layer, an improvement film may be disposed on the bonding layer (S202). FIG. 4 illustrates a corresponding structure.
As shown in FIG. 4, an improvement film 202 is disposed on a surface of the bonding layer 201. A material of the improvement film 202 includes a photoresist, and a forming process of the improvement film 202 includes a printing process or a spin coating process.
The improvement film 202 may be used to subsequently form an improvement layer. The improvement film 202 has a second thermal expansion coefficient, and the second thermal expansion coefficient may be high. A difference between the second thermal expansion coefficient and the first thermal expansion coefficient falls within a preset range. Specifically, the preset range may be approximately −50 to 50. Accordingly, relative displacements between the improvement layer 202 and the adhesion layer 201 may not easily occur during subsequent high temperature processes. Further, subsequent openings in the improvement layer may limit displacements of chips. Accordingly, deflection and warpage of the packaging structure may be reduced.
A thickness of the improvement film 202 is in a range of approximately 20 micrometers to 100 micrometers. The improvement film 202 may be used to subsequently form an improvement layer. If the thickness of the improvement film 202 is less than 20 micrometers, a thickness of the improvement layer may be less than 20 micrometers. Accordingly, subsequent chips are partially embedded in openings between the improvement layers. The improvement layer at sidewalls of the openings may have a weak ability in limiting the chips, and the chips may be still prone to relative displacements during subsequent high temperature processes. Accordingly, performances of the package structure may not be improved. If the thickness of the improved film 202 is greater than 100 micrometers, excessive cost of the material of the improvement film 202 may occur, and thus cost saving may not be achieved.
Returning to FIG. 2, after the improvement film is disposed on the bonding layer, the improvement film may be exposed and developed to form an improvement layer (S203). FIG. 5 illustrates a corresponding structure.
Referring to FIG. 5, the improvement film 202 (see FIG. 4) is exposed and developed to form an improvement layer 220, and openings 203 are disposed in the improvement layer 220. Bottoms of the openings 203 expose a top surface of the bonding layer 201.
Since the improvement layer 220 is formed from the improvement film 202, the improvement layer 220 has the second thermal expansion coefficient. The difference between the second thermal expansion coefficient and the first thermal expansion coefficient falls within the preset range. Accordingly, in subsequent high temperature processes, relative displacements between the improvement layer 220 and the adhesion layer 201 may not easily occur.
Moreover, since the improvement film 202 is thick, the openings 203 formed are deep. Accordingly, the improvement layer 220 at the sidewalls of the openings 203 may have a strong ability in limiting subsequent chips, and the chips may be less likely to be relatively displaced. As such, relative displacements between the chips, the improvement layer 220 and the bonding layer 201 may not easily occur, and thus the deflection and warpage of the packaging structure may be reduced.
A thickness of the improvement layer 220 is determined by the thickness of the improvement film 202. Accordingly, the thickness of the improvement layer is in a range of approximately 20 micrometers to 100 micrometers. The thickness of the improvement layer determines a depth of the openings. Accordingly, the depth of the openings is in a range of approximately 20 micrometers to 100 micrometers.
If the depth of the openings 203 is less than approximately 20 micrometers, subsequent chips may be partially embedded in the openings between the improvement layers. The improvement layer at the sidewalls of the openings may have a weak ability in limiting the chips, and the chips may be still prone to relative displacements during subsequent high temperature processes. Accordingly, performances of the package structure may not be improved. If the depth of the openings is larger than approximately 100 micrometers, the improved film 202 may be required to have a large thickness. Consequently excessive cost of the material of the improvement film 202 may occur, and thus cost saving may not be achieved.
Returning to FIG. 2, after the improvement layer is formed, chips 204 may be provided (S204). FIG. 6 illustrates a corresponding structure.
As shown in FIG. 6, chips 204 are provided. The chips 204 include functional surfaces 11, and the functional surfaces 11 are disposed with pads 204 a. The chips 204 are mounted on the substrate 200 such that the functional surfaces 11 are bonded to the bonding layer 201 at bottoms of the openings 203 (see FIG. 5). The top surfaces of the chips 204 are lower than or flush with the surface of the improvement layer 220.
A material of the chips 204 includes silicon, and the chips 204 have a thermal expansion coefficient in a range of approximately 2.2 to 2.4. The pads 204 a may be used to output electrical signals in the chips 204. A thickness of the chips 204 is in a range of approximately 20 micrometers to 100 micrometers.
The chips 204 are mounted on the substrate 200 through the bonding layer 201. Since the top surfaces of the chips 204 are lower than or flush with the surface of the improvement layer 220, the chips 204 may be completely embedded in the openings 203. The improvement layer 220 at the sidewalls of the opening 203 may have a strong ability in limiting positions of the chips 204. Accordingly, the chips 204 is less prone to displacement, and the deflection and warpage of the packaging structure may thus be reduced. As such, the structure shown in FIG. 6 can be more stable for storing, transportation, and/or further processing for “future” use. For example, a packaging process may be performed as desired, based on the structure shown in FIG. 6. FIGS. 7-13 illustrates an exemplary packaging process based on the structure shown in FIG. 6 containing chips 204.
Returning to FIG. 2, after the chips 204 are provided, an encapsulation layer may be formed on a surface of the improvement layer and the top surfaces and sidewalls of the chips (S205). FIG. 7 illustrates a corresponding structure.
As shown in FIG. 7, an encapsulation layer 205 is formed on a surface of the improvement layer 220 and the top surfaces and sidewalls of the chips 204. The encapsulation layer 205 may protect the chips 204 and may serve as a carrier of subsequent processes.
In one embodiment, a material of the encapsulation layer 205 includes epoxy resin. The epoxy resin may have good encapsulation performances and may be easily molded, and thus the epoxy resin may be a preferred material for forming the encapsulation layer 205.
In some other embodiments, the material of the encapsulation layer may be a encapsulation material. The encapsulation material includes polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, and polyvinyl alcohol.
In one embodiment, a forming process of the encapsulation layer 205 includes an injection molding process. In some other embodiments, the forming process of the encapsulation layer may include a transfer molding process or a screen-printing process.
The injection molding process for forming the encapsulation layer 205 includes providing a mold and filling the mold with a encapsulation material, wherein the encapsulation material covers the chips 204. The injection molding process also includes heating and curing the encapsulation material to form the encapsulation layer 205.
In the structure shown in FIG. 7, difference between the thermal expansion coefficient of the material of the chips 204 and the thermal expansion coefficients of the improvement layer 220 and the bonding layer 201 may be large. But, in the process of forming the encapsulation layer 205, since the chips 204 are completely located in the openings 203, the improvement layer 220 at the sidewalls of the openings 203 may limit the relative displacements between the chips 204 and the improvement layer 220 and the adhesion layer 201 during heating and curing processes. Moreover, the difference between the thermal expansion coefficient of the improvement layer 220 and the thermal expansion coefficient of the bonding layer 201 falls within the preset range. Thus, the relative displacement between the improvement layer 220 and the bonding layer 201 may not easily occur during the heating and curing process. As such, the relative displacements between the chip 204, the improvement layer 220 and the bonding layer 201 may not easily occur, and the deflection and warpage of the packaging structure may thus be reduced.
In one embodiment, after the encapsulation layer 205 is formed, the encapsulation layer 205 is not subjected to a thinning treatment. In some other embodiments, after the encapsulation c seal layer is formed, the encapsulation layer may be subjected to a thinning treatment until the top surfaces of the chips are exposed.
Returning to FIG. 2, after the encapsulation layer is formed, the substrate and the bonding layer may be removed to expose the functional surfaces of the chips (S206). FIG. 8 illustrates a corresponding structure.
As shown in FIG. 8, after the encapsulation layer 205 is formed, the substrate 200 (see FIG. 7) and the bonding layer 201 (see FIG. 7) are removed to expose the functional surfaces 11 of the chips 204.
In one embodiment, a material of the bonding layer 201 is an ultraviolet adhesive. A process of removing the substrate 200 (see FIG. 7) and the bonding layer 201 (see FIG. 7) includes irradiation with ultraviolet light. Due to the irradiation with ultraviolet light, adhesiveness of the bonding layer 201 may decrease, and thus the bonding layer 201 and the substrate 200 may be peeled off.
After the substrate 200 (see FIG. 7) and the bonding layer 201 (see FIG. 7) are removed, the functional surface 11 of the chip 204 may be directly exposed. Since a thinning treatment for the encapsulation layer 205 may not be needed for exposing the functional surfaces 11, process complexity may be reduced.
Returning to FIG. 2, after the substrate and the bonding layer are removed, a wiring layer may be formed on the pads (S207). FIG. 9 illustrates a corresponding structure.
Referring to FIG. 9, after the substrate 200 and the bonding layer 201 are removed, a wiring layer 206 is formed on surfaces of the pads 204 a. A material of the wiring layer 206 may be a metal, such as aluminum, copper, tin, nickel, gold or silver. A forming process of the wiring layer 206 includes an evaporation process, a sputtering process, an electroplating process, or a chemical plating process.
A bottom of the wiring layer 206 is electrically connected to tops of the pads 204 a, and a top of the wiring layer 206 is electrically connected to subsequent solder balls.
Returning to FIG. 2, after the wiring layer is formed on the pads, a passivation layer may be formed on a surface of the improvement layer and a sidewall of the wiring layer (S208). FIG. 10 illustrates a corresponding structure.
As shown in FIG. 10, a passivation layer 207 is formed on a surface of the improvement layer 220 and a sidewall of the wiring layer 206. The passivation layer 207 is disposed with solder openings 208 exposing a surface of the wiring layer 206.
A material of the passivation layer 207 includes polyimide, polyparaphenylene benzobisoxazole or photosensitive benzocyclobutene. A forming process of the passivation layer 207 includes a spin coating process or a printing process.
As the passivation layer 207 exposes a portion of the wiring layer 206, solder balls may be electrically connected to the wiring layer 206 in a subsequent process. The solder openings 208 may accommodate solder balls in a subsequent process.
Returning to FIG. 2, after the passivation layer is formed, solder balls may be formed in the solder openings (S209). FIG. 11 illustrates a corresponding structure.
As shown in FIG. 11, solder balls 209 are formed in the solder openings 208 (see FIG. 10). The solder balls 209 include gold tin solder balls, silver-tin solder balls or copper-tin solder balls.
In one embodiment, the solder balls 209 are gold-tin solder balls. A process of forming the gold-tin solder balls includes forming a gold-tin layer in the solder openings 208. After the gold-tin layer is formed, a high temperature reflow process is performed to make the gold-tin layer reflow into a spherical shape, and the gold-tin solder balls are formed after temperature is decreased.
Returning to FIG. 2, after the solder balls are formed, the encapsulation layer may be thinned until the top surfaces of the chips 204 are exposed (S210). FIG. 12 illustrates a corresponding structure.
Referring to FIG. 12, after the solder balls 209 are formed, the encapsulation layer 205 is thinned until the top surfaces of the chips 204 are exposed. Since the chips 204 are completely embedded in the openings 203, when the encapsulation layer 205 is thinned to expose the top surfaces of the chips 204, the encapsulation layer 205 on the top of the improving layer 220 may be completely removed. Accordingly, the improvement layer 220 may be exposed, and the improvement layer 220 may thus be removed in subsequent processes.
Returning to FIG. 2, after the top surfaces of the chips 204 are exposed, the improvement layer may be removed (S211). FIG. 13 illustrates a corresponding structure.
Referring to FIG. 13, after the top surfaces of the chips 204 are exposed, the improvement layer 220 is removed. A process of removing the improvement layer 220 includes one or a combination of a dry etching process and a wet etching process.
Returning to FIG. 2, after the improvement layer is removed, a dicing process may be performed between adjacent chips to form chip structures (S212). FIG. 14 illustrates a corresponding structure.
Referring to FIG. 14, after the improvement layer 220 is removed, a dicing process is performed between adjacent chips 204 to form chip structures 250. Since only the passivation layer 207 is present between adjacent chips 204 after the improvement layer 220 is removed, only the passivation layer 207 is cut in the dicing process.
FIG. 15 illustrates another exemplary packaging structure consistent with the disclosed embodiments. As shown in FIG. 15, after the solder balls 209 are formed, a dicing process is performed to form chip structures 300. It should be noted that the chip structure 300 shown in FIG. 15 is formed from the structure shown in FIG. 11.
In one embodiment, the chip structure 300 does not include the improvement layer 220, and thus a subsequent process of removing the improvement layer 220 is not required. Accordingly, some processing steps may be omitted, and process complexity may thus be reduced.
In one embodiment, after the chip structure 300 is formed, the encapsulation layer 205 is not thinned. In some other embodiments, after the chip structure 300 is formed, the encapsulation layer is thinned until the surface of the chip is exposed.
FIGS. 16 to 18 illustrate structures corresponding to certain stages of another exemplary forming process of a packaging structure.
Referring to FIG. 16, after the solder balls are formed, a dicing process is performed to form chip structures 400. It should be noted that the chip structure 400 shown in FIG. 16 is formed from the structure shown in FIG. 11. In one embodiment, the chip structure 400 includes a portion of the improvement layer 220.
Referring to FIG. 17, after the chip structure 400 is formed, the improvement layer 220 is removed. A process of removing the improvement layer 220 includes one or a combination of a dry etching process and a wet etching process.
Referring to FIG. 18, after the improvement layer 220 is removed, the encapsulation layer 205 is thinned until the top of the chip 204 is exposed.
The present disclosure also provides a packaging structure. Referring to FIG. 6, the packaging structure includes a substrate 200, wherein a bonding layer 201 is disposed on a surface of the substrate 200. The packaging structure also includes an improvement layer 220 disposed on a surface of the bonding layer 201. The improvement layer 220 has openings 203 (see FIG. 5), and bottoms of the openings 203 expose the surface of the bonding layer 201. The packaging structure also includes chips 204 located in the openings 203. The chips 204 includes functional surfaces 11 that adhere to the bonding layer 201. Top surfaces of the chips 204 are lower than or flush with a surface of the improvement layer 220. The bonding layer 201 includes an ultraviolet adhesive, an acrylic pressure sensitive adhesive, or an epoxy pressure sensitive adhesive. A material of the improvement layer 220 includes a photoresist.
As disclosed, the technical solutions of the present disclosure have the following advantages.
In the process of forming a packaging structure provided by the technical solutions of the present invention, the improvement layer contains openings for subsequently accommodating chips. Moreover, the top surfaces of the chips are lower than or flush with the surface of the improvement layer, and thus the chips are completely embedded in the openings. The improvement layer at sidewalls of the openings may limit the chips to be offset, and thus chip offset may not easily occur. Accordingly, the forming process may improve performances of the packaging structure.
The embodiments disclosed herein are exemplary only and not limiting the scope of the present disclosure. Various combinations, alternations, modifications, or equivalents to the technical solutions of the disclosed embodiments can be obvious to those skilled in the art and can be included in the present disclosure. Without departing from the spirit and scope of the invention, such other modifications, equivalents, or improvements to the disclosed embodiments are intended to be encompassed within the scope of the present disclosure.

Claims

What is claimed is:

1. A packaging structure, comprising:

a substrate;

a bonding layer on the substrate;

an improvement layer on the bonding layer, wherein the improvement layer contains openings exposing surface portions of the bonding layer at bottoms of the openings; and

chips located in the openings, wherein the chips include functional surfaces that bond to the bonding layer, and top surfaces of the chips are lower than or flush with a top surface of the improvement layer.

2. The structure according to claim 1, wherein the bonding layer includes an ultraviolet adhesive, an acrylic pressure sensitive adhesive, or an epoxy pressure sensitive adhesive.

3. The structure according to claim 1, wherein the improvement layer is made of a material including a photoresist.

4. The structure according to claim 1, wherein the substrate is made of a material including glass, ceramic, metal, or polymer.

5. The structure according to claim 1, wherein the chips have a thickness in a range of approximately 20 micrometers to 100 micrometers.

6. The structure according to claim 1, wherein the openings have a depth in a range of approximately 20 micrometers to 100 micrometers.

7. The structure according to claim 1, wherein:

a difference between a thermal expansion coefficient of the bonding layer and a thermal expansion coefficient of the improvement layer is within a preset range to prevent a relative displacement between the chips and the bonding layer, and

the preset range is between −50 and 50.

8. A packaging structure, comprising:

chips;

an improvement layer, wherein:

the chips are interspersed in the improvement layer,

each chip includes a functional surface coplanar with a first surface of the improvement layer, and another surface lower than or flush with a second surface of the improvement layer, and

a gap is formed between each sidewall of the chips and the improvement layer; and

an encapsulation layer formed in the gap between each chip and the improvement layer.

9. The structure according to claim 8, further including:

a wiring layer on the functional surface; and

a passivation layer on the wiring layer, wherein the passivation layer includes solder openings that expose surface portions of the wiring layer.

10. The structure according to claim 9, further including:

solder balls in the solder openings.

11. The structure according to claim 10, wherein the solder balls include gold tin-solder balls, silver-tin solder balls or copper-tin solder balls.

12. The structure according to claim 9, further including:

the encapsulation layer exposes the another surface of the chip.

13. The structure according to claim 9, wherein a material of the wiring layer includes a metal, including aluminum, copper, tin, nickel, gold, silver, or a combination thereof.

14. The structure according to claim 9, wherein a material of the passivation layer includes polyimide, polyparaphenylene benzobisoxazole or photosensitive benzocyclobutene.

15. The structure according to claim 8, wherein the bonding layer includes an ultraviolet adhesive, an acrylic pressure sensitive adhesive, or an epoxy pressure sensitive adhesive.

16. The structure according to claim 8, wherein the chips have a thickness in a range of approximately 20 micrometers to 100 micrometers.

17. The structure according to claim 8, wherein the improvement layer has a thickness in a range of approximately 20 micrometers to 100 micrometers.

18. The structure according to claim 8, wherein a portion of the encapsulation layer further covers the another surface of the chips and a surface of the improvement layer.

19. The structure according to claim 8, wherein:

the preset range is between −50 and 50.