US20140299872A1

US20140299872A1 - Heterogeneous intergration of group iii-v or ii-vi materials with silicon or germanium

Info

Publication number: US20140299872A1
Application number: US14/110,139
Authority: US
Inventors: Peter Wilshaw; Kanad Mallik; Doug Jordan; Cornelis de Groot
Original assignee: Oxford University Innovation Ltd
Current assignee: Oxford University Innovation Ltd
Priority date: 2011-04-06
Filing date: 2012-04-04
Publication date: 2014-10-09
Also published as: EP2695186A1; US20150037967A1; WO2012136999A1; US20140291815A1; US9293329B2; EP2695185A1; WO2012136998A1; EP2695184A1; EP2695184B1; WO2012137000A1

Abstract

Substrates for an electronic circuit and device manufacturing methods are disclosed. According to an embodiment, the substrate comprises: a silicon or germanium wafer impregnated with impurities that form one or more deep energy levels within the band gap of the material forming the wafer, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and a device layer formed on a surface of said wafer, said device layer comprising electronically functional components formed in a layer of Periodic Table Group III-V or II-VI material. The wafer may be formed from Cz silicon or Cz germanium, for example.

Description

The present invention relates to a substrate for use in the fabrication of semiconductor devices, particularly high frequency and/or high power semiconductor devices.
There is considerable interest in the integration of compound semiconductor (e.g. III/V and II/VI) devices on silicon substrates. Many compound semiconductors have a direct bandgap and hence can be used to produce photonic devices such as lasers. The integration of compound semiconductor devices on silicon substrates therefore allows photonic devices to be integrated with silicon electronics to produce integrated optoelectronic systems. Many compound semiconductors also have a wide bandgap, which provides a high breakdown voltage and enables device operation at high temperatures, both of which are needed for power electronics applications. The integration of wide bandgap compound semiconductor (e.g. GaN) devices with silicon CMOS electronics would enable integrated power management systems to be produced for a wide range of electronic products. Many compound semiconductors also have a high mobility. The integration of high mobility compound semiconductor devices on silicon substrates would enable even higher speed electronics than is currently possible with CMOS. The use of thin films of compound semiconductor (III-V and II/VI compounds, such as GaAs, GaN etc.) on silicon handle wafers is known for high power, high frequency and optoelectronic architectures, but very high resistivity silicon is preferred.
Using conventional production techniques, it is difficult to avoid the presence of background carriers in silicon wafers, which leads to a reduced resistivity of the wafer. However high resistivity substrates are required for reducing transmission line losses, making high-Q inductors and minimising substrate crosstalk in high frequency applications and monolithic circuits. This degradation in the characteristics effectively prevents the use of silicon wafers for many high frequency devices.
To tackle these problems, several special processes have been described in the prior art for producing high resistivity substrates. These include the so-called float-zone (FZ) method for producing very high purity silicon.
Silicon wafers produced using the float-zone method can have resistivities of the order of 10 kΩcm or more, but their maximum diameter is typically limited to about 150 mm. This is unsuitable for modern VLSI technology where the standard wafer diameter is 300 mm. The other major problem of float zone wafers is the absence of oxygen, which internally getters metallic impurities in the substrate during device processing and improves reliability. Thus, float-zone substrates tend to have less reliable properties. There are also attempts to make high resistivity Cz silicon but these are presently limited to around 1 kΩcmm and are more expensive than conventional Cz silicon wafers.
Semicond. Sci. Technol. 18 (2003) 517-524 describes the use of deep level impurities to obtain “semi-insulating” (high resistivity) Czochralski (Cz) silicon. This academic study investigates values of deep impurity levels and their concentrations that are suitable for raising the resistivity of the silicon to near intrinsic levels. No details regarding commercial application of the technology are disclosed. Furthermore, the skilled person would be strongly disinclined to use the kind of impurities that act to increase the resistivity of silicon anywhere in a semiconductor manufacturing facility because of the risk of contamination of silicon device layers, which is known to seriously damage or destroy their performance.
WO 2009/034362 discloses the use of deep level impurities to increase the resistivity of a substrate for high frequency circuits, but requires full encapsulation of the substrate, and/or of a device layer mounted on the substrate, by a diffusion barrier layer.
In the description which follows, reference to “wafer” is understood to encompass both a whole (undiced) wafer and a portion of a whole wafer (for example a diced portion of a whole wafer).
It is an object of the present invention to address at least some of the problems discussed above in relation to the prior art.
According to an aspect of the invention, there is provided a substrate for an electronic circuit, comprising: a silicon or germanium wafer impregnated with impurities that form one or more deep energy levels within the band gap of the material forming the wafer, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and a device layer formed on a surface of said wafer, said device layer comprising electronically functional components formed in a layer of Periodic Table Group III-V or II-VI material, wherein: the Periodic Table Group III-V or II-VI material layer is formed using an epitaxial deposition process.
The wafer may be formed from Czochralski silicon or Czochralski germanium, for example. Preferably, the wafer is formed from silicon or germanium grown using the magnetic Czochralski method. Such wafers have lower levels of oxygen and are particularly advantageous where Au is used as the deep-level impurity because the rate of injection of self interstitials, which tend to displace Au atoms from substitutional sites, is reduced.
The use of a layer of group III-V or II-VI material on a silicon wafer enables the advantageous thermal and mechanical properties of silicon to be exploited while at the same time benefiting from the improved performance of group III-V or II-VI materials at high frequencies and high powers. Impurities which act as deep level dopants for Si (or Ge) will generally be less active (or not at all significantly active) for the group III-V or II-VI materials, so that the device layer can be formed directly on the wafer, optionally via a transition layer that need not substantially inhibit diffusion of the impurities through it. In the case where deep level impurities are significantly active for certain group III-V or II-VI materials, they may have lower diffusion and/or solubility in these materials compared to Si so that insufficient impurity will enter the material to be damaging. The inclusion of the deep level impurities in the wafer enables the resistivity of the wafer to be maintained at a high enough level to avoid significant losses, without the need to form the wafer using an expensive, and potentially unreliable, float zone technique. The wafer can be formed by the Czochralski method, for example. In addition, the approach of the present invention enables much higher resistivities to be obtained than those available with float zone techniques. For example, in excess of 100 kΩcm at room temperature can be achieved (in the case of silicon).
The use of an epitaxial deposition process requires the presence of a crystalline interface which is not present in the amorphous diffusion barrier layers that the prior art teaches should be provided where deep-level impurities are present.
According to an alternative aspect of the invention, there is provided a device manufacturing method, comprising the following steps: forming a device layer on a silicon or germanium wafer, said device layer comprising electronically functional components formed in a Periodic Table Group III-V or II-VI material layer; and impregnating the wafer with impurities that form one or more deep energy levels within the band gap of the material forming the wafer, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level, wherein: the Periodic Table Group III-V or II-VI material layer is formed using an epitaxial deposition process.
In an embodiment the step of impregnating the wafer with the deep-level impurities is carried out after the formation, by epitaxy, of the Periodic Table Group III-V or II-VI material layer. The inventors have recognised that the deep-level impurities will not be damaging for the device layer because they will be either electrically inactive or not sufficiently mobile to migrate into the device layer to the extent necessary to degrade performance unacceptably (for the typical temperatures to which the device will be exposed while the device layer and deep-level impregnated wafer are both present). However, in certain embodiments it will be important to avoid the presence of deep-level impurity contaminants in the environment during the formation of the Periodic Table Group III-V or II-VI material layer because of the gradual nature of the deposition process. If the environment is contaminated, deep-level impurities could enter the device layer throughout the deposition process, leading to the deep-level impurities being distributed throughout the layer. This would be more likely to degrade performance of the device layer. Performing the impregnation with the deep level impurities after the deposition process facilitates avoidance of contamination of the deposition process by the deep level impurities.
The inventors have recognized that processing at elevated temperatures (such as the temperatures that would be used in typical device manufacturing steps) of silicon doped with deep level impurities, for example Au, can cause a thin deep-level impurity rich layer to be produced at the surface of the material. Optionally, after the impregnation step: a layer at the surface of the silicon wafer (e.g. comprising the deep-level impurity only or a mixture of the deep-level impurity and silicon) is removed by etching and/or an anneal is performed that redistributes impurities away from a surface layer (e.g. an anneal at about 1150 degrees C. for a short period, for example about two to five minutes, followed by rapid cooling, for example at about 40 degrees C. per minute or more for at least a proportion of the cooling, for example down to about 650 degrees C.). The etching and/or anneal reduces the concentration of deep-level impurities on or near the surface and reduces any deleterious effect on performance.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:

FIG. 1 is a schematic illustration of a device comprising a GaN device layer, a transition layer, and a wafer processed according to embodiments of the invention.

As has been discussed above, at high frequencies silicon wafers become problematic because of high absorption of microwave power by background free carriers of the material, causing a reduction in the performance of the complete circuit.
Silicon has a relatively low band gap of 1.12 eV at room temperature, which sets its intrinsic (100% pure material) free carrier concentration at 10¹⁰cm⁻³and hence its nominal resistivity at 300 kΩcm or greater. However, it is extremely difficult to avoid background impurities being incorporated into the silicon during single crystal growth (particularly with the otherwise highly favourable Czochralski (Cz) growth method), and in practice it is very challenging to reduce the free carrier concentration much below 10¹³cm⁻³.
For radio frequency CMOS devices operating up to around 2 GHz, special high resistivity silicon tends to be used, which has a resistivity of around 1 kΩcm. However, it has been shown that a silicon wafer resistivity of at least 1 kΩcm is required for satisfactorily low absorption loss and operation comparable with GaAs (a group III-V material) substrates, for example, operating at frequencies of more than a few MHz. At higher operating frequencies even higher substrate resistivities are required to obtain satisfactory operation.
The present invention is based on introducing deep level impurities into a wafer layer to compensate the free carriers remaining after the single crystal growth process of the wafer. In this way, it is possible efficiently to produce wafers of extremely high resistivity (thus reducing absorption losses) and of dimensions and physical properties suitable for conventional semi-conducting processing systems.
The concentration of deep level impurities may be chosen to be in the range of 10¹³to 10¹⁸cm⁻³. Preferably, the concentration is in the range of 10¹⁴to 10¹⁷cm⁻³. More preferably, the concentration is in the range of 10¹⁴to 10¹⁶cm⁻³. In the case of a silicon wafer, the impurities may preferably increase the resistivity to at least 1 kΩcm, more preferably to at least 2 kΩcm, more preferably to at least 4 kΩcm, more preferably to at least 10 kΩcm, at the operating temperature of the high frequency device, for example at about 293 K, 323 K or 353 K. Preferably, the impurities may increase the resistivity to at least 100 kΩcm at room temperature. Any combination of the above concentrations, resistivities and temperatures may be used.
In the case where the wafer is formed from germanium, the deep level impurities may raise the resistivity to about 100 Ωcm at room temperature. It is expected, however, that the main applications for systems using germanium will operate at lower temperatures, for example at liquid nitrogen temperatures, which will result in higher resistivities.
The impurities are effective to increase the resistivity because they act to compensate for shallow donor and acceptor levels that arise in the band gap of the material forming the wafer due to background impurities (also referred to as “shallow level dopants”) introduced during the manufacturing process. For example, where the Cz technique is used to fabricate a silicon wafer layer, shallow level dopants such as phosphorous and boron are common. It is extremely difficult to eliminate such background impurities from the manufacturing process. Other shallow levels may also be introduced during the manufacturing process. For example, thermal donors may be formed during the processing of Cz silicon and these will also be compensated by the intentionally introduced deep level impurities.
In general, the effect on the resistivity of the impurities which are deliberately added to increase the resistivity will depend on the type of impurity and on the concentration of the impurity. The type of impurity determines the nature of the energy levels that the impurity introduces into the band structure of the material forming the wafer. Broadly speaking, where an energy level is formed which is relatively close to either the valence or conduction band, the effect of the impurity on the resistivity tends to vary significantly as a function of the concentration of the added impurity. On the other hand, where impurities are chosen which introduce energy levels deep within the band gap, a rise in resistivity is achieved over a broader range of concentrations of the added impurity. Impurities which introduce one or more energy levels deep within the band gap are referred to as deep level impurities and are in general preferred over shallower level impurities (which are nevertheless deep enough to provide some increase in resistivity) because the increased resistivity occurs over a broader range of concentrations and is also less sensitive to the concentration of the shallow level dopants that are being compensated.
Further details about the expected effect of different deep level impurities on the resistivity of Czochralski silicon can be found in the research paper Semicond. Sci. Technol. 18 (2003) 517-524, herein incorporated in its entirety by reference, the teaching of which can be applied to the impurities used in the present invention.
A number of potentially suitable deep level impurities exist. These include gold, silver, chromium, cobalt, palladium, platinum, vanadium and manganese. The effect on the resistivity of silicon of such materials has meant that they have traditionally been excluded from semiconductor manufacturing facilities because of the risk of contamination of silicon device layers. This is particularly true for gold and silver which have very high diffusivities, which increases the risk that they will find their way into the device layers. A possible exception is the fast switching diode, for which Au is deliberately introduced as a “lifetime killer” (to reduce minority carrier lifetime). However, this is unusual. In general, the presence of a lifetime killer is considered highly undesirable and great care is taken to avoid them. Embodiments of the present invention have been developed despite this commonly held fear in the field, based on the recognition that a broad class of devices are insensitive to the deep level impurities (e.g. passives) and that, for devices which are sensitive, careful positioning of the devices relative to impregnated wafers, careful design of substrates (e.g. to include diffusion barrier shields) and/or careful choice of manufacturing sequences can sufficiently reduce the risk of performance disruption due to contamination of device layers by the deep level impurities.
The deep-level impurities may be chosen so that the impurity energy levels pin the Fermi level near the middle of the band gap. The pinning of the Fermi level in this way may prevent the production of an inversion layer. This is a significant problem as the inversion layer may otherwise reduce the effective substrate resistance in high resistivity silicon substrates with low background doping and can be a particular problem when float-zone material is used in this role.
Whether or not the energy level introduced by a given impurity is deep enough to increase the resistivity of the wafer will depend on the nature of the wafer and how it was manufactured (i.e. on which shallow level dopants are intrinsically present and in which concentrations—both the energy level of the impurity and its concentration are relevant factors). However, it is typically expected that impurities having energy levels which are more than 0.3 eV deep in the band gap (the relevant depth being the energy difference between the deep level and the conduction band for donor states and between the energy level and the valence band for acceptor states) would be suitable. Larger separations (i.e. deeper energy levels) generally produce higher resistivity material over a larger range of concentrations. In the case of silicon, as an example of a suitable concentration for a particular application theory suggests that a concentration of 5×10¹³cm⁻³of boron would require about 10¹⁵cm⁻³of gold to produce satisfactory compensation. However, a higher concentration of Au would result in an even higher resistivity. The inventors have found that compensation works better for n-type rather than p-type material. Therefore, it may be desirable to start with an n-type material (e.g. phosphorous doped) of about 1×10¹⁴cm⁻³. This approach can result in resistivities greater than 100 kOhmcm at room temperature.
Deep level impurity dopants are found to fall into two broad categories according to the nature of compensation produced. For the addition of Au or Ag to p-type substrates, the resistivity saturates with increasing concentrations of the deep dopant, whereas for Mn and V the resistivity peaks and then tails off quickly with increasing deep dopant concentration. The different behaviour is due to the presence of both acceptor and donor states very near mid-gap for the first category of impurities, whilst the second type only have a single type of level very near mid-gap. The first category of impurities can trap both electrons and holes and are thus able to compensate, for example, for the presence of residual boron atoms in Cz—Si and also any thermal donors which might be formed during processing. The second category can only compensate for a single carrier type. From this picture, using the first category of dopants, for which resistivity saturates at high impurity concentrations, it can be easier to achieve uniformly high resistivity in the substrate without requiring precise control over the spatial distribution of the compensating deep impurity concentration.
The properties of Au make it a particularly promising candidate for the deep level impurity. Assuming that a minimum guaranteed concentration of residual B that can be achieved in Cz—Si, at reasonable economic cost, is 5×10¹³cm⁻³, it is expected that introduction of about 10¹⁶cm⁻³Au atoms into a silicon wafer will achieve a resistivity greater than about 3 kΩcm at room temperature.
From the solubility of Au in Si, calculated using thermodynamic data and an experimentally derived phase diagram, it is expected that temperatures of around 1000° C. would be required to introduce gold concentrations up to 10¹⁶cm⁻³, whilst at 1200° C. the solubility is around 10¹⁷cm⁻³, much more than sufficient to compensate low B doped Cz—Si, although the effects of clustering may become relevant at these higher concentrations (see below).
Diffusion of Au in bulk Si occurs by either the dissociative Frank-Turnbull mechanism or by the kick-out mechanism. At temperatures above around 800° C., the kick-out mechanism dominates. Au diffuses very quickly as an interstitial but its interstitial solubility is very low whereas substitutional Au is a slow diffuser, but has a much higher solubility. Thus the transport of Au involves three stages: i) rapid interstitial diffusion, ii) the interchange between interstitial and substitutional states by the kick-out mechanism, which creates a super saturation of self-interstitials and finally, iii) the out-diffusion of these self-interstitials to the Si surface, which is normally assumed to act as an infinite sink. This last step is usually rate limiting and results in a “U-shaped” concentration profile (i.e. with higher concentrations near the surfaces of the Si and a lower concentration trough towards the centre of the Si away from the surfaces), typical of Au diffusion in Si. More generally, the U-shaped concentration profile will arise for Au, Pt, Zn, for example, which diffuse by the Kick-out mechanism, and Ni, for example, which diffuses via the Frank Turnbull mechanism.
The effective diffusivity of Au does not depend on the diffusivity of any Au species, but only on the diffusivity of Si self-interstitials and the equilibrium concentrations of Si self-interstitials and substitutional Au. Transport of Au to both surfaces of wafers, from a single surface, is rapid but it takes longer for the Au concentration in the centre of the wafer to reach its solid solubility value.
The resistivity of Si can be calculated for different concentrations of Au according to the compensation mechanism detailed in K. Mallik, R. J. Falster, and P. R. Wilshaw, Semiconductor Science Technology, 2003. 18: p. 517. When this analysis is combined with expressions for Au concentration obtained after diffusion, the resistivity at any depth in a silicon wafer can be calculated. For example, assuming a silicon wafer with a background B concentration of 5×10¹³cm⁻³, and using values for the Au donor and acceptor energy levels of E_v+0.35 and E_c−0.55 eV, resistivity in excess of 3 kΩcm should be possible throughout the silicon wafer, after an anneal of 40 minutes at 1050° C.
A number of standard approaches are available for incorporating the deep level impurity atoms. For example, the impurities may be deposited on the surface of a raw wafer (e.g. a Cz-produced single crystal silicon wafer) in a concentrated form and left to diffuse into the bulk at elevated temperatures. The speed of this process could be increased by increasing the temperature, for example. Alternatively, ion implantation may be used to “fire” (project) impurities into the silicon wafer followed by anneal to in-diffuse the impurities.
Si-based active components (e.g. semiconductor devices such as transistors) and diodes will generally be highly sensitive to the deep level impurities used to increase the resistivity of a silicon wafer, so that great care needs to be taken to ensure that they are not contaminated. However, active components based on periodic table group III-V or II-VI materials will not generally behave in the same manner as silicon-based active components and in many situations will be significantly less sensitive, or not sensitive to any significant degree, to the impurities which act as deep level impurities in a silicon wafer.
For example, GaN, which is a wide bandgap III-V material, is a particularly promising example for high power applications and is discussed in further detail below. Other semiconductors that could be used in the device layer include GaAs, InGaAs, GaAlAs, GaAlN, AlN, GaAlInN, ZnTe, ZnS and ZnO. In an embodiment, the layer of III-V or II-VI material comprises a plurality of layers (or “sublayers”) of different compositions. In an embodiment, one or more of these sublayers comprises one or more of GaAs, InGaAs, GaN, GaAIAs, GaAlN, AlN, GaAlInN, ZnTe, ZnS and ZnO. In an embodiment, fewer than all of the sublayers comprise material that is group III-V or II-VI material (i.e. materials of other compositions may be used in combination with the group III-V or II-VI material) within the layer of group III-V or II-VI material.
GaN-based components (e.g. transistors or diodes) on a silicon wafer that has been treated with deep level impurities is a particularly useful variation because of the advantages of GaN in high frequency/high power applications. Such a configuration is illustrated schematically in FIG. 1, which shows a device 10 comprising a GaN device layer 12 formed on a transition layer 14 that, in turn, is formed on a silicon wafer 15 impregnated with deep level impurities. The transition layer 14 serves to compensate for mismatches between the lattice parameters and the thermal expansion properties of the GaN device layer and the lattice parameters and thermal expansion properties of the silicon wafer 15. In essence, the transition layer 14 provides a more gradual change in these properties than would be the case if the GaN device layer were connected directly to the silicon wafer 15. This approach helps to avoid strain and/or heat induced defects in the GaN layer, which might affect performance or reliability in use.
The transition layer may comprise a layer of AIN (aluminium nitride) for example.
The GaN layer 12 may be formed as a thin film using an epitaxial deposition process, for example comprising metal-organic chemical vapour deposition, or the hydride vapour phase epitaxy process.
The GaN device layer 12 is particularly well suited to implementing high electron mobility transistors (HEMTs) for use in high power RF applications. These applications require very high resistivity substrates to be efficient and have only been tried in the prior art using very high purity float zone silicon (which has various disadvantages, not least expense), or different materials altogether, such as sapphire, SiC, or native GaN substrates. The realisation that Czochralski silicon can be used instead of the float zone silicon, when it is suitably impregnated with deep level impurities to raise its resistivity, provides the potential to greatly reduce costs.
Optionally, a diffusion barrier layer may be provided between the layer of Group III-V or II-VI material and the wafer to prevent (or substantially reduce) the transport of deep level impurities from the wafer to the device layer.
Optionally, either or both of the Periodic Table Group III-V or II-VI material layer and the electronically functional components therein is/are formed before the step of impregnating the wafer with impurities that form the one or more deep energy levels. This approach facilitates the avoidance of contamination of the epitaxial growth environment by deep-level impurities, which reduces the risk of the deep-level impurities being spread throughout the device layer even though their mobility within the device layer material may be very low.
Optionally, either or both of the Periodic Table Group III-V or II-VI material layer and the electronically functional components therein is/are formed during the step of impregnating the wafer with impurities that form the one or more deep energy levels. Optionally, either or both of the Periodic Table Group III-V or II-VI material layer and the electronically functional components therein is/are formed after the step of impregnating the wafer with impurities that form the one or more deep energy levels.
The wafers (including whole wafers and diced portions of wafers) discussed above may be formed from silicon, particularly Czochralski silicon. Optionally, the wafers may be formed from germanium, particularly Czochralski germanium.
Germanium provides a closer lattice match for certain Group III-V and II-VI materials (e.g. GaN), which may obviate the need for a transition layer between the wafer and the Group III-V and II-VI materials, or at least require a simpler transition layer than that needed in the case of a silicon wafer.
Devices based on germanium wafers may be used as part of sensitive detectors, sensors and/or imaging devices, for example. This is particularly the case where the devices are likely to be used at temperatures below room temperature, where the intrinsic resistivity of the germanium will be higher and the use of deep impurity level impregnation will generally be more effective/relevant. Due to the size of the band gap in germanium (0.7 eV), even a wafer that is fully compensated by deep level impurities will have a significant conductivity at room temperature.
For example, the use of a deep level impurity impregnated germanium wafer would be particularly useful in an infrared detector based on a Group II-VI material. The Group II-VI material might be formed efficiently on germanium for epitaxial reasons, and the infrared detector would tend to be operated at temperatures well below room temperature, for example at liquid nitrogen temperatures, anyway (so that no additional cooling is required). At liquid nitrogen temperatures, the intrinsic resistivity of germanium would be such as to allow significant benefit (in terms of enhanced resistitivity) to be derived from the treated wafer. The increased resistivity may allow more efficient integration (i.e. improved performance) with electronic components in a high speed detection system, for example.
More generally, it is expected that many Group II-VI and III-V devices will be formed more efficiently on Ge substrates. Although devices, such as the infrared detector discussed above, that are normally operated at low temperatures will be the most natural candidates for fabrication using an impurity treated germanium wafer, other devices that are not normally cooled may still be considered. In particular, the additional advantages that the present development offers may in some cases make cooling of a device worthwhile in terms of cost when previously this was not the case.
The inventors have found that thermal anneals of silicon doped with Au can cause a thin Au rich layer to be produced at the surface of wafers. This layer is to some extent conductive and would reduce the effective resistivity of the wafer if it were to be used as a substrate in a device. Such a layer can be observed after an anneal to impregnate the silicon wafer with the Au for example, depending on the cooling rate after this anneal. The inventors have found that this Au rich layer can be removed by chemical etching in, for example, aqua regia or an aqueous potassium iodide/iodine solution. In an example it was found that a piece of Au doped silicon that showed an effective resistivity of ˜50 kohm cm when measured using a four point contact method immediately after an impregnation anneal, showed a resistivity of ˜150 kohm cm when re-measured after using a Au removing etch. However, if the wafer has a surface layer of another material, for example silicon oxide or a III-V semiconductor, then the Au rich layer can form at the interface between the two materials and in this case cannot be removed by a chemical etch. The application of a short, high temperature anneal followed by a rapid cool, for example as routinely used in Rapid Thermal Anneals (RTAs), can remove the Au rich layer by redistributing the Au deeper into the silicon. This process may be carried out on silicon either with or without the presence of surface layers of another material. The duration of this anneal step will typically be two to five minutes at a temperature of approximately 1150 C. The cooling rate after such an anneal should be greater than about 40 C per minute down to a temperature of around 650 C. Below about this temperature the cooling rate can be slower.
It has been found that annealing Au containing Si at high temperatures can induce clustering of the Au which reduces the number of deep levels in the material associated with the impurity. This process can change the resistivity of the material in an undesired way. These clusters of Au can be broken up by a relatively short, high temperature anneal at a temperature such that the concentration of Au in the material (including that in both the substitutional and clustered state) is below the solid solubility for Au in silicon at that temperature. An example of such an anneal to break up Au clusters would be 1150 C for 20 minutes.
The precipitation of oxygen present in a silicon wafer can lead to the injection of silicon self interstitials that displace Au atoms lying on substitutional sites so as to move them onto interstitial sites which may change the resistivity of the material in an undesired way. The rate of oxygen precipitation is strongly dependent on (amongst other things) the concentration of oxygen interstitials present in the wafer. This concentration can be reduced by purposely precipitating much of the oxygen before Au is introduced into the wafer but it can also be reduced by the selection of Czochralski wafers that have been grown using the so called magnetic Czochralski process. In this process a strong magnetic field is applied to the silicon melt during ingot growth. This has the effect of damping convective currents in the melt which in turn reduces the amount of oxygen interstitials incorporated into the growing ingot. Typical oxygen concentrations in standard Czochralski (CZ) silicon are above 7×10¹⁷cm⁻³whereas for magnetic Czochralski (MCZ) silicon they are normally below 5×10¹⁷cm⁻³. MCZ silicon is sometimes used where it is wished to suppress thermal donor generation (thermal donors are electrically active oxygen complexes whose rate of generation increases with increasing interstitial oxygen concentration). However, this functionality will not normally be relevant in the present application because the Au deep levels will effectively compensate for the thermal donor energy levels. The production of MCZ wafers is also more expensive than standard CZ wafers and MCZ wafers are mechanically weaker (their yield strength may be as much as 15% lower). Nevertheless, the inventors have recognised that the benefits described above in terms of reducing the displacement of substitutional Au onto interstitial sites make it attractive to use MCZ wafers for high resitivity Au doped silicon substrates despite the extra cost involved and the mechanically weaker material produced.
Any of the aspects of the invention can be combined together in any combination.

Claims

1. A substrate for an electronic circuit, comprising:

a silicon or germanium wafer impregnated with impurities that form one or more deep energy levels within the band gap of the material forming the wafer, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and

a device layer formed on a surface of said wafer, said device layer comprising electronically functional components formed in a layer of Periodic Table Group III-V or II-VI material, wherein:

said Periodic Table Group III-V or II-VI material layer is formed using an epitaxial deposition process.

2. A substrate according to claim 1, wherein the Periodic Table Group III-V or II-VI material comprises a III-Nitride alloy or a III-Arsenide alloy.

3. A substrate according to claim 1, wherein:

said Periodic Table Group III-V or II-VI material is one of the following: GaAs, InGaAs, GaN, GaAlAs, GaAlN, AN, GaAlInN, ZnTe, ZnS and ZnO.

4. A substrate according to claim 1, wherein the wafer is formed from material grown using the magnetic Czochralski method.

5. A substrate according to claim 1, wherein said device layer further comprises:

a transition layer formed between said wafer and said Periodic Table Group III-V or II-VI material layer, said transition layer being effective to at least partially compensate for either or both of the following: a lattice mismatch between the material of said wafer and said Periodic Table Group III-V or II-VI material layer; a thermal expansion coefficient mismatch between the material of said wafer and said Periodic Table Group III-V or II-VI material layer.

6. A substrate according to claim 5 when said Periodic Table Group III-V or II-VI material layer is GaN or GaAlN, wherein said transition layer comprises an AlN layer.

7. A substrate according to claim 1, wherein said epitaxial deposition process is metal-organic chemical vapour deposition or the hydride vapour phase epitaxy process.

8. A substrate according to claim 1, further comprising:

a diffusion barrier layer between said wafer and said device layer, said diffusion barrier layer having the property of substantially preventing diffusion of said impurities through it.

9. A high electron mobility transistor comprising a substrate according to claim 1.

10. An infrared detector comprising a substrate according to claim 1.

11. A device manufacturing method, comprising the following steps:

forming a device layer on a silicon or germanium wafer, said device layer comprising electronically functional components formed in a Periodic Table Group III-V or II-VI material layer; and

impregnating the wafer with impurities that form one or more deep energy levels within the band gap of the material forming the wafer, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level, wherein:

12. A method according to claim 11, wherein said step of forming a device layer comprises forming a transition layer between said wafer and said Periodic Table Group III-V or II-VI material layer, said transition layer being effective to at least partially compensate for either or both of the following: a lattice mismatch between the material of said wafer and said Periodic Table Group III-V or II-VI material layer; a thermal expansion coefficient mismatch between the material of said wafer and said Periodic Table Group III-V or II-VI material layer.

13. A method according to claim 11, wherein the Periodic Table Group III-V or II-VI material layer is formed before the step of impregnating the wafer with impurities that form one or more deep energy levels.

14. A method according to claim 11, wherein the wafer is formed from material grown using the magnetic Czochralski method.

15. A method according to claim 11, further comprising, after the impregnation step:

removing a layer at the surface of the wafer by etching; or

performing an anneal to redistribute said impurities away from a surface layer.

16. A substrate according to claim 1, wherein said impurities include one or more of the following: gold, silver, chromium, cobalt, palladium, platinum, vanadium and manganese.

17. A substrate according to claim 1, wherein said wafer is formed from Czochralski silicon or Czochralski germanium.

18. A substrate according to claim 1 or wherein the concentration of said impurities is between 10¹³to 10¹⁸cm⁻³.

19. A substrate according to claim 1 wherein the layer of Periodic Table Group III-V or II-VI material comprises a plurality of sublayers, one or more of the sublayers comprising one or more of GaAs, InGaAs, GaN, GaAlAs, GaAlN, AN, GaAlInN, ZnTe, ZnS and ZnO.

20.-21. (canceled)