US20140048907A1

US20140048907A1 - Power tsvs of semiconductor device

Info

Publication number: US20140048907A1
Application number: US13/720,432
Authority: US
Inventors: Young Hee YOON; Ga Young Lee
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2012-08-17
Filing date: 2012-12-19
Publication date: 2014-02-20
Also published as: US9620483B2; US20160056130A1; KR20140023706A

Abstract

A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs.

Description

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2012-0090005, filed on Aug. 17, 2012, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device with power through silicon vias (TSV)s.
2. Related Art
In recent semiconductor devices, technology for stacking a plurality of semiconductor integrated circuits is being adopted. To achieve high performance while providing a reduction in the size of electrical/electronic products, various techniques for fabricating a stacked package are being developed.
A stacked package in the semiconductor industry field refers to two or more semiconductor chips or packages that are vertically piled up (i.e. stacked vertically). In accordance with this stacked package, for example, a semiconductor memory device can be implemented to have a memory capacity that is twice or more than the memory capacity that can otherwise be achieved for a given chip area using a given semiconductor process technology. Furthermore, the stacked package is advantageous over standard packages in that the memory capacity can be increased while keeping the circuit board mounting area and mounting area efficiency of the device relatively unchanged. Thus, research and development for manufacturing stacked packages are being accelerated.
A stacked package can be fabricated by using a method of stacking pre-packaged semiconductor chips and then packaging the stacked semiconductor chips at once, or by using a method of stacking post-packaged semiconductor chips. The semiconductor chips of a stacked package can be electrically coupled together by using metal wires or by using through silicon vias (TSVs). In particular, a stacked package using the through silicon vias approach has a structure in which the through silicon vias are formed within the semiconductor chips, and the semiconductor chips are vertically coupled using the through silicon vias to physically and electrically connect the semiconductor chips.
A semiconductor device can include distinct regions which can be classified as an active region that includes active circuitry such as memory banks, or a peripheral region that includes pads for interfacing signals and power to other devices.
FIG. 1 is a diagram showing an example arrangement of a semiconductor device. As shown in FIG. 1, the semiconductor device includes a plurality of power lines VDD 1 and VSS 2.
The power lines 1, which are spaced apart from each other, are coupled by metal lines so that power lines 1 have the same VDD voltage potential. Similarly, the power lines 2, which are spaced apart from each other, are coupled by metal lines so that power lines 2 have the same VSS voltage potential. Furthermore, a plurality of cap regions 3 is included between the power lines 1 and 2. Each of the cap regions 3 implements a reservoir capacitor.
A reservoir capacitor functions to compensate for the unstable supply of power due to the parasitic capacitance of a power source. More particularly, the reservoir capacitor can stabilize a power source because the reservoir capacitor provides durability and solidarity against the shaking of the power source and/or various noises on the power signal.
Meanwhile, a dummy region 4 is disposed between the cap regions 3.
The dummy region 4 is a region that includes dummy metal lines. The metal lines within the dummy region 4 are assumed to be in a floating or unconnected state.
Signal TSVs S and power TSVs P are disposed under the region where power lines 1 and 2 run (i.e. outside the active region). The region in which the signal TSVs S and the power TSVs P are disposed is a pad region (i.e. part of the peripheral region where pads are disposed).
In a semiconductor device such as the one described above, the intensity of a power source decreases gradually according to the number of stacked semiconductor chips. FIG. 2 is a perspective view showing that the intensity of a power source voltage is reduced according to an increase in the number of stacked semiconductor chips. In other words, the intensity of power at each incrementally stacked semiconductor chip becomes less and less.
Accordingly, it is desirable to supply a stable and consistent power supply to each semiconductor chip when a plurality of semiconductor chips is stacked.

SUMMARY

In one embodiment of the present invention, a semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs.
In another embodiment of the present invention, a semiconductor device includes a pad region having a chip power pad, and an active region including circuitry for performing a function of the semiconductor device, a plurality of power lines, and power through silicon vias (TSVs) coupled to the chip power pad.

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

FIG. 1 illustrates an arrangement of a semiconductor device;

FIG. 2 illustrates the intensity of a power source voltage in stacked semiconductor chips;

FIG. 3 shows an arrangement of a semiconductor device in accordance with an embodiment of the present invention; and

FIG. 4 shows an arrangement of a semiconductor device in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION

Hereinafter, a semiconductor device according to the present invention will be described below with reference to the accompanying drawings through exemplary embodiments.
FIG. 3 shows an arrangement of a semiconductor device including power lines in accordance with an embodiment of the present invention.
Referring to FIG. 3, the semiconductor device includes power TSVs in accordance with an embodiment of the present invention, and also includes an active region A, that is, a first region, and a pad region B, that is, a second region.
The active region A includes active circuitry such as memory banks to carry out the functionality of the semiconductor device (not shown), and a plurality of power lines 10, 10-1, 20, and 20-1. According to some embodiments, the active region A is bounded by the set of power lines 10 and 20 and the set of power lines 10-1 and 20-1.
The power lines can supply power sources to circuit units (not shown) within the active region A. That is, the power lines 10 and 10-1 can supply VDD power sources, and the power lines 20 and 20-1 can supply VSS power sources. The power lines are spaced apart from each other, but power lines that are used to supply the same voltage potential are coupled by one or more metal lines. Here, the VDD power lines 10 and 10-1 for supplying the VDD power sources are electrically coupled with each other, and the VSS power lines 20 and 20-1 for supplying the VSS power sources are electrically coupled with each other. The power lines as shown in FIG. 3 are illustrated as being coupled with a third metal line M3 (e.g., metal lines of a third metal layer), but are not limited thereto.
Cap regions 30 and dummy regions 40 are disposed in the space between the set of power lines 10 and 20 and the set of power lines 10-1 and 20-1.
Each of the cap regions 30 in accordance with an embodiment of the present invention has a cutout portion, for example, a cutout portion along one or more sides of the cap region. In other words, at least one side of each cap region 30 may have an indentation or a notch receding from the edge. Thus, unlike the semiconductor device shown in FIG. 1, the shape of the cap regions 30 according to embodiments of the present invention may not be a regular rectangular shape. In other embodiments, the cutout portion can span the entire length or width of an edge such that the entire length or width of the cap region is reduced. Power TSVs 50 and 60 within the active region A in accordance with an embodiment of the present invention are placed within the cutout portions of the cap regions 30.
More particularly, each of the cap regions 30 is a reservoir capacitor as described above and is a capacitor region used for compensating for the instability of a power source, for example, to reduce noise and ringing on a power signal that can be caused by the parasitic capacitance of TSVs through which power from a power source is supplied. The cap region 30 in accordance with an embodiment of the present invention can have an area smaller than an area of the cap region used in devices such as the one shown in FIG. 1 because of the cutout or notch provided on one or more sides. Furthermore, the power TSVs 50 and 60 in accordance with an embodiment of the present invention are placed in the respective cutout portions. Accordingly, TSVs can be included in the active region A without having to add additional area to the semiconductor device.
Meanwhile, metal lines within the dummy region 40 are hereinafter illustrated as being first metal lines M1 (e.g., metal lines of a first metal layer), but are not limited thereto. Furthermore, when coupling a chip power pad to the power TSV using the metal lines corresponding to dummy region 40, the chip power pad and the power TSV can be coupled at the edge of a chip pad.
The first metal lines M1 within the dummy region 40 are provided so that they can be coupled when power sources need to be coupled (e.g., to distribute power to different regions), but are otherwise assumed to be in a floating or unconnected state. Accordingly, the power TSVs 50 and 60 within the active region A can be coupled using some of the first metal lines M1 within the respective dummy region 40. Here, the first metal lines M1 used for coupling the power TSVs are illustrated as being metal lines on both sides (that is, the top and bottom, or opposing sides or portions) within the dummy region 40. This arrangement provides for a more balanced and stable supply of power, and also assists in distributing a shock that may occur, for example, when probing is performed in a subsequent test process.
Furthermore, the power TSVs 50 and 60 within the active region A can be coupled to the power lines 10, 10-1, 20, and 20-1, for example, by second metal lines M2 (e.g., metal lines of a second metal layer). Moreover, the power TSVs 50 and 60 within the active region A can also be connected to the chip power pad within the pad region B by the second metal lines M2, so that power from an external source supplied through the chip power pad can be supplied within the active region A through this path.
In other words, the power TSVs connected to the VDD power lines 10 and 10-1 can additionally supply a VDD power source within the active region A, and the TSVs connected to the VSS power lines 20 and 20-1 can additionally supply a VSS power source within the active region A.
In particularly, the power TSVs disposed within the active region A in accordance with an embodiment of the present invention can deliver a more stable and consistent power supply to active region A, because the power TSVs provide active region A with a more direct connection to the chip power pad of the pad region B. That is, a stable power source through a reduced resistance path can be supplied to circuits within the active region A, because the power source is supplied to the circuits using the metal lines coupled to the power TSVs within active region A.
In the prior art, a power source is supplied only from the power pad in the pad region. Accordingly, resistance is increased because the supply path of the power source is complicated, and thus the intensity of the power source is reduced according to an increase in the number of stack semiconductor devices.
In the semiconductor device in accordance with an embodiment of the present invention, since the TSVs are disposed within the active region A, resistance can be reduced and a stable power source can be supplied because the power source is directly supplied within the active region A using the metal lines coupled to the power TSVs.
In other words, an external power source voltage is supplied to the chip power pad of the pad region B, the power source voltage is supplied from the chip power pad to the power TSVs within the active region A through the second metal lines M2, and the power source voltage is then supplied from the power TSVs to the circuits within the active region A through the first metal lines M1.
FIG. 4 shows an arrangement of a semiconductor device in accordance with another embodiment of the present invention.
The semiconductor device is described with reference to FIG. 4, but details of portions redundant with those of FIG. 3 are either not repeated or are described in brief.
In FIG. 4, the number of power TSVs with the active region is increased as compared to that of the embodiment shown in FIG. 3.
VDD power lines 10 and 10-1 are coupled by second metal lines M2 to have the same voltage potential.
VSS power lines 20 and 20-1 are coupled by second metal lines M2 to have the same voltage potential.
Meanwhile, the number of power TSVs connected to the VDD power lines 10 and 10-1 is four. The number of power TSVs within the active region can be increased in order to supply stable VDD power sources.
Likewise, the number of TSVs connected to the VSS power lines 20 and 20-1 is four. The number of power TSVs within the active region can be added in order to supply stable VSS power sources.
The additional power TSVs allow stable power sources to be supplied to a plurality of stacked chips through paths having further reduced resistance.
It is to be noted that in some embodiments, the number of TSVs can be increased or reduced independently for a specific power source voltage as understood and modified by those skilled in the art. In other words, for different power source voltages, the number of TSVs can be different.
For example, in another embodiment, the number of TSVs for the VDD power source within the active region can be four in order to supply the VDD power source more stably, whereas the number of TSVs for the VSS power source can be two.
As another example, in a further embodiment, the number of TSVs for a VDD power source within the active region can be two, and the number of TSVs for the VSS power source within the active region can be four.
While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor device described herein should not be limited based on the described embodiments. Rather, the device described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.

Claims

What is claimed is:

1. A semiconductor device having a chip stack structure, comprising:

a chip power pad placed in a first region of a chip;

power through silicon vias (TSVs) coupled to the chip power pad and placed in a second region of each of a plurality of chips in the chip stack structure where no pads are disposed; and

metal lines configured to couple the chip power pad and the power TSVs.

2. The semiconductor device according to claim 1, wherein:

the first region is a pad region of the chip, and

the second region of each of the plurality of chips is an active region of the respective chip.

3. The semiconductor device according to claim 2, wherein the power TSVs are used to deliver a power source directly within the active region of each chip.

4. The semiconductor device according to claim 3, wherein the power TSVs are coupled to circuits within the active region of each chip by metal lines in a first metal layer of each chip, the first metal layer being a different metal layer than a second metal layer of the metal lines that are used to couple the chip power pad to the power TSVs.

5. The semiconductor device according to claim 1, wherein the chip power pad and the power TSVs are coupled at an edge of the chip power pad.

6. The semiconductor device according to claim 3, wherein the power TSVs are coupled by dummy metal lines.

7. A semiconductor device having a chip stack structure, comprising:

a pad region having a plurality of pads including a chip power pad; and

an active region including circuitry for performing a function of is the semiconductor device, a plurality of power lines, and power through silicon vias (TSVs) coupled to the chip power pad.

8. The semiconductor device according to claim 7, wherein the active region further comprises:

cap regions each configured to comprise a reservoir capacitor and a cutout portion; and

dummy regions each disposed by at least one of the cap regions, each of the dummy regions comprising a plurality of dummy metal lines.

9. The semiconductor device according to claim 8, wherein the power TSVs are coupled by the dummy metal lines.

10. The semiconductor device according to claim 8, wherein each of the power TSVs is placed within one of the cutout portions of the cap regions.

11. The semiconductor device according to claim 7, wherein the chip power pad and the power TSV coupled to the chip power pad have an identical voltage potential.

12. The semiconductor device according to claim 11, wherein when the identical voltage potential is a VDD voltage potential.

13. The semiconductor device according to claim 11, wherein when the identical voltage potential is a VSS voltage potential.

14. The semiconductor device according to claim 8, wherein the cap region compensates for parasitic capacitance of the power TSVs to reduce power noise.

15. The semiconductor device according to claim 9, wherein the dummy metal lines for coupling the power TSVs comprise metal lines placed on opposing sides within the dummy region.

16. The semiconductor device according to claim 7, wherein the plurality of power lines comprises:

a first set of power lines including a first VDD power line and a first VSS power line; and

a second set of power lines including a second VDD power line and a second VSS power line, and

wherein the active region is a region bounded by the first and second set of power lines.

17. The semiconductor device according to claim 8, wherein at least one of the cap regions has more than one cutout portion, and each of the more than one cutout portion includes a respective power TSV disposed therein.