[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

US20090152636A1 - High-k/metal gate stack using capping layer methods, ic and related transistors - Google Patents

High-k/metal gate stack using capping layer methods, ic and related transistors Download PDF

Info

Publication number
US20090152636A1
US20090152636A1 US11/954,749 US95474907A US2009152636A1 US 20090152636 A1 US20090152636 A1 US 20090152636A1 US 95474907 A US95474907 A US 95474907A US 2009152636 A1 US2009152636 A1 US 2009152636A1
Authority
US
United States
Prior art keywords
oxide
metal
dielectric layer
over
type transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/954,749
Inventor
Michael P. Chudzik
Naim Moumen
Vijay Narayanan
Dae-Gyu Park
Vamsi K. Paruchuri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alsephina Innovations Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US11/954,749 priority Critical patent/US20090152636A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PARUCHURI, VAMSI K, MOUMEN, NAIM, NARAYANAN, VIJAY, PARK, DAE-GYU, CHUDZIK, MICHAEL P
Publication of US20090152636A1 publication Critical patent/US20090152636A1/en
Priority to US13/433,659 priority patent/US9236314B2/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Assigned to ALSEPHINA INNOVATIONS INC. reassignment ALSEPHINA INNOVATIONS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES INC.
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • the disclosure relates generally to integrated circuit (IC) fabrication, and more particularly, to forming of high dielectric constant (high-k) and metal gate stacks using a capping layer.
  • IC integrated circuit
  • Metal gate electrodes are being pursued for, for example, the 45 nanometer (nm) and 32 nm technology nodes as a replacement for doped polysilicon (poly-Si) gate electrodes for a number of reasons.
  • Metal gate electrodes include a high dielectric constant (high-k) dielectric within a metal gate stack.
  • CMOS complementary metal oxide semiconductor
  • FET field effect transistor
  • Vt threshold voltage
  • dual metal/dual dielectric gate stacks One challenge for this technology is that the continual reduction in device dimensions that define, for example, the 45 nm and 32 nm technology nodes, impose an ever reducing distance between the different active regions, e.g., approximately 102 nm for the 45 nm node and approximately 72 nm for the 32 nm node.
  • the reduction in device dimensions presents a problem because tuning layers for NMOS and PMOS regions are not interchangeable.
  • gate stack layers particular to each region must be formed in both regions and then the opposing NMOS and PMOS region's stack must be completely removed, which is costly and induces process variations.
  • the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
  • a first aspect of the disclosure provides a method comprising: providing an implanted substrate with a n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region; depositing a high dielectric constant (high-k) dielectric layer over the implanted substrate; forming a first metal having a work function commensurate with a first one of the NMOS region and the PMOS region over the first one of the NMOS and the PMOS regions only, leaving the high-k dielectric layer exposed over a second one of the NMOS and PMOS regions; depositing a second metal having a work function commensurate with the second one of the NMOS region and the PMOS region over the implanted substrate; depositing a polysilicon over the implanted substrate; and patterning to form a first gate stack over the NMOS region and a second gate stack over the PMOS region on the implanted substrate.
  • NMOS n-type metal oxide semiconductor
  • PMOS p-type metal oxide semiconductor
  • a second aspect of the disclosure provides an integrated circuit comprising: a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
  • a third aspect of the disclosure provides a transistor comprising: a gate stack including: a high dielectric constant (high-k) dielectric layer over a substrate, a capping layer including an oxide of a rare earth metal over the high-k dielectric layer, a metal over the oxide of the rare earth metal, the metal having a work function commensurate with a well in the substrate, and a polysilicon over the metal.
  • a gate stack including: a high dielectric constant (high-k) dielectric layer over a substrate, a capping layer including an oxide of a rare earth metal over the high-k dielectric layer, a metal over the oxide of the rare earth metal, the metal having a work function commensurate with a well in the substrate, and a polysilicon over the metal.
  • a fourth aspect of the disclosure provides a transistor comprising: a gate stack including: a high dielectric constant (high-k) dielectric layer over a substrate, the high-k dielectric layer including oxygen, a first metal having a work function commensurate with a well in the substrate, a capping layer including a rare earth metal over the first metal, a second metal over the capping layer, the second metal having a work function incompatible with the well in the substrate, and a polysilicon over the second metal.
  • a gate stack including: a high dielectric constant (high-k) dielectric layer over a substrate, the high-k dielectric layer including oxygen, a first metal having a work function commensurate with a well in the substrate, a capping layer including a rare earth metal over the first metal, a second metal over the capping layer, the second metal having a work function incompatible with the well in the substrate, and a polysilicon over the second metal.
  • FIGS. 1-6 show embodiments of a method according to the disclosure, with FIG. 6 showing embodiments of an integrated circuit (IC) and related transistors according to the disclosure.
  • IC integrated circuit
  • FIG. 1 shows providing an implanted substrate 120 including an n-type metal oxide semiconductor (NMOS) region 116 and a p-type metal oxide semiconductor (PMOS) region 118 .
  • NMOS region 116 and PMOS region 118 may include a doped N-well 122 and doped P-well 124 , respectively, separated by an isolation region 126 , e.g., a shallow trench isolation (STI) of silicon oxide.
  • N-type and p-type dopants may be any appropriate dopants now known or later developed.
  • FIG. 1 also shows depositing a high dielectric constant (high-k) dielectric layer 130 over implanted substrate 120 .
  • high-k dielectric layer 130 may include any dielectric including oxygen and having dielectric constant greater than that of the vacuum level (K>1).
  • High-k dielectric 130 may include, but is not limited to: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), hafnium silicon oxide (HfSiO x ), hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), yttrium oxide (Y 2 O 3 ), strontium oxide (SrO) and strontium titanium oxide (SrTiO).
  • Depositing may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
  • CVD chemical vapor deposition
  • LPCVD low-pressure CVD
  • PECVD plasma-enhanced CVD
  • SACVD semi
  • FIGS. 1-2 show forming of a first metal 140 (e.g., deposited or grown ( FIG. 1 )) having a work function commensurate with a first one of NMOS region 116 and PMOS region 118 over the first one of NMOS and PMOS regions 116 , 118 only.
  • “commensurate with” indicates that the metal is commensurate with a doping of the region 116 , 118 in question, i.e., it's work function enhances performance of devices built in that particular region.
  • first metal 140 is formed over PMOS region 118 , and thus first metal 140 would be commensurate with PMOS region 118 .
  • first metal 140 would have a work function that would cause a threshold voltage to a band edge for a PFET 200 ( FIG. 6 ) to be formed over PMOS region 118 .
  • First metal 140 may be deposited, as shown in FIG. 1 , and then patterned and etched off of a second one of NMOS and PMOS regions 116 , 118 , as shown in FIG. 2 , leaving high-k dielectric layer 130 exposed over the second one of NMOS and PMOS regions 116 , 118 . In this case, high-k dielectric layer 130 of NMOS region 116 is exposed. This is in contrast to conventional techniques that would remove high-k dielectric layer 130 from NMOS region 116 .
  • First metal 140 may be removed using any now known or later developed technique, e.g., depositing a photoresist, patterning and etching the photoresist and etching first metal 140 using the photoresist. It is emphasized that first metal 140 may be for either NMOS region 116 or PMOS region 118 , i.e., the order of which region is generated first may switch without departing from the scope of the disclosure.
  • first metal 140 may include, but is not limited to: titanium nitride (TiN), ruthenium (Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium (V) and aluminum (Al).
  • FIG. 3 shows depositing a second metal 150 having a work function commensurate with the second one of NMOS and PMOS regions 116 , 118 over implanted substrate 120 .
  • the second one is the NMOS region 116 .
  • second metal 150 may include, but is not limited to: titanium nitride (TiN ⁇ , ruthenium (Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium (V) and aluminum (Al).
  • metal over NMOS may be also selected from this list when it is the first metal deposited, rather than the second as illustrated.
  • metal over PMOS may be selected from the above-described list therefor when it is the second metal deposited, rather than the first as illustrated.
  • FIG. 4 shows an optional process that includes depositing a capping layer 160 over implanted substrate 120 prior to depositing second metal 150 , then depositing second metal 150 .
  • Capping layer 160 can take a variety of forms.
  • capping layer 160 includes but is not limited to a dielectric such as: lanthanum oxide (La 2 O 3 ), dysprosium oxide (DyO), yttrium oxide (Y 2 O 3 ), barium oxide (BaO), strontium oxide (SrO), scandium oxide (ScO), cerium oxide (CeO), praseodymium oxide (PrO), neodymium (NdO), gadolinium oxide (GdO), erbium oxide (ErO).
  • lanthanum oxide La 2 O 3
  • DyO dysprosium oxide
  • Y 2 O 3 barium oxide
  • ScO scandium oxide
  • CeO cerium oxide
  • PrO praseodymium oxide
  • NdO
  • capping layer 160 may provide extra threshold voltage (Vt) shift—here NFET capping layer.
  • capping layer 160 may include a metal such as, but not limited to: lanthanum (La), dysprosium (Dy), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd), erbium (Er).
  • La lanthanum
  • Dy dysprosium
  • Y yttrium
  • strontium Sr
  • Sc scandium
  • barium Ba
  • Ce cerium
  • Pr praseodymium
  • Nd neodymium
  • Gd gadolinium
  • Er erbium
  • capping layer 160 includes a metal, typically a rare earth metal, that reacts with high-k dielectric layer 130 over the first one of the NMOS and PMOS regions (i.e., NMOS region 116 as illustrated) to form a dielectric 180 , but remains metallic 190 over the second one of the NMOS and PMOS regions 116 , 118 (i.e., PMOS region 116 as illustrated).
  • the rare earth metal may include a multilayer composite of metals (known as a bilayer). In terms of dielectric 180 , rare earth metal reacts with the oxygen in high-k dielectric layer 130 to form an oxide that is formed from the rare earth metal.
  • Capping layer 160 may include a rare earth metal such as, but not limited to: ytterbium (Yb), dysprosium (Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd) and erbium (Er).
  • Yb ytterbium
  • Dy dysprosium
  • La lanthanum
  • Y yttrium
  • strontium Sr
  • Sc scandium
  • barium Ba
  • Ce cerium
  • Pr praseodymium
  • Nd neodymium
  • Gd gadolinium
  • Er erbium
  • FIG. 5 shows depositing a polysilicon 170 over implanted substrate 120 based on the FIG. 4 embodiment.
  • FIG. 6 shows patterning to form a first gate stack 194 over NMOS region 116 and a second gate stack 196 over PMOS region 118 on implanted substrate 120 .
  • each gate stack 194 , 196 eventually becomes a gate electrode 194 , 196 for an n-type field effect transistor (NFET) 202 and a p-type field effect transistor (PFET) 200 , respectively.
  • NFET n-type field effect transistor
  • PFET p-type field effect transistor
  • An integrated circuit 210 including PFET 200 and NFET 202 thus includes a first type transistor (i.e., PFET 200 as illustrated) having gate electrode 194 including a first metal 140 , a second metal 150 having a work function commensurate with the second type transistor (i.e., NFET 202 as illustrated) and a first dielectric layer 130 including oxygen.
  • IC 210 also includes a second type transistor (i.e., NFET 202 as illustrated) separated from first type transistor (PFET) 200 by an isolation region 126 .
  • the second type transistor (NFET) 202 includes gate electrode 196 including second metal 150 and first dielectric layer 130 .
  • Gate electrode 194 of first type transistor (PFET) 200 also includes a rare earth metal 190 between first metal 140 and second metal 150
  • gate electrode 196 of second type transistor (NFET) 202 includes a second dielectric layer 180 made of an oxide of the rare earth metal.
  • First dielectric layer 130 is under first metal 140 in PFET 200 so as to act as a gate dielectric for gate electrode 194 .
  • second dielectric layer 180 contacts first dielectric layer 130 in first type transistor (NFET) 202 , and thus collectively act as a gate dielectric for gate electrode 196 .
  • Each gate electrode 194 , 196 further includes a polysilicon portion 170 .
  • second metal 150 in first type transistor (PFET) 200 and second type transistor (NFET) 202 are electrically coupled, which is impossible with conventional processing due to the gap that forms between devices during the patterning and removal process.
  • a transistor 200 includes gate stack 194 including high-k dielectric layer 130 over substrate 120 , first metal 140 having a work function commensurate with a well 124 in the substrate, capping layer 160 including a rare earth metal 190 over first metal 140 , a second metal 150 over capping layer 160 , and a polysilicon 170 over second metal 150 .
  • second metal 150 has a work function incompatible with well 124 (p-well) in substrate 120 , i.e., it is harmful to threshold voltage (Vt) if allowed to impact operation.
  • Transistor (NFET) 202 includes a gate stack 196 including high-k dielectric layer 130 over substrate 120 , capping layer 160 including an oxide 180 of a rare earth metal over high-k dielectric layer 130 , a metal 150 over the oxide of the rare earth metal, the metal having a work function commensurate with a well 122 (n-well) in substrate 120 , and a polysilicon 170 over the metal 150 .
  • the above-described methods, IC and transistors incorporate a capping layer in the form of an rare earth metal to intermix with high-k dielectric layer 130 (and not the metal 150 ) to shift the work function of the NMOS region 116 to band-edge, but when interposed in the metals 140 , 150 they do not cause a threshold voltage shift in the PMOS region 118 .
  • the methods allow for meeting of ground rules, and do not require removal of both NMOS and PMOS region metals form the opposing region.
  • the methods also allow for butted junctions with the NFET 202 always self-aligned to PFET 200 since only one metal layer is removed over isolation region 126 , i.e., second metal 150 .
  • the method as described above is used in the fabrication of integrated circuit chips.
  • the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
  • the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
  • the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
  • the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Composite Materials (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

Description

    BACKGROUND
  • 1. Technical Field
  • The disclosure relates generally to integrated circuit (IC) fabrication, and more particularly, to forming of high dielectric constant (high-k) and metal gate stacks using a capping layer.
  • 2. Background Art
  • In the integrated circuit (IC) fabrication industry, metal gate electrodes are being pursued for, for example, the 45 nanometer (nm) and 32 nm technology nodes as a replacement for doped polysilicon (poly-Si) gate electrodes for a number of reasons. Metal gate electrodes include a high dielectric constant (high-k) dielectric within a metal gate stack. The best known self aligned process flows for complementary metal oxide semiconductor (CMOS) fabrication with the high-k dielectrics and metal gate stack use a dual field effect transistor (FET) threshold voltage (Vt) work function tuning layers scheme to tune the threshold voltage of adjacent n-type metal oxide semiconductor (NMOS) region (for NFETs) and p-type metal oxide semiconductor (PMOS) region (for PFETs). That is, dual metal/dual dielectric gate stacks. One challenge for this technology is that the continual reduction in device dimensions that define, for example, the 45 nm and 32 nm technology nodes, impose an ever reducing distance between the different active regions, e.g., approximately 102 nm for the 45 nm node and approximately 72 nm for the 32 nm node. The reduction in device dimensions presents a problem because tuning layers for NMOS and PMOS regions are not interchangeable. As a result, in order to accommodate formation of the appropriate gate stack for each region, gate stack layers particular to each region must be formed in both regions and then the opposing NMOS and PMOS region's stack must be completely removed, which is costly and induces process variations. Since the distance between active regions is so small, etching the gate stacks and continuing to meet ground rule restrictions is currently unachievable for the 45 nm and 32 nm CMOS technology nodes, and beyond. In particular, the ability to form material layers such that they are thin enough to fill a gap between partially formed gate stacks and such that the materials can be removed from the gap to ultimately form the gate stacks in the NMOS and PMOS regions is currently unfeasible. Butted junctions are also not available using current practices because of the removal of layers between the different NMOS and PMOS gate stacks.
    • SUMMARY
  • Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
  • A first aspect of the disclosure provides a method comprising: providing an implanted substrate with a n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region; depositing a high dielectric constant (high-k) dielectric layer over the implanted substrate; forming a first metal having a work function commensurate with a first one of the NMOS region and the PMOS region over the first one of the NMOS and the PMOS regions only, leaving the high-k dielectric layer exposed over a second one of the NMOS and PMOS regions; depositing a second metal having a work function commensurate with the second one of the NMOS region and the PMOS region over the implanted substrate; depositing a polysilicon over the implanted substrate; and patterning to form a first gate stack over the NMOS region and a second gate stack over the PMOS region on the implanted substrate.
  • A second aspect of the disclosure provides an integrated circuit comprising: a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
  • A third aspect of the disclosure provides a transistor comprising: a gate stack including: a high dielectric constant (high-k) dielectric layer over a substrate, a capping layer including an oxide of a rare earth metal over the high-k dielectric layer, a metal over the oxide of the rare earth metal, the metal having a work function commensurate with a well in the substrate, and a polysilicon over the metal.
  • A fourth aspect of the disclosure provides a transistor comprising: a gate stack including: a high dielectric constant (high-k) dielectric layer over a substrate, the high-k dielectric layer including oxygen, a first metal having a work function commensurate with a well in the substrate, a capping layer including a rare earth metal over the first metal, a second metal over the capping layer, the second metal having a work function incompatible with the well in the substrate, and a polysilicon over the second metal.
  • The illustrative aspects of the present disclosure are designed to solve the problems herein described and/or other problems not discussed.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure, in which:
  • FIGS. 1-6 show embodiments of a method according to the disclosure, with FIG. 6 showing embodiments of an integrated circuit (IC) and related transistors according to the disclosure.
    •
  • It is noted that the drawings of the disclosure are not to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.
    • DETAILED DESCRIPTION
  • Referring to the drawings, embodiments of a method according to the disclosure are shown in FIGS. 1-6. FIG. 1 shows providing an implanted substrate 120 including an n-type metal oxide semiconductor (NMOS) region 116 and a p-type metal oxide semiconductor (PMOS) region 118. In particular, NMOS region 116 and PMOS region 118 may include a doped N-well 122 and doped P-well 124, respectively, separated by an isolation region 126, e.g., a shallow trench isolation (STI) of silicon oxide. N-type and p-type dopants may be any appropriate dopants now known or later developed. Implanted substrate 120 may include but is not limited to silicon, germanium, silicon germanium, silicon carbide, and those consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substrates include II-VI compound semiconductors having a composition ZnA1CdA2SeB1TeB2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Furthermore, a portion or entire semiconductor substrate 120 may be strained. Implanted substrate 120 may be formed using any now known or later developed processes, e.g., deposition, masking, ion implantation, etc.
  • FIG. 1 also shows depositing a high dielectric constant (high-k) dielectric layer 130 over implanted substrate 120. In one embodiment, high-k dielectric layer 130 may include any dielectric including oxygen and having dielectric constant greater than that of the vacuum level (K>1). High-k dielectric 130 may include, but is not limited to: hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), hafnium silicon oxide (HfSiOx), hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), yttrium oxide (Y2O3), strontium oxide (SrO) and strontium titanium oxide (SrTiO). “Depositing,” as used herein, may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
  • FIGS. 1-2 show forming of a first metal 140 (e.g., deposited or grown (FIG. 1)) having a work function commensurate with a first one of NMOS region 116 and PMOS region 118 over the first one of NMOS and PMOS regions 116, 118 only. As used herein, “commensurate with” indicates that the metal is commensurate with a doping of the region 116, 118 in question, i.e., it's work function enhances performance of devices built in that particular region. As illustrated, first metal 140 is formed over PMOS region 118, and thus first metal 140 would be commensurate with PMOS region 118. For example, first metal 140 would have a work function that would cause a threshold voltage to a band edge for a PFET 200 (FIG. 6) to be formed over PMOS region 118. First metal 140 may be deposited, as shown in FIG. 1, and then patterned and etched off of a second one of NMOS and PMOS regions 116, 118, as shown in FIG. 2, leaving high-k dielectric layer 130 exposed over the second one of NMOS and PMOS regions 116, 118. In this case, high-k dielectric layer 130 of NMOS region 116 is exposed. This is in contrast to conventional techniques that would remove high-k dielectric layer 130 from NMOS region 116. First metal 140 may be removed using any now known or later developed technique, e.g., depositing a photoresist, patterning and etching the photoresist and etching first metal 140 using the photoresist. It is emphasized that first metal 140 may be for either NMOS region 116 or PMOS region 118, i.e., the order of which region is generated first may switch without departing from the scope of the disclosure. Where first metal 140 is over PMOS region 118, first metal 140 may include, but is not limited to: titanium nitride (TiN), ruthenium (Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium (V) and aluminum (Al).
  • FIG. 3 shows depositing a second metal 150 having a work function commensurate with the second one of NMOS and PMOS regions 116, 118 over implanted substrate 120. In the illustrative case, the second one is the NMOS region 116. Where second metal 150 is over NMOS region 116, second metal 150 may include, but is not limited to: titanium nitride (TiN}, ruthenium (Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium (V) and aluminum (Al). It is understood that the metal over NMOS may be also selected from this list when it is the first metal deposited, rather than the second as illustrated. Similarly, it is understood that the metal over PMOS may be selected from the above-described list therefor when it is the second metal deposited, rather than the first as illustrated.
  • FIG. 4 shows an optional process that includes depositing a capping layer 160 over implanted substrate 120 prior to depositing second metal 150, then depositing second metal 150. Capping layer 160 can take a variety of forms. In one embodiment, capping layer 160 includes but is not limited to a dielectric such as: lanthanum oxide (La2O3), dysprosium oxide (DyO), yttrium oxide (Y2O3), barium oxide (BaO), strontium oxide (SrO), scandium oxide (ScO), cerium oxide (CeO), praseodymium oxide (PrO), neodymium (NdO), gadolinium oxide (GdO), erbium oxide (ErO). In this case, capping layer 160 may provide extra threshold voltage (Vt) shift—here NFET capping layer. In another embodiment, capping layer 160 may include a metal such as, but not limited to: lanthanum (La), dysprosium (Dy), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd), erbium (Er). In another embodiment, as shown in FIG. 5, capping layer 160 includes a metal, typically a rare earth metal, that reacts with high-k dielectric layer 130 over the first one of the NMOS and PMOS regions (i.e., NMOS region 116 as illustrated) to form a dielectric 180, but remains metallic 190 over the second one of the NMOS and PMOS regions 116, 118 (i.e., PMOS region 116 as illustrated). The rare earth metal may include a multilayer composite of metals (known as a bilayer). In terms of dielectric 180, rare earth metal reacts with the oxygen in high-k dielectric layer 130 to form an oxide that is formed from the rare earth metal. Where rare earth metal 190 remains metallic it is sealed between first metal 140 and second metal 150, and thus is sealed against reaction with the atmosphere. Capping layer 160 may include a rare earth metal such as, but not limited to: ytterbium (Yb), dysprosium (Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd) and erbium (Er).
  • FIG. 5 shows depositing a polysilicon 170 over implanted substrate 120 based on the FIG. 4 embodiment. FIG. 6 shows patterning to form a first gate stack 194 over NMOS region 116 and a second gate stack 196 over PMOS region 118 on implanted substrate 120. As understood, each gate stack 194, 196 eventually becomes a gate electrode 194, 196 for an n-type field effect transistor (NFET) 202 and a p-type field effect transistor (PFET) 200, respectively. An integrated circuit 210 including PFET 200 and NFET 202 thus includes a first type transistor (i.e., PFET 200 as illustrated) having gate electrode 194 including a first metal 140, a second metal 150 having a work function commensurate with the second type transistor (i.e., NFET 202 as illustrated) and a first dielectric layer 130 including oxygen. IC 210 also includes a second type transistor (i.e., NFET 202 as illustrated) separated from first type transistor (PFET) 200 by an isolation region 126. The second type transistor (NFET) 202 includes gate electrode 196 including second metal 150 and first dielectric layer 130. Gate electrode 194 of first type transistor (PFET) 200 also includes a rare earth metal 190 between first metal 140 and second metal 150, and gate electrode 196 of second type transistor (NFET) 202 includes a second dielectric layer 180 made of an oxide of the rare earth metal. First dielectric layer 130 is under first metal 140 in PFET 200 so as to act as a gate dielectric for gate electrode 194. Similarly, second dielectric layer 180 contacts first dielectric layer 130 in first type transistor (NFET) 202, and thus collectively act as a gate dielectric for gate electrode 196. Each gate electrode 194, 196 further includes a polysilicon portion 170. In one embodiment, second metal 150 in first type transistor (PFET) 200 and second type transistor (NFET) 202 are electrically coupled, which is impossible with conventional processing due to the gap that forms between devices during the patterning and removal process.
  • As also shown in FIG. 6, a transistor 200 includes gate stack 194 including high-k dielectric layer 130 over substrate 120, first metal 140 having a work function commensurate with a well 124 in the substrate, capping layer 160 including a rare earth metal 190 over first metal 140, a second metal 150 over capping layer 160, and a polysilicon 170 over second metal 150. In this case, second metal 150 has a work function incompatible with well 124 (p-well) in substrate 120, i.e., it is harmful to threshold voltage (Vt) if allowed to impact operation. Transistor (NFET) 202 includes a gate stack 196 including high-k dielectric layer 130 over substrate 120, capping layer 160 including an oxide 180 of a rare earth metal over high-k dielectric layer 130, a metal 150 over the oxide of the rare earth metal, the metal having a work function commensurate with a well 122 (n-well) in substrate 120, and a polysilicon 170 over the metal 150.
  • The above-described methods, IC and transistors incorporate a capping layer in the form of an rare earth metal to intermix with high-k dielectric layer 130 (and not the metal 150) to shift the work function of the NMOS region 116 to band-edge, but when interposed in the metals 140, 150 they do not cause a threshold voltage shift in the PMOS region 118. In addition, the methods allow for meeting of ground rules, and do not require removal of both NMOS and PMOS region metals form the opposing region. The methods also allow for butted junctions with the NFET 202 always self-aligned to PFET 200 since only one metal layer is removed over isolation region 126, i.e., second metal 150.
  • The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
  • The foregoing description of various aspects of the disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the disclosure as defined by the accompanying claims.

Claims (25)

1. A method comprising:
providing an implanted substrate with a n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region;
depositing a high dielectric constant (high-k) dielectric layer over the implanted substrate;
forming a first metal having a work function commensurate with a first one of the NMOS region and the PMOS region over the first one of the NMOS and the PMOS regions only, leaving the high-k dielectric layer exposed over a second one of the NMOS and PMOS regions;
depositing a second metal having a work function commensurate with the second one of the NMOS region and the PMOS region over the implanted substrate;
depositing a polysilicon over the implanted substrate; and
patterning to form a first gate stack over the NMOS region and a second gate stack over the PMOS region on the implanted substrate.
2. The method of claim 1, further comprising depositing a capping layer over the implanted substrate prior to depositing the second metal.
3. The method of claim 2, wherein the capping layer includes a dielectric.
4. The method of claim 3, wherein the capping layer is selected from the group consisting of: lanthanum oxide (La2O3), dysprosium oxide (DyO), yttrium oxide (Y2O3), barium oxide (BaO), strontium oxide (SrO), scandium oxide (ScO), cerium oxide (CeO), praseodymium oxide (PrO), neodymium (NdO), gadolinium oxide (GdO), erbium oxide (ErO).
5. The method of claim 2, wherein the capping layer includes a metal.
6. The method of claim 5, wherein the capping layer is selected from the group consisting of: lanthanum (La), dysprosium (Dy), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd), erbium (Er).
7. The method of claim 2, wherein the high-k dielectric layer includes oxygen and the capping layer includes a rare earth metal that reacts with the high-k dielectric over the first one of the NMOS region and the PMOS region to form a dielectric, and remains metallic over the second one of the NMOS region and the PMOS region.
8. The method of claim 7, wherein the capping layer is selected from the group consisting of: ytterbium (Yb), dysprosium (Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd) and erbium (Er).
9. The method of claim 1, wherein the high-k dielectric layer is selected from the group consisting of: hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), hafnium silicon oxide (HfSiOx), hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), yttrium oxide (Y2O3), strontium oxide (SrO) and strontium titanium oxide (SrTiO).
10. The method of claim 1, wherein the first one of the NMOS and PMOS region is the PMOS region, and the first metal is selected from the group consisting of: titanium nitride (TiN), ruthenium (Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium (V) and aluminum (Al).
11. The method of claim 1, wherein the second one of the NMOS and PMOS region is the NMOS region, and the second metal is selected from the group consisting of: titanium nitride (TiN), ruthenium (Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium (V) and aluminum (Al).
12. An integrated circuit comprising:
a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen;
a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and
wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
13. The IC of claim 12, wherein the first dielectric layer is under the first metal in the gate electrode in the first type transistor.
14. The IC of claim 12, wherein the second dielectric layer contacts the first dielectric layer in the second type transistor.
15. The IC of claim 12, wherein the first type transistor includes an p-type field effect transistor (PFET) and the second type transistor includes a n-type field effect transistor (NFET).
16. The IC of claim 12, wherein each gate electrode further includes a polysilicon portion.
17. The IC of claim 12, wherein the second metal in the first type transistor and the second type transistor are electrically coupled.
18. The IC of claim 12, wherein the rare earth metal is selected from the group consisting of: ytterbium (Yb), dysprosium (Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd) and erbium (Er).
19. A transistor comprising:
a gate stack including:
a high dielectric constant (high-k) dielectric layer over a substrate,
a capping layer including an oxide of a rare earth metal over the high-k dielectric layer,
a metal over the oxide of the rare earth metal, the metal having a work function commensurate with a well in the substrate, and
a polysilicon over the metal.
20. The transistor of claim 19, wherein the rare earth metal is selected from the group consisting of: ytterbium (Yb), dysprosium (Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd) and erbium (Er).
21. The transistor of claim 19, wherein the high-k dielectric layer is selected from the group consisting of: hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), hafnium silicon oxide (HfSiOx), hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), yttrium oxide (Y2O3), strontium oxide (SrO) and strontium titanium oxide (SrTiO).
22. A transistor comprising:
a gate stack including:
a high dielectric constant (high-k) dielectric layer over a substrate, the high-k dielectric layer including oxygen,
a first metal having a work function commensurate with a well in the substrate,
a capping layer including a rare earth metal over the first metal,
a second metal over the capping layer, the second metal having a work function incompatible with the well in the substrate, and
a polysilicon over the second metal.
23. The transistor of claim 22, wherein the rare earth metal is selected from the group consisting of: ytterbium (Yb), dysprosium (Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd) and erbium (Er).
24. The transistor of claim 22, wherein the high-k dielectric layer is selected from the group consisting of: hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), hafnium silicon oxide (HfSiOx), hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), yttrium oxide (Y2O3), strontium oxide (SrO) and strontium titanium oxide (SrTiO).
25. The transistor of claim 22, wherein the well is a p-type well.
US11/954,749 2007-12-12 2007-12-12 High-k/metal gate stack using capping layer methods, ic and related transistors Abandoned US20090152636A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/954,749 US20090152636A1 (en) 2007-12-12 2007-12-12 High-k/metal gate stack using capping layer methods, ic and related transistors
US13/433,659 US9236314B2 (en) 2007-12-12 2012-03-29 High-K/metal gate stack using capping layer methods, IC and related transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/954,749 US20090152636A1 (en) 2007-12-12 2007-12-12 High-k/metal gate stack using capping layer methods, ic and related transistors

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/433,659 Division US9236314B2 (en) 2007-12-12 2012-03-29 High-K/metal gate stack using capping layer methods, IC and related transistors

Publications (1)

Publication Number Publication Date
US20090152636A1 true US20090152636A1 (en) 2009-06-18

Family

ID=40752068

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/954,749 Abandoned US20090152636A1 (en) 2007-12-12 2007-12-12 High-k/metal gate stack using capping layer methods, ic and related transistors
US13/433,659 Expired - Fee Related US9236314B2 (en) 2007-12-12 2012-03-29 High-K/metal gate stack using capping layer methods, IC and related transistors

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/433,659 Expired - Fee Related US9236314B2 (en) 2007-12-12 2012-03-29 High-K/metal gate stack using capping layer methods, IC and related transistors

Country Status (1)

Country Link
US (2) US20090152636A1 (en)

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080277736A1 (en) * 2007-05-08 2008-11-13 Kazuaki Nakajima Semiconductor device and method of manufacturing the same
US20090090971A1 (en) * 2007-09-20 2009-04-09 Interuniversitair Microelektronica Centrum Vzw (Imec) Mosfet devices and methods for making them
US20090212369A1 (en) * 2008-02-26 2009-08-27 International Business Machines Corporation Gate Effective-Workfunction Modification for CMOS
US20090230479A1 (en) * 2008-03-12 2009-09-17 Peng-Fu Hsu Hybrid Process for Forming Metal Gates of MOS Devices
US20090294867A1 (en) * 2008-05-30 2009-12-03 Lee Byoung H Dual metal gates using one metal to alter work function of another metal
US20100059833A1 (en) * 2008-09-11 2010-03-11 Chih-Hao Yu Metal gate transistor and method for fabricating the same
US20100102393A1 (en) * 2008-10-29 2010-04-29 Chartered Semiconductor Manufacturing, Ltd. Metal gate transistors
US20100327364A1 (en) * 2009-06-29 2010-12-30 Toshiba America Electronic Components, Inc. Semiconductor device with metal gate
US20110001194A1 (en) * 2007-01-23 2011-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Process for Forming Metal Gates
US20110223756A1 (en) * 2010-03-11 2011-09-15 Schaeffer James K Method of Enhancing Photoresist Adhesion to Rare Earth Oxides
US20110291198A1 (en) * 2010-05-27 2011-12-01 International Business Machines Corporation Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices
CN102299155A (en) * 2010-06-22 2011-12-28 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
US20120080760A1 (en) * 2010-10-01 2012-04-05 National Chiao Tung University Dielectric structure, transistor and manufacturing method thereof
US20120139014A1 (en) * 2010-12-01 2012-06-07 International Business Machines Corporation Structure and method for low temperature gate stack for advanced substrates
US20120187502A1 (en) * 2009-10-20 2012-07-26 International Business Machines Corporation Application of cluster beam implantation for fabricating threshold voltage adjusted fets
US20130032872A1 (en) * 2011-08-05 2013-02-07 Silicon Storage Technology, Inc. Non-volatile Memory Cell Having A High K Dielectric And Metal Gate
CN103165606A (en) * 2011-12-16 2013-06-19 台湾积体电路制造股份有限公司 Enhanced gate replacement process for high-k metal gate technology
US8492852B2 (en) 2010-06-02 2013-07-23 International Business Machines Corporation Interface structure for channel mobility improvement in high-k metal gate stack
CN103367132A (en) * 2012-03-29 2013-10-23 台湾积体电路制造股份有限公司 Method of fabricating a metal gate semiconductor device
US8853751B2 (en) * 2012-06-28 2014-10-07 International Business Machines Corporation Reducing the inversion oxide thickness of a high-K stack fabricated on high mobility semiconductor material
KR20150054422A (en) * 2013-11-12 2015-05-20 에스케이하이닉스 주식회사 Method and gate ructure for threshold voltage modulation in transistors
US20150263124A1 (en) * 2012-08-29 2015-09-17 Ps4 Luxco S.A.R.L. Semiconductor device, and method for producing same
US9153584B2 (en) * 2008-06-09 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor device and a method of manufacturing same
US9177956B2 (en) * 2013-07-31 2015-11-03 Globalfoundries Inc. Field effect transistor (FET) with self-aligned contacts, integrated circuit (IC) chip and method of manufacture
US20150325681A1 (en) * 2014-05-06 2015-11-12 GlobalFoundries, Inc. Methods of fabricating integrated circuits
US9190409B2 (en) 2013-02-25 2015-11-17 Renesas Electronics Corporation Replacement metal gate transistor with controlled threshold voltage
US9553092B2 (en) 2015-06-12 2017-01-24 Globalfoundries Inc. Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
US20170154890A1 (en) * 2015-11-30 2017-06-01 Samsung Electronics Co., Ltd. One time programmable memory device, method of manufacturing the same, and electronic device including the same
US9859392B2 (en) 2015-09-21 2018-01-02 Samsung Electronics Co., Ltd. Integrated circuit device and method of manufacturing the same
CN109801878A (en) * 2017-11-16 2019-05-24 三星电子株式会社 Semiconductor device and the method for gate structure is provided for its multiple component
US10319818B2 (en) 2017-10-30 2019-06-11 International Business Machines Corporation Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end
US10804158B2 (en) * 2018-04-10 2020-10-13 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices including differing barrier layer structures

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102066851B1 (en) 2013-02-25 2020-02-11 삼성전자 주식회사 Semiconductor device and the fabricating method thereof
KR102056582B1 (en) 2013-06-05 2020-01-22 삼성전자 주식회사 Semiconductor device and method for the same
US11088258B2 (en) * 2017-11-16 2021-08-10 Samsung Electronics Co., Ltd. Method of forming multiple-Vt FETs for CMOS circuit applications
US11289579B2 (en) 2019-09-29 2022-03-29 Applied Materials, Inc. P-type dipole for p-FET
US12112951B2 (en) 2022-02-17 2024-10-08 Applied Materials, Inc. Integrated dipole region for transistor

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020142624A1 (en) * 2000-09-19 2002-10-03 Mattson Technology, Inc. Method of forming dielectric films
US20040023478A1 (en) * 2002-07-31 2004-02-05 Samavedam Srikanth B. Capped dual metal gate transistors for CMOS process and method for making the same
US20040106249A1 (en) * 2002-12-03 2004-06-03 Hannu Huotari Method to fabricate dual metal CMOS devices
US20050224897A1 (en) * 2004-03-26 2005-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. High-K gate dielectric stack with buffer layer to improve threshold voltage characteristics
US20050280105A1 (en) * 2004-06-22 2005-12-22 International Business Machines Corporation Method of forming metal/high-k gate stacks with high mobility
US20060084247A1 (en) * 2004-10-20 2006-04-20 Kaiping Liu Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation
US7105889B2 (en) * 2004-06-04 2006-09-12 International Business Machines Corporation Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics
US20070148838A1 (en) * 2005-12-28 2007-06-28 International Business Machines Corporation Metal gate CMOS with at least a single gate metal and dual gate dielectrics
US20070152276A1 (en) * 2005-12-30 2007-07-05 International Business Machines Corporation High performance CMOS circuits, and methods for fabricating the same
US7378713B2 (en) * 2006-10-25 2008-05-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with dual-metal gate structures and fabrication methods thereof
US20090039447A1 (en) * 2007-08-06 2009-02-12 Copel Matthew W FET Device with Stabilized Threshold Modifying Material

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7445976B2 (en) * 2006-05-26 2008-11-04 Freescale Semiconductor, Inc. Method of forming a semiconductor device having an interlayer and structure therefor
US7863124B2 (en) * 2007-05-10 2011-01-04 International Business Machines Corporation Residue free patterned layer formation method applicable to CMOS structures

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020142624A1 (en) * 2000-09-19 2002-10-03 Mattson Technology, Inc. Method of forming dielectric films
US20040023478A1 (en) * 2002-07-31 2004-02-05 Samavedam Srikanth B. Capped dual metal gate transistors for CMOS process and method for making the same
US20040106249A1 (en) * 2002-12-03 2004-06-03 Hannu Huotari Method to fabricate dual metal CMOS devices
US20050224897A1 (en) * 2004-03-26 2005-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. High-K gate dielectric stack with buffer layer to improve threshold voltage characteristics
US7105889B2 (en) * 2004-06-04 2006-09-12 International Business Machines Corporation Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics
US20050280105A1 (en) * 2004-06-22 2005-12-22 International Business Machines Corporation Method of forming metal/high-k gate stacks with high mobility
US7115959B2 (en) * 2004-06-22 2006-10-03 International Business Machines Corporation Method of forming metal/high-k gate stacks with high mobility
US20060289903A1 (en) * 2004-06-22 2006-12-28 Wanda Andreoni Method of forming metal/high-k gate stacks with high mobility
US20060084247A1 (en) * 2004-10-20 2006-04-20 Kaiping Liu Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation
US20070148838A1 (en) * 2005-12-28 2007-06-28 International Business Machines Corporation Metal gate CMOS with at least a single gate metal and dual gate dielectrics
US20070152276A1 (en) * 2005-12-30 2007-07-05 International Business Machines Corporation High performance CMOS circuits, and methods for fabricating the same
US7378713B2 (en) * 2006-10-25 2008-05-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with dual-metal gate structures and fabrication methods thereof
US20090039447A1 (en) * 2007-08-06 2009-02-12 Copel Matthew W FET Device with Stabilized Threshold Modifying Material

Cited By (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8836038B2 (en) 2007-01-23 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS dual metal gate semiconductor device
US20110001194A1 (en) * 2007-01-23 2011-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Process for Forming Metal Gates
US7768076B2 (en) * 2007-05-08 2010-08-03 Kabushiki Kaisha Toshiba Semiconductor device comprising an n-channel and p-channel MISFET
US20080277736A1 (en) * 2007-05-08 2008-11-13 Kazuaki Nakajima Semiconductor device and method of manufacturing the same
US20090090971A1 (en) * 2007-09-20 2009-04-09 Interuniversitair Microelektronica Centrum Vzw (Imec) Mosfet devices and methods for making them
US7812413B2 (en) * 2007-09-20 2010-10-12 Imec MOSFET devices and methods for making them
US20110121401A1 (en) * 2008-02-26 2011-05-26 International Business Machines Corporation Gate Effective-Workfunction Modification for CMOS
US7947549B2 (en) * 2008-02-26 2011-05-24 International Business Machines Corporation Gate effective-workfunction modification for CMOS
US20090212369A1 (en) * 2008-02-26 2009-08-27 International Business Machines Corporation Gate Effective-Workfunction Modification for CMOS
US8183642B2 (en) 2008-02-26 2012-05-22 International Business Machines Corporation Gate effective-workfunction modification for CMOS
US20090230479A1 (en) * 2008-03-12 2009-09-17 Peng-Fu Hsu Hybrid Process for Forming Metal Gates of MOS Devices
US8536660B2 (en) * 2008-03-12 2013-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid process for forming metal gates of MOS devices
US8236686B2 (en) * 2008-05-30 2012-08-07 International Business Machines Corporation Dual metal gates using one metal to alter work function of another metal
US20090294867A1 (en) * 2008-05-30 2009-12-03 Lee Byoung H Dual metal gates using one metal to alter work function of another metal
US9646892B2 (en) 2008-06-09 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor device and a method of manufacturing same
US9153584B2 (en) * 2008-06-09 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor device and a method of manufacturing same
US20100059833A1 (en) * 2008-09-11 2010-03-11 Chih-Hao Yu Metal gate transistor and method for fabricating the same
US8404535B2 (en) 2008-09-11 2013-03-26 United Microelectronics Corp. Metal gate transistor and method for fabricating the same
US8084824B2 (en) * 2008-09-11 2011-12-27 United Microelectronics Corp. Metal gate transistor and method for fabricating the same
US20100102393A1 (en) * 2008-10-29 2010-04-29 Chartered Semiconductor Manufacturing, Ltd. Metal gate transistors
US20100327364A1 (en) * 2009-06-29 2010-12-30 Toshiba America Electronic Components, Inc. Semiconductor device with metal gate
US20120187502A1 (en) * 2009-10-20 2012-07-26 International Business Machines Corporation Application of cluster beam implantation for fabricating threshold voltage adjusted fets
US8557652B2 (en) 2009-10-20 2013-10-15 International Business Machines Corporation Application of cluster beam implantation for fabricating threshold voltage adjusted FETs
US8492848B2 (en) * 2009-10-20 2013-07-23 International Business Machines Corporation Application of cluster beam implantation for fabricating threshold voltage adjusted FETs
US8415212B2 (en) 2010-03-11 2013-04-09 Freescale Semiconductor, Inc. Method of enhancing photoresist adhesion to rare earth oxides
US20110223756A1 (en) * 2010-03-11 2011-09-15 Schaeffer James K Method of Enhancing Photoresist Adhesion to Rare Earth Oxides
US8940599B2 (en) * 2010-05-27 2015-01-27 International Business Machines Corporation Scaled equivalent oxide thickness for field effect transistor devices
US20110291198A1 (en) * 2010-05-27 2011-12-01 International Business Machines Corporation Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices
US8343839B2 (en) * 2010-05-27 2013-01-01 International Business Machines Corporation Scaled equivalent oxide thickness for field effect transistor devices
US20120286363A1 (en) * 2010-05-27 2012-11-15 International Business Machines Corporation Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices
US20140199828A1 (en) * 2010-05-27 2014-07-17 International Business Machines Corporation Scaled equivalent oxide thickness for field effect transistor devices
US8716813B2 (en) * 2010-05-27 2014-05-06 International Business Machines Corporation Scaled equivalent oxide thickness for field effect transistor devices
US8492852B2 (en) 2010-06-02 2013-07-23 International Business Machines Corporation Interface structure for channel mobility improvement in high-k metal gate stack
CN102299155A (en) * 2010-06-22 2011-12-28 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
US20120080760A1 (en) * 2010-10-01 2012-04-05 National Chiao Tung University Dielectric structure, transistor and manufacturing method thereof
US20120139014A1 (en) * 2010-12-01 2012-06-07 International Business Machines Corporation Structure and method for low temperature gate stack for advanced substrates
CN103748686A (en) * 2011-08-05 2014-04-23 硅存储技术公司 A non-volatile memory cell having a high k dielectric and metal gate
TWI473210B (en) * 2011-08-05 2015-02-11 Silicon Storage Tech Inc A non-volatile memory cell having a high k dielectric and metal gate
US20130032872A1 (en) * 2011-08-05 2013-02-07 Silicon Storage Technology, Inc. Non-volatile Memory Cell Having A High K Dielectric And Metal Gate
WO2013022618A1 (en) * 2011-08-05 2013-02-14 Silicon Storage Technology, Inc. A non-volatile memory cell having a high k dielectric and metal gate
KR101552448B1 (en) * 2011-08-05 2015-09-10 실리콘 스토리지 테크놀로지 인크 A non-volatile memory cell having a high k dielectric and metal gate
US8883592B2 (en) * 2011-08-05 2014-11-11 Silicon Storage Technology, Inc. Non-volatile memory cell having a high K dielectric and metal gate
CN103165606A (en) * 2011-12-16 2013-06-19 台湾积体电路制造股份有限公司 Enhanced gate replacement process for high-k metal gate technology
US20130154021A1 (en) * 2011-12-16 2013-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced gate replacement process for high-k metal gate technology
US9177870B2 (en) * 2011-12-16 2015-11-03 Taiwan Semiconductor Manufacturing Company Ltd. Enhanced gate replacement process for high-K metal gate technology
US9691876B2 (en) 2011-12-16 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced gate replacement process for high-K metal gate technology
CN103367132A (en) * 2012-03-29 2013-10-23 台湾积体电路制造股份有限公司 Method of fabricating a metal gate semiconductor device
US8865551B2 (en) * 2012-06-28 2014-10-21 International Business Machines Corporation Reducing the inversion oxide thickness of a high-k stack fabricated on high mobility semiconductor material
US8853751B2 (en) * 2012-06-28 2014-10-07 International Business Machines Corporation Reducing the inversion oxide thickness of a high-K stack fabricated on high mobility semiconductor material
US20150263124A1 (en) * 2012-08-29 2015-09-17 Ps4 Luxco S.A.R.L. Semiconductor device, and method for producing same
US9786762B2 (en) * 2012-08-29 2017-10-10 Longitude Semiconductor S.A.R.L. Gate electrode of a semiconductor device, and method for producing same
US9190409B2 (en) 2013-02-25 2015-11-17 Renesas Electronics Corporation Replacement metal gate transistor with controlled threshold voltage
US9177956B2 (en) * 2013-07-31 2015-11-03 Globalfoundries Inc. Field effect transistor (FET) with self-aligned contacts, integrated circuit (IC) chip and method of manufacture
US9281310B2 (en) 2013-11-12 2016-03-08 SK Hynix Inc. Semiconductor device including gate structure for threshold voltage modulation in transistors and method for fabricating the same
US9548304B2 (en) * 2013-11-12 2017-01-17 SK Hynix Inc. Semiconductor device including gate structure for threshold voltage modulation in transistors and method for fabricating the same
KR102128450B1 (en) * 2013-11-12 2020-06-30 에스케이하이닉스 주식회사 Method and gate ructure for threshold voltage modulation in transistors
KR20150054422A (en) * 2013-11-12 2015-05-20 에스케이하이닉스 주식회사 Method and gate ructure for threshold voltage modulation in transistors
US9472465B2 (en) * 2014-05-06 2016-10-18 GlobalFoundries, Inc. Methods of fabricating integrated circuits
US20150325681A1 (en) * 2014-05-06 2015-11-12 GlobalFoundries, Inc. Methods of fabricating integrated circuits
US9553092B2 (en) 2015-06-12 2017-01-24 Globalfoundries Inc. Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
US9905476B2 (en) 2015-06-12 2018-02-27 Globalfoundries Inc. Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
US9859392B2 (en) 2015-09-21 2018-01-02 Samsung Electronics Co., Ltd. Integrated circuit device and method of manufacturing the same
US10312341B2 (en) 2015-09-21 2019-06-04 Samsung Electronics Co., Ltd. Integrated circuit device and method of manufacturing the same
US20170154890A1 (en) * 2015-11-30 2017-06-01 Samsung Electronics Co., Ltd. One time programmable memory device, method of manufacturing the same, and electronic device including the same
CN106910740A (en) * 2015-11-30 2017-06-30 三星电子株式会社 One Time Programmable storage device
US10186516B2 (en) * 2015-11-30 2019-01-22 Samsung Electronics Co., Ltd. One time programmable memory device, method of manufacturing the same, and electronic device including the same
US10686039B2 (en) 2017-10-30 2020-06-16 International Business Machines Corporation Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end
US10319818B2 (en) 2017-10-30 2019-06-11 International Business Machines Corporation Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end
US10686040B2 (en) 2017-10-30 2020-06-16 International Business Machines Corporation Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end
CN109801878A (en) * 2017-11-16 2019-05-24 三星电子株式会社 Semiconductor device and the method for gate structure is provided for its multiple component
US10804158B2 (en) * 2018-04-10 2020-10-13 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices including differing barrier layer structures

Also Published As

Publication number Publication date
US20120184093A1 (en) 2012-07-19
US9236314B2 (en) 2016-01-12

Similar Documents

Publication Publication Date Title
US9236314B2 (en) High-K/metal gate stack using capping layer methods, IC and related transistors
US8021939B2 (en) High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods
US8383483B2 (en) High performance CMOS circuits, and methods for fabricating same
US10424517B2 (en) Method for manufacturing a dual work function semiconductor device and the semiconductor device made thereof
CN101421839B (en) Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled cmos devices
US8704280B2 (en) Semiconductor device with strained channels induced by high-k capping metal layers
US7592678B2 (en) CMOS transistors with dual high-k gate dielectric and methods of manufacture thereof
US7425497B2 (en) Introduction of metal impurity to change workfunction of conductive electrodes
US6653698B2 (en) Integration of dual workfunction metal gate CMOS devices
US8685814B2 (en) Transistor device and method of manufacture thereof
US7432567B2 (en) Metal gate CMOS with at least a single gate metal and dual gate dielectrics
US8053306B2 (en) PFET with tailored dielectric and related methods and integrated circuit
EP2112687B1 (en) Method for fabricating a dual workfunction semiconductor device and the device made thereof
US8105892B2 (en) Thermal dual gate oxide device integration
US20120273890A1 (en) Method of Fabricating a Gate Stack Integration of Complementary MOS Device
US8786022B2 (en) Semiconductor device and semiconductor device manufacturing method
US20100308418A1 (en) Semiconductor Devices and Methods of Manufacture Thereof
KR20110050599A (en) Changing effective work function using ion implantation during dual work function metal gate integration
US7833849B2 (en) Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode
US8846474B2 (en) Dual workfunction semiconductor devices and methods for forming thereof
US20090250760A1 (en) Methods of forming high-k/metal gates for nfets and pfets

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHUDZIK, MICHAEL P;MOUMEN, NAIM;NARAYANAN, VIJAY;AND OTHERS;REEL/FRAME:020235/0018;SIGNING DATES FROM 20071115 TO 20071130

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910

AS Assignment

Owner name: ALSEPHINA INNOVATIONS INC., CANADA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049709/0871

Effective date: 20181126