US20090148594A1

US20090148594A1 - Interconnection element with plated posts formed on mandrel

Info

Publication number: US20090148594A1
Application number: US12/228,896
Authority: US
Inventors: Sean Moran; Jinsu Kwon; Kimitaka Endo
Original assignee: Tessera LLC
Current assignee: Adeia Semiconductor Solutions LLC
Priority date: 2007-08-15
Filing date: 2008-08-15
Publication date: 2009-06-11
Also published as: EP2186132B1; US8505199B2; WO2009023284A3; WO2009023283A2; US20090145645A1; JP2010537403A; US20130286619A1; WO2009023283A3; WO2009023284A2; US9282640B2; KR101542478B1; CN101809735A; KR20100061462A; EP2186132A2; EP2186132A4; CN101809735B

Abstract

An interconnection element can be formed by plating a metal layer within holes in an essentially non-metallic layer of a mandrel, wherein posts can be plated onto a metal layer exposed within the holes, e.g., a metal layer covering the holes in the non-metallic layer. The tips of the posts can be formed adjacent to ends or bottoms of the blind holes. Terminals can be formed in conductive communication with the conductive posts. The terminals can be connected through a dielectric layer to the conductive posts. At least a portion of the mandrel can then be removed from at least ends of the holes. In this way, the tips of the conductive posts can become raised above a major surface of the interconnection element such that at least the tips of the posts project beyond the major surface.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of the filing dates of U.S. Provisional Application No. 60/964,823 filed Aug. 15, 2007 and 61/004,308 filed Nov. 26, 2007, the disclosures of which are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

The subject matter of the present application relates to microelectronic interconnection elements and assemblies and fabrication methods therefor, and more particularly to microelectronic interconnection elements and assemblies having protruding metal posts, especially metal posts defined by plating.
A current need exists to provide interconnection elements, e.g., chip carriers, package substrates, substrates of multiple chip modules, and other similar elements suitable for surface-mounting (flip-chip interconnection) of a microelectronic element thereon. Such need is felt especially for microelectronic elements which have fine-pitch contacts. With traditional technologies such as solder-to-solder interconnections, e.g., arrays of solder bumps, or bumps formed by screen-printing technology, it is becoming increasingly difficult to form conductive bumps of sufficient volume for flip-chip interconnection. The need is felt especially where the pitch of the conductive bumps is smaller than 150 microns.

SUMMARY OF THE INVENTION

In accordance with an embodiment, a method is provided for fabricating an interconnection element, such as a package element, chip carrier, or other such element for interconnection to a microelectronic element, e.g., a semiconductor chip or packaged semiconductor chip.
The interconnection element can have raised conductive posts for conductive interconnection with another element, e.g., an element having least one of microelectronic devices or wiring thereon. In accordance with an embodiment, a first element, e.g., a mandrel, is provided on which features can be plated. The first element can include an essentially non-metallic layer having a top surface, a bottom surface remote from the top surface and a plurality of holes extending between the top and bottom surfaces. A lower metal layer can overlie the bottom surface of the essentially non-metallic layer such that the lower metal layer covers the bottoms of the holes. Within such blind holes of the first element a metal layer can be plated to form conductive posts having tips adjacent to ends or bottoms of the blind holes. Terminals can be formed in conductive communication with the conductive posts. The terminals can be connected through a dielectric layer to the conductive posts. At least a portion of the first element can then be removed from at least the ends of the holes. In this way, the tips of the conductive posts can become raised above a major surface of the interconnection element such that at least the tips of the posts project beyond the major surface.
In one embodiment, the first element can be formed by joining the lower metal layer with the essentially non-metallic layer and then forming the plurality of holes. In one example, the lower metal layer can consist essentially of copper. In a particular embodiment, the holes can have a pitch less than about 150 microns.
In one embodiment, when removing the first element or portion thereof, it can be removed selectively relative to a metal layer that spans the holes. Such hole-spanning metal layer can be disposed entirely between the top and bottom surfaces of the essentially non-metallic layer. In a particular embodiment, such hole-spanning metal layer can be plated onto a surface of the first metal layer which is exposed within the holes. The hole-spanning metal layer may not fully cover interior walls of the holes.
In a particular embodiment, a metal liner lines the holes of the first element when the metal layer is plated within the blind holes of the first element. Subsequently, the first element or portion thereof can be removed selectively relative to the metal liner. The metal layer can be such that it resists attack by an etchant used to selectively etch the first element. In one example, the metal liner can be a first metal layer which contacts a surface of an essentially non-metallic layer exposed within the holes. In such case, the formation of the conductive posts can include forming a second metal layer which contacts the first metal layer. In one embodiment, the first metal layer can be formed by processing including plating. In such case, the second metal layer can be plated onto the first metal layer.
In one embodiment, the second metal layer can fill the space overlying the metal liner within the holes. In a particular embodiment, the metal liner includes nickel. In a particular embodiment, the second metal layer includes copper. In one embodiment, the metal line can include nickel and the second metal layer can include copper.
In one embodiment, a plurality of conductive traces connected to the conductive posts can be formed at locations away from the tips of the conductive posts, such traces being formed simultaneously with the posts. In a particular embodiment, gaps between the conductive traces can be formed by subtractive processing after plating the metal layer. Alternatively, or in addition thereto, gaps between the conductive traces can be defined by plating the metal in an additive manner between features of a mask layer.
In accordance with an embodiment, a method is provided for fabricating an interconnection element. In such method, a metal can be plated within a plurality of blind holes of a first element, e.g., a mandrel, to form a plurality of conductive posts having tips formed adjacent to ends of the blind holes. Each conductive post may include a second metal layer which contacts a first metal layer that lines the holes of the first element. In one embodiment, the second metal layer can be resistant to attack by an etchant which attacks the first metal layer. Terminals can be formed which are exposed at a bottom surface of a dielectric layer of the interconnection element. The formed terminals can be in conductive communication with the conductive posts. At least a portion of the first element which is adjacent to the ends of the holes can then be removed. In such way, at least portions, e.g., at least the tips, of the conductive posts can be caused to protrude beyond a major surface of the interconnection element.
In accordance with an embodiment, a method is provided for fabricating an interconnection element. In such method, a metal can be plated within a plurality of blind holes of a first element, e.g., a mandrel, to form a plurality of conductive posts having tips formed adjacent to ends of the blind holes. In such case, the first element, e.g., mandrel, can include a first metal layer and a second metal layer which extends along the first metal layer. A third layer can overlie the first and second metal layers. The first element can have a plurality of holes extending through the third layer so as to form a plurality of blind holes atop the second metal layer, with the second metal layer exposed within the blind holes at ends thereof.
A metal layer can then be plated within the blind holes to form a plurality of conductive posts having tips formed adjacent to the ends of the blind holes. Each conductive post may further include a third metal layer in contact with the second metal layer. In one embodiment, such third metal layer can be resistant to attack by an etchant which attacks the first metal layer. Terminals can be formed which are exposed at a surface of a dielectric layer of the interconnection element. The terminals can be in conductive communication with the conductive posts. After forming the posts, at least a portion of the first element adjacent to the ends of the blind holes can be removed. In this way, at least portions of the conductive posts may be caused to protrude beyond the surface of the interconnection element.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 13A are fragmentary sectional views illustrating a series of stages in a method of fabricating an interconnection element in accordance with an embodiment.

FIG. 13B is a fragmentary plan view corresponding to

FIG. 13A illustrating an interconnection element in accordance with an embodiment.

FIG. 14A is a fragmentary sectional view illustrating a microelectronic assembly including an interconnection element as illustrated in FIGS. 13A-B as assembled with a microelectronic element and circuit panel in accordance with an embodiment.

FIG. 14B is a fragmentary plan view illustrating an interconnection element in accordance with a variation of the embodiment illustrated in FIGS. 13A-B.

FIG. 14C is a fragmentary sectional view illustrating a microelectronic assembly including an interconnection element as depicted in FIG. 14B, together with a microelectronic element and circuit panel connected thereto in accordance with a variation of the embodiment shown in FIG. 14A.

FIG. 14D is a fragmentary plan view illustrating an interconnection element in accordance with a variation of the embodiment illustrated in FIGS. 13A-B.

FIGS. 15 through 17 are fragmentary sectional views illustrating a series of stages in a method of fabricating an interconnection element in accordance with a variation of the embodiment shown in FIGS. 1 through 13B.

FIGS. 18 through 26 are fragmentary sectional views illustrating a series of stages in a method of fabricating an interconnection element in accordance with another variation of the embodiment described with respect to FIGS. 1 through 13B.

FIGS. 27 and 28 are fragmentary sectional views illustrating a series of stages in a method of fabricating an interconnection element in accordance with a variation of the embodiment described with respect to FIGS. 18 through 26.

FIG. 29 through 39 are fragmentary sectional views illustrating a series of stages in a method of fabricating an interconnection element in accordance with another variation of the embodiment described with respect to FIGS. 1 through 13B.

FIGS. 40 and 41 are fragmentary sectional views illustrating a series of stages in a method of fabricating an interconnection element in accordance with a variation of the embodiment described with respect to FIGS. 29 through 39.

FIG. 42 through 48 are fragmentary sectional views illustrating a series of stages in a method of fabricating an interconnection element in accordance with another variation of the embodiment described with respect to FIGS. 1 through 13B.

FIGS. 49 and 50 are fragmentary sectional views illustrating a series of stages in a method of fabricating an interconnection element in accordance with a variation of the embodiment described with respect to FIGS. 42 through 48.

DETAILED DESCRIPTION

As used in this disclosure, a terminal, contact, layer or other feature “exposed at” a surface of a dielectric element may be flush with such surface; recessed relative to such surface; or protruding from such surface, so long as that feature is accessible for contact by a theoretical point moving towards the surface in a direction perpendicular to the surface.
In accordance with an embodiment, a method will now be described for fabricating an interconnection element having raised conductive posts formed by plating, the posts usable to conductively connect the interconnection element to another element such as a microelectronic element or a wiring element, e.g., a circuit panel. As will be discussed in detail below, through use of an interconnection element having protruding conductive posts as discussed herein, interconnection can be provided to microelectronic elements or other elements having arrays of contacts arranged at a fine pitch, e.g., at a pitch less than 150 microns as measured center-to-center.
FIG. 1 illustrates a preliminary stage in fabrication of an interconnection element in accordance with an embodiment. As illustrated therein, a metal layer 102, e.g., a continuous sheet or foil consisting essentially of a metal is joined with a patternable layer 104. The patternable layer 104 can consist essentially of a single material or can be composed of a variety of materials. In one example, the patternable layer includes or consists essentially of a dielectric material. For example, without limitation, a polymeric layer or other layer of organic or inorganic material can be utilized as layer 104. In another example, the patternable layer can include or consist essentially of one or more semiconductor materials. In another example, the patternable layer can include or consist essentially of a metal. The patternable layer forms a portion of a mandrel on which features, i.e., conductive posts of the interconnection element are formed. The conductive posts typically are solid metal structures formed on interior walls of holes in the mandrel, as will be discussed in the following. After forming the conductive posts, the patternable layer is removed, or in some cases may be recessed in height, such that the conductive posts extend beyond a major surface of that layer. A copper layer, for example, can be patterned in accordance with methods as described herein and can be subsequently removed.
When the patternable layer 104 includes a polymeric layer, the layer may also be a sacrificial layer as used. In an exemplary embodiment, the patternable layer can have a thickness ranging from greater than ten microns up to more than one hundred microns. The metal layer 102 need not be very thick; its thickness can range upwards from a few microns to a few tens of microns, for example. The patternable layer 104 can be formed separately from the metal layer 102 and then joined thereto via a lamination process such as, for example, press lamination or roll lamination. A polymeric patternable layer can be formed by depositing an uncured material onto the metal layer by various means, such as, without limitation, roller coating, spin-coating, spray deposition or by contacting an underlying surface of the metal layer with a bath of the uncured material. The viscosity and characteristics of the deposition can be selected or modulated so as to achieve a patternable layer having the desired thickness. Multiple depositions can be utilized, if necessary to achieve a desired thickness or material characteristics of the patternable layer.
In a variation of the above-described process, the metal layer 102 can be formed by electroplating onto the patternable layer 104 after an appropriate electrically conductive commoning layer (not shown) is formed on layer 104, such as by electroless plating or sputtering, for example.
As illustrated in FIG. 2, the patternable layer is patterned to form holes 106 extending from an exposed surface 108 of the patternable layer 104 to the underlying metal layer 102. For example, a photoimageable layer (not shown) can be deposited onto the exposed surface 108 and patterned to form openings in a mask layer, such as by photolithography, after which the holes 106 are formed by etching layer 104 by applying an etchant thereto through the openings in the mask layer. Etching the layer 104 results in the holes 106 having sloped walls 110 which are tapered inwardly such that the dimensions 112, e.g., diameter of each hole at the exposed surface 108 are larger than the dimensions 114 of each hole at the metal layer 102.
Alternatively, the holes can be patterned by optical ablation, e.g., laser drilling, such as by laser light. In some cases, the laser light may have visible or ultraviolet wavelengths or a combination of visible and non-visible wavelengths. For example, the through holes can be formed by drilling using a laser such as an ultraviolet wavelength (UV) YAG laser, i.e., one made from yttrium aluminum garnet (YAG) which typically is doped with neodymium or other dopant. Holes produced by such UV YAG laser can have walls 110 which are nearly vertical, i.e., at relatively small angles to the vertical direction, where “vertical” is defined by a normal angle to the top surface 104. Thus, in the direction from the top surface to the bottom surface the walls 110 slant inward such that the width 110 of the through holes becomes smaller in that direction. Through holes in an element having a thickness 105 of 70 microns can be drilled to widths 112 of 50 microns, for example, and can be arranged at a pitch 116 such as 60 microns. Of course, through holes having greater widths and pitch can be attained within such element, as needed.
In a variation of the above process, the patternable layer 104 can be patterned to form through holes therein prior to joining with the metal layer 102, such as through use of a mechanical drilling or punching apparatus or laser drilling apparatus. After patterning, the layer 104 having through holes therein is joined with the metal layer 102, such as by press lamination or roll lamination, for example.
Subsequently, as illustrated in FIG. 3, a first plated layer 122 is formed on the metal layer 102 and walls 110 of the holes 106 in the mandrel 120. To promote formation of layer 122, an electrical commoning layer can be deposited initially to form an electrically conductive film lining the holes, such as by electroless plating, chemical vapor deposition (CVD) or physical vapor deposition (PVD) (sputtering). Subsequently, the first plated layer 122 is formed by electroplating. The first plated may consist essentially of a metal which is not attacked by an etchant that attacks the underlying metal of the conductive mandrel 120. For example, when the conductive mandrel 120 consists essentially of copper, the first metal layer can include or consist essentially of a metal such as nickel. Such layer is plated or deposited to a sub-micron thickness or to a thickness of a few microns, for example, 3 microns. Etchants are known which can be used to etch copper features while selectively preserving nickel features with which they come in contact. The importance of the type of metal used in the first plated layer will become apparent from the description of subsequent processing below.
As illustrated in FIG. 4, a second plated layer 124 is electroplated onto the first plated layer 122. The second plated layer overlies the first plated layer 122 and fills the remaining space within the holes 106. The electroplating process results in the second plated layer also overlying the top surface 108 of the mandrel 120. In a particular embodiment, the second plated layer includes or consists essentially of copper.
Subsequently, as illustrated in FIG. 5, a mask layer 128 is provided atop an exposed surface 126 of the second plated layer. For example, a photoimageable layer, e.g., a photoresist, can be deposited and patterned by photolithography to form the mask layer 128 as shown in FIG. 5. Thereafter, as illustrated in FIG. 6, the second plated layer is patterned in accordance with the mask layer to form conductive features, e.g., conductive traces 131 and individual conductive posts 130 of the second plated layer. For example, the second plated layer 124 can be patterned by selective etching with respect to a metal included in the first plated layer. Illustratively, using a suitable etchant, a second plated layer consisting essentially of copper can be patterned selectively with respect to an underlying first plated layer 122 which may consist essentially of nickel. FIG. 6 illustrates the structure after etching the second plated layer and subsequently removing the mask layer.
As illustrated in FIG. 7, a dielectric layer 132 of the structure is formed such that it overlies the exposed bases 133 of the conductive posts 130. The dielectric layer can be formed by any suitable method such as by pressing or laminating a partially cured layer thereto, with or without the application of heat, or can be formed using a flowable dielectric material which optionally may be hardened or densified through subsequent treatment such as heating.
Referring to FIG. 8, the dielectric layer 132 is patterned to form openings extending downward from a top surface 140 of the dielectric layer 130 to expose at least portions of the conductive posts. The openings 134 are formed in alignment, e.g., in axial alignment, with the conductive posts 130. In one example, the dielectric layer 132 can be patterned by photolithographically patterning openings in a resist layer (not shown) atop the dielectric layer, followed by etching the dielectric layer through the openings in the resist layer. Alternatively, the openings can be formed by laser drilling with a CO2 laser or excimer laser, for example.
Subsequently, a third metal layer is electroplated onto the structure to form conductive vias 136 filling the holes 134, as well as a metal layer 142 extending along the top surface 140. In one example, the third metal layer consists essentially of copper. A conductive layer, e.g., a conductive seed layer may be first formed in the openings and exposed surfaces of the dielectric layer as an electrical commoning prior to plating the third metal layer thereon.
FIG. 9 illustrates the third metal layer after subsequent patterning to form individual traces 138 or other features extending along the top surface 140.
Subsequently, as illustrated in FIG. 9, a second dielectric layer 144 is formed and holes are patterned therein. A fourth metal layer then is electroplated thereon to fill the holes in the second dielectric layer, forming second conductive vias 146 and other conductive features 150, e.g., traces 150, pads, or both atop the dielectric layer 144. The second dielectric layer 144 can be formed and patterned in similar manner to the first dielectric layer 132 and the fourth metal layer can be formed and patterned in similar manner to the third metal layer. In one example, the fourth metal layer consists essentially of copper. Through such processing, the structure now includes two wiring layers 142, 148 at different levels which are conductively interconnected by conductive vias 146. Each of the wiring layers 142, 148 may include metal lines or metal traces 138, 150 which are oriented in the same direction or in different directions from each other. In this way, metal lines 138 can be used to conductively connect the vias 136 and metal lines 150 can be used to connect vias 146. Wiring layer 148 may also include conductive pads 151 overlying some of the vias 146.
Thereafter, the metal layer 102 then is removed to result in the structure as illustrated in FIG. 10, such as by etching selectively with respect to the metal of the first plated layer. The view shown in FIG. 10 is inverted in relation to that shown in FIG. 9.
Subsequently, the remaining layer 104 (FIG. 10) of the mandrel is removed, resulting in the structure as illustrated in FIG. 11. For example, the layer 104 can be a sacrificial structure which is removed by selectively etching the material of the mandrel so as to preserve the material of the first plated layer 122 within the holes. In a particular example, the first plated layer 122 consists essentially of nickel and the layer 104 is etched selectively with respect to nickel. Subsequently, the first plated layer 122 can be removed by selective etching with respect to the underlying second plated layer 124, such that the second plated layer 124 becomes exposed as illustrated in FIG. 12. When the second plated layer 124 and exposed fourth metal layer 148 each consist essentially of copper, a selective etching process can be applied to safely remove the first plated layer 122 having a different metal composition without attacking the exposed second and fourth layers.
As a result, the conductive posts 130 now extend upwardly away from an exposed bottom surface 152 of the dielectric layer 132. The resulting conductive posts may have different possible shapes. For example, the posts may have frusto-conical shape, of which tips 160 can be flat or essentially flat. Alternatively, the posts may be cylindrical in shape. Other shapes are also possible, which may include posts which are elongated in a horizontal direction, i.e., in a direction parallel to the major surface 152 of the dielectric element, such that the posts may appear as rails protruding from the dielectric element 132.
The conductive posts extend a height 164 from an exposed major surface 152 of the dielectric layer. In one embodiment, the height can range from a few tens of microns to a few hundred microns, depending on the depth of the holes 106 within the mandrel 120 (FIG. 2) used to form the conductive posts. The pitch 166, defined as the distance between centers of adjacent conductive posts, can range upwards from several tens of microns. The conductive posts at the bases thereof have width 168 which can range upwards from a few tens of microns. At tips 160, the conductive posts can have width 161 which may be the same, nearly the same, or somewhat smaller than the width 168 at the base of the conductive posts. In a particular example, the height 164 of each post is approximately 70 microns, the width 168 at the base is approximately 60 microns, and the width 161 at the tip of approximately 50 microns is nearly the same as the base width 168. In such example, the pitch 166 can range upwards from 80 microns, for example, a pitch of 100 microns.
Through fabrication of the conductive posts using mandrel 120 having holes of regular height 105 (FIG. 2), the tips of the conductive posts can be made co-planar to facilitate joining of the conductive posts with co-planar features of another conductive element. Moreover, by plating within holes of a mandrel 120 conductive posts 130 can be produced which have broad tips having the same width or nearly the same width as the bases of the posts. These features can be beneficial when joining the conductive posts to lands, conductive pads or conductive bumps of a microelectronic element, e.g., a semiconductor chip having devices thereon, or alternatively, to a wiring element, e.g., a circuit panel.
In subsequent processing, solder masks 156, 158 may be formed overlying each of the bottom and major surfaces 152, 154 of the dielectric layer, respectively. After forming the solder masks, optionally a finish metal layer 162 such as gold or other metal may be applied to exposed tips 160 of the posts and terminals 151 exposed within openings in solder mask 158, resulting in the interconnection element 170 as illustrated in FIG. 13A.
The interconnection element 170 (FIG. 13A) can be relatively thin, having a sheet-like dielectric element 187 formed by the combination of dielectric layers 132 and 144 with a thickness 185 from as little as a few tens of microns. The dielectric element typically has lateral dimensions in directions along its major surface 176 (in a direction of the pitch 166 of posts and a second direction transverse thereto) which range upwards from a few millimeters to one hundred millimeters or more. The dielectric element can be flexible, rigid or semi-rigid, depending upon its thickness and the elastic modulus of the dielectric material or materials from which it is fabricated.
As shown in plan view in FIG. 13B, the posts 130 typically are laid out in a grid pattern corresponding with a land grid array (“LGA”) or ball grid array (“BGA”) exposed at the surface 175 of the microelectronic element. Alternatively, the posts 130 can be laid out in a plurality of rows or in a perimeter or radial layout arrangement.
As further shown in FIGS. 13A-B, traces 250, 252, 254 extend in at least one direction along a major surface 176 of the dielectric layer 187. For example, one dimension of the traces 250, 252, 254 is in a direction 173 to which the posts depicted in FIG. 13A are aligned. Alternatively, or in addition thereto, the traces 250, 252, 254 can extend in a direction 179 along the major surface of the dielectric layer 187 which is transverse to the direction in which the posts are aligned. For example, the traces 250, 252 and 254 can be disposed as shown in FIG. 13B, such that the traces extend in a direction into and out of the plane in which the interconnect element is depicted in FIG. 13A. As depicted in FIGS. 13A-B, traces 250, 252, 254 can be electrically insulated from adjacent metal posts 130, e.g., posts 130 a, 130 b, 130 c and 130 d. However, as illustrated in FIG. 13B, trace 250 is conductively connected with post 130 e and trace 252 is conductively interconnected with post 130 f.
In one example, interconnection element can function as a package substrate or chip carrier in a package including the microelectronic element and interconnection element. FIG. 14A illustrates the interconnection element 170 as joined in flip-chip manner with a microelectronic element 172, e.g., a semiconductor chip having active devices, passive devices or both active and passive devices thereon. The interconnection element may function as a fan-out element with features 138 carrying signals, voltages and ground to and from the microelectronic element to locations beyond edges of the microelectronic element. Thus, the contacts 174 of the chip have a pitch 195 in a left-right direction shown and the metal posts 130, 130 a can have a pitch 166 which matches the pitch 195 of the chip contacts 174. Alternatively, the interconnection element can function as a carrier to which a plurality of microelectronic elements and optionally other circuit elements, e.g., integrated passive devices, discrete passive devices or discrete active devices or a combination thereof are directly connected.
The tips 160 of the conductive posts, which protrude beyond an upper face 176 of the interconnection element 170, are joined to corresponding conductive pads 174 of the microelectronic element. As illustrated in FIG. 14A, the posts can be joined to the microelectronic element through a fusible metal such as a solder, tin or a eutectic composition, the fusible metal wetting the posts and the pads to form wetted or soldered joints. For example, the fusible metal can be provided in form of solder bumps 177, exposed at a surface 175 of the microelectronic element, the bumps being provided on conductive pads 174 having suitable under bump metal structures. In another example, solder masses or tin carried on the tips 160 of the conductive posts can form part of the joints. Alternatively, the posts of the interconnection element can be joined to the conductive pads without intervening masses of solder, such as through a diffusion bond formed between a finish metal at the tips 160 of the posts, e.g., gold, and another metal present in the conductive pads and the posts.
The conductive posts 130, which are solid metal structures throughout, have relatively high current-carrying capacity, making the interconnection element suitable for interconnection with microelectronic elements, i.e., chips having high current density. Elements typically included within a processor such as microprocessors, co-processors, logic chips, and the like, have high current density and typically also have high interconnect density (high numbers of relatively fine pitch pads 174). The high current-carrying capacity of the solid metal posts 130 of interconnection element 170 make them suitable for interconnection with such chips.
At a lower face 178 of the interconnection element, terminals 151 are joined to corresponding terminals 182 of a circuit panel, wiring element, packaged microelectronic element or other conductive element. For example, as illustrated in FIG. 14, the terminals 151 can be joined to terminals 182 of a circuit panel 184 via conductive masses 180. In one example, the conductive masses 180 can include a fusible metal such as solder, tin or a eutectic composition.
FIGS. 14B-C illustrate a variation of the above-described embodiment in which a trace 354 extends in a direction 173 along the major surface of the dielectric element such that it conductively connects adjacent posts 130 a′, 130 b′. Some traces, e.g., trace 350 can be conductively connected to one adjacent conductive post 130 c′. Other traces, e.g., trace 352, can be disposed between adjacent conductive posts 130 b′, 130 c′ and be electrically insulated from the adjacent conductive posts by the dielectric element 187 including dielectric layer 132.
In another variation, although not specifically depicted in FIG. 14B, traces along the surface of the dielectric element need not be conductively connected to any of the conductive posts.
In yet another variation (FIG. 14D) of the above-described embodiment, there need not be any traces extending along the major surface 176′ of the dielectric element. Instead, only the conductive posts 130 may be present at surface 176′ of the dielectric element, the conductive posts projecting outwardly from the surface.
In another variation of the above-described embodiment (FIGS. 1-13B), processing which forms the second dielectric layer and fourth metal layer as described above with reference to FIG. 9 is omitted. In such case, the resulting interconnection element does not include the second dielectric layer. Terminals of the interconnection element are formed using the metal features 138 of the third metal layer. Such interconnection element may function as a chip carrier to provide fan-out as described above.
FIGS. 15 through 17 illustrate a method of forming an interconnection element in accordance with a variation of the above-described embodiment. Referring to FIG. 15, after forming the first plated layer 122 in accordance with the processing described above (FIG. 3), a photoimageable layer 190, e.g., a photoresist, is deposited onto an exposed surface of the first plated layer 122. Subsequently, as illustrated in FIG. 16, the photoimageable layer 190 is patterned, e.g., via photolithography, to form a mask layer 192 as shown. The mask layer can include mask patterns 194 overlying portions of the first plated layer above the major surface 108 of the mandrel. Thereafter, as illustrated in FIG. 17, the second plated layer 124 is plated onto portions of the first plated layer 122 which are exposed by the mask patterns 194.
In an embodiment according to another variation of the above-described method (FIG. 18), instead of forming a first plated layer which fully covers exposed walls of the holes 106 and the major surface 108 of the mandrel, metal plugs 222 are formed by electroplating onto a surface of the metal layer 102 exposed within each hole 106. Such plated plug 222 can include a metal which resists attack by an etchant usable to pattern a metal included in the metal layer 102. For example, the plug 222 may consist essentially of nickel when the metal layer 102 consists essentially of copper. The metal plugs can be formed by omitting the above-described formation of an electrical commoning layer, e.g., a conductive seed layer, such as formed by electroless plating, sputtering or other technique. In such case, the metal plugs 222 are formed by electroplating onto the exposed surfaces of the metal layer 102 within the holes 106 and the metal plugs form only in contact with the metal layer 102. During such electroplating step, a lower surface 226 of the first metal layer is covered by a dielectric film, carrier or other material to avoid metal from being plated onto that surface.
Subsequently, as illustrated in FIG. 19, a second plated layer 224 is formed within the holes 106 and overlying the major surface 108 of the mandrel. The second plated layer 224 can be formed by electroplating a metal, e.g., such as copper onto the walls 109 within the holes 106 and onto the major surface 108 of the mandrel. An electrical commoning layer, e.g., a conductive seed layer can be formed on the walls 109 of the holes and exposed major surface 108 of the mandrel to facilitate coverage onto the surfaces. Referring to FIGS. 20 through FIG. 25, processing is performed as described above with respect to FIGS. 5 through 10 to pattern the second metal layer 224 and form additional metal layers defining features, e.g., wiring traces, pads, conductive vias etc. In this case, portions of the second metal layer 224 which are exposed by a masking layer 228 (FIG. 20) are removed from above the major surface 108 (FIG. 21) of the mandrel, such as by a selective etching process.
The plugs 222 may remain attached to the posts 230 when the mandrel is removed from the posts 230 (FIG. 26). The plugs can then be removed from the posts 230 via subsequent etching performed selectively with respect to the material of the posts and the second plated layer 224.
FIGS. 27 and 28 illustrate a variation of the embodiment (FIGS. 18 through 26) in which the patterns of the second plated layer 224 are formed by way of a semi-additive electroplating process onto portions of the major surface 108 exposed by a masking layer 294, similar to the process described above with reference to FIGS. 15-17.
Referring to FIGS. 29 through 39, a process will now be described in accordance with another variation of the above-described embodiment (FIGS. 1-13). As illustrated in FIG. 29, a first plated layer 301 is formed which uniformly covers the first metal layer 302. The first plated layer 301 can include a metal which is not attacked by an etchant suitable for etching the metal layer 302. In a particular example, the first metal layer 302 includes or consists essentially of copper and the first plated layer includes or consists essentially of nickel. As illustrated in FIG. 30, the first metal layer with the first plated layer thereon then is joined, e.g., laminated, with a patternable layer 304 to form a mandrel 320.
Subsequently, as illustrated in FIG. 31, holes 306 are formed which extend inwardly from the major surface 308 of the mandrel. As a result, the first plated layer 301 becomes exposed within the holes 308. In one embodiment, the material of the mandrel 320 is removed selectively with respect to the metal included in the first plated layer 301.
Subsequently, as illustrated in FIGS. 32 through 37, further processing is performed as described above with reference to FIGS. 4 through 9. Thereafter, as illustrated in FIG. 38, the first metal layer is removed selectively with respect to the first plated layer 301, leaving the first plated layer overlying layer 304 of the mandrel. The first plated layer can then be removed from the mandrel layer 304 and tips 360 of the posts 330, resulting in the structure as illustrated in FIG. 39. Further processing can then be performed to complete the interconnect element as described above with respect to FIGS. 12 and 13A-B.
FIGS. 40 and 41 illustrate a variation of the embodiment (FIGS. 29-39) in which the second plated layer is formed by a semi-additive process, such as described above with reference to FIGS. 15 through 17.
Referring to FIGS. 42 through 48, in another variation of the above-described embodiment, the first plated layer is omitted. In such embodiment, the first metal layer 402 can be include or consist essentially of one or more metals. For example, the first metal layer can include or consist essentially of copper and, after formation of an electrically conductive commoning layer, a layer 424 of copper can then be plated onto exposed surfaces of the mandrel to form the structure as illustrated in FIG. 42. Referring to FIGS. 43 through 47, processing can then be performed as described above (FIGS. 5 through 9) to form an interconnect element on the mandrel 420. Subsequently, as illustrated in FIG. 48, the first metal layer is removed from the mandrel. A variety of methods can be use to remove the metal layer, such as, without limitation, selective or non-selective etching, or mechanically, e.g., as by polishing or peeling.
Finally, as illustrated in FIGS. 49 through 50, in an alternative embodiment, the plated layer 424′ (FIG. 50) can be formed by way of a semi-additive process on portions of the surface 408 exposed by patterns 494 of a mask layer 492 (FIG. 49). The mask layer 492 can be formed after forming the electrically conductive commoning layer on the mandrel 420, such that the plated layer 424′ (FIG. 50) forms on surfaces not covered by the mask layer 492.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A method of fabricating an interconnection element having raised conductive posts for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon, comprising:

a) plating a metal within a plurality of blind holes of a first element to form conductive posts having tips formed adjacent to ends of the blind holes, the first element including an essentially non-metallic layer having a top surface, a bottom surface remote from the top surface and a plurality of holes extending between the top and bottom surfaces, the first element including a lower metal layer overlying the bottom surface of the essentially non-metallic layer, the lower metal layer covering the holes;

b) forming terminals in conductive communication with the conductive posts, the terminals being connected through a dielectric layer to the conductive posts; and

c) removing at least a portion of the first element at the ends of the holes to cause the tips of the conductive posts to become raised above a major surface of the interconnection element.

2. The method as claimed in claim 1, wherein the first element is formed by joining the lower metal layer with the essentially non-metallic layer and then forming the plurality of holes.

3. The method as claimed in claim 1, wherein the at least a portion of the first element is removed selectively relative to a hole-spanning metal layer disposed entirely between the top and bottom surfaces of the essentially non-metallic layer.

4. The method as claimed in claim 3, further comprising plating the hole-spanning metal layer onto a surface of the first metal layer exposed within the holes.

5. The method as claimed in claim 4, wherein the hole-spanning metal layer does not fully cover walls of the holes.

6. The method as claimed in claim 1, wherein a metal liner lines the holes of the first element when step (a) is performed and the at least a portion of the first element is removed selectively relative to the metal liner.

7. The method as claimed in claim 6, wherein the metal liner resists attack by an etchant used to selectively etch the first element.

8. The method as claimed in claim 7, wherein the metal liner is a first metal layer contacting a surface of an essentially non-metallic layer exposed within the holes and step (a) includes forming a second metal layer contacting the first metal layer.

9. The method as claimed in claim 8, further comprising forming the first metal layer by processing including plating.

10. The method as claimed in claimed in claim 9, wherein second metal layer is plated onto the first metal layer.

11. The method as claimed in claim 9, wherein the second metal layer fills the space overlying the metal liner within the holes.

12. The method as claimed in claim 9, wherein the metal liner includes nickel and the second metal layer includes copper.

13. The method as claimed in claim 1, wherein the lower metal layer consists essentially of copper and the holes have a pitch less than about 150 microns.

14. The method as claimed in claim 1, wherein the conductive posts have frusto-conical shape.

15. The method as claimed in claim 1, wherein conductive posts have cylindrical shape.

16. The method as claimed in claim 1, wherein step (a) includes forming a plurality of conductive traces connected to the conductive posts at locations away from the tips.

17. The method as claimed in claim 16, wherein step (a) further comprises defining gaps between the conductive traces by subtractive processing after plating the metal layer.

18. The method as claimed in claim 16, wherein gaps between the conductive traces are defined by plating the metal in additive manner between features of a mask layer.

19. A method of fabricating an interconnection element, comprising:

a) plating a metal within a plurality of blind holes of a first element to form a plurality of conductive posts having tips formed adjacent to ends of the blind holes, each conductive post including a second metal layer contacting a first metal layer lining the holes, the second metal layer being resistant to attack by an etchant which attacks the first metal layer;

b) forming terminals exposed at a bottom surface of a dielectric layer, the terminals being in conductive communication with the conductive posts; and

c) removing at least a portion of the first element adjacent to the ends of the holes to cause at least portions of the conductive posts to protrude beyond the surface of the interconnection element.

20. A method of fabricating an interconnection element, comprising:

a) providing a first element including a first metal layer, a second metal layer extending along the first metal layer and a third layer overlying the first and second metal layers, the first element having a plurality of holes extending through the third layer to form a plurality of blind holes atop the second metal layer and the second metal layer being exposed at ends of the blind holes;

b) plating a metal within the blind holes to form a plurality of conductive posts having tips formed adjacent to the ends of the blind holes, each conductive post including a third metal layer contacting the second metal layer, the third metal layer being resistant to attack by an etchant which attacks the first metal layer;

c) forming terminals exposed at a surface of a dielectric layer, the terminals being in conductive communication with the conductive posts; and

d) removing at least a portion of the first element adjacent to the ends of the blind holes to cause at least portions of the conductive posts to protrude beyond the surface of the interconnection element.