US20090017729A1

US20090017729A1 - Polishing pad and methods of improving pad removal rates and planarization

Info

Publication number: US20090017729A1
Application number: US11/574,188
Authority: US
Inventors: Dwaine Halberg; Peter Renteln
Original assignee: JH Rhodes Co Inc
Current assignee: JH Rhodes Co Inc
Priority date: 2004-08-25
Filing date: 2005-08-24
Publication date: 2009-01-15

Abstract

A method of improving a removal rate of a pad includes producing a body of a pad of polyurethane from a mix; and introducing into the mix an additive which decreases an elastic rebound of the pad so as to increase a chemical-mechanical planarization removal rate; and using as the additive a substance which at least contains starch. In another embodiment, in a CMP process that includes removing a barrier and buffing a polyurethane after a bulk copper removal process, a polishing pad is used having a shore D hardness less than 35% and having at least one layer made from a mix composed of at least one of a prepolymer with an isocyanate concentration of between 6.5% and 11.0% to achieve a molal concentration, and a monomer in combination with an addition of isocyanate to achieve the substantially same molal concentration.

Description

BACKGROUND OF THE INVENTION

The present invention generally relates to polishing pads, and, in particular to chemical-mechanical polishing (CMP) with a slurry. Moreover, the present invention relates to methods for increasing the CMP removal rate of polishing pads, improving the planarization of work pieces by polishing pads, and improving the General Planarization Efficiency of polishing pads.
CMP is a process step in the semiconductor fabrication sequence that has generally become an integral part of the manufacture of semiconductor wafers. CMP is used in a variety of applications in the semiconductor fabrication sequence. For example, CMP is used in applications referred to as “oxide” or “ILD/PMD”, “STI”, “copper”, “barrier”, “poly” and “tungsten”. These terms generally indicate the type of material that is being removed. The CMP process preferably is configured to expediently remove material and planarize the surface, while leaving it defect free and contamination free. Each of these applications may use a different slurry, and therefore the removal mechanism is generally different for each application. For that reason, the optimal condition of each of the applications tends to be different as well.
In each of these CMP processes, a silicon substrate is placed in direct contact with a moving polishing pad. A wafer carrier applies pressure against the backside of the substrate, usually while simultaneously rotating the pad. During this process a slurry is made available, and is generally carried between the wafer and the pad by the motion of the pad. The composition of the slurry may vary from one CMP application to another. In general, slurries that are designed to remove insulating materials consist of water, an abrasive and an alkali formulation designed to “hydrolyze” the insulating material. Copper slurries on the other hand, generally comprise a combination of: water, an abrasive, an oxidizing agent, a complexing agent, and a chemical to passivize the surface. A typical slurry often has very low removal rate on a material it was not designed to remove.
The CMP polishing pad preferably performs a plurality of engineering functions. The pad may desirably be configured to polish at a high removal rate, planarize short (<100 micrometer) distances, planarize long (>100 micrometer) distances up to a certain Planarization Length (see below) determined by the quality of the silicon substrate, not planarize beyond that length, transport slurry, maintain the same friction with the wafer for wafers polished sequentially and without interruptions for hundreds of wafers, clean the wafer surface, not scratch the wafer surface, be replaceable in minimal time, and/or other functions.
Thus, it is desirable to develop methods of making a pad that can improve one or more of these functions of polishing pads. In particular, it is desirable to improve the removal rate of the polishing pad, to improve the planarization of work pieces, and to improve the General Planarization Efficiency of polishing pads.
In this regard, various aspects of the present invention contemplate both short and long range planarization. Generally, long range planarization is controlled by the bulk properties of the pad and short range planarization is controlled by the surface properties of the pad. A concept useful in describing long range planarization is the Planarization Length (L), defined as a lateral dimension characteristic of the pad's ability to planarize. Intrinsic to this concept is Preston's equation, which maintains that when polishing, the removal rate is proportional to force. There are significant deviations to this relationship, but it holds generally. A feature that is to be planarized may be modeled as an upraised element. A polishing pad will try to planarize this feature, and will succeed in doing so when the pressure exerted by the pad at the top of the feature exceeds the pressure exerted adjacent to the feature. According to the Preston equation, the removal rate at the top of the feature will exceed the removal rate adjacent to the feature and over time the feature will decrease in height with polishing. One definition of planarization length is the distance from the feature that the pressure has increased to 1/e of the pressure infinitely far from the feature (e is ln(10)).
Short range planarization has no analog to L. Since the short range planarization is affected by the surface properties, it can vary dramatically using the same polishing pad by varying the amount of diamond conditioning received by the pad, an action that affects the pad's surface roughness. However, generally the pad surface is conditioned for the purpose of maintaining the removal rate. Therefore with regard to short range planarization, the engineering constraint placed on the pad is rather results-oriented. If written, it would read something like, “. . . when consistently using a standard conditioning process the pad should exhibit adequate removal rate as well as high short range planarization . . . ”. Because of this, the short range planarization requirement generally comes from empirical results. For the copper application, these results would typically be expressed in dishing, which describes the amount of material removed from a narrow copper line. For oxide applications, the results would typically be expressed by the planarization performance of a test structure designed to measure short range planarization.
Various U.S. patents contemplate improvements in planarization. See, James, U.S. Pat. Nos. 6,454,634, 6,582,283, 6,736,709 and 6,749,485. While James offers an example of an additive that allegedly achieves a desired high KEL value, the teachings and data support the desired property only for what has been described above as short range planarization, namely planarization which occurs over a distance of less than 100 micrometers.
Thus, it is desirable to develop formulations which improve both short and long range planarization.
A specific application of CMP is known as “copper CMP,” which entails the polishing of a copper film deposited on the work surface of a semiconductor wafer. The copper is typically deposited through the use of electro-deposition, and is typically deposited on a surface in which submicron channels in the underlying oxide layer have been created. The copper is deposited in the channels as well as on top of the areas between channels (the “field”). The copper deposited in the field between channels is often called the “overburden.” A “barrier layer” is provided on the oxide surface before depositing the copper since the copper would otherwise diffuse into the oxide layer and potentially reach the sensitive silicon substrate below, destroying the transistors. Accordingly, the barrier clads the copper channels, preventing diffusion of the copper into the oxide. Typical materials for the barrier layer are tantalum (Ta) and tantalum nitride (TaN). During copper CMP, both the copper overburden and the barrier layer are removed from the field by polishing, leaving the copper in the channels to act as conducting interconnecting lines.
The objective of the CMP process is to remove substantially all of the copper from the field area and leave the copper in the trenches at the level of the oxide. The surface of the copper in the channels is preferably flat and substantially without oxidation, contamination or corrosion on its surface. These conditions are also desirable for other larger areas of copper known as “bond pads,” which allow probes to make contact with the conductor, and are typically 100 um by 50-75 μm in dimension. The process is usually performed in three steps, involving three rotating platens normally found on commercially available CMP tools. The steps include: 1) removal of the bulk copper; 2) removal of the barrier layer; and 3) buffing of the final surface to remove substantially all residue and to passivate the copper surface. After these three steps, the wafer may be cleaned and dried prior to further processing. Often, the step of removal of the copper is divided into two steps. In the first step, half or more of the copper film is removed leaving the surface substantially planar. In the second step, the remainder of the copper is removed, leaving only barrier material.
There are, therefore, two primary process sequences used on a three-platen tool during conventional copper CMP. In the first sequence, Sequence #1, Platen 1 removes bulk copper to the barrier material, Platen 2 removes the barrier material and Platen 3 buffs. In the second sequence, Sequence #2, Platen 1 removes bulk copper, Platen 2 finishes copper removal, and Platen 3 removes barrier material and buffs. There also exist small variations to these two sequences that could include variations in the chemistries and slurries used, the processing conditions and times, and the exact division of all the required steps. The polishing pads and slurries/chemistries used in these three steps are generally different.
In one example, a typical way to carry out process Sequence #1 could be to use the following: Platen 1) An IC1000 pad (such as supplied by Rohm and Haas) and a copper slurry such as Cabot 5001; Platen 2) An IC1000 pad and a barrier slurry such as Hitachi T-605; and Platen 3) A Politex pad (such as supplied by Rohm and Haas) and water or water and a passivize chemical such as BTA. Conversely, a typical way to carry out process Sequence #2 could be to use the following: Platen 1) An IC1000 pad and a copper slurry such as Cabot 5001; Platen 2) An IC1000 pad and a copper slurry such as Cabot 5001; Platen 3) A Politex pad and a barrier slurry such as Hitachi T-605, followed by a rinse with water or water and BTA for passivation.
Step 3 in the last case could also be performed with an IC1000 pad, but is much more typically performed with a Politex pad. The disadvantage of using the Politex for this purpose is that the pad is basically too soft for the application. A typical Politex pad is composed of several layers. The bottom layer is a polyurethane impregnated polyester felt. The next layer is a very porous urethane, and the top layer consists of vertical urethane structures having tapered pores which are wider on the bottom and narrower on top.
Although the softness of the pad is advantageous in delivering a very nice final surface (buff), both clean and scratch-free, the net result of using this pad for the barrier removal step is that the resulting planarity of the wafer is poor. As a barrier remover, the pad is exposed initially to both copper and tantalum simultaneously and later when the barrier is cleared, to oxide, copper and tantalum simultaneously. A pad with poor planarizing properties will do a poor job of uniformly removing these materials. This nonplanarity can result in bridging (a conductive material remaining where it is supposed to be removed resulting in undesired electrical contact), dishing/erosion (material being removed by the process that should remain in place causing an increase in resistivity if it is copper or shorts if it is oxide), or undesirable surface features that encourage bridging.
Another issue with the use of the Politex pad is the relatively low lifetime of the pad. In the presence of certain chemicals, the pad will tend to lose integrity, resulting in shortened lifetime. In general, the blown polyurethane material is chemically inert, and is not known to disintegrate in the presence of any of the chemicals it is normally exposed to during CMP.
The alternative case, using the highly planarizing, highly inert, IC1000 on the third platen will result in a very planar surface without the problems listed above, but with a much higher rate of scratching. Scratching, of course, is unacceptable as it can result in shorts (bridging) and opens (a conductive line interrupted). Thus a need exists for a pad having various properties in a range between those offered by the Politex and the IC1000 pads.
In light of these issues Sequence #1 apparently satisfies all requirements; however, it is very slow. It has a much slower throughput (“tpt”), and thus the polishing equipment is poorly utilized. Just like any assembly line, the tpt of a tool is a function of its slowest step. Generally, the robots moving the wafers from station to station on such tools (see, for example, the Mira Mesa, supplied by Applied Materials) are fast. The slowest step is typically the slowest of the platen steps. Since Sequence #1 involves bulk removal of the copper at the first platen, that platen is likely the tpt limiter. It is not uncommon for that first step to take 3 or 4 minutes, resulting in a maximum tpt of the tool of 15-20 wafers per hour (“wph”). A higher tpt is generally desired.
Accordingly, there is a need for an improved CMP pad and an improved method of copper CMP providing increased tpt and improved bulk copper removal and/or planarization.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a method of improving the chemical-mechanical planarization removal rate of polishing pads, to provide an improved method of chemical mechanical polishing, and to provide an improved polishing pad.
In accordance with one aspect of an exemplary embodiment of the present invention, the method of improving a removal rate of a pad, comprises the steps of: producing a body of a pad of which at least the top layer is polyurethane; introducing into the body an additive which decreases the ER of the pad so as to increase a chemical-mechanical planarization removal rate; and using as the additive a substance which at least contains starch. In accordance with still a further feature of the present invention, said using step includes introducing substantially one pound of starch in a 25 pound mix to reduce the elastic rebound by approximately eight percentage points.
In accordance with various aspects of the present invention, introduction of at least a substance containing starch into the polyurethane body of the pad significantly decreases the elastic rebound and as a result the chemical-mechanical planarization removal rate of the pad is increased.
In keeping with these objects and with others that will become apparent hereinafter, one feature of the present invention includes a method of copper CMP for copper film deposited on a surface of a semiconductor wafer. The method comprises the steps of removing a bulk copper to a barrier; substantially removing the barrier; and subsequently buffing, and wherein said barrier removing and buffing includes using a polyurethane polishing pad having at least one layer fabricated from a mix composed of a prepolymer with an isocyanate concentration of between about 6.5% and about 11.0% or from a monomer and an addition of isocyanate to achieve substantially the same molal concentration, in which a shore D hardness of the layer is less than about 35%.
An exemplary embodiment of the present invention includes a polishing pad for removal of a barrier and subsequent buffing in CMP of a copper film deposited on a surface of a semiconductor wafer. The polishing pad is fabricated from a mix composed of the polymer with an isocyanate concentration of between about 6.5% and about 11.0% or from a monomer and an addition of isocyanate to achieve substantially the same molal concentration, and has a shore D hardness less than about 35%.
The novel features which are considered as characteristic of the present invention are set forth in particular in the appended claims. The invention itself, however, both as to its construction and its method of operation, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present invention may be derived by referring to the detailed description and claims when considered in connection with the Figures, wherein

FIG. 1 illustrates a planarization of urethane polishing pads as a function of NCO concentration produced in accordance with the present invention; and

FIG. 2 is a plot illustrating a relationship between a hardness of a pad and a number of scratches.

DETAILED DESCRIPTION

The description that follows is not intended to limit the scope, applicability or configuration of the invention in any way; rather, it is intended to provide a convenient illustration for implementing various embodiments of the invention. As will become apparent, various changes may be made in the function and arrangement of the elements described in these embodiments without departing from the scope of the invention. It should be appreciated that the description herein may be adapted to be employed with alternatively configured pads having different shapes, components, and the like and still fall within the scope of the present invention. Thus, the detailed description herein is presented for purposes of illustration only and not of limitation.
In accordance with one aspect of an exemplary embodiment of the present invention, a method is provided for improving the removal rate of a polishing pad. Although removal rates may be affected by the composition of the slurry used with the pad, several pad-related factors affect removal rates as well. For example, grooves can improve removal rates by, for example, delivering the slurry to the wafer-pad interface. Various patterns, pitches, widths and depths of these grooves may be also affect removal rates. Removal rates are also related to the friction which exists between the wafer and the pad in the presence of the slurry. This friction differs for different pads and can be affected by factors such as the size of pores in the pad, the density of the pad, the material composition of the pad, and/or the like.
Generally, the pads used for CMP are anelastic. An anelastic material exhibits both elastic and inelastic properties. A measure of the amount of inelasticity of a material is the Elastic Rebound, or the Elastic Recovery (ER). When compressed and released, the fractional amount of recovery after a set period of time is the ER. The higher the elastic rebound, the more elastic the material, while the lower the elastic rebound the more plastic is the material. In accordance with one aspect of an exemplary embodiment of the present invention, polyurethane pads and oxide wafers exhibit CMP removal rates that have been found to be strongly negatively correlated with ER.
Thus, in accordance with one aspect of an exemplary embodiment of the present invention, a method of improving the removal rate of a polishing pad includes constructing the pad to have a lower ER and thus a higher removal rate. It has been found that the ER of a pad may be lowered by adding starch to the pad components during the mixing of the pad ingredients (as described more fully below).
Although the introduction of starch into a urethane mix is known for a variety of purposes, it has not been used to improve removal rates in polishing pads. Starch is a known urethane additive, for example to increase biodegradability (e.g. U.S. Pat. No. 6,228,969), improve flame retardance and to enhance foaming, (e.g. U.S. Pat. No. 4,374,208).
In accordance with one aspect of an exemplary embodiment of the present invention, a CMP pad may comprise, in addition to other components, a starch. For example, a CMP pad may comprise: 20 lbs ADIPRENE L325 Liquid Polyether Urethane from Crompton Uniroyal, 4.7 lbs MOCA (4,4-methylene-bis-chloroaniline), 0.5 lb L-6100 silicone surfactant from GE Silicones, and 1 lb starch.
Furthermore, other quantities of the aforementioned components may be used, and the relative proportions may be varied. Moreover, it will be appreciated that starch may be added to other combinations of components typically used to create polyurethane pads. In accordance with one exemplary embodiment of the present invention, the method comprises the steps of mixing, for about 5 minutes, the starch (or a starch-containing additive) together with the L-325 Liquid Polymer Urethane and with the L-6100 silicone surfactant. The method may further comprise the step of mixing (for about one additional minute) an accelerant, such as MOCA, with the mixed starch/L-325/L-6100. The method may further include the steps of pouring the mix into a mold, curing it at room temperature for 15 minutes, placing it into an oven at a temperature of approximately 250° F. for approximately 8 hours, cooling the resultant cake and slicing it with a skiving-type blade. The slices are then fashioned into polishing pads through additional steps such as grooving, applying adhesive and/or applying a subpad.
In accordance with one exemplary embodiment of the present invention, as compared with a pad made of the same components but without starch, when one pound of starch is introduced into the mix, the Elastic Rebound of the pads is reduced by a full eight absolute percentage points, from about 94% to about 86%, with an r-square value of approximately 66%. In another exemplary embodiment, if the amount of starch added to the mix is only 0.5 pound of starch, as compared with a non-starch pad the ER may be reduced from approximately 94% to approximately 90%.
Thus, a new method of improving the removal rate has been presented. The CMP removal rate is increased by reducing the elastic rebound of the pad through the addition of starch or a starch like substance to the pad during its formation. Furthermore, in accordance with various aspects of the present invention, planarization of the work piece may also be improved.
The measurement of planarization may be made using planarization test structures, which are topographical structures which contain regular periodic arrays arranged in regions of different pitch and width. Due to practical limitations related to metrology, the smallest of these to yield an accurate measurement has a 100 micrometer pitch at 50% density (i.e. alternating high and low structures of equal width) and the largest had a 500 micrometer pitch at 50% density. Planarization capability is measured by a repeating sequential polish/measure action in which the remaining amplitude and the average amount of oxide removed is recorded for each step. The sequence is complete when the structure is planarized below a “noise” level. This sequence yields a curve which can be further reduced to single figure of merit of planarization called the Planarization Efficiency. In order to capture both short and long range planarization together, and in accordance with one aspect of an exemplary embodiment of the present invention, a parameter has been developed called the General Planarization Efficiency (GPE) which consists of the average of the short and long range efficiencies. The GPE ranges from 0% to 100%, in which 0% represents no planarization at all (i.e. perfect etching), while 100% represents perfect planarization (material removed only from high areas, none whatsoever from low areas). In an exemplary embodiment of the present invention, the GPE is improved through the methods described herein.
In this regard, and in accordance with yet another aspect of an exemplary embodiment of the present invention, urethane polishing pads are produced by combining a basic polyol resin with an isocyanate (“NCO”). It is to be understood that the whole pad can be produced in this way or only its working layer, in the event when the pad is a multi-layer pad. In a new and special way, the isocyanate is introduced with a concentration of between about 6.5% and about 11.0% into the basic resin.
Tests have been conducted to determine the planarization of the pad produced in accordance with the present invention. Four polishing pads have been tested, in particular a polishing pad L-100 with isocyanate concentration of 4.0%, a polishing pad L-200 with isocyanate concentration of 7.5% and L-325 with isocyanate concentration of 9.5% from the Adiprene series, and resin 2505 with isocyanate concentration of 11.6% from the Royalcast series, all from Crompton Uniroyal Chemical. As shown in FIG. 1, when the urethane polishing pads with isocyanate concentration between about 6.5% and about 11.0% were tested, they achieved the planarization within the range of about 72% to about 95%.
A breakdown of the data into groups normally expected to affect planarization does not alter the result. For example, grooving is known to generally negatively affect the GPE of the pad by structurally weakening the surface. However, the aforementioned planarization range was found to hold both for pads with and without grooving. It is also known that the use of a soft subpad can negatively affect the GPE (by virtue of its effect on the long range planarization). Again in this case the results were unaffected when considering solo pads and pad stacks separately. It is therefore understood that the NCO concentration controls physical properties of the pad which affect both the short and the long range planarization capability.
In accordance with an advantageous feature of the present invention, the concentration of the isocyanate can be within a range of about 6.5% to about 8.5%. In this case the urethane pad or its working layer is softer and suitable for barrier buff. In accordance with another preferable feature of the present invention, the concentration of the isocyanate can be within a range of about 8.5% to about 11.0%. In this case the urethane pad or its working layer is harder and is suitable for interlayer dielectric.
The urethane pad or its layer can be composed of polyester polyurethane or a polyether polyurethane. Furthermore, the urethane pad or its working layer can contain abrasive particles which may comprise one or more of the following components: silica, alumina, ceria, titania, diamond, and silicon carbide. Alternatively, the urethane pad or its working layer can be absent of abrasive particles. In addition, the urethane pad or its working layer in accordance with the present invention may also include a filler.
The above presented ranges of planarization are highly efficient for the urethane polishing pads. As can be seen, if this isocyanate concentration is less than about 6.5% and more than about 11.0%, the planarization property of the urethane polishing pads worsens.
Furthermore, with respect to CMP of copper, in one exemplary embodiment of the present invention, a method is provided for improving CMP of a copper film deposited on a surface of a semiconductor wafer. The method may, for example, comprise the steps of removing the bulk copper to a barrier; removing the barrier; and subsequently buffing, wherein said barrier removal and buffing include using a polyurethane polishing pad fabricated from a mix composed of a prepolymer or a monomer and an addition isocyanate to achieve substantially the same molal concentration, in which a shore D hardness is less than about 35%. In a preferred embodiment, the isocyanate concentration is between about 6.5% and about 8.5%, the smaller value generally leading to a softer polishing pad.
The present invention also relates to a polyurethane polishing pad for removal of a barrier and subsequent buffing in a chemical mechanical polishing process of a copper film deposited on a surface of a semiconductor wafer, the polishing pad fabricated from a mix composed of prepolymer with an isocyanate concentration of between about 6.5% and about 11.0% or from a monomer and an addition of isocyanate at a concentration to achieve substantially the same molal concentration, with a shore D hardness less than about 35%. In a preferred embodiment, the pad is made from a polyurethane mix in which the isocyanate concentration is between about 6.5% and about 8.5%, resulting in pads on the softer side of the hardness spectrum.
In developing the inventive method and the inventive pad it was determined that hardness is a significant parameter in predicting scratching. This is illustrated in FIG. 2 where the y-axis is the number of scratches and the x-axis is the Shore D hardness. The number of scratches comes from a test developed to elicit scratches in various cases, even from the softest of pads. The test consisted of using a known aggressive barrier slurry, which is generally incapable of removing copper, and using it to “polish” —at fairly high downforce (4 psi)—a pristine blanket copper film in which the number of pre-polish scratches has already been determined. The copper wafer is polished for 1 minute and then remeasured for scratches (using dark-field microscopy at low magnification). The increase in the number of scratches is then plotted:
The graph indicates the desirable hardness of the pad is approximately under 35 on the Shore D scale. The Politex is measured to be 25 on this scale by the same measurements (indicated on graph), and for reference, the IC1000 is measured to be 56 (indicated on graph) and reported to be 55 in information published by Rohm and Haas Corporation.
A planarization figure of merit, called General Planarization Efficiency (“GPE”) was developed to determine exactly what material or materials govern planarization. It was determined that GPE is a function of the isocyanate (“NCO”) concentration of the base resin. Resins that fell within the 6.5% to 11.0% range delivered high GPE and resins outside that range resulted in low GPE. Therefore, a resin from this range is proposed.
In one embodiment, a chemical-inert blown polyurethane is selected for the inventive pad. Therefore, in accordance with the present invention the above described polyurethane polishing pad is proposed as well as the above described method of removing barrier and buffing.
In various embodiments, a polyurethane polishing pad may comprise an additive which includes methyl alcohol, or water, or starch of any type including corn starch. The pad can have a thickness of between 10 mils and 200 mils, and preferably of 80 mils.
In accordance with various aspects of an exemplary embodiment of the present invention, the pad can be stacked on a subpad or the pad may be a single-layered pad. Furthermore, the pad in accordance with the present invention can be grooved or ungrooved, perforated or unperforated.
An exemplary method of manufacturing the pad in accordance with the present invention is now presented. First, as with all urethanes, the composition begins with either a prepolymer resin with an NCO concentration of between about 6.5% and about 11.0%, or a polyol and an amount of isocyanate required to achieve the same molal concentration. The prepolymer is preheated to about 100° F., and may be mixed until said temperature is achieved. Additives may then be added as desired. Exemplary additives include initiators such as water, blowing agents such as Vazo, catalysts such as a tertiary amine, and surfactants such as L-6100, and a silicone surfactant typically used to regulate cell size supplied by Crompton. An exothermic reaction begins once an accelerant, such as MOCA (4,4′-Methylenebis-[o-chloroaniline]), also known as a chain extender, is added.
In one embodiment, the pad is formed from a mix comprising at least one of a prepolymer in combination with an isocyanate concentration of between about 6.5% and about 11.0% to achieve a molal concentration, and a monomer in combination with sufficient isocyanate to achieve substantially the same molal concentration.
Pores may be created either by the incorporation of air during the mixing or by the intentional addition of pore creators, such as microballoons as taught in Reinhardt, U.S. Pat. No. 5,578,362. The mix is pored into a mold, which may be preheated. While the exothermic reaction is sufficient to bring the temperature of the center of the cake to some 270° F. and thus to a complete reaction, surface cooling may prevent the outside of the cake from reacting in a reasonable period of time. Therefore, the cake may be cured in an oven. This is typically performed at a temperature of about 240° F. for about 6 hours. The cake is then cooled and sliced to fabricate the polishing pads.
After curing, the cake is allowed to cool, and once cooled, it can be sliced using, for example, a stationary skiving blade and movable table. Usable slices of the ‘cake’ are then made into pads by applying adhesive to one face, mounting to a subpad, if desired, grooving the usable surface, finishing with a smoothing process, inspecting, and/or packaging the pad.
Often, if a pad can both planarize and pass the scratch-inducing test, then it can also be used in applications where a buff alone is needed. As such, some pads might have additional applications such as post-oxide buff. Further, one could conceive of other simple non-CMP cleaning applications commonly carried out in a semiconductor fabrication environment.
Again, since the pad planarizes, one could conceive of using it for example, to remove remaining copper to the barrier. In this case, since it is softer than the primary pad it will not have the same long-range planarization. However, if the first copper removal step is done with the hard pad, the copper surface should be well-planarized, making use of a slightly softer pad feasible. Another potential application of this pad is therefore also primary copper CMP.
In general, and in accordance with further aspects of exemplary embodiments of the present invention, the pad may be used on any of a number of substrates, such as a bare silicon wafer, a semiconductor device wafer, a magnetic memory disk, and/or the like. Furthermore, the pads can be made by any one of a number of polymer processing methods, such as but not limited to, casting, compression, injection molding, extruding, web-coating, and sintering. At least one layer of the pads may be single phase or multiphase, where the second phase could include polymeric microballoons, gases or fluids. The second phase could also be an abrasive such as silica, alumina, calcium carbonate, ceria, titania, germanium, diamond, silicon carbide or combinations thereof.
It will be understood that each of the elements described above, or two or more together, may also find a useful application in other types of constructions differing from the types described above. While the invention has been illustrated and described as embodied in a method of chemical mechanical polishing, and a pad provided therefore, it is not intended to be limited to the details shown, since various modifications and structural changes may be made without departing in any way from the spirit of the present invention.
Without further analysis, the foregoing will so fully reveal the gist of the present invention that others can, by applying current knowledge, readily adapt it for various applications without omitting features that, from the standpoint of prior art, fairly constitute essential characteristics of the generic or specific aspects of this invention.
It will be understood that each of the elements described above, or two or more together, may also find a use in other applications and in other types of constructions differing from the types described above. While the invention has been illustrated and described as embodied in a polyurethane polishing pad and method of producing the same, it is not intended to be limited to the details shown. Various modifications and structural changes and changes in the selection, design, and arrangement of the various components and steps discussed herein may be made without departing from the scope of the invention. For example, the various components may be implemented in alternate ways. These alternatives can be suitably selected depending upon the particular application or in consideration of any number of factors associated with the operation of the system. In addition, the techniques described herein may be extended or modified for use with other types of devices. These and other changes or modifications are intended to be included within the scope of the present invention.

Claims

1. An polishing pad comprising:

a pad, wherein the pad comprises a urethane, a starch, and an isocyanate;

wherein the urethane comprises a base resin;

wherein the starch is configured to both reduce the elastic rebound of the pad and to improve the CMP removal rate of the pad compared to a similar urethane pad that does not include starch; and,

wherein the concentration of the isocyanate is within a range of 6.5% to 11.0% of the urethane in the pad.

2. The polishing pad of claim 1, wherein the Global Planarization Efficiency is 75% to 90%.

3. A method of improving a removal rate of a polishing pad, at least one layer of which is constructed comprising the steps of producing a body of a pad of polyurethane from a mix; introducing into the mix an additive which decreases an elastic rebound of the pad so as to increase a chemical-mechanical planarization removal rate; and using as the additive a substance which at least contains a starch.

4. A polishing pad, at least one layer of which is constructed comprising the steps of producing a body of a pad of polyurethane from a mix; and introducing into the mix an additive which decreases an elastic rebound of the pad so as to increase a chemical-mechanical planarization removal rate; and using as the additive a substance which at least contains a starch.

5. A method as defined in claim 3, wherein said using step includes introducing substantially one pound of starch in a 25 pound mix to reduce the elastic rebound of the pad by eight percentage points.

6. A pad according to claim 3 wherein said layer comprises at least one of a polyether urethane, a polyester polyurethane, and a polycarbonate.

7. A pad according to claim 3 wherein said layer contains abrasive particles selected from any of silica, alumina, ceria, titania, diamond and silicon carbide.

8. A pad according to claim 3 wherein said layer comprises at least one of a filler, and a nylon.

9. A pad according to claim 3 wherein said layer is absent abrasive particles.

10. A method of improving planarization of a urethane polishing pad, comprising the steps of combining a base resin; and introducing in the base resin and an isocyanate to form a urethane polishing pad; and selecting a concentration of the isocyanate to be within a range of 6.5% to 11.0% of said base resin to obtain a high planarization property.

11. The method of claim 10, wherein said selecting step includes selecting a concentration of the isocyanate within a range of 6.5 to 8.5%.

12. The method of claim 10, wherein said selecting step includes selecting a concentration of said isocyanate within a range of 8.5% to 11.0%.

13. The method of claim 10, wherein said layer is composed of a polyurethane selected from the group consisting of a polyether polyurethane and polyester polyurethane.

14. The method of claim 10, and further comprising the step of combining a plurality of abrasive particles with said base resin and said isocyanate, wherein said plurality of abrasive particles are selected from the group consisting of silica, alumina, ceria, titania, diamond and silicon carbide.

15. The method of claim 10, wherein said method does not include the step of urethane polishing pad combining abrasive particles with said base resin and said isocyanate.

16. The method of claim 10, further comprising the step of combining a filler with said base resin and said isocyanate.

17. A urethane polishing pad, comprising at least one layer having a base resin, and isocyanate introduced in the base resin, wherein a concentration of the isocyanate in the base resin is within a range of 6.5% to 11.0%.

18. The urethane polishing pad as defined in claim 17, wherein the concentration of the isocyanate in the base resin is within a range of 6.5% to 8.5%.

19. The urethane polishing pad of claim 17, wherein the concentration of the isocyanate in the base resin is within a range of 8.5% to 11.0%.

20. The urethane polishing pad of claim 17, wherein said at least one layer comprises polyurethane selected from the group consisting of a polyether polyurethane and polyester polyurethane.

21. The urethane polishing pad of claim 17, wherein said at least one layer contains abrasive particles selected from the group consisting of silica, alumina, ceria, titania, diamond, and silicon carbide.

22. The urethane polishing pad of claim 17, wherein at least one layer is absent of abrasive particles.

23. The urethane polishing pad of claim 17, wherein said at least one layer includes a filler.

24. A method of chemical mechanical polishing of a copper film deposited on a surface of a semiconductor wafer, comprising the steps of:

removing a bulk copper layer to a barrier;

removing the barrier; and

buffing, wherein said removing the barrier and buffing include using a polyurethane polishing pad having a shore D hardness of less than about 35% and having a layer made of a mix comprising at least one of (i) a prepolymer in combination with an isocyanate concentration of between 6.5% and 11.0% to achieve a molal concentration, and (ii) a monomer in combination with sufficient isocyanate to achieve substantially the same molal concentration as in (i).

25. The method of claim 24, wherein the pad comprises an additive including at least one of a methyl alcohol, water and starch.

26. The method of claim 24, wherein the pad has a thickness between 10 mils and 200 mils.

27. The method of claim 26, wherein the pad has a thickness of between 40 and 100 mils.

28. The method of claim 24, wherein the pad is a single open-layered pad.

29. The method of claim 24, wherein the pad is stacked on and attached to a sub pad.

30. The method of claim 24, wherein said pad includes grooves.

31. The method of claim 24, wherein said pad includes perforations.

32. The method of claim 24, wherein said layer is comprises at least one of a polyether polyurethane and polyester polyurethane.

33. The method of claim 24, further comprising introducing in said layer abrasive particles comprising at least one of silica, alumina, ceria, titania, diamond and silicon carbide.

34. The method of claim 24; and further comprising introducing a filler into said mix.

35. A polishing pad for removal of a barrier and buffing after a bulk copper removal to the barrier in a chemical mechanical polishing of a copper film deposited on a surface of a semiconductor wafer, the polishing pad having a shore D hardness of less than 35% and having at least one layer made of a mix comprising at least one of (i) a prepolymer with an isocyanate concentration of between 6.5% and 11.0% to achieve a molal concentration, and (ii) a monomer in combination with sufficient isocyanate to achieve substantially the same molal concentration as in (i).

36. The pad of claim 35, wherein the pad includes an additive comprising at least one of methyl alcohol, water, and starch.

37. The pad of claim 36, wherein the pad is a single open-layered pad.

38. The pad of claim 35, wherein the pad has a thickness between 10 mils and 200 mils.

39. The pad of claim 35, wherein the pad has a thickness of between 40 and 100 mils.

40. The pad of claim 35, wherein the pad is stacked on and attached to a sub pad.

41. The pad of claim 35, wherein said pad includes grooves.

42. The pad of claim 35, wherein said pad includes perforations.

43. The pad of claim 35, wherein said layer comprises at least on of polyether polyurethane and polyester polyurethane.

44. The pad of claim 35, further comprising abrasive particles comprising at least one of silica, alumina, ceria, titania, diamond and silicon carbide.

45. The pad of claim 35; and further comprising a filler introduced into said mix.

46. A method of chemical mechanical polishing of a copper film deposited on a surface of a semiconductor wafer, the method comprising:

removing bulk copper to a barrier;

removing the barrier; and

buffing, and wherein said removing the barrier and buffing include using a polyurethane polishing pad having a shore D hardness of less than 35% and having a layer made from a mix comprising at least one of a prepolymer with an isocyanate concentration of between 6.5% and 8.5% to achieve a molal concentration, and a monomer in combination with sufficient isocyanate to achieve substantially the same molal concentration.