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US20080224169A1 - Submount for diode with single bottom electrode - Google Patents

Submount for diode with single bottom electrode Download PDF

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Publication number
US20080224169A1
US20080224169A1 US12/154,977 US15497708A US2008224169A1 US 20080224169 A1 US20080224169 A1 US 20080224169A1 US 15497708 A US15497708 A US 15497708A US 2008224169 A1 US2008224169 A1 US 2008224169A1
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Prior art keywords
submount
metal
diode
shows
present
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US12/154,977
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Jiahn-Chang Wu
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Cheng Kung Capital LLC
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Individual
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Assigned to CHENG KUNG CAPITAL, LLC reassignment CHENG KUNG CAPITAL, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WU, JIAHN-CHANG
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections

Definitions

  • This invention relates to diode package, particularly to light emitting diodes or face emission laser diode.
  • U.S. Pat. No. 6,642,618B2 disclosed a light emitting diode (LED) 102 .
  • the LED has two bottom electrodes mounted on a submount 108 through solder bumps 103 .
  • the submount has two metallic sections 109 contacting to two respective electrodes.
  • the submount 108 has two through holes 111 lined with metallic lining for coupling the two top metallic sections 109 to the bottom of the submount as extensions 110 . Subsequently, the submount 108 can be placed on a printed circuit board 101 a , which has two metal pads 101 b for coupling with the extensions 110 .
  • the structure forms a diode unit or a matrix array.
  • the prior art used a printed circuit board 101 a as a motherboard, and the submount 108 is connected to the motherboard 101 a by means of soldering.
  • a bottleneck in the application of LEDs is the heat dissipation problem.
  • the glass fiber circuit board does not have good heat dissipating property.
  • a ceramic board has better heat dissipation property, but is more costly and requires time-consuming soldering to mount the submount to the motherboard.
  • An object of the present invention is to provide a submount for a diode that has good heat sinking property. Another object of the invention is to eliminate soldering the submount to the motherboard. Still another object of the invention is to self-align the diode in a package.
  • the diode on a substrate with two coplanar metal areas on the top surface, each connected to respective electrodes of the LED.
  • One of the coplanar areas is connected through a via to the bottom surface of the submount.
  • the submount is clamped between a top metal sheet and a bottom metal sheet.
  • the top metal sheet of the clamp has a through-hole to anchor the diode for self-alignment.
  • the large coplanar areas on the submount facilitate heat transferring and the clamp by two metallic plates to overcome the poor heat sinking and slow soldering drawbacks.
  • the clamping with two metal sheets provides pressure contact for electrical coupling and eliminates traditional soldering process. However, soldering process can be added for enhancing product reliability.
  • the alternative soldering process is speeded up by pre-painting some soldering material at the contacting regions of the clamping metal sheets and followed with a subsequent overall heating to make the contacts. With improved heat sinking and speedup of soldering processing, the reliability of the LED package is improved.
  • Two metal surfaces are formed on the substrate 22 , one metal surface on top and the other one on bottom to form the extensions of the electrodes of the LED, so that one extension faces upward and another extension faces downward facilitate the metal clamping.
  • the clamping eliminates soldering to the diode electrodes to the clamping metal sheets.
  • the upper sheet of the clamp has at least one through-hole slightly larger than the diode chip.
  • the chip is mated with the through-hole to provide accurate positioning with respect to the package. This accurate positioning is especially important either in single package or matrix LED array especially in the field of optical communication; alignment is usually with reference to the outline of a package, therefore, the relative accuracy of a light emitting diode with reference to its package peripherals.
  • the upper metal clamping plate is provided with a large number of through-holes and each inserted with an LED chip to form an array
  • FIG. 1 shows a prior art submount for a light emitting diode soldered to a motherboard.
  • FIG. 2 shows the first embodiment of the submount of the present invention.
  • FIG. 3 shows the top view of the submount of FIG. 2 .
  • FIG. 4 shows the second embodiment of the submount of the present invention.
  • FIG. 5 shows the third embodiment of the submount of the present invention.
  • FIG. 6 shows a clamp for holding an array of submounts.
  • FIG. 7 shows the fourth embodiment of the submounts for housing in the clamp in FIG. 6 .
  • FIG. 8 shows the fifth embodiment of present invention with a window on top of the clamp in FIG. 7 .
  • FIG. 9 shows the sixth embodiment of the present invention for a diode with a top electrode and a bottom electrode.
  • FIG. 10 shows the seventh embodiment of the present invention having glue sealing the structure in FIG. 9 .
  • FIG. 11 shows the eighth embodiment of the present invention with a clamp for the structure shown in FIG. 9 .
  • FIG. 12 shows the ninth embodiment of the present invention with sealing glue for the structure in FIG. 11 .
  • FIG. 13 shows the tenth embodiment of the present invention with a transparent window for the structure in FIG. 12 .
  • FIG. 14 shows the eleventh embodiment of the present invention with wire-bonding for the structure in FIG. 9 .
  • FIG. 15 shows the twelfth embodiment of the present invention with protective glue for the structure in FIG. 14 .
  • FIG. 16 shows the thirteenth embodiment of the present invention with transparent window for the structure in FIG. 14 .
  • FIG. 17 shows the fourteenth embodiment of the submount of the present invention with two top diode electrodes.
  • FIG. 18 shows the fifteenth embodiment of the present invention with protective glue over the structure in FIG. 17 .
  • FIG. 19 shows the sixteenth embodiment of the present invention with metal sheets to clamp the submount shown in FIG. 17 .
  • FIG. 20 shows the seventeenth embodiment of the present invention with protective glue to seal the structure in FIG. 19 .
  • FIG. 21 shows the eighteenth embodiment of the submount of the present invention for a diode with two top electrodes.
  • FIG. 22 shows the nineteenth embodiment of the present invention with protective glue covering the structure in FIG. 21 .
  • FIG. 23 shows the twentieth embodiment of the present invention with metal sheets to clamp the submount shown in FIG. 21 .
  • FIG. 24 shows the twenty-first embodiment of the present invention with metal sheets to clamp the submount in FIG. 22 .
  • FIG. 25 shows the twenty-second embodiment of the present invention where the upper metal sheet is zigzag.
  • FIG. 26 shows the twenty-third embodiment of the present invention using the clamp in FIG. 25 in conjunction with a submount shown in FIG. 2 .
  • FIG. 2 shows the first embodiment of the submount for holding a light emitting diode (LED) chip based on the present invention.
  • the LED chip 20 having a first electrode 201 and a second electrode 202 straddles between two metallic printed-circuit areas 221 , 222 each soldered to the two electrodes respectively through solder bumps 203 .
  • the two metal areas are placed on the upper surface of a substrate 22 .
  • a vertical metallic conduit 25 in the substrate 22 connects the metal area 221 to a lower metal area 24 beneath the lower surface of the substrate 22 , so that the two extension metals appear one on the upper surface of the substrate 22 and the other one on the bottom of the substrate 22 .
  • FIG. 3 shows the top view of the submount in FIG. 2 with the first metallic area 221 and second metallic area 222 .
  • the first metallic area 221 has a metal conduit 25 , which extends to the lower metal area 24 beneath the substrate 22 .
  • FIG. 4 shows the second embodiment of the present invention.
  • the metal conduct 252 is placed at the end of the substrate 22 .
  • the LED diode 20 has two bottom electrodes 201 and 202 , each contacting the two metal areas 221 and 222 respectively.
  • the lower metal area 24 serves as one terminal for the diode 20 .
  • FIG. 5 shows the third embodiment of the present invention.
  • a coating of protective glue 26 is used to seal over the chip 20 to improve the reliability.
  • FIG. 6 and FIG. 7 show the fourth embodiment of the present invention.
  • the top metal sheet 27 and a bottom metal sheet 28 is used to clamp the substrate 22 .
  • the top metal sheet 27 has at least a through hole 271 to anchor the LED chip 20 mounted on the substrate 22 .
  • the bottom metal sheet 28 is placed below the substrate 22 to contact the lower metal area 24 of the submount. With this anchoring, the chip 20 is self-aligned with reference to the peripheral of the package.
  • FIG. 8 shows the fifth embodiment of the present invention.
  • the thorough-hole 271 in the top metal sheet is covered with transparent material 23 to improve the reliability.
  • FIG. 9 shows the sixth embodiment of the present invention.
  • the structure is similar to that shown in FIG. 2 except that the LED chip 30 has a top electrode 302 and a bottom electrode 301 .
  • the submount has at least printed circuit area 221 electrically coupled to the bottom electrode 301 .
  • FIG. 10 shows the seventh embodiment of the present invention.
  • a coating of protective glue 26 is used to seal at least the edges of the chip 30 except the top electrode 302 , which is wire-bonded.
  • FIG. 11 shows the eighth embodiment of the present invention.
  • the submount shown in FIG. 9 is clamped by a top metal sheet 27 and a bottom metal sheet 28 .
  • the top metal sheet has at least one through-hole 271 to anchor the LED chip 30 and to couple to the bottom electrode of the chip.
  • a bonding wire is used to connect the top electrode 302 of the chip to the top metal sheet 27 .
  • FIG. 12 shows the ninth embodiment of the present invention.
  • protective glue 26 can be used to seal at least the edges of the diode chip 30 except the top surface which must be exposed for wire bonding but can be sealed after bonding.
  • FIG. 13 shows the tenth embodiment of the present invention.
  • a transparent material 23 is used to cover the top of the through hole.
  • FIG. 14 shows the eleventh embodiment of the present invention.
  • the metal printed-circuit area 222 is wire-bonded to the electrode 302 of the diode chip 30 .
  • FIG. 15 shows the twelfth embodiment of the present invention.
  • protective glue 26 is used to seal the diode chip 30 , the top electrode 302 and the bonding wire 292 .
  • FIG. 16 shows the thirteenth embodiment of the present invention.
  • a transparent window 23 is used to cover the top of the through-hole 271 in the top metal sheet 27 to improve the reliability.
  • FIG. 17 shows the fourteenth embodiment of the present invention.
  • a diode chip is mounted on the submount is similar to that shown in FIG. 14 , except that the diode chip 40 has two top electrodes 401 , 402 .
  • the upper surface of the submount has at least one section of printed circuit area 221 , which can be wire-bonded to the electrode 401 .
  • FIG. 18 shows the fifteenth embodiment of the present invention.
  • protective glue 26 is used to seal at least the electrode 401 and the bonding wire 293 .
  • FIG. 19 shows the sixteenth embodiment of the present invention.
  • a top metal sheet 27 and a bottom metal sheet 28 are used to clamp the submount.
  • the top metal sheet has a conduit 271 to anchor a chip 40 and to couple to the bottom metal sheet 28 .
  • the bottom metal sheet 28 makes contact with the lower metal area 24 of the submount.
  • the second electrode 402 of the diode is wire-bonded the top metal sheet 27 through wire 291 .
  • FIG. 20 shows the seventeenth embodiment of the present invention.
  • protective glue 26 is used to seal at least the first electrode 401 and the bonding wire 293 .
  • FIG. 21 shows the eighteenth embodiment of the present invention.
  • the submount structure is similar to that in FIG. 17 , except that the diode chip has two top electrodes.
  • one top electrode 402 is wire-bonded with wire 292 to the printed wiring 222 on the top metal area of the submount.
  • Another electrode 401 is wire bonded to the top metal area 221 .
  • FIG. 22 shows the nineteenth embodiment of the present invention.
  • protective glue 26 is used to seal the two electrodes 401 , 402 , the diode chip 40 and the two bonding wires 292 , 293 .
  • FIG. 23 shows the twentieth embodiment of the present invention.
  • two metal sheets 27 , 28 are used to clamp the submount.
  • the top metal sheet 27 has a through-hole 271 to anchor the diode chip 40 and is electrically coupled to the top electrode 402 .
  • the bottom metal sheet 28 is placed below and in contact with the metal surface 24 of the submount.
  • FIG. 24 shows the twenty-first embodiment of the present invention.
  • protective glue 26 is used to seal the two electrodes 401 , 402 , and the bonding wires 292 , 293 .
  • FIG. 25 shows the twenty-second embodiment of the present invention.
  • the top metal sheet 37 can be of zigzag shape, so that the lower part of the metal sheet 37 is planarized with that the bottom metal sheet 38 of the clamp.
  • FIG. 26 shows the twenty-third embodiment of the present invention.
  • the figure shows how the zigzag top metal sheet 37 and the bottom metal sheet 38 clamp the submount.
  • the zigzag metal sheet has a through-hole 371 to anchor the diode chip 20 .
  • the two clamping metal sheets are each coupled to the two electrodes of the diode electrodes without individual soldering.
  • the submount in this figure is similar to that shown in FIG. 7 .
  • These planarized bottom surface can be painted with solder and be batch soldered upon subsequent heating.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

A submount is used to mount a diode between two metal areas on the upper surface of a substrate. One of the areas is connected to a metal plate at the lower surface of the substrate through a via. The submount is clamped between two metal sheets. The top metal sheet has a through-hole for anchoring and self-aligning the diode. The electrodes of the diode are each coupled to one of the clamping metal sheets. Clamping metals provide pressure contact without soldering to the contact. But soldering can be alternatively used to enhance product reliability. Either the top metal sheet or the bottom metal sheet can be fully or selectively coating of solder for batch soldering at the contact point upon heating. The large metal plates and the large metal clamping sheets provide good heat sink and speedy soldering.

Description

  • This application is a division of application Ser. No. 10/847, 225, filed May 18, 2004, now pending. and allowed.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention relates to diode package, particularly to light emitting diodes or face emission laser diode.
  • 2. Brief Description of Related Art
  • U.S. Pat. No. 6,642,618B2 disclosed a light emitting diode (LED)102. The LED has two bottom electrodes mounted on a submount 108 through solder bumps 103. The submount has two metallic sections 109 contacting to two respective electrodes. The submount 108 has two through holes 111 lined with metallic lining for coupling the two top metallic sections 109 to the bottom of the submount as extensions 110. Subsequently, the submount 108 can be placed on a printed circuit board 101 a, which has two metal pads 101 b for coupling with the extensions 110. The structure forms a diode unit or a matrix array.
  • The prior art used a printed circuit board 101 a as a motherboard, and the submount 108 is connected to the motherboard 101 a by means of soldering. In recent years, a bottleneck in the application of LEDs is the heat dissipation problem. The glass fiber circuit board does not have good heat dissipating property. A ceramic board has better heat dissipation property, but is more costly and requires time-consuming soldering to mount the submount to the motherboard.
    • SUMMARY OF THE INVENTION
  • An object of the present invention is to provide a submount for a diode that has good heat sinking property. Another object of the invention is to eliminate soldering the submount to the motherboard. Still another object of the invention is to self-align the diode in a package.
  • These objects are achieved by mounting the diode on a substrate with two coplanar metal areas on the top surface, each connected to respective electrodes of the LED. One of the coplanar areas is connected through a via to the bottom surface of the submount. The submount is clamped between a top metal sheet and a bottom metal sheet. The top metal sheet of the clamp has a through-hole to anchor the diode for self-alignment. The large coplanar areas on the submount facilitate heat transferring and the clamp by two metallic plates to overcome the poor heat sinking and slow soldering drawbacks. The clamping with two metal sheets provides pressure contact for electrical coupling and eliminates traditional soldering process. However, soldering process can be added for enhancing product reliability. The alternative soldering process is speeded up by pre-painting some soldering material at the contacting regions of the clamping metal sheets and followed with a subsequent overall heating to make the contacts. With improved heat sinking and speedup of soldering processing, the reliability of the LED package is improved.
  • Two metal surfaces are formed on the substrate 22, one metal surface on top and the other one on bottom to form the extensions of the electrodes of the LED, so that one extension faces upward and another extension faces downward facilitate the metal clamping. The clamping eliminates soldering to the diode electrodes to the clamping metal sheets.
  • The upper sheet of the clamp has at least one through-hole slightly larger than the diode chip. The chip is mated with the through-hole to provide accurate positioning with respect to the package. This accurate positioning is especially important either in single package or matrix LED array especially in the field of optical communication; alignment is usually with reference to the outline of a package, therefore, the relative accuracy of a light emitting diode with reference to its package peripherals. In a matrix application, the upper metal clamping plate is provided with a large number of through-holes and each inserted with an LED chip to form an array
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a prior art submount for a light emitting diode soldered to a motherboard.
  • FIG. 2 shows the first embodiment of the submount of the present invention.
  • FIG. 3 shows the top view of the submount of FIG. 2.
  • FIG. 4 shows the second embodiment of the submount of the present invention.
  • FIG. 5 shows the third embodiment of the submount of the present invention.
  • FIG. 6 shows a clamp for holding an array of submounts.
  • FIG. 7 shows the fourth embodiment of the submounts for housing in the clamp in FIG. 6.
  • FIG. 8 shows the fifth embodiment of present invention with a window on top of the clamp in FIG. 7.
  • FIG. 9 shows the sixth embodiment of the present invention for a diode with a top electrode and a bottom electrode.
  • FIG. 10 shows the seventh embodiment of the present invention having glue sealing the structure in FIG. 9.
  • FIG. 11 shows the eighth embodiment of the present invention with a clamp for the structure shown in FIG. 9.
  • FIG. 12 shows the ninth embodiment of the present invention with sealing glue for the structure in FIG. 11.
  • FIG. 13 shows the tenth embodiment of the present invention with a transparent window for the structure in FIG. 12.
  • FIG. 14 shows the eleventh embodiment of the present invention with wire-bonding for the structure in FIG. 9.
  • FIG. 15 shows the twelfth embodiment of the present invention with protective glue for the structure in FIG. 14.
  • FIG. 16 shows the thirteenth embodiment of the present invention with transparent window for the structure in FIG. 14.
  • FIG. 17 shows the fourteenth embodiment of the submount of the present invention with two top diode electrodes.
  • FIG. 18 shows the fifteenth embodiment of the present invention with protective glue over the structure in FIG. 17.
  • FIG. 19 shows the sixteenth embodiment of the present invention with metal sheets to clamp the submount shown in FIG. 17.
  • FIG. 20 shows the seventeenth embodiment of the present invention with protective glue to seal the structure in FIG. 19.
  • FIG. 21 shows the eighteenth embodiment of the submount of the present invention for a diode with two top electrodes.
  • FIG. 22 shows the nineteenth embodiment of the present invention with protective glue covering the structure in FIG. 21.
  • FIG. 23 shows the twentieth embodiment of the present invention with metal sheets to clamp the submount shown in FIG. 21.
  • FIG. 24 shows the twenty-first embodiment of the present invention with metal sheets to clamp the submount in FIG. 22.
  • FIG. 25 shows the twenty-second embodiment of the present invention where the upper metal sheet is zigzag.
  • FIG. 26 shows the twenty-third embodiment of the present invention using the clamp in FIG. 25 in conjunction with a submount shown in FIG. 2.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 2 shows the first embodiment of the submount for holding a light emitting diode (LED) chip based on the present invention. The LED chip 20 having a first electrode 201 and a second electrode 202 straddles between two metallic printed- circuit areas 221, 222 each soldered to the two electrodes respectively through solder bumps 203. The two metal areas are placed on the upper surface of a substrate 22. A vertical metallic conduit 25 in the substrate 22 connects the metal area 221 to a lower metal area 24 beneath the lower surface of the substrate 22, so that the two extension metals appear one on the upper surface of the substrate 22 and the other one on the bottom of the substrate 22.
  • FIG. 3 shows the top view of the submount in FIG. 2 with the first metallic area 221 and second metallic area 222. The first metallic area 221 has a metal conduit 25, which extends to the lower metal area 24 beneath the substrate 22.
  • FIG. 4 shows the second embodiment of the present invention. Instead of the metal through-hole in FIG. 3, the metal conduct 252 is placed at the end of the substrate 22. The LED diode 20 has two bottom electrodes 201 and 202, each contacting the two metal areas 221 and 222 respectively. The lower metal area 24 serves as one terminal for the diode 20.
  • FIG. 5 shows the third embodiment of the present invention. In addition to the structure shown in FIG. 4, a coating of protective glue 26 is used to seal over the chip 20 to improve the reliability.
  • FIG. 6 and FIG. 7 show the fourth embodiment of the present invention. The top metal sheet 27 and a bottom metal sheet 28 is used to clamp the substrate 22. The top metal sheet 27 has at least a through hole 271 to anchor the LED chip 20 mounted on the substrate 22. The bottom metal sheet 28 is placed below the substrate 22 to contact the lower metal area 24 of the submount. With this anchoring, the chip 20 is self-aligned with reference to the peripheral of the package.
  • FIG. 8 shows the fifth embodiment of the present invention. In addition to the structure shown in FIG. 7, the thorough-hole 271 in the top metal sheet is covered with transparent material 23 to improve the reliability.
  • FIG. 9 shows the sixth embodiment of the present invention. The structure is similar to that shown in FIG. 2 except that the LED chip 30 has a top electrode 302 and a bottom electrode 301. The submount has at least printed circuit area 221 electrically coupled to the bottom electrode 301.
  • FIG. 10 shows the seventh embodiment of the present invention. In addition to the structure shown in FIG. 9, a coating of protective glue 26 is used to seal at least the edges of the chip 30 except the top electrode 302, which is wire-bonded.
  • FIG. 11 shows the eighth embodiment of the present invention. The submount shown in FIG. 9 is clamped by a top metal sheet 27 and a bottom metal sheet 28. The top metal sheet has at least one through-hole 271 to anchor the LED chip 30 and to couple to the bottom electrode of the chip. A bonding wire is used to connect the top electrode 302 of the chip to the top metal sheet 27.
  • FIG. 12 shows the ninth embodiment of the present invention. In addition to the clamped structure shown in FIG. 11, protective glue 26 can be used to seal at least the edges of the diode chip 30 except the top surface which must be exposed for wire bonding but can be sealed after bonding.
  • FIG. 13 shows the tenth embodiment of the present invention. In addition to the structure in FIG. 12, a transparent material 23 is used to cover the top of the through hole.
  • FIG. 14 shows the eleventh embodiment of the present invention. In the submount shown in FIG. 9, the metal printed-circuit area 222 is wire-bonded to the electrode 302 of the diode chip 30.
  • FIG. 15 shows the twelfth embodiment of the present invention. In addition to the structure shown In FIG. 14, protective glue 26 is used to seal the diode chip 30, the top electrode 302 and the bonding wire 292.
  • FIG. 16 shows the thirteenth embodiment of the present invention. In the addition to the structure shown in FIG. 15, a transparent window 23 is used to cover the top of the through-hole 271 in the top metal sheet 27 to improve the reliability.
  • FIG. 17 shows the fourteenth embodiment of the present invention. A diode chip is mounted on the submount is similar to that shown in FIG. 14, except that the diode chip 40 has two top electrodes 401, 402. The upper surface of the submount has at least one section of printed circuit area 221, which can be wire-bonded to the electrode 401.
  • FIG. 18 shows the fifteenth embodiment of the present invention. In addition to the structure shown in FIG. 17, protective glue 26 is used to seal at least the electrode 401 and the bonding wire 293.
  • FIG. 19 shows the sixteenth embodiment of the present invention. In addition to the submount shown in FIG. 18, a top metal sheet 27 and a bottom metal sheet 28 are used to clamp the submount. The top metal sheet has a conduit 271 to anchor a chip 40 and to couple to the bottom metal sheet 28. The bottom metal sheet 28 makes contact with the lower metal area 24 of the submount. The second electrode 402 of the diode is wire-bonded the top metal sheet 27 through wire 291.
  • FIG. 20 shows the seventeenth embodiment of the present invention. In addition to the structure shown in FIG. 19, protective glue 26 is used to seal at least the first electrode 401 and the bonding wire 293.
  • FIG. 21 shows the eighteenth embodiment of the present invention. The submount structure is similar to that in FIG. 17, except that the diode chip has two top electrodes. Here, one top electrode 402 is wire-bonded with wire 292 to the printed wiring 222 on the top metal area of the submount. Another electrode 401 is wire bonded to the top metal area 221.
  • FIG. 22 shows the nineteenth embodiment of the present invention. In addition to the submount structure shown in FIG. 21, protective glue 26 is used to seal the two electrodes 401, 402, the diode chip 40 and the two bonding wires 292, 293.
  • FIG. 23 shows the twentieth embodiment of the present invention. In addition to the submount structure shown in FIG. 21, two metal sheets 27, 28 are used to clamp the submount. The top metal sheet 27 has a through-hole 271 to anchor the diode chip 40 and is electrically coupled to the top electrode 402. The bottom metal sheet 28 is placed below and in contact with the metal surface 24 of the submount.
  • FIG. 24 shows the twenty-first embodiment of the present invention. In addition to the structure shown in FIG. 23, protective glue 26 is used to seal the two electrodes 401, 402, and the bonding wires 292, 293.
  • FIG. 25 shows the twenty-second embodiment of the present invention. In the forgoing embodiments where a clamping metal is incorporated such as those in FIGS. 7, 8, 11, 12, 13, 16, 19, 20, 23 and 24, the top metal sheet 37 can be of zigzag shape, so that the lower part of the metal sheet 37 is planarized with that the bottom metal sheet 38 of the clamp.
  • FIG. 26 shows the twenty-third embodiment of the present invention. The figure shows how the zigzag top metal sheet 37 and the bottom metal sheet 38 clamp the submount. The zigzag metal sheet has a through-hole 371 to anchor the diode chip 20. The two clamping metal sheets are each coupled to the two electrodes of the diode electrodes without individual soldering. The submount in this figure is similar to that shown in FIG. 7. These planarized bottom surface can be painted with solder and be batch soldered upon subsequent heating.
  • While the preferred embodiments of the invention have been described, it will be apparent to those skilled in the art that various modifications may be made without departing from the spirit of the present invention. Such modifications are all within the scope of the present invention.

Claims (4)

1. A display module with a submount for a diode, comprising:
a substrate;
a first upper metal area on a top surface of said substrate;
a second upper metal area on a top surface of said substrate encircling the first upper metal area;
a lower metal area covering a bottom surface of said substrate;
an electrically conducting conduit, coupling said first upper metal area with said lower metal area;
a diode chip having a first electrode and a second electrode electrically coupling respectively to said first upper metal area and said second upper metal area;
a top metal sheet, having a through hole to anchor said diode chip, electrically coupling to said second upper metal area; and
a bottom metal sheet, below said diode chip, electrically coupling to said lower metal area.
2. The module as described in claim 1, further comprising a transparent material to cover said through-hole.
3. The module as described in claim 1, further comprising a protective glue to cover said diode chip.
4. The module as described in claim 1, wherein the top metal sheet is of zigzag metal, the zigzag metal having a lower section which having a bottom surface coplanar with a bottom surface of said bottom metal sheet.
US12/154,977 2004-05-18 2008-05-30 Submount for diode with single bottom electrode Abandoned US20080224169A1 (en)

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CN102456295A (en) * 2010-10-14 2012-05-16 上海科斗电子科技有限公司 Interlayer led display
US20120153340A1 (en) * 2009-06-05 2012-06-21 Advanced Photonics, Inc. Submount, optical module provided therewith, and submount manufacturing method
CN106157824A (en) * 2015-04-13 2016-11-23 弘凯光电(深圳)有限公司 Led display panel
JP2018032748A (en) * 2016-08-24 2018-03-01 パナソニックＩｐマネジメント株式会社 Light-emitting device, illumination apparatus and manufacturing method of light-emitting device
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US20120153340A1 (en) * 2009-06-05 2012-06-21 Advanced Photonics, Inc. Submount, optical module provided therewith, and submount manufacturing method
US9240527B2 (en) 2009-06-05 2016-01-19 Advanced Photonics, Inc. Submount, optical module provided with submount, and submount manufacturing method
US20110089541A1 (en) * 2009-10-19 2011-04-21 Jeng-Jye Shau Area reduction for electrical diode chips
CN102456295A (en) * 2010-10-14 2012-05-16 上海科斗电子科技有限公司 Interlayer led display
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CN106157824A (en) * 2015-04-13 2016-11-23 弘凯光电(深圳)有限公司 Led display panel
JP2018032748A (en) * 2016-08-24 2018-03-01 パナソニックＩｐマネジメント株式会社 Light-emitting device, illumination apparatus and manufacturing method of light-emitting device
US20190273031A1 (en) * 2018-03-05 2019-09-05 Win Semiconductors Corp. Semiconductor Device with Antenna Integrated
US10679924B2 (en) * 2018-03-05 2020-06-09 Win Semiconductors Corp. Semiconductor device with antenna integrated
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