US20070131647A1

US20070131647A1 - Semiconductor device and support method for designing the same

Info

Publication number: US20070131647A1
Application number: US11/637,035
Authority: US
Inventors: Hiroshi Katsuta
Original assignee: NEC Electronics Corp
Current assignee: NEC Electronics Corp
Priority date: 2005-12-13
Filing date: 2006-12-12
Publication date: 2007-06-14
Also published as: JP2007165489A

Abstract

A semiconductor device includes a bundle of wiring lines arranged in parallel and connected to a macro cell to transfer a same signal; and a bridge wiring line configured to bridge adjacent ones of the wiring lines of the bundle. Wiring line resistances between ends of the adjacent wiring lines in the macro cell and nodes of the bridge wiring line with the adjacent two wiring lines are different from each other.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device and a support method for designing a layout of wiring lines of a semiconductor device.
2. Description of the Related Art
In a semiconductor device, there is a case that an upper limit is set for a resistance value of wiring lines for connection between macro cells. For example, an upper limit of the resistance value to power supply wiring lines for connection to analog circuit macro cells is set because of an analog property. Conventionally, as wiring line material, Al is used in many cases. In that case, in order to decrease the resistance value, a wiring line width is set relatively wide.
In recent years, as the wiring line material for a lower resistance value, Cu has been mainly introduced instead of Al. When Cu is used as the wiring line material, a phenomenon referred to as dishing is generated in a manufacturing process if the wiring line is designed to be wide. Specifically, at a CMP (Chemical Mechanical Polishing) step when a device is manufactured, a concave portion such as the shape of a dish is formed in the surface of the wide Cu wiring line. This implies the reduction in the flatness of the Cu wiring line and the reduction in a film thickness, and consequently leads to increase in the wiring line resistance.
In order to suppress the dishing, it is necessary to limit the wiring line width to a predetermined upper value or less. In order to meet the limit of the wiring line width, one wiring line may be considered to be divided into a plurality of thin wiring lines. For example, in FIG. 1, a power supply wiring line for connection between a first macro cell 101 and a second macro cell 102 is divided into a plurality of wiring lines 110 (hereafter, referred to as [Split Wiring Lines 110]). The plurality of split wiring lines 110 are a wiring line to send a same signal between the macro cells, and their potentials are all equal to each other. That is, the plurality of split wiring lines 110 can be collectively referred to as a bundle of wiring lines 111 to send a certain signal. Since the width W of each split wiring line 110 is limited, the dishing is suppressed.
As technologies associated with wiring design, Japanese Laid Open Patent Application (JP-P2003-141200A) discloses a layout design method aiming at realization of such a design that allows a wiring line occupation rate to meet a standard. According to this conventional layout design method, first, arrangement of the slit wiring lines is performed. Next, a wiring line occupation rate of a certain region including the slit wiring lines is calculated. Next, based on the wiring occupation rate thus calculated, a wiring inhibition area is calculated, that is unlikely to cause a wiring line occupation rate error in the subsequent wiring step. Next, the wiring line inhibition area is set in the above-described certain region.
As described above, in the wide width wiring line such as the power wiring line, a “bundle of wiring lines” is necessary to suppress dishing. A technique capable of further reducing a resistance value of the bundle of wiring lines is desired.

SUMMARY OF THE INVENTION

In an aspect of the present invention, a semiconductor device includes a bundle of wiring lines arranged in parallel and connected to a macro cell to transfer a same signal; and a bridge wiring line configured to bridge adjacent ones of the wiring lines of the bundle. Wiring line resistances between ends of the adjacent wiring lines in the macro cell and nodes of the bridge wiring line with the adjacent two wiring lines are different from each other.
Here, the bundle of wiring lines may include a first wiring line connected at a first end with the macro cell; and a second wiring line connected at a second end with the macro cell. The bridge wiring line may connect first and second nodes on the first and second wiring lines, and a wiring line resistance between the first end and the first node may be different from a wiring line resistance between the second end and the second node.
Also, a distance between the first end and the first node may be different from a distance between the second end and the second node.
Also, a line width of the first wiring line between the first ends and the first node may be different from a line width of the second wiring line between the second ends and the second node.
Also, the bundle of wiring lines may include a first wiring line; a second wiring line arranged adjacently to the first wiring line; and a third wiring line arranged adjacently to the second wiring line. A first bridge wiring line may extend along a first line to bridge the first wiring line and the second wiring line, and a second bridge wiring line may extend along a second line different from the first line to bridge the second wiring line and the third wiring line.
Also, the bundle of wiring lines may include a first wiring layer wiring line formed in a first wiring layer; and a second wiring layer wiring line formed in a second wiring layer. The first wiring layer wiring line and the second wiring layer wiring line may be connected to each other by a via-contact in an overlapping area, and the bridge wiring line may be provided in the overlapping area.
In another aspect of the present invention, a support method for designing a semiconductor device, is achieved by arranging a bundle of wiring lines in parallel in a wiring layer to transfer a same signal; and by arranging a bridge wiring line in the wiring layer to bridge adjacent wiring lines. The bundle of wiring lines and the bridge wiring line are arranged such that wiring line resistances between ends of adjacent wiring lines of the bundle and nodes of the bridge wiring line with the adjacent wiring lines are different from each other.
Here, the arranging a bundle of wiring lines may include arranging a first wiring line connected at a first end with a macro cell; and arranging a second wiring line connected at a second end with the macro cell. The arranging a bridge wiring line may be achieved by arranging the bridge wiring line to connect a first node on the first wiring line and a second node on the second wiring line. A wiring line resistance between the first end and the first node may be different from a wiring line resistance between the second end and the second node.
Also, the arranging a bundle of wiring lines may include arranging a first wiring line connected at a first end with a macro cell; and arranging a second wiring line connected at a second end with the macro cell. The arranging a bridge wiring line may include arranging the bridge wiring line to connect a first node on the first wiring line and a second node on the second wiring line. A distance between the first end and the first node may be different from a distance between the second end and the second node.
Also, the arranging a bundle of wiring lines may include arranging a first wiring line connected at a first end with a macro cell; and arranging a second wiring line connected at a second end with the macro cell. The arranging a bridge wiring line may include arranging the bridge wiring line to connect a first node on the first wiring line and a second node on the second wiring line. A line width of the first wiring line between the first ends and the first node may be different from a line width of the second wiring line between the second ends and the second node.
Also, the arranging a bundle of wiring lines may include a first wiring line; a second wiring line arranged adjacently to the second wiring line; and a third wiring line arranged adjacently to the second wiring line. A first bridge wiring line may extend along a first line to bridge the first wiring line and the second wiring line, and a second bridge wiring line may extend along a second line different from the first line to bridge the second wiring line and the third wiring line.
Also, the bundle of wiring lines may include a first wiring layer wiring line formed in a first wiring layer; and a second wiring layer wiring line formed in a second wiring layer. The first wiring layer wiring line and the second wiring layer wiring line may be connected to each other by a via-contact in an overlapping area, and the bridge wiring line may be provided in the overlapping area.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a structure of a conventional bundle of wiring lines;
FIG. 2 is a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention;
FIG. 3 is a drawing showing connection of a bridge wiring line according to the first embodiment;
FIG. 4A is a drawing showing a combination resistance in a certain circuit;
FIG. 4B is a drawing showing a combination resistance in a circuit example having a bridge wiring line;
FIG. 5 is a plan view showing a structure of the semiconductor device according to a second embodiment according of the present invention;
FIG. 6 is a drawing showing connection of the bridge wiring line of according to the second embodiment;
FIG. 7 is a plan view showing a structure of the semiconductor device according to a third embodiment of the present invention;
FIG. 8 is a drawing showing connection of the bridge wiring line according to the third embodiment;
FIG. 9 is a plan view showing a structure of the semiconductor device according to the embodiment of the present invention;
FIG. 10 is a block diagram showing the configuration of the semiconductor device designing support system according to the embodiment of the present invention;
FIG. 11 is a flowchart showing semiconductor device designing support method according to the embodiment of the present invention; and
FIG. 12 is a drawing showing the semiconductor device designing support method according to the embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a semiconductor device and a support method for designing the semiconductor device according to the present invention will be described in detail with reference to the attached drawings.

First Embodiment

FIG. 2 schematically shows a structure of a semiconductor device according to the first embodiment of the present invention. The semiconductor device includes a first macro cell 1 having a first terminal section 1 a, a second macro cell 2 having a second terminal section 2 a. As the first macro cell 1 and the second macro cell 2, analog circuits are exemplified. A wiring line for connection between the first macro cell 1 and the second macro cell 2, e.g., a power supply wiring line is composed of a plurality of wiring lines 10 and bridge wiring lines 20 disposed in parallel each other.
The plurality of wiring lines 10 connect between the first terminal section 1 a and the second terminal section 2 a in parallel. Namely, the plurality of wiring lines 10 are wiring lines for conveying a same signal among macro cells. In this sense, the plurality of wiring lines 10 may be called collectively as a “bundle of wiring lines 11” for conveying one signal among macro cells. Further, each of wiring lines 10 is referred hereunder to as “split wiring line 10”. Namely, the bundle of wiring lines 11 is composed of a plurality of split wiring lines 10. As for the number of split wiring lines 10, from 50 to 100 wiring lines are exemplified. In order to reduce the wiring line resistance value, Cu is used as the material of the bundle of wiring lines 11. Besides, a wiring line width of each of split wiring lines 10 is limited for the sake of suppression of the dishing.
In the meantime, a bridge wiring line 20 is a wiring line to provide bridging among the plurality of split wiring lines 10. According to the present embodiment, as shown in FIG. 2, the bridge wiring line 20 is provided obliquely with respect to parallel split wiring lines 10. In other words, an angle formed by the bridge wiring line 20 and the split wiring line 10 is less than 90 degrees. For example, it is considered that the plurality of split wiring lines 20 are formed along Y-direction. Further, it is considered that a direction orthogonal to a Y-direction is an X-direction. In this case, the bridge wiring line 20 is formed along a direction intermediate between the X-direction and the Y-direction. For the sake of reduction the wiring line resistance value, Cu is employed as the material for the bridge wiring line 20. Further, the wiring line width of each bridge wiring line 20 is limited, thereby suppressing the dishing.
FIG. 3 shows in detail a relationship between the bundle of wiring lines 11 and the bridge wiring lines 20 associated with the present embodiment. In FIG. 3, of the plurality of split wiring lines 10, two adjacent wiring lines (a first wiring line 10-1, a second wiring line 10-2) are shown. An end T1 of the first wiring line 10-1 and an end T2 of the second wiring line 10-2 are connected to a terminal section of the same macro cell. The bridge wiring lines 20 serve as bridging between the first wiring line 10-1 and the second wiring line 10-2. Specifically, a bridge wiring line 20-1 connects a node N1 on the first wiring line 10-1 and a node N2 on the second wiring line 10-2. Further, a bridge wiring line 20-2 connects a node N3 on the first wiring line 10-1 and a node N4 on the second wiring line 10-2.
According to the present embodiment, the bridge wiring line 20-1 is provided obliquely with respect to the split wiring line 10. Accordingly, a distance L1 between the end T1 of the first wiring line 10-1 and the node N1 is different from a distance L2 between the end T2 of the second wiring line 10-2 and the node N2. In this case, a wiring line resistance between the end T1 and the node N1 is different from a wiring line resistance between the end T2 and the node N2. In other words, wiring line resistances between the ends T1 and T2 and the ends N1 and N2 of the bridge wiring line 20-1 are different from each other.
The same description can be also applied to the bridge wiring line 20-2. A distance L3 between the end T1 of the first wiring line 10-1 and the node N3 is different from a distance L4 between the end T2 of the second wiring line 10-2 and the node N4. In this case, a wiring line resistance between the end T1 and the no de N3 is different from a wiring line resistance between the end T2 and the node N4. In other words, the wiring line resistances between the end T1 and T2 and the nodes N3 and N4 of the bridge wiring line 20-2 are different from each other.
As describe d above, a resistance value between both ends of the bride wiring line 20 and macro cell terminal sections is different. In this case, an electric potential difference or voltage is caused between the nodes N1 and N2 (or N3 and N4) of the bridge wiring line 20. When the voltage is generated between the nodes of the bridge wiring line 20, the bridge wiring line 20 plays a role of reducing resistance value of the bundle of wiring lines 11. The following description will show reduction in resistance value by using examples.
In FIG. 4A, two wiring lines are used to connect macro cells. Each wiring line has three resistances R1 connected in series. When a resistance value of one resistance R1 is “4”, a synthetic resistance R will be “6”. In the meantime, in FIG. 4B, a resistance R2 is added to the configuration shown in FIG. 4A. This resistance R2 bridges two wiring lines and is corresponding to the bridge wiring line 20. Further, the resistance R2 is provided obliquely with respect to each wiring line and an electric potential difference or a voltage is generated between the nodes of the resistance R2. For example, when a resistance value of the resistance R2 is “5”, the synthetic resistance R is calculated to be “5.64”. In this way, when the bridge wiring line 20 is provided to generate a voltage between the nodes, the synthetic resistance R is reduced. Although cases of two wiring lines are shown in FIGS. 4A and 4B, there are numerous split wiring lines 10 in practice, and the bridge wiring lines 20 are also provided in large numbers. In such a case, a rate of reduction in the synthetic resistance R is further increased, and a resistance value is reduced by approximately 20% as a whole.

Second Embodiment

FIG. 5 schematically shows a structure of a semiconductor device according to the second embodiment of the present invention. In FIG. 5, the same components are assigned with the same reference numerals as those shown in FIG. 2, and the same description is omitted accordingly.
In the present embodiment, the bundle of wiring lines 11 includes the split wiring lines 10 with different width. Preferably, the wiring line widths are different among the adjacent split wiring lines 10. Further, as shown in FIG. 5, the wiring line width may be different depending on position in the split wiring line 10. In this way, according to the present embodiment, the bundle of wiring lines 11 are formed so that the wiring line widths become uneven intentionally. In FIG. 5, the plurality of split wiring lines 10 are formed in parallel along the Y-direction, while the bridge wiring lines 20 are formed along X-direction to bridge the adjacent split wiring lines 10. However, similarly to the first embodiment, the bridge wiring line 20 may be provided obliquely with respect to the split wiring lines 10.
In FIG. 6, a relationship between the bundle of wiring lines 11 and the bridge wiring lines 20 according to the present embodiment is illustrated in detail. In FIG. 6, of the plurality of split wiring lines 10, adjacent two (the first wiring line 10-1, the second wiring line 10-2) are shown. The end T1 of the first wiring line 10-1 and the end T2 of the second wiring line 10-2 are connected to the terminal section of the same macro cell. The bridge wiring lines 20 bridge the adjacent first wiring line 10-1 and the second wiring line 10-2. Specifically, the bridge wiring line 20-1 connects the node N1 on the first wiring line 10-1 with the node N2 on the second wiring line 10-2. Further, the bridge wiring line 20-2 connects the node N3 on the first wiring line 10-1 with the node N4 on the second wiring line 10-2.
According to the present embodiment, a wiring line width W1 between the end T1 of the first wiring line 10-1 and the node N1 is different from the wiring line width W2 between the end T2 of the second wiring line 10-2 and the node N2. In this case, the wiring line resistance between the end T1 and the node N1 is different from the wiring line resistance between the end T2 and the node N2. In other words, the wiring line resistance between the ends T1 and T2, and the nodes N1 and N2 of the bridge wiring line 20-1 are different from each other.
The same description can be also applied to the bridge wiring line 20-2. The wiring line width W3 between the node N1 and the node N3 is different from a wiring line width W4 between the node N2 and the node N4. In this case, a wiring line resistance between the nodes N1 and N3 is different from wiring line resistance between the nodes N2 and N4. Preferably, a wiring line resistance between the end T1 and the node N3 is different from a wiring line resistance between the end T2 and the node N4.
As described above, resistance values between both ends of the bridge wiring line 20 and ends in the macro cell terminal section are different. In this case, a voltage is generated between the nodes N1 and N2 (or N3 and N4) of the bridge wiring line 20. Since the voltage is generated between the nodes of the bridge wiring line 20, a resistance value of the bundle of wiring lines 11 is reduced as a whole.

Third Embodiment

FIG. 7 schematically shows a structure of the semiconductor device according to the third embodiment of the present invention. In FIG. 7, the same components as those shown in FIG. 2 are assigned with the same reference numerals as those shown in FIG. 2, and the same description is omitted accordingly.
In the present embodiment, the bundle of wiring lines 11 includes the plurality of split wiring lines 10 formed along the Y-direction. The wiring line widths of the plurality of these split wiring lines 10 may be identical. Further, the bridge wiring lines 20 are formed along the X-direction to bridge the adjacent split wiring lines 10. Here, the plurality of bridge wiring lines 20 are provided in staggered manner. In other words, the plurality of bridge wiring lines 20 are provided to be distributed in a scattered fashion. In other words, the bundle of wiring lines 11 and the bridge wiring lines 20 are composed to generate an asymmetrical layout pattern as a whole.
In FIG. 8, a relationship between the bundle of wiring lines 11 and the bridge wiring lines 20 according to the present embodiment is shown in further detail. In FIG. 8, of the plurality of split wiring lines 10, adjacent three wiring lines (first wiring line 10-1, second wiring line 10-2, and third wiring line 10-3) are shown. The end T1 of the first wiring line 10-1, the end T2 of the second wiring line 10-2, an end T3 of the third wiring line 10-3 are connected to a terminal section of the same macro cell. The bridge wiring line 20-1 bridges between the first wiring line 10-1 and the second wiring line 10-2, and connects between a node N1 on the first wiring line 10-1 and a node N2 on the second wiring line 10-2. The bridge wiring line 20-2 bridges between the second wiring line 10-2 and the third wiring line 10-3, and connects between a node N3 on the second wiring line 10-2 and a node N4 on the third wiring line 10-3. The bridge wiring line 20-3 bridges between the first wiring line 10-1 and the second wiring line 10-2, and connects between a node N5 on the first wiring line 10-1 and a node N6 on the second wiring line 10-2.
In the present embodiment, the bridge wiring line 20-1 and the bridge wiring line 20-2 are not arranged on the same straight line. In other words, when the bridge wiring line 20-1 is formed along a certain straight line, the bridge wiring line 20-2 is formed along a straight line different from said straight line. In addition, the bridge wiring line 20-2 and the bridge wiring line 20-3 are not arranged on the same straight line. In other words, when the bridge wiring line 20-2 is formed along a certain straight line, the bridge 20-3 is formed along a straight line different from the straight line.
As described above, if the bridge wiring lines 20 are arranged asymmetrically in a scattered fashion, a resistance value between the nodes of the bridge wiring line 20 and ends in the macro cell terminal section are different from each other. In this case, a voltage is generated between the nodes of the bridge wiring line 20. Since the voltage is generated between the nodes of the bridge wiring line 20, the resistance value of the bundle of wiring lines 11 is reduced as a whole.
FIG. 9 shows a case where the bundle of wiring lines 11 cover more than one wiring line layers. In FIG. 9, a bundle of wiring lines connecting between the first macro cell 1 and the second macro cell 2 includes a first bundle of wiring lines 11-1 formed in a first wiring line layer and a second bundle of wiring lines 11-2 formed in a second wiring line layer. The first bundle of wiring lines 11-1 and the second bundle of wiring lines 11-2 overlap each other in an overlapping region RO. The first bundle of wiring lines 11-1 and the second bundle of wiring lines 11-2 are connected to each other through via-contacts 30 in the overlapping region RO. Even in such a case, the bridge wiring lines 20 re disposed in each wiring line layer in a similar fashion as described above. Particularly, it should be noted that the bridge wiring line 20 is also formed in the overlapping region RO. With this structure, a resistance value is reduced as a whole of the bundle of wiring lines. Although FIG. 9 shows a case that the third embodiment is applied, other embodiments may be applied.
[Semiconductor Device Designing Support System]
A semiconductor device designing support system will be shown hereafter. FIG. 10 is a block diagram showing one example of the semiconductor device designing support system 40. The semiconductor device designing support system 40 is a computer system including a storage unit 41, a processing unit 42, an input unit 43, and a display unit 44.
As for the storage unit 41, HDD, RAM or the like are exemplified. Various data are stored in the storage unit 41. A net list 51 shows a desired connection relationship between elements in a semiconductor device. A wiring rule data 52 shows a design rule relating to wiring lines. A bundle of wiring position data 53 shows a position of a disposed bundle of wiring lines and is used when the bridge wiring lines 20 are disposed. A layout data 54 shows a layout of the semiconductor device obtained after a layout design.
The processing unit 42 can access to the storage unit 41. As the input unit 43, a keyboard and a mouse are exemplified. By using the input unit 43, a user can set the wiring line width and the wiring line interval or to input various commands. Besides, the user can perform the layout design while referring to data displayed on the display unit 44.
Further, the semiconductor device designing support system 40 has a design program (layout program) 45. The design program 45 is a computer software executed by the processing unit 42. The design program 45 may be recorded into a computer-readable recording medium. A system executing the following circuit design processing is constructed by the design program 45 and the processing unit 42.
FIG. 11 is a flowchart showing a layout method of wiring lines according to the present invention. First, the system reads from the storage unit 41 the net list 51 and the wiring rule data 52 (step S11). The wiring rule data 52 shows the rule (design standard) for generating the wiring lines. As the wiring line rule, a maximum wiring line width, a limit value for the wiring line interval, a minimum area enclosed by the wiring line layer wiring lines are mentioned. The maximum wiring line width is specified so that dishing in a manufacturing process can be prevented. Further, the limit value for the wiring line interval depends upon the maximum wiring width.
Next, the number of wiring lines, the wiring line width and the wiring line layer as a layout object are specified (step S12). This specification is carried out by the user using the input unit 43. Upon completion of the specification by the user, the system checks whether or not the specification does not violate the wiring rule (step S13). When the specification violates the wiring rule (step S13; NG), the user executes the specification again.
When the foregoing specification meets the wiring rule (step S13; OK), a position of arrangement of the bundle of wiring lines (start point and end point) is specified (step S14). This specification is carried out by the user using the input unit 43. Upon completion of the specification by the user, the system checks whether or not it is possible to arrange the bundle of wiring lines in the specified position (step S15). When it is not possible to arrange the wiring lines (step S15; NG), a control flow returns to the step S12. When it is possible to arrange the wiring lines (step S15; Yes), the system disposes the bundle of wiring lines in the specified position on the specified layer (step S16).
As shown in the embodiments described previously, the bundle of wiring lines is composed of the plurality of split wiring lines for conveying the same signal. From the viewpoint of the netlist 51, it may be said that the bundle of wiring lines is a wiring line associated with the same net. After the bundle of wiring lines is disposed, the system prepares the wiring position data 53 showing the position (start point and end point) of the bundle of wiring lines, and stores it to the storage unit 41.
Next, the arrangement of the bridge wiring lines is performed. First, the system reads out from the storage unit 41 the above-described wiring position data 53 (step S21). Next, the system calculates the position (start point and end point) of bridge wiring lines for bridging adjacent split wiring lines by referring to the position of the bundle of wiring lines (step S22). It is possible to dispose one bridge wiring line across more than two split wiring lines. Here, as shown in the embodiment shown previously, the position of the bridge wiring line is determined so that upon device start, a voltage is generated between the nodes of the bridge wiring line concerned. When no voltage is generated between the nodes of the bridge wiring line, the bridge wiring line has no influence upon resistance value of the bundle of wiring lines. However, when the voltage is generated between the nodes of the bridge wiring line, a resistance value of the bundle of wiring lines is reduced by the bridge wiring line.
Next, the system checks whether or not the position of the determined bridge wiring line violates the above-described wiring rule (step S23). One example of bridge wiring line checking is shown in FIG. 12. In FIG. 12, two split wiring lines 10-1, 10-2 for connecting between the macro cell terminal section 1 a and 1 b are disposed. Further, the bridge wiring lines 20-1 through 20-4 for bridging two split wiring lines 10-1, 10-2 are disposed. In a step S23, it is checked whether or not the interval between the adjacent bridge wiring lines 20 is more than a limit value specified based on the wiring rule. Further, it is checked whether or not an area enclosed by the split wiring lines 10 and the bridge wiring lines 20 is more than the minimum area specified based on the wiring rule. When the position of the determined bridge wiring line violates the wiring rule (step S23; NG), the position of the bridge wiring line is calculated again.
Alternatively, determination of a bridge wiring line position (step S22) and a position checking (step S23) may be performed in parallel. Referring to FIG. 12, a position of the bridge wiring line 20-1 that is the closest to the macro cell terminal section 1 a is determined to meet a predetermined minimum area. Subsequently, a position of the bridge wiring line 20-2 adjacent to the bridge wiring line 20-1 is determined to meet the predetermined minimum wiring interval and the minimum area. Similarly, positions of the bridge wiring lines 20-3 and 20-4 are determined in turn. In this way, referring to the wiring rule data 52, a position of the bridge wiring line 20 is determined in turn so as to meet the wiring rule. In order to reduce a resistance value of the bundle of wiring lines 11 furthermore, it is preferable to provide as many bridge wiring lines 20 as possible.
Referring again to FIG. 11, when a position of the determined bridge wiring line meets the wiring rule (step S23; Yes), the system disposes the bridge wiring line in the determined position on the specified wiring layer (step S24). Subsequently, when the bridge wiring line is necessary for another bundle of wiring lines (step S25; No), the processing is repeated from step S21. When arrangement of the bridge wiring line is finalized (step S25; Yes) and arrangement of all wiring lines is completed (step S30), the control flow is completed. The layout data showing a layout of the semiconductor device is stored in the storage unit 41.
In the first embodiment, in the above-mentioned step S16 (arrangement of bundle of wiring lines), the bundle of wiring lines is specified in a conventional manner. After that, in the above-described step S22 (determination of a position of a bridge wiring line), the bridge wiring line is designed so that an angle formed between the bridge wiring line and the split wiring line becomes less than 90 degrees (see FIGS. 2 and 3). In case of the first embodiment, as shown in FIG. 2, it is possible to dispose one bridge wiring line across more than two split wiring lines. Therefore, a design process is comparatively simplified. In addition, there is such an advantage that an amount of data for expressing a position (start point and end point) of the bridge wiring line is reduced due to fewer number of the bridge wiring lines.
In the second embodiment, in the above-described step S16 (arrangement of the bundle of wiring lines), the bundle of wiring lines is specified so as to include split wiring lines with different wiring line widths (see FIGS. 5, and 6). Thereafter, in the above-described step S22 (determination of the position of bridge wiring line), the bridge wiring line is specified to connect the split wiring lines having different wiring line widths. In case of the third embodiment, in the above-mentioned step S16 (arrangement of the bundle of wiring lines), the bundle of wiring lines is specified in the conventional manner. Thereafter, in the above-described step S22 (determination of a position of the bridge wiring line), the bridge wiring lines are provided asymmetrically in a scattered fashion (see FIGS. 7, and 8).
As shown above, the bundle of wiring lines and the bridge wiring lines are laid out so that wiring line resistances between nodes of the bridge wiring line and ends in the macro cell terminal sections are different from each other. With this structure, upon a device start, the voltage is generated between the nodes of the bridge wiring line and a resistance value of the bundle of wiring lines is reduced as a whole.
According to the semiconductor device and designing support method thereof of the present invention, a resistance value of the bundle of wiring lines is reduced as a whole.

Claims

1. A semiconductor device comprising:

a bundle of wiring lines arranged in parallel and connected to a macro cell to transfer a same signal; and

a bridge wiring line configured to bridge adjacent ones of said wiring lines of the bundle,

wherein wiring line resistances between ends of said adjacent wiring lines in said macro cell and nodes of said bridge wiring line with said adjacent two wiring lines are different from each other.

2. The semiconductor device according to claim 1, wherein said bundle of wiring lines comprises:

a first wiring line connected at a first end with said macro cell; and

a second wiring line connected at a second end with said macro cell,

said bridge wiring line connects first and second nodes on said first and second wiring lines, and

a wiring line resistance between said first end and said first node is different from a wiring line resistance between said second end and said second node.

3. The semiconductor device according to claim 2, wherein a distance between said first end and said first node is different from a distance between said second end and said second node.

4. The semiconductor device according to claim 2, wherein a line width of said first wiring line between said first ends and said first node is different from a line width of said second wiring line between said second ends and said second node.

5. The semiconductor device according to claim 1, wherein said bundle of wiring lines comprises:

a first wiring line;

a second wiring line arranged adjacently to said first wiring line; and

a third wiring line arranged adjacently to said second wiring line,

a first bridge wiring line extends along a first line to bridge said first wiring line and said second wiring line, and

a second bridge wiring line extends along a second line different from said first line to bridge said second wiring line and said third wiring line.

6. The semiconductor device according to claim 1, wherein said bundle of wiring lines comprises:

a first wiring layer wiring line formed in a first wiring layer; and

a second wiring layer wiring line formed in a second wiring layer,

said first wiring layer wiring line and said second wiring layer wiring line are connected to each other by a via-contact in an overlapping area, and

said bridge wiring line is provided in said overlapping area.

7. A support method for designing a semiconductor device, comprising:

arranging a bundle of wiring lines in parallel in a wiring layer to transfer a same signal; and

arranging a bridge wiring line in said wiring layer to bridge adjacent wiring lines,

said bundle of wiring lines and said bridge wiring line are arranged such that wiring line resistances between ends of adjacent wiring lines of the bundle and nodes of said bridge wiring line with said adjacent wiring lines are different from each other.

8. The support method according to claim 7, wherein said arranging a bundle of wiring lines comprises:

arranging a first wiring line connected at a first end with a macro cell; and

arranging a second wiring line connected at a second end with said macro cell,

said arranging a bridge wiring line comprises:

arranging said bridge wiring line to connect a first node on said first wiring line and a second node on said second wiring line, and

9. The support method according to claim 7, wherein said arranging a bundle of wiring lines comprises:

arranging a first wiring line connected at a first end with a macro cell; and

arranging a second wiring line connected at a second end with said macro cell,

said arranging a bridge wiring line comprises:

a distance between said first end and said first node is different from a distance between said second end and said second node.

10. The support method according to claim 7, wherein said arranging a bundle of wiring lines comprises:

arranging a first wiring line connected at a first end with a macro cell; and

arranging a second wiring line connected at a second end with said macro cell, said arranging a bridge wiring line comprises:

a line width of said first wiring line between said first ends and said first node is different from a line width of said second wiring line between said second ends and said second node.

11. The support method according to claim 7, wherein said arranging a bundle of wiring lines comprises:

a first wiring line;

a second wiring line arranged adjacently to said second wiring line; and

a third wiring line arranged adjacently to said second wiring line,

12. The support method according to claim 7, wherein said bundle of wiring lines comprises:

a first wiring layer wiring line formed in a first wiring layer; and

a second wiring layer wiring line formed in a second wiring layer,

said bridge wiring line is provided in said overlapping area.