US20060026396A1

US20060026396A1 - Memory access instruction with optional error check

Info

Publication number: US20060026396A1
Application number: US11/116,893
Authority: US
Inventors: Jean-Philippe Lesot; Gerard Chauvel
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2004-07-27
Filing date: 2005-04-28
Publication date: 2006-02-02
Also published as: US20060026394A1; US7546437B2; US7533250B2; US7543285B2; US20060026563A1; US7930689B2; US8078842B2; US20060026353A1; US8024716B2; US20060026397A1; US20060023517A1; US7587583B2; US20060026370A1; US20060026405A1; US20060026392A1; US20060026393A1; US20060026404A1; US7752610B2; US7493476B2; US9201807B2

Abstract

A processor executes a load (or store) instruction that permits optional error checking to be performed. Based on a control bit in the load instruction, the processor executes the load instruction by causing contents of a source register to be compared to a predetermined value. If the contents of the source register equals the predetermined value, the processor executes an exception handler. However, if the source register contents differs from the predetermined value, the load instruction causes the processor to cause a data value from memory to be loaded into a destination register

Description

CROSS REFERENCE TO RELATED CASES

This application claims the benefit of European Patent Application No. 04291918.3, filed Jul. 27, 2004, incorporated by reference herein as if reproduced in full below.

BACKGROUND

1. Technical Field
The present subject matter relates generally to processors and more particularly to an executable load instruction that copies data from memory to a register and causes an optional check for an error condition to be performed.
2. Background Information
Many types of electronic devices are battery operated and thus preferably consume as little power as possible. An example is a cellular telephone. Further, it may be desirable to implement various types of multimedia functionality in an electronic device such as a cell phone. Examples of multimedia functionality may include, without limitation, games, audio decoders, digital cameras, etc. It is thus desirable to implement such functionality in an electronic device in a way that, all else being equal, is fast, consumes as little power as possible and requires as little memory as possible. Improvements in this area are desirable.

BRIEF SUMMARY

In at least one embodiment, a processor executes a load instruction (or a store instruction) that permits optional error checking to be performed. Based on a control bit in the load instruction, the processor executes the load instruction by causing contents of a source register to be compared to a predetermined value. If the contents of the source register equals the predetermined value, the processor executes an exception handler. However, if the source register contents differs from the predetermined value, the load instruction causes the processor to cause a data value from memory to be loaded into a destination register.
In accordance with another embodiment, a method is described for executing a load (or store) instruction that contains an identity of a source register and a destination register. The method comprises examining the instruction to determine a state of a control bit. If the control bit is at a first state, the method comprises comparing a value in the source register to an error value and generating an exception if the source register value equals the error value. However, if the control bit is at a second state, the method comprises loading data from a memory location into the destination register, wherein the memory location has an address based on the source register value.
In yet another embodiment, a system comprises a main processor unit and a co-processor coupled to the main processor unit. The co-processor comprises a plurality of registers and executes a load (or store) instruction. If a control bit in the load instruction is in a first state, the instruction causes contents of a source register to be compared to a predetermined value. If the contents equals the predetermined value, the load instruction causes an exception to be generated. However, if the control bit is in a second state, the instruction causes data to be loaded from a memory address into a register. The contents of the source register is used to calculate the memory address.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, various companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to.” Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more detailed description of the preferred embodiments of the present invention, reference will now be made to the accompanying drawings, wherein:
FIG. 1 shows a diagram of a system in accordance with preferred embodiments of the invention and including a Java Stack Machine (“JSM”) and a Main Processor Unit (“MPU”);
FIG. 2 illustrates an embodiment of the invention in the form of a battery operated, wireless communication device such as a cellular telephone;
FIG. 3 shows a block diagram of the JSM of FIG. 1 in accordance with preferred embodiments of the invention;
FIG. 4 shows various of the registers of the JSM;
FIGS. 5 and 6 show various embodiments of functions performed by a load instruction in accordance with the preferred embodiment of the invention; and
FIG. 7 shows an exemplary format of the load instruction in accordance with a preferred embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims, unless otherwise specified. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
The subject matter disclosed herein is directed to a programmable electronic device such as a processor that executes various instructions including, without limitation, a long load (“LLD”) instruction. As will be explained in detail below, the LLD instruction causes an optional error check to be performed. If the error check determines that no error condition exists, the LLD instruction then causes data from memory to be loaded into a register in the processor. If the error condition does exist, then the load operation is not performed and an exception is generated by which the processor handles and resolves the error condition. The LLD instruction includes values from which a memory address that contains the target data is calculated. In some embodiments, the optional error check involves determining whether a value in the LLD instruction that is used to calculate the memory address for the load is a particular value that is predetermined to be an incorrect value for purposes of calculating a memory address. That predetermined value is referred to herein as the “null” value and, in some embodiments, is the 0 value. In other embodiments, a store instruction is executed that can be configured to perform an optional error check.
The LLD instruction's ability to check for a null value is optional and can be enabled by setting a control bit in the instruction itself. Thus, if desired, the LLD instruction can be configured to perform the error check by setting the control bit, or alternatively the LLD instruction can be configured to avoid error checking. If error checking is enabled and the error condition exists, the target data from memory is not loaded into a register and, instead, the processor causes an error exception process to be performed.
The following describes the operation of a preferred embodiment of a processor on which the LLD instruction may run. Other processor architectures and embodiments may be available or developed on which to run the instruction and thus this disclosure and the claims which follow are not limited to any particular type of processor. Details regarding the operation and format of the LLD instruction follow the description of the processor.
The processor described herein is particularly suited for executing Java™ Bytecodes or comparable code. As is well known, Java is particularly suited for embedded applications. Java is a relatively “dense” language meaning that on average each instruction may perform a large number of functions compared to various other programming languages. The dense nature of Java is of particular benefit for portable, battery-operated devices that preferably include as little memory as possible to save space and power. The reason, however, for executing Java code is not material to this disclosure or the claims which follow. The processor described herein may be used in a wide variety of electronic systems. By way of example and without limitation, the Java-executing processor described herein may be used in a portable, battery-operated communication device such as a cellular telephone, personal data assistants (“PDAs”), etc. Further, the processor advantageously includes one or more features that permit the execution of the Java code to be accelerated.
Referring now to FIG. 1, a system 100 is shown in accordance with a preferred embodiment of the invention. As shown, the system includes at least two processors 102 and 104. Processor 102 is referred to for purposes of this disclosure as a Java Stack Machine (“JSM”) and processor 104 may be referred to as a Main Processor Unit (“MPU”). System 100 may also include memory 106 coupled to both the JSM 102 and MPU 104 and thus accessible by both processors. At least a portion of the memory 106 may be shared by both processors meaning that both processors may access the same shared memory locations. Further, if desired, a portion of the memory 106 may be designated as private to one processor or the other. System 100 also includes a Java Virtual Machine (“JVM”) 108, compiler 110, and a display 114. The JSM 102 and/or MPU 104 preferably includes an interface to one or more input/output (“I/O”) devices such as a keypad to permit a user to control various aspects of the system 100. In addition, data streams may be received from the I/O space into the JSM 102 to be processed by the JSM 102. Other components (not specifically shown) may include, without limitation, a battery and an analog transceiver to permit wireless communications with other devices. As noted above, while system 100 may be representative of, or adapted to, a wide variety of electronic systems, an exemplary electronic system may comprise a battery-operated, mobile cell phone such as that is shown in FIG. 2.
As shown in FIG. 2, a mobile communications device includes an integrated keypad 412 and display 414. Two processors and other components may be included in electronics package 410 connected to keypad 412, display 414, and radio frequency (“RF”) circuitry 416 which may be connected to an antenna 418.
As is generally well known, Java code comprises a plurality of “bytecodes” 112. Bytecodes 112 may be provided to the JVM 108, compiled by compiler 110 and provided to the JSM 102 and/or MPU 104 for execution therein. In accordance with a preferred embodiment of the invention, the JSM 102 may execute at least some, and generally most, of the Java bytecodes. When appropriate, however, the JSM 102 may request the MPU 104 to execute one or more Java bytecodes not executed or executable by the JSM 102. In addition to executing Java bytecodes, the MPU 104 also may execute non-Java instructions. The MPU 104 also hosts an operating system (“O/S”) (not specifically shown), which performs various functions including system memory management, system task management for scheduling the JVM 108 and most, or all, other native tasks running on the system, management of the display 114, receiving input from input devices, etc. Without limitation, Java code may be used to perform any one of a variety of applications including multimedia data processing, games or web-based applications, while non-Java code, which may comprise the O/S and other native applications, may still run on the system on the MPU 104.
The JVM 108 generally comprises a combination of software and hardware. The software may include the compiler 110 and the hardware may include the JSM 102. The JVM may include a class loader, bytecode verifier, garbage collector, and a bytecode interpreter loop to interpret the bytecodes that are not executed on the JSM processor 102.
In accordance with preferred embodiments of the invention, the JSM 102 may execute at least two instruction sets. One instruction set may comprise standard Java bytecodes. As is well-known, Java is a stack-based programming language in which instructions generally target a stack. For example, an integer add (“IADD”) Java instruction pops two integers off the top of the stack, adds them together, and pushes the sum back on the stack. The JSM 102 comprises a stack-based architecture with various features that accelerate the execution of stack-based Java code, such as those described in U.S. Pat. Pub. Nos. 2004/0078550, 2004/0078557, and 2004/0024999, all of which are incorporated herein by reference.
Another instruction set executed by the JSM 102 may include instructions other than standard Java instructions. In accordance with at least some embodiments of the invention, such other instruction set may include register-based and memory-based operations. This other instruction set generally complements the Java instruction set and, accordingly, may be referred to as a complementary instruction set architecture (“CISA”). By complementary, it is meant that the execution of one or more Java bytecodes may be substituted by “microsequences” using CISA instructions that enable faster, more efficient operation. The two sets of instructions may be used in a complementary fashion to obtain satisfactory code density and efficiency. As such, the JSM 102 generally comprises a stack-based architecture for efficient and accelerated execution of Java bytecodes combined with a register-based architecture for executing register and memory based CISA instructions. Both architectures preferably are tightly combined and integrated through the CISA.
FIG. 3 shows an exemplary block diagram of the JSM 102. As shown, the JSM includes a core 120 coupled to data storage 122 and instruction storage 130. The core may include one or more components as shown. Such components preferably include a plurality of registers 140, address generation units (“AGUs”) 142, 147, micro-translation lookaside buffers (micro-TLBs) 144,156, a multi-entry micro-stack 146, an arithmetic logic unit (“ALU”) 148, a multiplier 150, decode logic 152, and instruction fetch logic 154. In general, operands may be retrieved from data storage 122 or from the micro-stack 146 and processed by the ALU 148, while instructions may be fetched from instruction storage 130 by fetch logic 154 and decoded by decode logic 152. The address generation unit 142 may be used to calculate addresses based, at least in part, on data contained in the registers 140. The AGUs 142 may calculate addresses for CISA instructions. The AGUs 142 may support parallel data accesses for CISA instructions that perform array or other types of processing. AGU 147 couples to the micro-stack 146 and manages overflow and underflow conditions in the micro-stack, preferably in parallel. The micro-TLBs 144, 156 generally perform the function of a cache for the address translation and memory protection information bits that are preferably under the control of the operating system running on the MPU 104.
Referring now to FIG. 4, the registers 140 may include 16 registers designated as R0-R15. All registers are 32-bit registers in accordance with the preferred embodiment of the invention. Registers R0-R5 and R8-R14 may be used as general purpose (“GP”) registers, thereby usable for any purpose by the programmer. Other registers, and at least one of the GP purpose registers, may be used for specific functions. For example, in addition to use as a GP register, register R5 may be used to store the base address of a portion of memory in which Java local variables may be stored when used by the current Java method. The top of the micro-stack 146 is reflected in registers R6 and R7. The top of the micro-stack has a matching address in memory pointed to by register R6. The values contained in the micro-stack are the latest updated values, while their corresponding values in memory may or may not be up to date. Register R7 provides the data value stored at the top of the micro-stack. Register R15 is used for status and control of the JSM 102. Another register set may also be included in the JSM 102. That register set is shown in FIG. 3 as an “auxiliary” register set and may include one or more registers that include general purpose and specific use registers. Examples of specific use auxiliary registers include a register for storing the program counter (“PC”) and a register for storing a program counter for executing micro-sequences (“micro-PC”).
Referring again to FIG. 3, as noted above, the JSM 102 is adapted to process and execute instructions from at least two instruction sets. One instruction set includes stack-based operations and the second instruction set includes register-based and memory-based operations. The stack-based instruction set may include Java bytecodes. Java bytecodes pop, unless empty, data from and push data onto the micro-stack 146. The micro-stack 146 preferably comprises the top n entries of a larger stack that is implemented in data storage 122. Although the value of n may vary in different embodiments, in accordance with at least some embodiments, the size n of the micro-stack may be the top eight entries in the larger, memory-based stack. The micro-stack 146 preferably comprises a plurality of gates in the core 120 of the JSM 102. By implementing the micro-stack 146 in gates (e.g., registers) in the core 120 of the processor 102, access to the data contained in the micro-stack 146 is generally very fast, although any particular access speed is not a limitation on this disclosure.
The second, register-based, memory-based instruction set may comprise the CISA instruction set introduced above. The CISA instruction set preferably is complementary to the Java bytecode instruction set in that the CISA instructions may be used to accelerate or otherwise enhance the execution of Java bytecodes. For example, the compiler 110 may scan a series of Java bytes codes 112 and replace one or more of such bytecodes with an optimized code segment mixing CISA and bytecodes and which is capable of more efficiently performing the function(s) performed by the initial group of Java bytecodes. In at least this way, Java execution may be accelerated by the JSM 102. The CISA instruction set includes a plurality of instructions including a “LLD” instruction as mentioned above and explained below in detail.
Referring still to FIG. 3, the ALU 148 adds, subtracts, and shifts data. The multiplier 150 may be used to multiply two values together in one or more cycles. The instruction fetch logic 154 generally fetches instructions from instruction storage 130. The instructions are decoded by decode logic 152. Because the JSM 102 is adapted to process instructions from at least two instruction sets, the decode logic 152 generally comprises at least two modes of operation, one mode for each instruction set. As such, the decode logic unit 152 may include a Java mode in which Java instructions may be decoded and a CISA mode in which CISA instructions may be decoded. In a preferred embodiment, the decode logic provides the capability to decode, in a given mode, an instruction associated with the other mode without penalty using a specific prefix.
The data storage 122 generally comprises data cache (“D-cache”) 124 and data random access memory (“D-RAMset”) 126. Reference may be made to U.S. patent Publications Ser. No. 09/591,537 filed Jun. 9, 2000 (atty docket TI-29884), Ser. No. 09/591,656 filed Jun. 9, 2000 (atty docket TI-29960), Ser. No. 09/932,794 filed Aug. 17, 2001 (atty docket TI-31351), and U.S. Pat. Pub. No. 20040260904, all of which are incorporated herein by reference, for information related to the D-RAMset. The stack (excluding the micro-stack 146), arrays and non-critical data may be stored in the D-cache 124, while Java local variables, critical data and non-Java variables (e.g., C, C++) may be stored in D-RAMset 126. The instruction storage 130 may comprise instruction RAM (“I-RAM”) 132 and instruction cache (“I-cache”) 134.
One of the CISA instructions, as noted above, is the “LLD” instruction. Various embodiments of the function performed by the LLD instruction are illustrated in FIGS. 5 and 6. Referring first to the left-hand side of FIG. 5, the LLD instruction causes an error check to be performed in which the contents of a source register (“Rs1”) is compared to the NULL value. As noted above, the NULL value may be 0, but in general, can be any value. Typically, the NULL value is a value that, when used to calculate the target memory address of a load, would result in an incorrect address. An exception is generated if a control bit N contained in the LLD instruction is at a first logic state (e.g., “1”). The AND gate 170 functionally illustrates that the N bit enables or disables the optional error checking feature of the LLD instruction. The right-hand side of FIG. 5 relates to the calculation of a memory address to perform the load aspect of the LLD instruction. If an exception is generated, however, the load preferably is not performed and, instead, an exception is generated and processed by the processor. This portion of FIG. 5 illustrates that a memory address is calculated by adding together the contents of the Rs1 source register (assuming that it does not equal the NULL value) to an immediate value (“V”) which is contained in the LLD instruction. The contents of Rs1 represents a base address and the value V represents an index. The resulting address from the adder 171 is used as the memory address into the data storage 122 to cause a data value located at the calculated address to be loaded into a destination register. The destination data register is identified in the LLD instruction. In some embodiments, the destination register (Rd) is one of the general purpose registers in register set 140. In other embodiments, the destination register is one of the registers in the auxiliary register set 153.
FIG. 6 is similar to FIG. 5 in terms of the implementation of the optional error checking feature. The main difference in FIG. 6 involves the calculation of the memory address. Whereas in FIG. 5 the memory address is calculated by adding the contents of Rs1 to an immediate value (V) provided in the LLD instruction, in FIG. 6, the memory address is calculated by adding the base address from Rs1 to an index value from another source register (ARs). The identity of register ARs (which may be one of the auxiliary registers 153) is provided in the LLD instruction. FIG. 6 also illustrates that the index value contained in register ARs is post-incremented by an immediate value V contained in the instruction with the result stored back in register ARs. In this manner, the index value is updated for subsequent use (e.g., for the next execution of the LLD instruction). This type of addressing scheme with post increment is particularly useful for loading consecutive values from a data structure such as an array.
FIG. 7 illustrates an exemplary layout of the bits comprising a preferred embodiment of the LLD instruction. As shown, the LLD instruction comprises a 32-bit instruction, although the number of bits for the instruction can be varied as desired. In the embodiment of FIG. 7, the LLD instruction comprises fields 250-270. Field 250 comprises an instruction class field 250 that identifies the class to which the instruction pertains. Some classes may have only a single instruction pertaining thereto and thus the instruction class field 250 identifies the particular instruction (similar to an opcode). The LLD instruction pertains to an instruction class that includes multiple instructions including LLD and other instructions. In this situation, the particular instruction is identified by the OpX1 value in field 270. Thus, the OpX1 value in FIG. 7 is a value that uniquely identifies the instruction as an LLD instruction.
Bits 24 through 27 (field 252) comprises a 4-bit field that identifies the particular register to be used as the destination register Rd in which to load the data retrieved from memory. As shown in FIG. 3, at least two register sets 140 and 153 exist. The destination register may comprise a register from either register set. The A bit field 264 designates which of the register sets is to be used for the destination register. For example, if the A bit field is a logic “0,” then register set 140 is used, otherwise auxiliary register set 153 is used. Thus, if the Rd field 252 comprises a value of 3 and the A bit is a value of 0, then the destination register is register R3 from register set 140. Continuing this example, if the A bit is a value of 1, then the destination register is register R3 from auxiliary register set 153.
The N bit field 262 comprises the control bit explained above that is programmable to enable or disable error checking. The Rs1 source field 256 comprises the base address to be used in the address calculation. The index value to be added to the base address comes either from the V bit field 268 (which includes a sign bit S) or from another source register (ARs in bit field 260) depending on whether the state of the I bit field 254. For example, if the I bit is a 1, the immediate value V is added to the base address. If the I bit is a 0, the contents of the register identified in the ARs field 260 is added to the base address. The WB bit field 266 comprises a two-bit field that determines the size of the data value to be loaded from memory into the destination register. The data value size may be a single byte (8 bits), a short value (16 bits) or a word (32 bits). Bit field 258 (bit 19) is unused and is set to a value of 0.
The embodiments described above relate to a load instruction. In other embodiments, a store instruction (which writes data from a data register to memory) can be provided with an optional error check capability. Such a store instruction is configured much the same way as the LLD instruction described above, but rather than moving data from data storage 122 to data register Rd, a store causes data to be moved from the data register Rd to data storage 122. In general, the embodiments described herein apply to memory accesses, both loads and stores.
The embodiments described herein save memory and power in that a separate instruction specifically designed to perform the error check described herein is not needed. While the preferred embodiments of the present invention have been shown and described, modifications thereof can be made by one skilled in the art without departing from the spirit and teachings of the invention. The scope of protection is not limited by the description set out above. Each and every claim is incorporated into the specification as an embodiment of the present invention.

Claims

1. A processor, comprising:

an arithmetic logic unit (ALU); and

a plurality of registers coupled to the ALU;

wherein, based on a control bit in a memory access instruction, said processor executes said instruction by causing contents of a source register to be compared to a predetermined value and if said contents equals said predetermined value, said processor causes an exception to be generated; and

if said contents differs from said predetermined value, said instruction causes said processor to cause a data value to be moved between memory and a data register, said predetermined value being used to calculate a valid memory address from which to load the data value.

2. The processor of claim 1 wherein said control bit is programmable in said instruction.

3. The processor of claim 1 wherein said load instruction causes said processor to compare said contents to said predetermined value if the control bit is in a first logic state.

4. The processor of claim 3 wherein said processor does not compare said contents to said predetermined value if the control bit is in a second logic state.

5. The processor of claim 1 wherein said load instruction specifies one of a plurality of address calculation modes.

6. The processor of claim 1 wherein the predetermined value is 0.

7. The processor of claim 1 wherein the predetermined value comprises a value that would result in an invalid memory address being calculated if the source register contents equaled said predetermined value.

8. The processor of claim 1 wherein the instruction comprises a load instruction which, if said contents differs from said predetermined value, causes the data value to be loaded from the memory into the data register.

9. The processor claim 1, wherein the instruction comprises a store instruction which, if said contents differs from said predetermined value, causes the data value to be moved from the data register to the memory.

10. A method of executing an instruction that contains an identity of a source register and a data register, comprising:

examining the instruction to determine a state of a control bit;

if said control bit is at a first state, comparing a value in the source register to an error value and generating an exception if the source register value equals said error value; and

if said control bit is at a second state, moving data between a memory location and the data register, said memory location having an address based on the source register value.

11. The method of claim 10 further comprising not moving the data if the exception is generated.

12. The method of claim 10 wherein the error value is 0.

13. The method of claim 10 further comprising programming the state of the control bit in said instruction.

14. The method of claim 10 wherein moving the data comprises loading the data from the memory location into the data register.

15. The method of claim 10 wherein moving the data comprises storing the data from the data register into the memory location.

16. A system, comprising:

a main processor unit; and

a co-processor coupled to said main processor unit, wherein said co-processor comprises a plurality of registers and executes an instruction that, if a control bit in the instruction is in a first state, causes contents of a source register to be compared to a predetermined value and if said contents equals said predetermined value, causes an exception to be generated, but if the control bit is in a second state, the instruction causes data to be moved between a memory address and a data register, the memory address being calculated using the contents of the source register.

17. The system of claim 16 wherein said control bit is programmable in said instruction.

18. The system of claim 16 wherein said instruction specifies one of a plurality of memory address calculation modes.

19. The system of claim 16 wherein the predetermined value is 0.

20. The system of claim 16 wherein the predetermined value comprises a value that would result in an invalid memory address being calculated if the source register contents equaled said predetermined value

21. The system of claim 16 wherein if the exception is generated, the co-processor does not move data in accordance with said instruction.

22. The system of claim 16 wherein the system comprises a communication device.

23. The system of claim 16 wherein the instruction comprises a load instruction.

24. The system of claim 16 wherein the instruction comprises a store instruction.