US20060019468A1 - Method of manufacturing a plurality of electronic assemblies - Google Patents
Method of manufacturing a plurality of electronic assemblies Download PDFInfo
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- US20060019468A1 US20060019468A1 US10/897,067 US89706704A US2006019468A1 US 20060019468 A1 US20060019468 A1 US 20060019468A1 US 89706704 A US89706704 A US 89706704A US 2006019468 A1 US2006019468 A1 US 2006019468A1
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- assembly
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- combination
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- 230000000712 assembly Effects 0.000 title claims abstract description 23
- 238000000429 assembly Methods 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 239000000919 ceramic Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 abstract description 103
- 238000005498 polishing Methods 0.000 description 9
- 239000002184 metal Substances 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Definitions
- This invention relates generally to a method of manufacturing a plurality of electronic assemblies, and more specifically to improvements in fabrication at water level.
- Integrated circuits are usually manufactured in and on semiconductor wafers. Such an integrated circuit has millions of tiny electronic components such as transistors, capacitors, and diodes that are interconnected with conductive lines, plugs, and vias.
- One wafer typically has an array of identical circuits formed thereon.
- the wafer was is then “singulated” or “diced” by directing a blade through scribe streets between the integrated circuits, thereby separating the wafer into the individual dice.
- Each die is then separately mounted to a respective carrier substrate for purposes of providing structural rigidity to the die and to provide power, ground, and signals to and from the die.
- a plurality of conductive terminals are formed on the integrated circuits before the wafer is singulated.
- Such terminals are typically solder bumps that are formed according to a conventional “controlled collapsed chip connect” (C4) process. After the wafer is singulated, each one of the bumps is placed on a respective contact of the carrier substrate. The bumps are then reflowed so that they are structurally and electrically connected to the contacts. The process is repeated to connect each die singulated from the wafer to a separate carrier substrate to form separate electronic assemblies. Downstream fabrication is then separately carried out on each separate electronic assembly.
- C4 controlled collapsed chip connect
- FIG. 1 is a cross-sectional side view of first and second wafer assemblies that are used for forming a combination wafer assembly, according to an embodiment of the invention
- FIG. 2 is a view similar to FIG. 1 after the first and second wafer assemblies are connected to one another by reflowing the first and second terminals of respectively the first and second wafer assemblies with one another to form combined terminals;
- FIG. 3 is a view similar to FIG. 2 , further illustrating a system that is used to introduce an underfill material into a space between the combined terminals;
- FIG. 4 is a view similar to FIG. 3 of a portion of the combination wafer, illustrating how alignment between the first and second wafer assemblies is tested;
- FIG. 5 is a view similar to FIG. 2 , further illustrating how a device wafer of the first wafer assembly is thinned without the need to laminate the first wafer to a supporting substrate;
- FIG. 6 is a view similar to FIG. 2 , further illustrating how the combination wafer assembly is singulated into a plurality of electronic assemblies;
- FIGS. 7A, 7B , and 7 C are views similar to FIG. 6 , further illustrating packages that can be made from the electronic assemblies that are singulated out of the combination wafer as illustrated in FIG. 6 .
- a method of manufacturing a plurality of electronic devices is provided.
- Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly.
- the combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies.
- Each electronic assembly has a respective die from a separated portion of the device wafer and a carrier substrate from a separated portion of the carrier wafer.
- the process of fabricating electronic assemblies is simplified and costs are reduced because the dies are connected to the carrier substrate at wafer level, i.e., before singulation.
- the combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively.
- FIG. 1 of the accompanying drawings illustrates first and second wafer assemblies 10 and 12 that are used for manufacturing a combination wafer assembly and a plurality of electronic assemblies from the combination wafer assembly, according to an embodiment of the invention.
- the first wafer assembly 10 includes a device wafer 14 , a plurality of integrated circuits 16 formed on the device wafer 14 , and a plurality of conductive first terminals 18 formed on each one of the integrated circuits 16 .
- the device wafer 14 is made of a semiconductor material such as silicon.
- the integrated circuits 16 are typically identical to one another. Each integrated circuit 16 has a multitude of electronic elements such as transistors, capacitors, diodes, etc., formed in and on the material of the device wafer 14 .
- Each integrated circuit 16 has a plurality of alternating dielectric and metal layers formed above one another. The metal layers are patterned to form metal lines that interconnect the electronic components to one another.
- the first terminals 18 are bumps that are formed on the integrated circuit and connected through the metal lines, plugs and vias to the electronic components.
- the bumps are typically formed according to a conventional controlled collapsed chip connect (C4) process.
- the integrated circuits 16 are separated from one another by scribe streets 20 .
- a metal guard ring (not shown) typically surrounds each integrated circuit 16 to protect the respective integrated circuit 16 from delamination during downstream sawing or other singulation.
- the second wafer assembly 12 includes a carrier wafer 22 , typically of a strong material such as ceramic, and a second plurality of conductive terminals 24 formed on a lower surface of the carrier wafer 22 .
- the carrier wafer 22 is typically made of a ceramic material and has metal lines, plugs, and vias formed in the ceramic material for purposes of electric communication.
- the second terminals 24 are connected to the conductive metal lines, plugs, and vias.
- the second terminals 24 are typically made utilizing a C4 process.
- the layout of the second terminals 24 is a mirror image of the layout of the first terminals 18 , and each one of the second terminals 24 is located directly above a respective one of the first terminals 18 .
- the second wafer assembly 12 is then lowered onto the first wafer assembly 10 so that a respective one of the second terminals 24 is in contact with a respective one of the first terminals 18 .
- the combination is then heated to a temperature above a melting temperature of the first terminals 18 and 24 , so that each one of the second terminals 24 reflows together with the respective one of the first terminals 18 .
- the combination is then allowed to cool, so that the reflowed terminals again solidify.
- FIG. 2 illustrates a combination wafer assembly 28 that results after the first and second terminals 18 and 24 of FIG. 1 are reflowed together and allowed to cool.
- Combined terminals 30 are formed that interconnect the integrated circuits 16 with the carrier wafer 22 .
- a space 32 is maintained between the integrated circuits 16 and the carrier wafer 22 , and a volume between the combined terminals 30 is filled with a gas, typically air.
- Wafer-level interconnection simplifies the entire assembly process, thereby reducing cost. Wafer level interconnection also allows for downstream manufacture, including the introduction of underfill material and wafer thinning, to be carried out at wafer level, thereby further simplifying the entire process and further reducing cost.
- FIG. 3 illustrates a system 34 that is used to introduce an underfill material into the space 32 of the combination wafer assembly 28 .
- the system 34 includes a jig 36 , having upper and lower parts 38 and 39 , a reservoir 40 for underfill material 42 , a pump 44 , and a heater 46 .
- That lower part 39 of the jig 36 has a recess in which the combination wafer assembly 28 is received.
- Sidewalls 48 of the lower part 39 surround the combination wafer assembly 28 , in particular the space 32 .
- First and second passages 50 and 52 are formed through the sidewalls 48 and into and out of the space 32 .
- the reservoir 40 is connected through that pump 44 to the first passage 50 to allow for the underfill material 42 to be pumped by the pump 44 into the first passage 50 .
- the heater 46 is located in a position to heat the underfill material before being provided to the first passage 50 .
- the upper part 38 of the jig 36 is located on top of the combination wafer assembly 28 , the upper and lower parts 38 and 39 thereby forming a sealed enclosure around the combination wafer assembly 28 , except for the first and second passages 50 and 52 .
- the pump 44 is operated to pump the underfill material 42 out of the reservoir 40 past the heater 46 .
- the heater 46 then heats the underfill material 42 to lower its viscosity.
- the heated underfill material 42 then flows above atmospheric pressure through the first passage 50 into the space 32 .
- a gas located in the space 32 is vented through the second passage 52 .
- the process is continued until the space 32 is entirely filled with the underfill material 42 . It may be possible to provide more inlet passages than just the first passage 50 and/or more outlet passages than just the second passage 52 , and that the passages can be placed at select locations to tailor flow through the space 32 .
- the combination wafer assembly 28 may be removed from the jig 36 .
- the combination wafer assembly 28 with the underfill material 42 in the space 32 , can then be transported through a furnace.
- the underfill material 42 is heated to a select temperature and for a predetermined period of time to cure the underfill material 42 , also at wafer level.
- FIG. 4 illustrates how alignment between the first and second wafer assemblies 10 and 12 is tested before the combination wafer assembly 28 is singulated.
- First and second conductors 53 and 54 are formed through the device wafer 14 and the carrier wafer 22 , respectively. Both conductors 53 and 54 are connected to one of the combined terminals 30 if the second wafer assembly 12 has been properly aligned with the first wafer assembly 10 . No current will conduct if the second wafer assembly 12 is misaligned with respect to the first wafer assembly 10 .
- a circuit is completed by connecting the second conductor 54 through a power supply such as a battery 60 , a resistor 62 , and a current meter 64 to the first conductor 53 . A current will be displayed on the current meter 64 if the first and second wafer assemblies 10 and 12 are correctly aligned.
- the combination wafer assembly 28 also allows for thinning of the device wafer 14 without the need to laminate the first wafer assembly 10 to a supporting substrate, due to the strength provided by the ceramic carrier wafer 22 .
- the carrier wafer 22 is attached to a polishing chuck 70 .
- the polishing chuck 70 is then used to place the combination wafer assembly 28 with the device wafer 14 contacting a polishing pad 72 .
- the polishing chuck 70 and polishing pad 72 are then moved, typically rotated, relative to one another so that a lower surface of that device wafer 14 moves over an upper surface of the polishing pad 72 .
- An upper surface of the polishing pad 72 is abrasive so that lower portions of the device wafer 14 are removed.
- the device wafer 14 is so thinned down.
- the combination wafer assembly 28 is then removed from the polishing pad 72 and the polishing chuck 70 .
- the combination wafer assembly 28 is subsequently singulated into individual electronic assemblies 74 .
- a blade 76 is directed in x- and y-directions through the scribe streets 20 and through the carrier wafer 22 .
- Each electronic assembly 74 then has a respective die 78 from a respective portion of the device wafer 14 and one of the integrated circuits 16 on the respective die 78 .
- Each electronic assembly 74 also has a respective carrier substrate 79 from a respective portion of the carrier wafer 22 .
- the combination wafer assembly 28 is thus singulated after interconnection as illustrated in FIG. 2 , the introduction of an underfill material as illustrated in FIG. 3 , alignment testing as illustrated in FIG. 4 , and thinning as illustrated in FIG. 5 .
- FIGS. 7A, 7B , and 7 C illustrate various assembly packages 80 that can be made from one of the electronic assemblies 74 .
- Each one of the packages 80 includes a further substrate 82 that is made from a laminate of conductive and dielectric layers.
- the additional substrate 82 is formed directly on the electronic assembly 74 .
- additional conductive contacts interconnect the electronic assembly 74 with the additional substrate 82 .
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Abstract
A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly. The combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies. Each electronic assembly has a respective die from a separated portion of the device wafer and a carrier substrate from a separated portion of the carrier wafer. The process of fabricating electronic assemblies is simplified and costs are reduced because the dies are connected to the carrier substrate at wafer level, i.e. before singulation. The combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively.
Description
- 1). Field of the Invention
- This invention relates generally to a method of manufacturing a plurality of electronic assemblies, and more specifically to improvements in fabrication at water level.
- 2). Discussion of Related Art
- Integrated circuits are usually manufactured in and on semiconductor wafers. Such an integrated circuit has millions of tiny electronic components such as transistors, capacitors, and diodes that are interconnected with conductive lines, plugs, and vias.
- One wafer typically has an array of identical circuits formed thereon. The wafer was is then “singulated” or “diced” by directing a blade through scribe streets between the integrated circuits, thereby separating the wafer into the individual dice. Each die is then separately mounted to a respective carrier substrate for purposes of providing structural rigidity to the die and to provide power, ground, and signals to and from the die.
- A plurality of conductive terminals are formed on the integrated circuits before the wafer is singulated. Such terminals are typically solder bumps that are formed according to a conventional “controlled collapsed chip connect” (C4) process. After the wafer is singulated, each one of the bumps is placed on a respective contact of the carrier substrate. The bumps are then reflowed so that they are structurally and electrically connected to the contacts. The process is repeated to connect each die singulated from the wafer to a separate carrier substrate to form separate electronic assemblies. Downstream fabrication is then separately carried out on each separate electronic assembly.
- The invention is described by way of examples with reference to the accompanying drawings, wherein:
-
FIG. 1 is a cross-sectional side view of first and second wafer assemblies that are used for forming a combination wafer assembly, according to an embodiment of the invention; -
FIG. 2 is a view similar toFIG. 1 after the first and second wafer assemblies are connected to one another by reflowing the first and second terminals of respectively the first and second wafer assemblies with one another to form combined terminals; -
FIG. 3 is a view similar toFIG. 2 , further illustrating a system that is used to introduce an underfill material into a space between the combined terminals; -
FIG. 4 is a view similar toFIG. 3 of a portion of the combination wafer, illustrating how alignment between the first and second wafer assemblies is tested; -
FIG. 5 is a view similar toFIG. 2 , further illustrating how a device wafer of the first wafer assembly is thinned without the need to laminate the first wafer to a supporting substrate; -
FIG. 6 is a view similar toFIG. 2 , further illustrating how the combination wafer assembly is singulated into a plurality of electronic assemblies; and -
FIGS. 7A, 7B , and 7C are views similar toFIG. 6 , further illustrating packages that can be made from the electronic assemblies that are singulated out of the combination wafer as illustrated inFIG. 6 . - A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly. The combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies. Each electronic assembly has a respective die from a separated portion of the device wafer and a carrier substrate from a separated portion of the carrier wafer. The process of fabricating electronic assemblies is simplified and costs are reduced because the dies are connected to the carrier substrate at wafer level, i.e., before singulation. The combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively.
-
FIG. 1 of the accompanying drawings illustrates first andsecond wafer assemblies - The
first wafer assembly 10 includes adevice wafer 14, a plurality of integratedcircuits 16 formed on thedevice wafer 14, and a plurality of conductivefirst terminals 18 formed on each one of the integratedcircuits 16. Thedevice wafer 14 is made of a semiconductor material such as silicon. The integratedcircuits 16 are typically identical to one another. Each integratedcircuit 16 has a multitude of electronic elements such as transistors, capacitors, diodes, etc., formed in and on the material of the device wafer 14. Eachintegrated circuit 16 has a plurality of alternating dielectric and metal layers formed above one another. The metal layers are patterned to form metal lines that interconnect the electronic components to one another. Thefirst terminals 18 are bumps that are formed on the integrated circuit and connected through the metal lines, plugs and vias to the electronic components. The bumps are typically formed according to a conventional controlled collapsed chip connect (C4) process. The integratedcircuits 16 are separated from one another by scribestreets 20. A metal guard ring (not shown) typically surrounds each integratedcircuit 16 to protect the respectiveintegrated circuit 16 from delamination during downstream sawing or other singulation. - The
second wafer assembly 12 includes acarrier wafer 22, typically of a strong material such as ceramic, and a second plurality of conductive terminals 24 formed on a lower surface of thecarrier wafer 22. Thecarrier wafer 22 is typically made of a ceramic material and has metal lines, plugs, and vias formed in the ceramic material for purposes of electric communication. The second terminals 24 are connected to the conductive metal lines, plugs, and vias. The second terminals 24 are typically made utilizing a C4 process. - The layout of the second terminals 24 is a mirror image of the layout of the
first terminals 18, and each one of the second terminals 24 is located directly above a respective one of thefirst terminals 18. Thesecond wafer assembly 12 is then lowered onto thefirst wafer assembly 10 so that a respective one of the second terminals 24 is in contact with a respective one of thefirst terminals 18. The combination is then heated to a temperature above a melting temperature of thefirst terminals 18 and 24, so that each one of the second terminals 24 reflows together with the respective one of thefirst terminals 18. The combination is then allowed to cool, so that the reflowed terminals again solidify. -
FIG. 2 illustrates acombination wafer assembly 28 that results after the first andsecond terminals 18 and 24 ofFIG. 1 are reflowed together and allowed to cool. Combinedterminals 30 are formed that interconnect the integratedcircuits 16 with thecarrier wafer 22. Aspace 32 is maintained between the integratedcircuits 16 and the carrier wafer 22, and a volume between the combinedterminals 30 is filled with a gas, typically air. - It can be seen that the integrated
circuits 16 are connected to thecarrier wafer 22 without first singulating thefirst wafer assembly 10. Wafer-level interconnection simplifies the entire assembly process, thereby reducing cost. Wafer level interconnection also allows for downstream manufacture, including the introduction of underfill material and wafer thinning, to be carried out at wafer level, thereby further simplifying the entire process and further reducing cost. -
FIG. 3 illustrates asystem 34 that is used to introduce an underfill material into thespace 32 of thecombination wafer assembly 28. Thesystem 34 includes ajig 36, having upper andlower parts reservoir 40 forunderfill material 42, apump 44, and aheater 46. - That
lower part 39 of thejig 36 has a recess in which thecombination wafer assembly 28 is received.Sidewalls 48 of thelower part 39 surround thecombination wafer assembly 28, in particular thespace 32. First andsecond passages 50 and 52 are formed through thesidewalls 48 and into and out of thespace 32. Thereservoir 40 is connected through thatpump 44 to the first passage 50 to allow for theunderfill material 42 to be pumped by thepump 44 into the first passage 50. Theheater 46 is located in a position to heat the underfill material before being provided to the first passage 50. - The
upper part 38 of thejig 36 is located on top of thecombination wafer assembly 28, the upper andlower parts combination wafer assembly 28, except for the first andsecond passages 50 and 52. - In use, the
pump 44 is operated to pump theunderfill material 42 out of thereservoir 40 past theheater 46. Theheater 46 then heats theunderfill material 42 to lower its viscosity. Theheated underfill material 42 then flows above atmospheric pressure through the first passage 50 into thespace 32. A gas located in thespace 32 is vented through thesecond passage 52. The process is continued until thespace 32 is entirely filled with theunderfill material 42. It may be possible to provide more inlet passages than just the first passage 50 and/or more outlet passages than just thesecond passage 52, and that the passages can be placed at select locations to tailor flow through thespace 32. - After the
underfill material 42 is introduced at wafer level, thecombination wafer assembly 28 may be removed from thejig 36. Thecombination wafer assembly 28, with theunderfill material 42 in thespace 32, can then be transported through a furnace. Theunderfill material 42 is heated to a select temperature and for a predetermined period of time to cure theunderfill material 42, also at wafer level. -
FIG. 4 illustrates how alignment between the first andsecond wafer assemblies combination wafer assembly 28 is singulated. First andsecond conductors device wafer 14 and thecarrier wafer 22, respectively. Bothconductors terminals 30 if thesecond wafer assembly 12 has been properly aligned with thefirst wafer assembly 10. No current will conduct if thesecond wafer assembly 12 is misaligned with respect to thefirst wafer assembly 10. A circuit is completed by connecting thesecond conductor 54 through a power supply such as a battery 60, a resistor 62, and acurrent meter 64 to thefirst conductor 53. A current will be displayed on thecurrent meter 64 if the first andsecond wafer assemblies - As illustrated in
FIG. 5 , thecombination wafer assembly 28 also allows for thinning of thedevice wafer 14 without the need to laminate thefirst wafer assembly 10 to a supporting substrate, due to the strength provided by theceramic carrier wafer 22. Thecarrier wafer 22 is attached to a polishing chuck 70. The polishing chuck 70 is then used to place thecombination wafer assembly 28 with thedevice wafer 14 contacting apolishing pad 72. The polishing chuck 70 and polishingpad 72 are then moved, typically rotated, relative to one another so that a lower surface of thatdevice wafer 14 moves over an upper surface of thepolishing pad 72. An upper surface of thepolishing pad 72 is abrasive so that lower portions of thedevice wafer 14 are removed. Thedevice wafer 14 is so thinned down. Thecombination wafer assembly 28 is then removed from thepolishing pad 72 and the polishing chuck 70. - As illustrated in
FIG. 6 , thecombination wafer assembly 28 is subsequently singulated into individualelectronic assemblies 74. Ablade 76 is directed in x- and y-directions through thescribe streets 20 and through thecarrier wafer 22. Eachelectronic assembly 74 then has arespective die 78 from a respective portion of thedevice wafer 14 and one of theintegrated circuits 16 on therespective die 78. Eachelectronic assembly 74 also has arespective carrier substrate 79 from a respective portion of thecarrier wafer 22. Thecombination wafer assembly 28 is thus singulated after interconnection as illustrated inFIG. 2 , the introduction of an underfill material as illustrated inFIG. 3 , alignment testing as illustrated inFIG. 4 , and thinning as illustrated inFIG. 5 . -
FIGS. 7A, 7B , and 7C illustratevarious assembly packages 80 that can be made from one of theelectronic assemblies 74. Each one of thepackages 80 includes afurther substrate 82 that is made from a laminate of conductive and dielectric layers. In the embodiments ofFIGS. 7A and 7C , theadditional substrate 82 is formed directly on theelectronic assembly 74. In the embodiment ofFIG. 7B , additional conductive contacts interconnect theelectronic assembly 74 with theadditional substrate 82. - While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current invention and that this invention is not restricted to the specific constructions and arrangements shown and described since modifications may occur to those ordinarily skilled in the art.
Claims (18)
1. A method of manufacturing a of plurality of electronic assemblies, comprising:
connecting each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer to a respective one of a plurality of second conductive terminals on a carrier wafer to form a combination wafer assembly; and
singulating the combination wafer assembly between the integrated circuits to form the electronic assemblies, each electronic assembly having a respective die from a separated portion of the device wafer and a carrier substrate from a separated portion of the carrier wafer.
2. The method of claim 1 , further comprising:
introducing an underfill material that is located between the device wafer and the carrier wafer before singulating the combination wafer assembly; and
curing the underfill material.
3. The method of claim 2 , wherein the underfill material is introduced into a space between the device wafer and carrier wafer after connecting the first conductive terminals to the second conductive terminals.
4. The method of claim 3 , wherein the underfill material is introduced into the space at above atmospheric pressure.
5. The method of claim 4 , further comprising:
placing the combination wafer assembly in a jig; and
providing the underfill material through at least a first passage in the jig.
6. The method of claim 4 , further comprising:
heating the underfill material before introducing the underfill material into the space.
7. The method of claim 2 wherein the underfill material is cured before singulating the combination wafer assembly.
8. The method of claim 1 , further comprising:
thinning the device wafer before singulating the combination wafer assembly.
9. The method of claim 8 , further comprising:
introducing an underfill material that is located between the device wafer and the carrier wafer before singulating the combination wafer assembly; and
curing the underfill material.
10. The method of claim 8 , wherein the carrier wafer is made of ceramic.
11. The method of claim 1 , further comprising:
testing a current through at least one pair, the pair including a first conductive terminal and a second conductive terminal before singulating the combination wafer assembly.
12. The method of claim 11 , wherein current is provided through a first conductor extending through the device wafer and through a second conductor extending through that carrier wafer.
13. A method of manufacturing a plurality of electronic assemblies, comprising:
introducing an underfill material between a device wafer and a carrier wafer that form a combination wafer assembly;
curing the underfill material; and
singulating the combination wafer assembly between integrated circuits formed on the device wafer to form the electronic assemblies, each electronic assembly having a respective die from a separated portion of the device wafer and a respective carrier substrate from a separated portion of the carrier wafer, and a respective portion of the underfill material between the respective die and the respective carrier substrate.
14. The method of claim 13 , wherein the underfill material is cured before singulating the combination wafer assembly.
15. The method of claim 13 , wherein the underfill material is introduced between the device wafer and carrier wafer at above atmospheric pressure.
16. A combination wafer assembly, comprising:
a device wafer;
a plurality of integrated circuits formed on the device wafer;
a plurality of first conductive terminals on the integrated circuits;
a carrier wafer; and
a plurality of second conductive terminals on the carrier wafer, each being connected to a respective one of the first conductive terminals.
17. The combination wafer assembly of claim 16 , wherein the integrated circuits are identical to one another.
18. The combination wafer assembly of claim 16 , further comprising:
a plurality of interconnection elements connecting each one of the first conductive terminals to each one of the second conductive terminals; and
an underfill material in a space between the device wafer and the carrier wafer and between the interconnection elements, the underfill material having been cured.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
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US10/897,067 US20060019468A1 (en) | 2004-07-21 | 2004-07-21 | Method of manufacturing a plurality of electronic assemblies |
PCT/US2005/024487 WO2006019674A2 (en) | 2004-07-21 | 2005-07-08 | A method of manufacturing a plurality of electronic assemblies |
DE112005001736T DE112005001736B4 (en) | 2004-07-21 | 2005-07-08 | Method for producing a plurality of electronic assemblies and combination wafer assembly |
JP2007522545A JP4696115B2 (en) | 2004-07-21 | 2005-07-08 | Method for manufacturing a plurality of electronic assemblies |
CN200580024550.6A CN1989613A (en) | 2004-07-21 | 2005-07-08 | A method of manufacturing a plurality of electronic assemblies |
TW094123440A TWI285923B (en) | 2004-07-21 | 2005-07-11 | A method of manufacturing a plurality of electronic assemblies |
US13/620,477 US8709869B2 (en) | 2004-07-21 | 2012-09-14 | Method of manufacturing a plurality of electronic assemblies |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US10/897,067 US20060019468A1 (en) | 2004-07-21 | 2004-07-21 | Method of manufacturing a plurality of electronic assemblies |
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US13/620,477 Division US8709869B2 (en) | 2004-07-21 | 2012-09-14 | Method of manufacturing a plurality of electronic assemblies |
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US13/620,477 Expired - Lifetime US8709869B2 (en) | 2004-07-21 | 2012-09-14 | Method of manufacturing a plurality of electronic assemblies |
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US13/620,477 Expired - Lifetime US8709869B2 (en) | 2004-07-21 | 2012-09-14 | Method of manufacturing a plurality of electronic assemblies |
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US (2) | US20060019468A1 (en) |
JP (1) | JP4696115B2 (en) |
CN (1) | CN1989613A (en) |
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TW (1) | TWI285923B (en) |
WO (1) | WO2006019674A2 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080113457A1 (en) * | 2006-11-15 | 2008-05-15 | Airdio Wireless Inc. | Method of chip manufacturing |
WO2009091440A1 (en) | 2008-01-15 | 2009-07-23 | Dow Corning Corporation | Silsesquioxane resins |
US20110162578A1 (en) * | 2005-03-15 | 2011-07-07 | Panasonic Corporation | Flip-chip mounting method and bump formation method |
US20130330905A1 (en) * | 2006-10-10 | 2013-12-12 | Tessera, Inc. | Edge connect wafer level stacking |
US20140322866A1 (en) * | 2011-11-16 | 2014-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package for Three Dimensional Integrated Circuit |
US8883562B2 (en) | 2007-07-27 | 2014-11-11 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
US9048234B2 (en) | 2006-10-10 | 2015-06-02 | Tessera, Inc. | Off-chip vias in stacked chips |
US12112962B2 (en) | 2020-08-20 | 2024-10-08 | Shinkawa Ltd. | Arrangement apparatus and arrangement method |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5720245B2 (en) * | 2010-12-28 | 2015-05-20 | 富士通株式会社 | Multilayer wafer, resin sealing method, and semiconductor device manufacturing method |
JP2013008977A (en) * | 2012-07-31 | 2013-01-10 | Nikon Corp | Semiconductor device, and manufacturing method of semiconductor device |
US11171249B2 (en) * | 2017-07-25 | 2021-11-09 | Ams Sensors Singapore Pte. Ltd. | Wafer-level methods for manufacturing uniform layers of material on optoelectronic modules |
Citations (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5844320A (en) * | 1996-03-06 | 1998-12-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit with semiconductor device mounted with conductive adhesive |
US6213647B1 (en) * | 1998-05-15 | 2001-04-10 | Zhichan Lin | Damping thrust bearing for vehicle steering knuckle |
US6281046B1 (en) * | 2000-04-25 | 2001-08-28 | Atmel Corporation | Method of forming an integrated circuit package at a wafer level |
US6376278B1 (en) * | 1999-04-01 | 2002-04-23 | Oki Electric Industry Co., Ltd. | Methods for making a plurality of flip chip packages with a wafer scale resin sealing step |
US20020110953A1 (en) * | 2000-08-17 | 2002-08-15 | Ahn Kie Y. | Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing |
US20020195706A1 (en) * | 2001-06-25 | 2002-12-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor apparatus with misalignment mounting detection |
US20030122241A1 (en) * | 2002-01-02 | 2003-07-03 | Lejun Wang | Polybenzoxazine based wafer-level underfill material |
US6589801B1 (en) * | 1998-08-31 | 2003-07-08 | Amkor Technology, Inc. | Wafer-scale production of chip-scale semiconductor packages using wafer mapping techniques |
US20030166313A1 (en) * | 2001-09-26 | 2003-09-04 | Hidenobu Nishikawa | Semiconductor element mounting method |
US20040126927A1 (en) * | 2001-03-05 | 2004-07-01 | Shih-Hsiung Lin | Method of assembling chips |
US6777313B2 (en) * | 2001-07-04 | 2004-08-17 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method for reinforcing chip by use of seal member at pickup time |
US6815712B1 (en) * | 2000-10-02 | 2004-11-09 | Eaglestone Partners I, Llc | Method for selecting components for a matched set from a wafer-interposer assembly |
US20050029667A1 (en) * | 2002-08-09 | 2005-02-10 | Tsuyoshi Yamashita | Multi-functional solder and articles made therewith, such as microelectronic components |
US6906425B2 (en) * | 2002-03-05 | 2005-06-14 | Resolution Performance Products Llc | Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive |
US6940181B2 (en) * | 2003-10-21 | 2005-09-06 | Micron Technology, Inc. | Thinned, strengthened semiconductor substrates and packages including same |
US20050194695A1 (en) * | 2001-03-05 | 2005-09-08 | Shih-Hsiung Lin | Method of assembling chips |
US6982487B2 (en) * | 2003-03-25 | 2006-01-03 | Samsung Electronics Co., Ltd. | Wafer level package and multi-package stack |
US20060049498A1 (en) * | 1994-09-20 | 2006-03-09 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
US7348215B2 (en) * | 2002-03-04 | 2008-03-25 | Micron Technology, Inc. | Methods for assembly and packaging of flip chip configured dice with interposer |
US7358618B2 (en) * | 2002-07-15 | 2008-04-15 | Rohm Co., Ltd. | Semiconductor device and manufacturing method thereof |
US7411297B2 (en) * | 2004-06-14 | 2008-08-12 | Micron Technology, Inc. | Microfeature devices and methods for manufacturing microfeature devices |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07231020A (en) * | 1994-02-16 | 1995-08-29 | Toshiba Corp | Manufacture of semiconductor chip with area pad |
US5646067A (en) * | 1995-06-05 | 1997-07-08 | Harris Corporation | Method of bonding wafers having vias including conductive material |
JP3621182B2 (en) * | 1996-02-23 | 2005-02-16 | 株式会社シチズン電子 | Manufacturing method of chip size package |
JPH1027827A (en) * | 1996-07-10 | 1998-01-27 | Toshiba Corp | Manufacture of semiconductor device |
JPH10303151A (en) * | 1997-04-28 | 1998-11-13 | Sony Corp | Manufacture of electronic parts |
JP4034468B2 (en) * | 1999-04-15 | 2008-01-16 | ローム株式会社 | Manufacturing method of semiconductor device |
JP4087019B2 (en) * | 1999-07-16 | 2008-05-14 | 浜松ホトニクス株式会社 | Manufacturing method of semiconductor device |
JP4102534B2 (en) * | 1999-12-06 | 2008-06-18 | Towa株式会社 | Resin sealing molding method for electronic parts |
US6440771B1 (en) * | 2001-03-23 | 2002-08-27 | Eaglestone Partners I, Llc | Method for constructing a wafer interposer by using conductive columns |
TW560020B (en) * | 2002-04-15 | 2003-11-01 | Advanced Semiconductor Eng | A wafer-level package with a cavity and fabricating method thereof |
KR100537892B1 (en) * | 2003-08-26 | 2005-12-21 | 삼성전자주식회사 | Chip stack package and manufacturing method thereof |
US6897125B2 (en) * | 2003-09-17 | 2005-05-24 | Intel Corporation | Methods of forming backside connections on a wafer stack |
JP2005277079A (en) * | 2004-03-24 | 2005-10-06 | Nec Semicon Package Solutions Ltd | Semiconductor device, its manufacturing equipment and manufacturing method |
-
2004
- 2004-07-21 US US10/897,067 patent/US20060019468A1/en not_active Abandoned
-
2005
- 2005-07-08 WO PCT/US2005/024487 patent/WO2006019674A2/en active Application Filing
- 2005-07-08 JP JP2007522545A patent/JP4696115B2/en not_active Expired - Fee Related
- 2005-07-08 CN CN200580024550.6A patent/CN1989613A/en active Pending
- 2005-07-08 DE DE112005001736T patent/DE112005001736B4/en not_active Expired - Fee Related
- 2005-07-11 TW TW094123440A patent/TWI285923B/en not_active IP Right Cessation
-
2012
- 2012-09-14 US US13/620,477 patent/US8709869B2/en not_active Expired - Lifetime
Patent Citations (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060049498A1 (en) * | 1994-09-20 | 2006-03-09 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
US5844320A (en) * | 1996-03-06 | 1998-12-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit with semiconductor device mounted with conductive adhesive |
US6213647B1 (en) * | 1998-05-15 | 2001-04-10 | Zhichan Lin | Damping thrust bearing for vehicle steering knuckle |
US6589801B1 (en) * | 1998-08-31 | 2003-07-08 | Amkor Technology, Inc. | Wafer-scale production of chip-scale semiconductor packages using wafer mapping techniques |
US6376278B1 (en) * | 1999-04-01 | 2002-04-23 | Oki Electric Industry Co., Ltd. | Methods for making a plurality of flip chip packages with a wafer scale resin sealing step |
US6281046B1 (en) * | 2000-04-25 | 2001-08-28 | Atmel Corporation | Method of forming an integrated circuit package at a wafer level |
US20020110953A1 (en) * | 2000-08-17 | 2002-08-15 | Ahn Kie Y. | Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing |
US6815712B1 (en) * | 2000-10-02 | 2004-11-09 | Eaglestone Partners I, Llc | Method for selecting components for a matched set from a wafer-interposer assembly |
US20050194695A1 (en) * | 2001-03-05 | 2005-09-08 | Shih-Hsiung Lin | Method of assembling chips |
US20040126927A1 (en) * | 2001-03-05 | 2004-07-01 | Shih-Hsiung Lin | Method of assembling chips |
US20020195706A1 (en) * | 2001-06-25 | 2002-12-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor apparatus with misalignment mounting detection |
US6777313B2 (en) * | 2001-07-04 | 2004-08-17 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method for reinforcing chip by use of seal member at pickup time |
US20030166313A1 (en) * | 2001-09-26 | 2003-09-04 | Hidenobu Nishikawa | Semiconductor element mounting method |
US20030122241A1 (en) * | 2002-01-02 | 2003-07-03 | Lejun Wang | Polybenzoxazine based wafer-level underfill material |
US7348215B2 (en) * | 2002-03-04 | 2008-03-25 | Micron Technology, Inc. | Methods for assembly and packaging of flip chip configured dice with interposer |
US6906425B2 (en) * | 2002-03-05 | 2005-06-14 | Resolution Performance Products Llc | Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive |
US7358618B2 (en) * | 2002-07-15 | 2008-04-15 | Rohm Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20050029667A1 (en) * | 2002-08-09 | 2005-02-10 | Tsuyoshi Yamashita | Multi-functional solder and articles made therewith, such as microelectronic components |
US6982487B2 (en) * | 2003-03-25 | 2006-01-03 | Samsung Electronics Co., Ltd. | Wafer level package and multi-package stack |
US6940181B2 (en) * | 2003-10-21 | 2005-09-06 | Micron Technology, Inc. | Thinned, strengthened semiconductor substrates and packages including same |
US7411297B2 (en) * | 2004-06-14 | 2008-08-12 | Micron Technology, Inc. | Microfeature devices and methods for manufacturing microfeature devices |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110162578A1 (en) * | 2005-03-15 | 2011-07-07 | Panasonic Corporation | Flip-chip mounting method and bump formation method |
US8691683B2 (en) * | 2005-03-15 | 2014-04-08 | Panasonic Corporation | Flip-chip mounting method and bump formation method |
US9048234B2 (en) | 2006-10-10 | 2015-06-02 | Tessera, Inc. | Off-chip vias in stacked chips |
US20130330905A1 (en) * | 2006-10-10 | 2013-12-12 | Tessera, Inc. | Edge connect wafer level stacking |
US8999810B2 (en) * | 2006-10-10 | 2015-04-07 | Tessera, Inc. | Method of making a stacked microelectronic package |
US9378967B2 (en) * | 2006-10-10 | 2016-06-28 | Tessera, Inc. | Method of making a stacked microelectronic package |
US9899353B2 (en) | 2006-10-10 | 2018-02-20 | Tessera, Inc. | Off-chip vias in stacked chips |
US7476555B2 (en) * | 2006-11-15 | 2009-01-13 | Airdio Wireless Inc. | Method of chip manufacturing |
US20080113457A1 (en) * | 2006-11-15 | 2008-05-15 | Airdio Wireless Inc. | Method of chip manufacturing |
US8883562B2 (en) | 2007-07-27 | 2014-11-11 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
WO2009091440A1 (en) | 2008-01-15 | 2009-07-23 | Dow Corning Corporation | Silsesquioxane resins |
US20140322866A1 (en) * | 2011-11-16 | 2014-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package for Three Dimensional Integrated Circuit |
US9337063B2 (en) * | 2011-11-16 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package for three dimensional integrated circuit |
US12112962B2 (en) | 2020-08-20 | 2024-10-08 | Shinkawa Ltd. | Arrangement apparatus and arrangement method |
Also Published As
Publication number | Publication date |
---|---|
JP4696115B2 (en) | 2011-06-08 |
DE112005001736T5 (en) | 2007-07-26 |
WO2006019674A2 (en) | 2006-02-23 |
DE112005001736B4 (en) | 2010-06-24 |
TW200608484A (en) | 2006-03-01 |
CN1989613A (en) | 2007-06-27 |
JP2008507844A (en) | 2008-03-13 |
US20130032953A1 (en) | 2013-02-07 |
WO2006019674A3 (en) | 2006-06-29 |
TWI285923B (en) | 2007-08-21 |
US8709869B2 (en) | 2014-04-29 |
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