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US20050051824A1 - Semiconductor device having a thin film capacitor and method for fabricating the same - Google Patents

Semiconductor device having a thin film capacitor and method for fabricating the same Download PDF

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Publication number
US20050051824A1
US20050051824A1 US10/967,436 US96743604A US2005051824A1 US 20050051824 A1 US20050051824 A1 US 20050051824A1 US 96743604 A US96743604 A US 96743604A US 2005051824 A1 US2005051824 A1 US 2005051824A1
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Prior art keywords
capacitor
electrode
dielectric film
forming
metal
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US10/967,436
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Toshihiro Iizuka
Tomoe Yamamoto
Mami Toda
Shintaro Yamamichi
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Individual
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Priority to US10/967,436 priority Critical patent/US20050051824A1/en
Publication of US20050051824A1 publication Critical patent/US20050051824A1/en
Priority to US11/637,147 priority patent/US8169013B2/en
Priority to US11/928,460 priority patent/US8815678B2/en
Priority to US14/332,687 priority patent/US20140327064A1/en
Abandoned legal-status Critical Current

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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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Definitions

  • the present invention relates to a semiconductor device having a thin film capacitor and a method for fabricating the same.
  • Ta 2 O 5 having a high dielectric constant has been considered as a capacitor dielectric film in a memory cell.
  • a lower electrode of a capacitor is formed of a polysilicon layer which can be formed to have a concavo-convex surface (for example, so called HSG (hemi-spherical grain) structure) in order to increase a capacitance per a unitary area.
  • HSG hemi-spherical grain
  • a high temperature process on the order of 700 to 900 degrees Celsius is required.
  • gate electrodes and source/drain diffused regions in the logic section are required to be provided with a cobalt (Co) silicide for a speedup of transistors.
  • the cobalt silicide layer can realize a low resistance, however, if the temperature is elevated, aggregation occurs in the cobalt silicide layer so that the resistance value of the gate electrodes and the diffused layers increases. Therefore, in a process after formation of the cobalt silicide layer, the process temperature cannot be elevated. For example, in the generation of the gate length of 0.15 micron, about 600 degrees Celsius is an upper limit.
  • Ta 2 O 5 is used to form a capacitor dielectric film in the memory section of the logic mixed DRAM and if a polysilicon layer is used to form a lower capacitor electrode, a high temperature process is required to form the polysilicon layer, with the result that the transistors in the logic section become deteriorated through the high temperature process. Therefore, in the generation of the gate length of 0.15 micron and in succeeding generations, it is not possible to use the polysilicon for the lower capacitor electrode.
  • a metal or a metal nitride for example, TiN (titanium nitride), W (tungsten) or Ru (ruthenium), which can be formed at a low temperature of not greater than 500 degrees Celsius where no aggregation occurs in the cobalt silicide.
  • a lower electrode of TiN, W or Ru is formed by a CVD (chemical vapor deposition) or a PVD (physical vapor deposition), and then, a Ta 2 O 5 capacitor dielectric film is formed by a thermal CVD process. Thereafter, in order to reduce a leakage current in the Ta 2 O 5 capacitor, a post anneal is carried out with a RTO (rapid thermal oxidation) or a UV-O 3 oxidation at a temperature of not less than 500 degrees Celsius. Furthermore, an upper electrode of TiN or another is formed by the CVD process or the PVD process, and then, a patterning is carried out to have a desired shape. Thus, the thin film capacitor of a MIM structure having the capacitor dielectric film formed of Ta 2 O 5 is obtained.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • FIG. 14A is a diagrammatic section view of a capacitor formed of a capacitor dielectric film formed of Ta 2 O 5 and upper and lower capacitor electrodes of TiN.
  • FIG. 14B is a graph illustrating a relation between an electrode-to-electrode voltage (Vp) and a leakage current in the structure shown in FIG. 14A .
  • FIG. 14B shows the leakage current at temperatures of 25 degrees Celsius, 85 degrees Celsius and 125 degrees Celsius. It would be seen from this figure that the leakage current remarkably increases when the temperature becomes not less than 85 degrees Celsius which is a device operation guarantee temperature.
  • a decoupling capacitor is provided to compensate for a voltage drop which is caused for a parasite inductance existing between a power supply and interconnections of the LSI.
  • FIG. 15 a conventional decoupling capacitor is shown.
  • a number of laminated ceramic capacitors 93 are located around a LSI chip 92 mounted on a printed circuit substrate 91 , so that those capacitors function as the decoupling capacitor.
  • a resonance frequency of the laminated ceramic capacitor is on the order of about 80 MHz, and therefore, when the LSI is speeded up to several hundred MHz to several GHz, a satisfactory electric charge compensation cannot be carried out, so that it does not function as the decoupling capacitor.
  • FIG. 16 illustrates a thin film capacitor used as the decoupling capacitor.
  • a high dielectric constant thin film capacitor is formed over an uppermost interconnection layer in a semiconductor device, so as to constitute an on-chip decoupling capacitor.
  • a lower electrode film, a capacitor dielectric film and an upper electrode film are deposited in the named order by a CVD process, and then, patterned into a desired shape, so as to form a thin film capacitor composed of a lower electrode 96 , a capacitor dielectric film 97 and an upper electrode 98 .
  • This thin film capacitor constitutes a decoupling capacitor 99 .
  • the lower electrode 96 and the upper electrode 98 are formed of TiN
  • the capacitor dielectric film 97 is formed of Ta 2 O 5 .
  • a UV-O 3 anneal is carried out at a temperature of 500 degrees Celsius.
  • the leakage current is no problem at a room temperature of 25 degrees Celsius, if the temperature is elevated to 85 degrees Celsius and further to 125 degrees Celsius, the leakage current increases, so that a sufficient capacitance characteristics cannot be ensured at a device operation guarantee temperature.
  • a copper wiring conductor is used for interconnection. Therefore, in the case that a capacitor is formed over the uppermost interconnection layer, if the temperature is elevated to not less than 450 degrees Celsius, the interconnection layer is oxidized, with the result that the characteristics is deteriorated and the yield of production lowers.
  • the conventional method for forming the thin film capacitor can realize a large-capacitance, low-inductance, one-chip decoupling capacitor which meet with the speedup of the LSI.
  • Another object of the present invention is to provide a capacitor which can realize a large capacitance and a small leakage current as a capacitor for a DRAM cell in a memory section of a semiconductor device having the memory section and a logic section formed on the same chip, without deterioration of a transistor characteristics attributable to deterioration in a silicide layer formed in gate electrodes and on source/drain diffused layer regions in the semiconductor device.
  • Still another object of the present invention is to provide a semiconductor device having the above mentioned capacitor formed after an interconnection layer is formed (namely, above the interconnection layer) and a method for fabricating the same.
  • MIM metal-insulator-metal
  • MIM metal-insulator-metal
  • a MIM metal-insulator-metal
  • Zr x , Hf 1-x )O 2 (0 ⁇ x ⁇ 1)
  • FIG. 1 is a diagrammatic view for illustrating the structure of one embodiment of the thin film capacitor in accordance with the present invention
  • FIG. 2 is a flow chart illustrating a process for forming a ZrO 2 thin film by use of an ALD apparatus
  • FIG. 3 is a graph illustrating a relation between an electrode-to-electrode voltage (Vp) of a thin film capacitor and a leakage current;
  • FIG. 4 is a graph illustrating a relation between teq (film thickness converted into SiO 2 ) and an actual film thickness
  • FIG. 5 is a graph illustrating a relation between teq (film thickness converted into SiO 2 ) and an actual film thickness
  • FIG. 6 is a graph illustrating a relation between a leakage current and teq (film thickness converted into SiO 2 );
  • FIGS. 7 and 8 are diagrammatic sectional views for illustrating a conventional method for forming a stacked MIM capacitor
  • FIGS. 9A to 9 N are diagrammatic sectional views for illustrating a method for forming a stacked MIM capacitor in accordance with the present invention.
  • FIG. 10 is a flow chart illustrating a process for forming a TiN thin film by use of an ALD apparatus
  • FIG. 11 is a diagrammatic sectional view of a planar capacitor
  • FIG. 12 is a diagrammatic sectional view of a box type capacitor
  • FIG. 13 is a diagrammatic sectional view illustrating a fourth embodiment of the present invention.
  • FIG. 14A is a diagrammatic sectional view of a conventional capacitor formed of a capacitor dielectric film formed of Ta 2 O 5 and upper and lower capacitor electrodes of TiN;
  • FIG. 14B is a graph illustrating a relation between an electrode-to-electrode voltage (Vp) and a leakage current in the conventional capacitor shown in FIG. 14A ;
  • FIG. 15 illustrates a conventional decoupling capacitor
  • FIG. 16 illustrates a conventional thin film capacitor used as the decoupling capacitor.
  • FIG. 1 there is shown a diagrammatic view for illustrating the structure of one embodiment of the thin film capacitor in accordance with the present invention.
  • the first embodiment is a thin film capacitor of a MIM (metal-insulator-metal) structure, provided in a semiconductor device.
  • This thin film capacitor includes a lower electrode 1 , a capacitor dielectric film 2 and an upper electrode 3 stacked in the named order.
  • Each of the upper electrode 3 and the lower electrode 1 is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru.
  • ALD atomic layer deposition
  • (Zr x , Hf 1-x )O 2 (0 ⁇ x ⁇ 1) is an oxide of a solid solution of Zr and Hf.
  • (Zr y , Ti 1-y )O 2 (0 ⁇ y ⁇ 1) is an oxide of a solid solution of Zr and Ti.
  • (Hf z , Ti 1-z )O 2 (0 ⁇ z ⁇ 1) is an oxide of a solid solution of Hf and Ti.
  • a method for forming the thin film capacitor in the case that the capacitor dielectric film is formed of ZrO 2 will be described.
  • a lower electrode thin film having a film thickness of 5 to 50 nm is formed of at least one material selected from the group consisting of TiN, Ti, W, WN, Pt, Ir, Ru, by means of a PVD process, a CVD process or a ALD process, and then, is patterned into a desired shape, so that a lower electrode 1 is formed.
  • FIG. 2 is a flow chart illustrating a process for forming a ZrO 2 thin film by use of an ALD apparatus
  • the ZrO 2 thin film is deposited by using ZrCl 4 as a starting material for Zr and H 2 O as an oxygen material, under a deposition temperature of 200 to 400 degrees Celsius.
  • ZrCl 4 is supplied as a starting material into a chamber of the ALD apparatus, so that only a one-atom layer is deposited on a surface of the lower electrode thin film by causing a reaction.
  • the supply of ZrCl 4 is stopped, and an inert gas represented by Ar or N 2 is introduced into the chamber as a purge gas so that an excessive unreacted ZrCl 4 is removed.
  • H 2 O is supplied to replace a Cl group which terminates Zr grown on the surface of the lower electrode thin film, with an OH group of H 2 O.
  • HCl is produced as a reaction subproduct.
  • the supply of H 2 O is stopped, and the inert gas represented by Ar or N 2 is introduced into the chamber as the purge gas so that an unreacted H 2 O and the reaction subproduct HCl are removed.
  • ZrCl 4 is supplied again so that only another one-atom layer is deposited.
  • the supply of ZrCl 4 is stopped, and the purge gas is produced so that an unreacted ZrCl 4 and the reaction subproduct HCl are removed.
  • an upper electrode thin film having a film thickness of 5 to 50 nm is formed of at least one material selected from the group consisting of TiN, Ti, W, WN, Pt, Ir, Ru, by means of a PVD process, a CVD process or a ALD process, and then, is patterned into a desired shape, so that an upper electrode 3 is formed.
  • the thin film capacitor is obtained.
  • the thin film capacitor formed as mentioned above has a small leakage current and a large capacitance, because the capacitor dielectric film is formed of ZrO 2 having a high electrical insulation property and a large dielectric constant, and because a leakage current increase is small even if the film thickness of ZrO 2 is reduced.
  • the ZrO 2 thin film is formed by the ALD process, it is possible to carry out a film formation at a low temperature and to omit a post anneal which is carried out in an oxidizing atmosphere. Therefore, it is possible to avoid the drop of the capacitance, the increase of the leakage current and the drop in the yield of production, caused by oxidation of the lower electrode.
  • FIG. 3 there is shown a graph illustrating a relation between an electrode-to-electrode voltage (Vp) of a thin film capacitor and a leakage current in the case that the capacitor dielectric film is formed of ZrO 2 and the upper and lower electrodes are formed of TiN. From comparison of FIG. 3 with FIG. 14B , it would be seen that the leakage current evidently becomes small in comparison with the thin film capacitor having the capacitor dielectric film formed of Ta 2 O 5 , shown in FIG. 14A .
  • Vp electrode-to-electrode voltage
  • the capacitor dielectric film is formed of ZrO 2 deposited by the ALD process.
  • the capacitor dielectric film is formed of HfO 2
  • HfCl 4 is used as a starting material for Hf
  • H 2 O is used as an oxygen material.
  • the capacitor dielectric film is formed of (Zr x , Hf 1-x )O 2
  • ZrCl 4 is used as a starting material for Zr
  • HfCl 4 is used as a starting material for Hf
  • H 2 O is used as an oxygen material.
  • the capacitor dielectric film is formed of (Zr y , Ti 1 ⁇ y )O 2 , ZrCl 4 is used as a starting material for Zr, TiCl 4 is used as a starting material for Ti, and H 2 O is used as an oxygen material.
  • the capacitor dielectric film is formed of (Hf z , Ti 1-z )O 2
  • HfCl 4 is used as a starting material for Hf
  • TiCl 4 is used as a starting material for Ti
  • H 2 O is used as an oxygen material.
  • the capacitor dielectric film is formed of (Zr k , Ti l , Hf m )O 2
  • ZrCl 4 is used as a starting material for Zr
  • TiCl 4 is used as a starting material for Ti
  • HfCl 4 is used as a starting material for Hf
  • H 2 O is used as an oxygen material.
  • a thin film capacitor of a MIM structure having a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO 2 , HfO 2 , (Zr x , Hf 1-x )O 2 (0 ⁇ x ⁇ 1), (Zr y , Ti 1-y )O 2 (0 ⁇ y ⁇ 1), (Hf z , Ti 1-z )O 2 (0 ⁇ z ⁇ 1), (Zr k , Ti l , Hf m )O 2 (0 ⁇ k, l, m ⁇ 1, k+l+m 1), deposited by means of the ALD process, an anneal is carried out after formation of the capacitor dielectric film.
  • the thin film capacitor of the MIM structure in accordance with the first embodiment having the capacitor dielectric film formed of at least one material selected from the group consisting of ZrO 2 , HfO 2 , (Zr x , Hf 1-x )O 2 (0 ⁇ x ⁇ 1), (Zr y , Ti 1-y )O 2 (0 ⁇ y ⁇ 1), (Hf z , Ti 1-z )O 2 (0 ⁇ Z ⁇ 1), (Zr k , Ti l , Hf m )O 2 (0 ⁇ k, l, m ⁇ 1, k+l+m 1), has a small leakage current and a large capacitance, in comparison with the thin film capacitor having the capacitor dielectric film formed of Ta 2 O 5 , and therefore, can be satisfactorily used as a memory capacitor in a DRAM cell.
  • the capacitance increase is small (namely, the decrease of teq is small)
  • the leakage current increases.
  • FIG. 4 there is shown a graph illustrating a relation between teq (film thickness converted into SiO 2 ) and an actual film thickness when the capacitor dielectric film formed of ZrO 2 and the upper and lower electrodes are formed of TiN. A capacitance drop caused by a low dielectric constant layer contribution would be seen from FIG. 4 .
  • the anneal is carried out at a temperature of 300 to 700 degrees Celsius after the deposition of the ZrO 2 thin film.
  • the thin film capacitor having the ZrO 2 thin film deposited on a metal electrode by the ALD process can be used as a memory capacitor in the DRAM cell.
  • the inventors of the present application uncovered that if an ZrO 2 thin film is only deposited on a metal electrode by the ALD process, an amorphous ZrO 2 layer region exists at a boundary between the lower electrode and the ZrO 2 layer, and it is not possible to obtain a characteristics intrinsic to the MIM structure thin film capacitor having the capacitor dielectric film of ZrO 2 . Namely, since the amorphous layer functions as a low dielectric constant layer in the MIM structure thin film capacitor, the obtained capacitance drops.
  • the inventors of the present application uncovered and confirmed that the amorphous ZrO 2 layer is crystallized by carrying out the anneal after the deposition of the ZrO 2 layer. With this crystallization, the ZrO 2 layer is homogenized, so that the above mentioned low dielectric constant boundary layer is removed. As a result, it was confirmed that a further large capacitance and a small leakage current are obtained in comparison with the case that no anneal was carried out.
  • the ZrO 2 capacitor dielectric film is deposited on the lower electrode of TiN by the ALD process at a temperature of 200 to 400 degrees Celsius, and thereafter, for example, the upper electrode of TiN is formed, and then, is patterned into a desired shape, so that the MIM thin film capacitor is obtained. Thereafter, the MIM thin film capacitor thus obtained is annealed at a temperature which is not lower than a ZrO 2 layer deposition temperature and which is in a range of 300 to 700 degrees Celsius.
  • the above mentioned amorphous layer is formed when the capacitor dielectric film is deposited, and the anneal may be carried out at any time after the deposition of the capacitor dielectric film.
  • the anneal may be carried out at any time after the deposition of the capacitor dielectric film.
  • a similar advantage can be obtained even if the anneal is carried out immediately after the deposition of the capacitor dielectric film or even if the anneal is carried out after the formation of the upper electrode.
  • the atmosphere in which the anneal is carried out is not important, but it is preferable to use a non-oxidizing atmosphere which does not cause a characteristics deterioration attributable to oxidation of the low electrode material, namely, N 2 , Ar, He, or a forming gas (H 2 +N 2 ).
  • FIG. 5 there is shown a graph illustrating a relation between teq (film thickness converted into SiO 2 ) and an actual film thickness in the case that the capacitor dielectric film is formed of ZrO 2 and the upper and lower electrodes are formed of TiN. It could be seen from FIG. 5 that, if the anneal is carried out, the low dielectric constant layer contribution becomes null.
  • a black solid circle indicates the thin film capacitor formed with no anneal, which is the same as the thin film capacitor shown in FIG. 4 .
  • a white circle indicates the thin film capacitor formed by carrying out the anneal under the atmosphere of a mixed gas of hydrogen and nitrogen, and a triangle indicates the thin film capacitor formed by carrying out the anneal under the atmosphere of only nitrogen.
  • FIG. 6 there is shown a graph illustrating a relation between a leakage current and teq (film thickness converted into SiO 2 ) in the case that the capacitor dielectric film is formed of ZrO 2 and the upper and lower electrodes are formed of TiN.
  • a white circle indicates the thin film capacitor formed with no anneal.
  • a square indicates the thin film capacitor formed by carrying out the anneal under a mixed gas of hydrogen and nitrogen, and a triangle indicates the thin film capacitor formed by carrying out the anneal under only a nitrogen. It could be seen from FIG. 6 that the case of carrying out the anneal under the mixed gas of hydrogen and nitrogen and the case of carrying out the anneal under only the nitrogen exhibit substantially the same leakage current value. Therefore, it would be seen that only the heat treatment is effective, and the atmosphere for the anneal does not give any influence.
  • the low dielectric constant layer (ZrO 2 boundary layer having poor crystallinity) existing just after the deposition of the ZrO 2 thin film, is improved in crystallinity by the anneal, so that it no longer functions as the low dielectric constant layer.
  • the capacitance is increased (namely, teq is decreased).
  • crystallinity is improved in the whole of the ZrO 2 thin film, the leakage current is decreased.
  • the capacitor dielectric film is formed of ZrO 2 .
  • the anneal condition is required at a temperature which is not lower than the ZrO 2 deposition temperature in the ALD process but which is not higher than a temperature where no aggregation of the refractory metal silicide occurs in the gate electrode and the source/drain diffused layer regions.
  • the aggregation of the silicide is remarkable in a region having a small area, namely, in the gate electrode rather than the source/drain diffused layer regions.
  • the aggregation temperature is about 600 degrees Celsius.
  • the anneal temperature is not lower than the ZrO 2 deposition temperature in the ALD process but not higher than 600 degrees Celsius.
  • a lower electrode, a capacitor dielectric film and an upper electrode are sequentially formed in the ALD process by use of an ALD apparatus.
  • a transistor is formed, and after a capacitor contact 11 is formed, an interlayer insulator film 12 is deposited. Then, an opening is formed in the interlayer insulator film 12 by use of lithography, and a lower electrode (metal) 13 is deposited. Thereafter, a resist 14 is filled into the opening to protect the opening, and only an upper portion of the interlayer insulator film is removed by an etch-back process or a CMP (chemical mechanical polishing) process, so that capacitors are separated from each other. Then, as shown in FIG. 8 , a capacitor dielectric film 15 and an upper electrode 16 are deposited, and a patterning is carried out to form a common electrode conductor (capacitor plate).
  • CMP chemical mechanical polishing
  • FIGS. 9A to 9 N diagrammatic sectional views of FIGS. 9A to 9 N.
  • a cylinder type capacitor which is one kind of the stacked capacitor, and which includes a capacitor dielectric film formed of ZrO 2 and upper and lower electrodes formed of TiN.
  • a device isolation region 22 is formed on a principal surface of a semiconductor substrate (silicon substrate) 21 to confirm a device formation region.
  • a gate electrode 23 is formed on a not-shown gate insulator film, and a source/drain diffused region 24 is formed in a surface region of the substrate at each side of the gate electrode.
  • This gate electrode 23 forms a word line in the DRAM.
  • a side wall 25 is formed on each side of the gate electrode 23 , and Co (cobalt) or Ni (nickel) is deposited on the gate electrodes 23 and the source/drain diffused regions 24 to form a cobalt silicide or a nickel silicide.
  • MOS transistors are formed.
  • an interlayer insulator film 26 is formed to cover the transistors, and an upper surface of the interlayer insulator film 26 is planarized.
  • a hole for a cell contact (capacitor contact) 27 and a hole for a cell contact (bit contact) 28 are formed in the interlayer insulator film 26 to reach the source/drain diffused regions 24 by a lithography, and W (tungsten) is charged into the holes thus formed, to form a W plug.
  • a bit line conductor layer is formed on the interlayer insulator film 26 and the cell contacts 27 and 28 , and is patterned to form a bit line 29 electrically connected to the W plug of the cell contact 28 .
  • an interlayer insulator film 30 is deposited to cover the bit line 29 , and then, and an upper surface of the interlayer insulator film 30 is planarized.
  • a hole for a capacitor contact 31 is formed in the interlayer insulator film 30 to reach the cell contact 27 by a lithography, and W (tungsten) is charged into the hole thus formed, to form a W plug.
  • an interlayer insulator film 32 is formed to cover the interlayer insulator film 30 and the capacitor contact 31 .
  • a cylinder 33 is formed in the interlayer insulator film 32 to reach the capacitor contact 31 by a lithography.
  • a lower electrode metal 34 of TiN, a capacitor dielectric film 35 of ZrO 2 and an upper electrode metal 36 a of TiN are continuously formed in the named order within the same machine without being exposed to air.
  • FIG. 10 there is shown a flow chart illustrating a process for forming a TiN film which constitutes the lower electrode metal 34 and the upper electrode metal 36 a , by use of the ALD apparatus.
  • TiCl 4 and NH 3 are used as a starting material gas.
  • a film deposition temperature is on the order of 300 to 500 degrees Celsius.
  • TiCl 4 is supplied to a chamber of the ALD apparatus. Thus, only a one-atom layer is deposited, by reaction, on a surface of the interlayer insulator film 32 including the surface of the cylinder formed in the interlayer insulator film 32 . Next, the supply of TiCl 4 is stopped, and a purge gas is introduced into the chamber so that an excessive unreacted TiCl 4 is removed.
  • NH 3 is supplied to replace a Cl group which terminates Ti grown on the surface of the interlayer insulator film, with a NH 2 group.
  • HCl is produced as a reaction subproduct.
  • the supply of NH 3 is stopped, and the inert gas represented by Ar or N 2 is introduced into the chamber as the purge gas so that an unreacted NH 3 and the reaction subproduct HCl are removed.
  • TiCl 4 is supplied again so that only another one-atom layer is deposited.
  • the supply of TiCl 4 is stopped, and the purge gas in introduced so that an unreacted TiCl 4 and the reaction subproduct HCl are removed.
  • the supply of the purge gas is stopped, and NH 3 is supplied.
  • the capacitor dielectric film 35 of ZrO 2 having the film thickness of 5 to 15 nm is formed on the lower electrode metal film 34 by alternately supplying ZrCl 4 and H 2 O.
  • the upper electrode metal film 36 a of TiN having the film thickness of 5 to 50 nm is formed on the capacitor dielectric film 35 by alternately supplying TiCl 4 and NH 3 , similarly to the procedure of the formation of the lower electrode metal film 34 as shown in FIG. 10 .
  • an upper electrode metal 36 b formed of W (tungsten) is deposited on the upper electrode metal film 36 a so that the upper electrode is formed of a double layer consisting of a TiN layer and a W layer.
  • the W layer is not necessarily required to be formed by use of the ALD process, but can be formed by use of a conventional CVD process or a sputtering.
  • the ALD process expends a time since it is necessary to alternately supply the different gases. Use of the CVD process or the sputtering is effective for a mass production of the device.
  • the lower electrode 34 can be formed first by the sputtering, for example, and then, only a portion of the lower electrode 34 corresponding to the boundary layer is formed by the ALD process, and thereafter, the capacitor dielectric film 35 and the upper electrode 36 a are succeedingly formed by the ALD process.
  • the lower electrode 34 and the upper electrode 36 a are sufficient if only a boundary portion to the capacitor dielectric film 35 is formed by the ALD process. Therefore, it is sufficient if the film thickness of each of the lower electrode 34 and the upper electrode 36 a to be formed by the ALD process has at least one-atom layer thickness.
  • each of the lower electrode 34 and the upper electrode 36 a is formed by the ALD process to have at least one-atom layer thickness, and the other portion of each of the lower electrode 34 and the upper electrode 36 a can be formed by use of the CVD process or the sputtering so that the whole film thickness of each of the lower electrode 34 and the upper electrode 36 a becomes 5 to 50 nm.
  • the stacked structure thus formed is divided into a plurality of individual cylinder type capacitors 37 each formed of the lower electrode 34 , the capacitor dielectric film 35 and the upper electrode 36 .
  • an insulating film 38 is deposited on the whole surface to isolate the lower electrode 34 and the upper electrode 36 from each other.
  • an opening 39 is formed through the insulating film 38 at only a position above the upper electrode 36 and to reach the upper electrode 36 . At this time, the opening 39 never extends to the lower electrode 34 .
  • a common interconnection layer 40 is formed to cover the upper surface and to charge into the opening 39 so that the upper electrodes 36 are connected in common to the common interconnection layer 40 .
  • an interlayer insulator film 41 is formed to cover the upper surface and the common interconnection layer 40 , and a first metal layer 42 is formed on the interlayer insulator film 41 so as to constitute a first level interconnection.
  • the lower electrode, the capacitor dielectric film and the upper electrode are continuously formed in the same machine (the same chamber) by use of the ALD apparatus which can control the composition of the film with an atom-layer level, it is possible to perfectly prevent the chemical and physical damages to the surface of the lower electrode, which would otherwise occur when the lower electrode is patterned and when the resist is removed. In addition, it is also possible to minimize deposition of carbons included in the air within the clean room, to the surface of the lower electrode and the surface of the capacitor dielectric film. Because of these reasons, it is possible to maintain a boundary between the lower electrode and the capacitor dielectric film and a boundary between the capacitor dielectric film and the upper electrode in a good condition. Furthermore, since the boundary between the lower electrode and the capacitor dielectric film is maintained in the good condition, it is possible to minimize the capacitance drop and the increase of the capacitor dielectric film leakage current.
  • the anneal is carried out similarly to the capacitor of the second embodiment, it is possible to realize a capacitor having a further large capacitance and a small leakage current.
  • the anneal is carried out at a temperature which is not lower than the ZrO 2 forming temperature in the ALD process but which is not higher than a temperature where no aggregation of a refractory metal silicide occurs in a gate electrode and source/drain diffused layer regions in the case that the refractory metal silicide is provided in the gate electrode and the source/drain diffused layer regions.
  • the present invention is in now way limited to the cylinder type capacitor, but can be applied to a planar capacitor and a box type capacitor.
  • FIG. 11 there is shown a diagrammatic sectional view of a planar capacitor to which the present invention can be applied.
  • a device isolation region 52 is formed on a principal surface of a semiconductor substrate (silicon substrate) 51 to confirm a device formation region.
  • a gate electrode 53 is formed on a not-shown gate insulator film, and a source/drain diffused region 54 having a cobalt silicide is formed in a surface region of the substrate at each side of the gate electrode.
  • An interlayer insulator film 55 is formed to cover the gate electrode 53 and the principal surface of the substrate.
  • a bit contact 56 is formed in the interlayer insulator film 55 to reach one of each pair of source/drain diffused regions 54 .
  • a bit line 57 is formed on the interlayer insulator film 55 to be electrically connected to the bit contact 56 .
  • an interlayer insulator film 58 is deposited to cover the bit line 57 and the interlayer insulator film 55 .
  • a lower electrode 59 formed of a metal of a metal nitride, a capacitor dielectric film 60 formed of ZrO 2 , and an upper electrode 61 formed of a metal of a metal nitride, are continuously formed in the named order by the ALD apparatus.
  • the lower electrode 59 is electrically connected to a capacitor contact 62 formed through the interlayer insulator films 58 and 55 to reach the other of each pair of source/drain diffused regions 54 .
  • a side wall 66 is formed on a side surface of each planar capacitor thus formed which is composed of the lower electrode 59 , the capacitor dielectric film 60 and the upper electrode 61 .
  • a common interconnection layer 63 is formed on the upper electrode 61 of each planar capacitor to interconnect the upper electrode 61 of the planar capacitors.
  • An interlayer insulator film 64 is formed to cover the common interconnection layer 63 , and a first metal layer 65 is formed on the interlayer insulator film 64 to constitute a first level metal interconnection.
  • FIG. 12 there is shown a diagrammatic sectional view of a box type capacitor to which the present invention can be applied.
  • a device isolation region 72 is formed on a principal surface of a semiconductor substrate (silicon substrate) 71 to confirm a device formation region.
  • a gate electrode 73 is formed on a not-shown gate insulator film and a source/drain diffused region 74 having a cobalt silicide is formed in a surface region of the substrate at each side of the gate electrode.
  • An interlayer insulator film 75 is formed to cover the gate electrode 73 and the principal surface of the substrate.
  • a bit contact 76 is formed in the interlayer insulator film 75 to reach one of each pair of source/drain diffused regions 74 .
  • a bit line 77 is formed on the interlayer insulator film 75 to be electrically connected to the bit contact 76 .
  • an interlayer insulator film 78 is deposited to cover the bit line 77 and the interlayer insulator film 75 .
  • a capacitor contact 82 is formed through the interlayer insulator films 78 and 75 to reach the other of each pair of source/drain diffused regions 74 .
  • a lower electrode 79 a of W (tungsten) is formed on the capacitor contact 82 .
  • a lower electrode 79 b formed of a metal of a metal nitride, a capacitor dielectric film 80 formed of ZrO 2 , and an upper electrode 81 formed of a metal of a metal nitride are continuously formed in the named order by the ALD apparatus.
  • the box type capacitor is composed of the lower electrodes 79 a and 79 b , the capacitor dielectric film 80 and the upper electrode 81 .
  • an insulator film 86 is formed to isolate the upper electrode 81 and the lower electrode 79 from each other.
  • a common interconnection layer 83 is formed to interconnect the upper electrode 81 b of the planar capacitors.
  • An interlayer insulator film 84 is formed to cover the common interconnection layer 83 , and a first metal layer 85 is formed on the interlayer insulator film 84 to constitute a first level metal interconnection.
  • a capacitor dielectric film of the MIS thin film capacitor is formed by the ALD process which can carry out a film deposition at a low temperature and which makes the post-anneal in an oxidizing atmosphere unnecessary, and the MIS thin film capacitor is located to function as a decoupling capacitor for power supply lines.
  • FIG. 13 there is shown a diagrammatic sectional view of a part of a semiconductor device, for illustrating the fourth embodiment of the present invention.
  • An interlayer insulator film 103 is formed to cover an uppermost interconnection (ground line) 101 , another uppermost interconnection (power supply line) 102 and an underlying interlayer insulator film.
  • a lower electrode 105 On the interlayer insulator film 103 , a lower electrode 105 , a capacitor dielectric film 106 and an upper electrode 107 are formed in the named order to constitute a decoupling capacitor 104 .
  • the lower electrode 105 is connected through a contact 108 to the uppermost interconnection (ground line) 101
  • the upper electrode 107 is connected through a contact 109 to the uppermost interconnection (power supply line) 102 .
  • a lower electrode film is formed of at least one material selected from the group consisting of TiN, Ti, TaN, Ta, W, WN, Pt, Ir, Ru, by means of a sputtering process or a ALD process, and then, is patterned into a desired shape, so that the lower electrode 105 is formed at a position above the uppermost interconnection (ground line) 101 and is connected to the contact 108 reaching the uppermost interconnection (ground line) 101 .
  • a capacitor dielectric film is deposited to cover the lower electrode 105 by use of the ALD process at a film deposition temperature of 200 to 400 degrees Celsius.
  • the capacitor dielectric film is patterned into a desired shape to form the capacitor dielectric film 106 .
  • an upper electrode film is formed of at least one material selected from the group consisting of TiN, Ti, TaN, Ta, W, WN, Pt, Ir, Ru, by means of a sputtering process or a ALD process, and then, is patterned into a desired shape, so that the upper electrode 107 is formed to partially cover the capacitor dielectric film 106 and is connected to the contact 109 reaching the uppermost interconnection (power supply line) 102 .
  • the thin film capacitor functioning as the decoupling capacitor is formed in the semiconductor device.
  • the lower electrode is connected to the uppermost interconnection (ground line) and the upper electrode is connected to the uppermost interconnection (power supply line).
  • the present invention is in no way limited to this fashion. It is a matter of course to persons skilled in the art that a similar advantage can be obtained in the case that the lower electrode is connected to the uppermost interconnection (power supply line) and the upper electrode is connected to the uppermost interconnection (ground line).
  • the thin film capacitor is formed over the uppermost interconnection of the semiconductor device to function as the decoupling capacitor.
  • the thin film capacitor can be formed within the inside of the semiconductor device or on a lower surface of the semiconductor device.
  • the thin film capacitor can be formed in the semiconductor device with no characteristics deterioration attributable to oxidation of the interconnection layer and with no drop in yield of production.
  • a silicide layer formed in a gate electrode and a source/drain diffused region is never deteriorated, and a sufficient capacitance value (a maximum capacitance value per a unitary area and a minimum leakage current value per a unitary area) can be ensured as a capacitor of each DRAM cell provided in a memory section.
  • a thin film capacitor having a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO 2 , HfO 2 , (Zr x , Hf 1-x )O 2 (0 ⁇ x ⁇ 1), (Zr y , Ti 1-y )O 2 (0 ⁇ Y ⁇ 1), (Hf z , Ti 1-z )O 2 (0 ⁇ z ⁇ 1), (Zr k , Ti l , Hf m )O 2 (0 ⁇ k, l, m ⁇ 1, k+l+m 1), is formed over an uppermost interconnection layer in a semiconductor device, it is possible to realize a low-inductance, large-capacitance, one-chip decoupling capacitor, which meets with a speedup of an LSI.

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Abstract

In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (O<z<l), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.

Description

    BACKGROUND OF THE INVENTION
  • The present invention relates to a semiconductor device having a thin film capacitor and a method for fabricating the same.
  • Heretofore, in a general purpose DRAM, Ta2O5 having a high dielectric constant has been considered as a capacitor dielectric film in a memory cell. In this case, it is an ordinary practice that a lower electrode of a capacitor is formed of a polysilicon layer which can be formed to have a concavo-convex surface (for example, so called HSG (hemi-spherical grain) structure) in order to increase a capacitance per a unitary area. In order to form this polysilicon layer, a high temperature process on the order of 700 to 900 degrees Celsius is required.
  • On the other hand, in a logic mixed DRAM in which a logic section and a memory section are formed on the same chip, gate electrodes and source/drain diffused regions in the logic section are required to be provided with a cobalt (Co) silicide for a speedup of transistors.
  • The cobalt silicide layer can realize a low resistance, however, if the temperature is elevated, aggregation occurs in the cobalt silicide layer so that the resistance value of the gate electrodes and the diffused layers increases. Therefore, in a process after formation of the cobalt silicide layer, the process temperature cannot be elevated. For example, in the generation of the gate length of 0.15 micron, about 600 degrees Celsius is an upper limit.
  • Accordingly, if Ta2O5 is used to form a capacitor dielectric film in the memory section of the logic mixed DRAM and if a polysilicon layer is used to form a lower capacitor electrode, a high temperature process is required to form the polysilicon layer, with the result that the transistors in the logic section become deteriorated through the high temperature process. Therefore, in the generation of the gate length of 0.15 micron and in succeeding generations, it is not possible to use the polysilicon for the lower capacitor electrode. Under this situation, there is a demand for constitute the electrode of the capacitor with a metal or a metal nitride, for example, TiN (titanium nitride), W (tungsten) or Ru (ruthenium), which can be formed at a low temperature of not greater than 500 degrees Celsius where no aggregation occurs in the cobalt silicide.
  • Now, explanation will be made on a conventional method for forming a thin film capacitor, using a metal or a metal nitride for the lower capacitor electrode and also using Ta2O5 for the capacitor dielectric film.
  • A lower electrode of TiN, W or Ru is formed by a CVD (chemical vapor deposition) or a PVD (physical vapor deposition), and then, a Ta2O5 capacitor dielectric film is formed by a thermal CVD process. Thereafter, in order to reduce a leakage current in the Ta2O5 capacitor, a post anneal is carried out with a RTO (rapid thermal oxidation) or a UV-O3 oxidation at a temperature of not less than 500 degrees Celsius. Furthermore, an upper electrode of TiN or another is formed by the CVD process or the PVD process, and then, a patterning is carried out to have a desired shape. Thus, the thin film capacitor of a MIM structure having the capacitor dielectric film formed of Ta2O5 is obtained.
  • FIG. 14A is a diagrammatic section view of a capacitor formed of a capacitor dielectric film formed of Ta2O5 and upper and lower capacitor electrodes of TiN. FIG. 14B is a graph illustrating a relation between an electrode-to-electrode voltage (Vp) and a leakage current in the structure shown in FIG. 14A. FIG. 14B shows the leakage current at temperatures of 25 degrees Celsius, 85 degrees Celsius and 125 degrees Celsius. It would be seen from this figure that the leakage current remarkably increases when the temperature becomes not less than 85 degrees Celsius which is a device operation guarantee temperature.
  • Furthermore, in a LSI chip, it is considered to form a high dielectric constant thin film capacitor above interconnections in the LSI, so as to use it as a decoupling capacitor. The decoupling capacitor is provided to compensate for a voltage drop which is caused for a parasite inductance existing between a power supply and interconnections of the LSI.
  • Referring to FIG. 15, a conventional decoupling capacitor is shown. In the prior art, as shown in FIG. 15, a number of laminated ceramic capacitors 93 are located around a LSI chip 92 mounted on a printed circuit substrate 91, so that those capacitors function as the decoupling capacitor. However, a resonance frequency of the laminated ceramic capacitor is on the order of about 80 MHz, and therefore, when the LSI is speeded up to several hundred MHz to several GHz, a satisfactory electric charge compensation cannot be carried out, so that it does not function as the decoupling capacitor.
  • FIG. 16 illustrates a thin film capacitor used as the decoupling capacitor. A high dielectric constant thin film capacitor is formed over an uppermost interconnection layer in a semiconductor device, so as to constitute an on-chip decoupling capacitor.
  • As shown in FIG. 16, over a wiring conductor or interconnection (ground line) 94 and a wiring conductor or interconnection (power supply line) 95, a lower electrode film, a capacitor dielectric film and an upper electrode film are deposited in the named order by a CVD process, and then, patterned into a desired shape, so as to form a thin film capacitor composed of a lower electrode 96, a capacitor dielectric film 97 and an upper electrode 98. This thin film capacitor constitutes a decoupling capacitor 99. Here, the lower electrode 96 and the upper electrode 98 are formed of TiN, and the capacitor dielectric film 97 is formed of Ta2O5. In addition, in order to reduce a leakage current, after the capacitor dielectric film 97 of Ta2O5 is formed, a UV-O3 anneal is carried out at a temperature of 500 degrees Celsius.
  • In the case of forming a high dielectric constant thin film capacitor over the uppermost interconnection layer in the semiconductor device to use it as the decoupling capacitor, the demand of a low inductance and a large capacitance is satisfied with a one-chip feature and use of a high dielectric constant capacitor,
  • As mentioned above, in the conventional thin film capacitor having the lower electrode formed of TiN, W or Ru and the capacitor dielectric film of Ta2O5, it is necessary to carry out the post-anneal in an oxidizing atmosphere since the leakage current is large in a condition just after the formation of Ta2O5. However, because of this post anneal, the lower electrode layer is oxidized so that a low dielectric constant film is formed. As a result, even if the thickness of the Ta2O5 film is reduced, a large capacitance cannot be obtained.
  • In addition, because of the oxidation occurring in the post anneal, a concavo-convex or a peeling occurs in the lower electrode layer, with the result that the yield of production lowers.
  • Furthermore, as shown in FIG. 14B, although the leakage current is no problem at a room temperature of 25 degrees Celsius, if the temperature is elevated to 85 degrees Celsius and further to 125 degrees Celsius, the leakage current increases, so that a sufficient capacitance characteristics cannot be ensured at a device operation guarantee temperature.
  • On the other hand, in the case that a high dielectric constant thin film capacitor is formed over the uppermost interconnection layer in the semiconductor device and is used as the decoupling capacitor, the demand of a low inductance and a large capacitance is satisfied with a one-chip feature and use of a high dielectric constant capacitor, but the present method for forming the thin film capacitor has a problem.
  • It has been proposed to use Ta2O5, SrTiO3 and (Ba, Sr)TiO3 formed by the PVD process or the CVD process, for the capacitor dielectric film of the above mentioned thin film capacitor. However, in order to obtain a capacitor dielectric film of an excellent quality having a large capacitance in the conventional method utilizing the PVD or CVD process, a high temperature of not less than 400 degrees Celsius is required. In addition, in order to reduce the leakage current, it is also necessary to carry out the post anneal in the oxidizing atmosphere at the temperature of not less than 450 degrees Celsius.
  • Furthermore, recently, a copper wiring conductor is used for interconnection. Therefore, in the case that a capacitor is formed over the uppermost interconnection layer, if the temperature is elevated to not less than 450 degrees Celsius, the interconnection layer is oxidized, with the result that the characteristics is deteriorated and the yield of production lowers.
  • In other word, the conventional method for forming the thin film capacitor can realize a large-capacitance, low-inductance, one-chip decoupling capacitor which meet with the speedup of the LSI.
    • BRIEF SUMMARY OF THE INVENTION
  • Accordingly, it is an object of the present invention to provide a thin film capacitor and a method for forming the same, which have overcome the above mentioned problems of the prior art.
  • Another object of the present invention is to provide a capacitor which can realize a large capacitance and a small leakage current as a capacitor for a DRAM cell in a memory section of a semiconductor device having the memory section and a logic section formed on the same chip, without deterioration of a transistor characteristics attributable to deterioration in a silicide layer formed in gate electrodes and on source/drain diffused layer regions in the semiconductor device.
  • Still another object of the present invention is to provide a semiconductor device having the above mentioned capacitor formed after an interconnection layer is formed (namely, above the interconnection layer) and a method for fabricating the same.
  • The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor device having a capacitor of a MIM (metal-insulator-metal) structure having a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, 1, m<1, k+l+m=1).
  • According to another aspect of the present invention, there is provided a semiconductor device including a transistor having a gate electrode and source/drain diffused layers having a refractory metal silicide, wherein a capacitor of a MIM (metal-insulator-metal) structure having a capacitor dielectric film, which is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and which is provided on an insulator film formed on the source/drain diffused layer.
  • According to still another aspect of the present invention, there is provided a semiconductor device wherein a capacitor of a MIM (metal-insulator-metal) structure having a capacitor dielectric film, which is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and which is provided on an insulator film formed on an interconnection.
  • According to a further aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of forming a lower electrode of a capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and, after formation of the capacitor dielectric film, carrying out a heat treatment at a temperature not lower than a film deposition temperature in the atomic layer deposition.
  • According to a still further aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of forming a lower electrode of a capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, 1, M<1, k+l+m=1), and, after formation of the capacitor dielectric film, carrying out a heat treatment at a temperature which is not lower than a film deposition temperature in the atomic layer deposition but which is not higher than a temperature where no aggregation of a refractory metal silicide occurs in a gate electrode and source/drain diffused layer regions in the case that the refractory metal silicide is provided in the gate electrode and the source/drain diffused layer regions.
  • According to a further aspect of the present invention, there is provided a method for fabricating a semiconductor device having a capacitor of a MIM (metal-insulator-metal) structure formed on an insulator film formed on an interconnection, comprising the steps of forming a lower electrode of the capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, 1, m<1, k+l+m=1), and then, forming an upper electrode on the capacitor dielectric film.
  • The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagrammatic view for illustrating the structure of one embodiment of the thin film capacitor in accordance with the present invention;
  • FIG. 2 is a flow chart illustrating a process for forming a ZrO2 thin film by use of an ALD apparatus;
  • FIG. 3 is a graph illustrating a relation between an electrode-to-electrode voltage (Vp) of a thin film capacitor and a leakage current;
  • FIG. 4 is a graph illustrating a relation between teq (film thickness converted into SiO2) and an actual film thickness;
  • FIG. 5 is a graph illustrating a relation between teq (film thickness converted into SiO2) and an actual film thickness;
  • FIG. 6 is a graph illustrating a relation between a leakage current and teq (film thickness converted into SiO2);
  • FIGS. 7 and 8 are diagrammatic sectional views for illustrating a conventional method for forming a stacked MIM capacitor;
  • FIGS. 9A to 9N are diagrammatic sectional views for illustrating a method for forming a stacked MIM capacitor in accordance with the present invention;
  • FIG. 10 is a flow chart illustrating a process for forming a TiN thin film by use of an ALD apparatus;
  • FIG. 11 is a diagrammatic sectional view of a planar capacitor;
  • FIG. 12 is a diagrammatic sectional view of a box type capacitor;
  • FIG. 13 is a diagrammatic sectional view illustrating a fourth embodiment of the present invention;
  • FIG. 14A is a diagrammatic sectional view of a conventional capacitor formed of a capacitor dielectric film formed of Ta2O5 and upper and lower capacitor electrodes of TiN;
  • FIG. 14B is a graph illustrating a relation between an electrode-to-electrode voltage (Vp) and a leakage current in the conventional capacitor shown in FIG. 14A;
  • FIG. 15 illustrates a conventional decoupling capacitor; and
  • FIG. 16 illustrates a conventional thin film capacitor used as the decoupling capacitor.
    • DETAILED DESCRIPTION OF THE INVENTION
  • Now, embodiments of the present invention will be described with reference to the drawings.
  • Referring to FIG. 1, there is shown a diagrammatic view for illustrating the structure of one embodiment of the thin film capacitor in accordance with the present invention.
  • The first embodiment is a thin film capacitor of a MIM (metal-insulator-metal) structure, provided in a semiconductor device. This thin film capacitor includes a lower electrode 1, a capacitor dielectric film 2 and an upper electrode 3 stacked in the named order. Each of the upper electrode 3 and the lower electrode 1 is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. The capacitor dielectric film 2 is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, 1, m<1, k+l+m=1), and formed by means of an atomic layer deposition (abbreviated to “ALD”).
  • Here, (Zrx, Hf1-x)O2 (0<x<1) is an oxide of a solid solution of Zr and Hf. (Zry, Ti1-y)O2 (0<y<1) is an oxide of a solid solution of Zr and Ti. (Hfz, Ti1-z)O2 (0<z<1) is an oxide of a solid solution of Hf and Ti. (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1) is an oxide of a solid solution of Zr, Ti and Hf.
  • Here, a method for forming the thin film capacitor in the case that the capacitor dielectric film is formed of ZrO2, will be described. First, a lower electrode thin film having a film thickness of 5 to 50 nm is formed of at least one material selected from the group consisting of TiN, Ti, W, WN, Pt, Ir, Ru, by means of a PVD process, a CVD process or a ALD process, and then, is patterned into a desired shape, so that a lower electrode 1 is formed.
  • Then, a capacitor dielectric film is formed of ZrO2 by means of the ALD process. FIG. 2 is a flow chart illustrating a process for forming a ZrO2 thin film by use of an ALD apparatus;
  • The ZrO2 thin film is deposited by using ZrCl4 as a starting material for Zr and H2O as an oxygen material, under a deposition temperature of 200 to 400 degrees Celsius.
  • First, ZrCl4 is supplied as a starting material into a chamber of the ALD apparatus, so that only a one-atom layer is deposited on a surface of the lower electrode thin film by causing a reaction. Next, the supply of ZrCl4 is stopped, and an inert gas represented by Ar or N2 is introduced into the chamber as a purge gas so that an excessive unreacted ZrCl4 is removed.
  • Thereafter, H2O is supplied to replace a Cl group which terminates Zr grown on the surface of the lower electrode thin film, with an OH group of H2O. In this process, HCl is produced as a reaction subproduct. Then, the supply of H2O is stopped, and the inert gas represented by Ar or N2 is introduced into the chamber as the purge gas so that an unreacted H2O and the reaction subproduct HCl are removed.
  • Then, ZrCl4 is supplied again so that only another one-atom layer is deposited. The supply of ZrCl4 is stopped, and the purge gas is produced so that an unreacted ZrCl4 and the reaction subproduct HCl are removed.
  • In this manner, a cycle of the ZrCl4 supply, the purge, the H2O supply and the purge sequentially carried in the named order, is repeated necessary times, until the capacitor dielectric film 2 of ZrO2 having the film thickness of 5 to 15 nm is obtained.
  • After the ZrO2 thin film is formed, an upper electrode thin film having a film thickness of 5 to 50 nm is formed of at least one material selected from the group consisting of TiN, Ti, W, WN, Pt, Ir, Ru, by means of a PVD process, a CVD process or a ALD process, and then, is patterned into a desired shape, so that an upper electrode 3 is formed. Thus, the thin film capacitor is obtained.
  • The thin film capacitor formed as mentioned above has a small leakage current and a large capacitance, because the capacitor dielectric film is formed of ZrO2 having a high electrical insulation property and a large dielectric constant, and because a leakage current increase is small even if the film thickness of ZrO2 is reduced.
  • In addition, if the ZrO2 thin film is formed by the ALD process, it is possible to carry out a film formation at a low temperature and to omit a post anneal which is carried out in an oxidizing atmosphere. Therefore, it is possible to avoid the drop of the capacitance, the increase of the leakage current and the drop in the yield of production, caused by oxidation of the lower electrode.
  • Referring to FIG. 3, there is shown a graph illustrating a relation between an electrode-to-electrode voltage (Vp) of a thin film capacitor and a leakage current in the case that the capacitor dielectric film is formed of ZrO2 and the upper and lower electrodes are formed of TiN. From comparison of FIG. 3 with FIG. 14B, it would be seen that the leakage current evidently becomes small in comparison with the thin film capacitor having the capacitor dielectric film formed of Ta2O5, shown in FIG. 14A.
  • In the above mentioned embodiment, the capacitor dielectric film is formed of ZrO2 deposited by the ALD process. However, a similar advantage can be obtained in the case that the capacitor dielectric film is formed of at least one material selected from the group consisting of HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), and (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1).
  • In the case that the capacitor dielectric film is formed of HfO2, HfCl4 is used as a starting material for Hf, and H2O is used as an oxygen material.
  • In the case that the capacitor dielectric film is formed of (Zrx, Hf1-x)O2, ZrCl4 is used as a starting material for Zr, HfCl4 is used as a starting material for Hf, and H2O is used as an oxygen material.
  • In the case that the capacitor dielectric film is formed of (Zry, Ti1−y)O2, ZrCl4 is used as a starting material for Zr, TiCl4 is used as a starting material for Ti, and H2O is used as an oxygen material.
  • In the case that the capacitor dielectric film is formed of (Hfz, Ti1-z)O2, HfCl4 is used as a starting material for Hf, TiCl4 is used as a starting material for Ti, and H2O is used as an oxygen material.
  • In the case that the capacitor dielectric film is formed of (Zrk, Til, Hfm)O2, ZrCl4 is used as a starting material for Zr, TiCl4 is used as a starting material for Ti, HfCl4 is used as a starting material for Hf, and H2O is used as an oxygen material.
  • Now, a second embodiment of the present invention will be described.
  • According to this second embodiment, in a thin film capacitor of a MIM structure having a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), deposited by means of the ALD process, an anneal is carried out after formation of the capacitor dielectric film.
  • The thin film capacitor of the MIM structure in accordance with the first embodiment having the capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<Z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), has a small leakage current and a large capacitance, in comparison with the thin film capacitor having the capacitor dielectric film formed of Ta2O5, and therefore, can be satisfactorily used as a memory capacitor in a DRAM cell. However, when the film thickness of the capacitor dielectric film is decreased, the capacitance increase is small (namely, the decrease of teq is small), and on the other hand, the leakage current increases.
  • Referring to FIG. 4, there is shown a graph illustrating a relation between teq (film thickness converted into SiO2) and an actual film thickness when the capacitor dielectric film formed of ZrO2 and the upper and lower electrodes are formed of TiN. A capacitance drop caused by a low dielectric constant layer contribution would be seen from FIG. 4.
  • The reason for this is considered as follows: Just after the deposition of the ZrO2 thin film, a ZrO2 boundary layer having poor crystallinity exists, which act as a low dielectric constant layer. Therefore, even if the film thickness is decreased, the low dielectric constant layer contribution is large, with the result that the capacitance of the capacitor as a whole cannot be correspondingly increased. On the other hand, the leakage current increases with the decrease of the film thickness.
  • In this second embodiment, on the other hand, in the thin film capacitor formed in accordance with the first embodiment, namely, in the thin film capacitor of the MIM structure having the capacitor dielectric film formed of the ZrO2 thin film formed by the ALD process, the anneal is carried out at a temperature of 300 to 700 degrees Celsius after the deposition of the ZrO2 thin film. As a result, a further large capacitance and a small leakage current are realized in the thin film capacitor.
  • As mentioned above, the thin film capacitor having the ZrO2 thin film deposited on a metal electrode by the ALD process can be used as a memory capacitor in the DRAM cell. However, in order to meet with the demand for a further microminiaturization and a further high integration, it is preferred to obtain a further large capacitance and a small leakage current.
  • The inventors of the present application uncovered that if an ZrO2 thin film is only deposited on a metal electrode by the ALD process, an amorphous ZrO2 layer region exists at a boundary between the lower electrode and the ZrO2 layer, and it is not possible to obtain a characteristics intrinsic to the MIM structure thin film capacitor having the capacitor dielectric film of ZrO2. Namely, since the amorphous layer functions as a low dielectric constant layer in the MIM structure thin film capacitor, the obtained capacitance drops.
  • Furthermore, the inventors of the present application uncovered and confirmed that the amorphous ZrO2 layer is crystallized by carrying out the anneal after the deposition of the ZrO2 layer. With this crystallization, the ZrO2 layer is homogenized, so that the above mentioned low dielectric constant boundary layer is removed. As a result, it was confirmed that a further large capacitance and a small leakage current are obtained in comparison with the case that no anneal was carried out.
  • For example, the ZrO2 capacitor dielectric film is deposited on the lower electrode of TiN by the ALD process at a temperature of 200 to 400 degrees Celsius, and thereafter, for example, the upper electrode of TiN is formed, and then, is patterned into a desired shape, so that the MIM thin film capacitor is obtained. Thereafter, the MIM thin film capacitor thus obtained is annealed at a temperature which is not lower than a ZrO2 layer deposition temperature and which is in a range of 300 to 700 degrees Celsius.
  • Incidentally, the above mentioned amorphous layer is formed when the capacitor dielectric film is deposited, and the anneal may be carried out at any time after the deposition of the capacitor dielectric film. For example, a similar advantage can be obtained even if the anneal is carried out immediately after the deposition of the capacitor dielectric film or even if the anneal is carried out after the formation of the upper electrode.
  • In addition, the atmosphere in which the anneal is carried out is not important, but it is preferable to use a non-oxidizing atmosphere which does not cause a characteristics deterioration attributable to oxidation of the low electrode material, namely, N2, Ar, He, or a forming gas (H2+N2).
  • Referring to FIG. 5, there is shown a graph illustrating a relation between teq (film thickness converted into SiO2) and an actual film thickness in the case that the capacitor dielectric film is formed of ZrO2 and the upper and lower electrodes are formed of TiN. It could be seen from FIG. 5 that, if the anneal is carried out, the low dielectric constant layer contribution becomes null. In FIG. 5, a black solid circle indicates the thin film capacitor formed with no anneal, which is the same as the thin film capacitor shown in FIG. 4. A white circle indicates the thin film capacitor formed by carrying out the anneal under the atmosphere of a mixed gas of hydrogen and nitrogen, and a triangle indicates the thin film capacitor formed by carrying out the anneal under the atmosphere of only nitrogen.
  • Referring to FIG. 6, there is shown a graph illustrating a relation between a leakage current and teq (film thickness converted into SiO2) in the case that the capacitor dielectric film is formed of ZrO2 and the upper and lower electrodes are formed of TiN. In FIG. 6, a white circle indicates the thin film capacitor formed with no anneal. A square indicates the thin film capacitor formed by carrying out the anneal under a mixed gas of hydrogen and nitrogen, and a triangle indicates the thin film capacitor formed by carrying out the anneal under only a nitrogen. It could be seen from FIG. 6 that the case of carrying out the anneal under the mixed gas of hydrogen and nitrogen and the case of carrying out the anneal under only the nitrogen exhibit substantially the same leakage current value. Therefore, it would be seen that only the heat treatment is effective, and the atmosphere for the anneal does not give any influence.
  • As seen from the above, in the thin film capacitor of the second embodiment, the low dielectric constant layer (ZrO2 boundary layer having poor crystallinity) existing just after the deposition of the ZrO2 thin film, is improved in crystallinity by the anneal, so that it no longer functions as the low dielectric constant layer. As a result, the capacitance is increased (namely, teq is decreased). In addition, since crystallinity is improved in the whole of the ZrO2 thin film, the leakage current is decreased.
  • In the above mentioned second embodiment, the capacitor dielectric film is formed of ZrO2. However, a similar advantage can be obtained in the case that the capacitor dielectric film is formed of at least one material selected from the group consisting of HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), and (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1).
  • In addition, when the thin film capacitor of the second embodiment is formed in a semiconductor device having a transistor in which a refractory metal silicide is provided in a gate electrode and source/drain diffused layer regions, the anneal condition is required at a temperature which is not lower than the ZrO2 deposition temperature in the ALD process but which is not higher than a temperature where no aggregation of the refractory metal silicide occurs in the gate electrode and the source/drain diffused layer regions. The aggregation of the silicide is remarkable in a region having a small area, namely, in the gate electrode rather than the source/drain diffused layer regions. For example, in the device on the generation of the gate length 0.15 micron, the aggregation temperature is about 600 degrees Celsius. In this case, the anneal temperature is not lower than the ZrO2 deposition temperature in the ALD process but not higher than 600 degrees Celsius.
  • Now, a third embodiment of the present invention will be described.
  • According to this third embodiment, in a stacked MIM (metal-insulator-metal) capacitor in a DRAM or a logic mixed DRAM having a logic section and a memory section formed on the same chip, a lower electrode, a capacitor dielectric film and an upper electrode are sequentially formed in the ALD process by use of an ALD apparatus.
  • First, a conventional method for forming the stacked MIM capacitor in a DRAM or a logic mixed DRAM will be described. As shown in FIG. 7, a transistor is formed, and after a capacitor contact 11 is formed, an interlayer insulator film 12 is deposited. Then, an opening is formed in the interlayer insulator film 12 by use of lithography, and a lower electrode (metal) 13 is deposited. Thereafter, a resist 14 is filled into the opening to protect the opening, and only an upper portion of the interlayer insulator film is removed by an etch-back process or a CMP (chemical mechanical polishing) process, so that capacitors are separated from each other. Then, as shown in FIG. 8, a capacitor dielectric film 15 and an upper electrode 16 are deposited, and a patterning is carried out to form a common electrode conductor (capacitor plate).
  • In this conventional method for forming the stacked MIM capacitor, when the lower electrode is selectively removed, it is necessary to charge the resist 14 into the opening so as to prevent a portion which will become the lower electrode of the capacitor, from the etching. For the purpose of removing this resist, it is possible to remove this resist by using acid, in a MIS (metal-insulator-silicon) capacitor having the lower electrode formed of polysilicon. However, in the MIM capacitor having the lower electrode formed of a metal such as TiN, it is impossible to remove this resist by using acid (SPM (sulfuric acid—peroxide mixture). Therefore, the resist is removed by a plasma removal processing plus an organic removal processing. However, this removal method is difficult to completely remove depositions which were generated in the etching and a removal residue of the resist.
  • Furthermore, in conventional method for forming the stacked MIM capacitor, it is difficult to avoid a plasma damage to the surface of the lower electrode when the lower electrode is selectively removed and when the resist is removed. In addition, since impurity such as carbon in atmosphere of a clean room deposits on the surface of the lower electrode, it is also difficult to maintain a boundary between the lower electrode and the capacitor dielectric film in a good condition, with the result that the characteristics of the capacitor dielectric film is deteriorated.
  • In the third embodiment of the present invention, on the other hand, in a thin film capacitor of a MIM structure in which each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru, and a capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), the lower electrode, the capacitor dielectric film and the upper electrode are sequentially formed in the same machine in the ALD process by using an ALD apparatus. With this arrangement, a boundary between the lower electrode and the capacitor dielectric film can be maintained in a good condition.
  • Now, a method in accordance with the third embodiment of the present invention for forming the stacked MIM capacitor in the DRAM or the logic mixed DRAM, will be described with reference to diagrammatic sectional views of FIGS. 9A to 9N. Here, explanation will be made on a cylinder type capacitor, which is one kind of the stacked capacitor, and which includes a capacitor dielectric film formed of ZrO2 and upper and lower electrodes formed of TiN.
  • First, as shown in FIG. 9A, a device isolation region 22 is formed on a principal surface of a semiconductor substrate (silicon substrate) 21 to confirm a device formation region. In the device formation region, a gate electrode 23 is formed on a not-shown gate insulator film, and a source/drain diffused region 24 is formed in a surface region of the substrate at each side of the gate electrode. This gate electrode 23 forms a word line in the DRAM. Then, a side wall 25 is formed on each side of the gate electrode 23, and Co (cobalt) or Ni (nickel) is deposited on the gate electrodes 23 and the source/drain diffused regions 24 to form a cobalt silicide or a nickel silicide. Thus, MOS transistors are formed.
  • Then, as shown in FIG. 9B, an interlayer insulator film 26 is formed to cover the transistors, and an upper surface of the interlayer insulator film 26 is planarized.
  • As shown in FIG. 9C, a hole for a cell contact (capacitor contact) 27 and a hole for a cell contact (bit contact) 28 are formed in the interlayer insulator film 26 to reach the source/drain diffused regions 24 by a lithography, and W (tungsten) is charged into the holes thus formed, to form a W plug.
  • As shown in FIG. 9D, a bit line conductor layer is formed on the interlayer insulator film 26 and the cell contacts 27 and 28, and is patterned to form a bit line 29 electrically connected to the W plug of the cell contact 28.
  • As shown in FIG. 9E, an interlayer insulator film 30 is deposited to cover the bit line 29, and then, and an upper surface of the interlayer insulator film 30 is planarized.
  • As shown in FIG. 9F, a hole for a capacitor contact 31 is formed in the interlayer insulator film 30 to reach the cell contact 27 by a lithography, and W (tungsten) is charged into the hole thus formed, to form a W plug.
  • As shown in FIG. 9G, an interlayer insulator film 32 is formed to cover the interlayer insulator film 30 and the capacitor contact 31.
  • As shown in FIG. 9H, a cylinder 33 is formed in the interlayer insulator film 32 to reach the capacitor contact 31 by a lithography.
  • As shown in FIG. 91, by using the ALD apparatus, a lower electrode metal 34 of TiN, a capacitor dielectric film 35 of ZrO2 and an upper electrode metal 36 a of TiN are continuously formed in the named order within the same machine without being exposed to air.
  • Here, referring to FIG. 10, there is shown a flow chart illustrating a process for forming a TiN film which constitutes the lower electrode metal 34 and the upper electrode metal 36 a, by use of the ALD apparatus.
  • For formation of the TiN film, TiCl4 and NH3 are used as a starting material gas. A film deposition temperature is on the order of 300 to 500 degrees Celsius.
  • First, TiCl4 is supplied to a chamber of the ALD apparatus. Thus, only a one-atom layer is deposited, by reaction, on a surface of the interlayer insulator film 32 including the surface of the cylinder formed in the interlayer insulator film 32. Next, the supply of TiCl4 is stopped, and a purge gas is introduced into the chamber so that an excessive unreacted TiCl4 is removed.
  • Thereafter, NH3 is supplied to replace a Cl group which terminates Ti grown on the surface of the interlayer insulator film, with a NH2 group. In this process, HCl is produced as a reaction subproduct. Then, the supply of NH3 is stopped, and the inert gas represented by Ar or N2 is introduced into the chamber as the purge gas so that an unreacted NH3 and the reaction subproduct HCl are removed.
  • Then, TiCl4 is supplied again so that only another one-atom layer is deposited. The supply of TiCl4 is stopped, and the purge gas in introduced so that an unreacted TiCl4 and the reaction subproduct HCl are removed. The supply of the purge gas is stopped, and NH3 is supplied.
  • In this manner, a cycle of the TiCl4 supply, the purge, the NH3 supply and the purge sequentially carried in the named order, is repeated necessary times, until the lower electrode metal film 34 of TiN having the film thickness of 5 to 50 nm is obtained.
  • Thereafter, similarly to the procedure of the formation of the ZrO2 thin film in the first embodiment as shown in FIG. 2, the capacitor dielectric film 35 of ZrO2 having the film thickness of 5 to 15 nm is formed on the lower electrode metal film 34 by alternately supplying ZrCl4 and H2O.
  • Furthermore, the upper electrode metal film 36 a of TiN having the film thickness of 5 to 50 nm is formed on the capacitor dielectric film 35 by alternately supplying TiCl4 and NH3, similarly to the procedure of the formation of the lower electrode metal film 34 as shown in FIG. 10.
  • In the example shown in FIG. 91, an upper electrode metal 36 b formed of W (tungsten) is deposited on the upper electrode metal film 36 a so that the upper electrode is formed of a double layer consisting of a TiN layer and a W layer. In this case, the W layer is not necessarily required to be formed by use of the ALD process, but can be formed by use of a conventional CVD process or a sputtering. The ALD process expends a time since it is necessary to alternately supply the different gases. Use of the CVD process or the sputtering is effective for a mass production of the device.
  • This can be applied to the lower electrode 34. Namely, it is not necessary to form the whole of the lower electrode 34 by use of the ALD process. The lower electrode 34 can be formed first by the sputtering, for example, and then, only a portion of the lower electrode 34 corresponding to the boundary layer is formed by the ALD process, and thereafter, the capacitor dielectric film 35 and the upper electrode 36 a are succeedingly formed by the ALD process.
  • In other words, the lower electrode 34 and the upper electrode 36 a are sufficient if only a boundary portion to the capacitor dielectric film 35 is formed by the ALD process. Therefore, it is sufficient if the film thickness of each of the lower electrode 34 and the upper electrode 36 a to be formed by the ALD process has at least one-atom layer thickness. Accordingly, only a boundary portion to the capacitor dielectric film 35, of each of the lower electrode 34 and the upper electrode 36 a, is formed by the ALD process to have at least one-atom layer thickness, and the other portion of each of the lower electrode 34 and the upper electrode 36 a can be formed by use of the CVD process or the sputtering so that the whole film thickness of each of the lower electrode 34 and the upper electrode 36 a becomes 5 to 50 nm.
  • Thereafter, as shown in FIG. 9J, by a patterning using the CMP, the etch-back or the lithography, the stacked structure thus formed is divided into a plurality of individual cylinder type capacitors 37 each formed of the lower electrode 34, the capacitor dielectric film 35 and the upper electrode 36.
  • Succeedingly, as shown in FIG. 9K, an insulating film 38 is deposited on the whole surface to isolate the lower electrode 34 and the upper electrode 36 from each other.
  • As shown in FIG. 9L, an opening 39 is formed through the insulating film 38 at only a position above the upper electrode 36 and to reach the upper electrode 36. At this time, the opening 39 never extends to the lower electrode 34.
  • As shown in FIG. 9M, a common interconnection layer 40 is formed to cover the upper surface and to charge into the opening 39 so that the upper electrodes 36 are connected in common to the common interconnection layer 40.
  • Furthermore, as shown in FIG. 9N, an interlayer insulator film 41 is formed to cover the upper surface and the common interconnection layer 40, and a first metal layer 42 is formed on the interlayer insulator film 41 so as to constitute a first level interconnection.
  • In this third embodiment, since the lower electrode, the capacitor dielectric film and the upper electrode are continuously formed in the same machine (the same chamber) by use of the ALD apparatus which can control the composition of the film with an atom-layer level, it is possible to perfectly prevent the chemical and physical damages to the surface of the lower electrode, which would otherwise occur when the lower electrode is patterned and when the resist is removed. In addition, it is also possible to minimize deposition of carbons included in the air within the clean room, to the surface of the lower electrode and the surface of the capacitor dielectric film. Because of these reasons, it is possible to maintain a boundary between the lower electrode and the capacitor dielectric film and a boundary between the capacitor dielectric film and the upper electrode in a good condition. Furthermore, since the boundary between the lower electrode and the capacitor dielectric film is maintained in the good condition, it is possible to minimize the capacitance drop and the increase of the capacitor dielectric film leakage current.
  • In addition, after the MIM structure capacitor is formed, if the anneal is carried out similarly to the capacitor of the second embodiment, it is possible to realize a capacitor having a further large capacitance and a small leakage current. In this case, the anneal is carried out at a temperature which is not lower than the ZrO2 forming temperature in the ALD process but which is not higher than a temperature where no aggregation of a refractory metal silicide occurs in a gate electrode and source/drain diffused layer regions in the case that the refractory metal silicide is provided in the gate electrode and the source/drain diffused layer regions.
  • The present invention is in now way limited to the cylinder type capacitor, but can be applied to a planar capacitor and a box type capacitor.
  • Referring to FIG. 11, there is shown a diagrammatic sectional view of a planar capacitor to which the present invention can be applied. A device isolation region 52 is formed on a principal surface of a semiconductor substrate (silicon substrate) 51 to confirm a device formation region. In the device formation region, a gate electrode 53 is formed on a not-shown gate insulator film, and a source/drain diffused region 54 having a cobalt silicide is formed in a surface region of the substrate at each side of the gate electrode. An interlayer insulator film 55 is formed to cover the gate electrode 53 and the principal surface of the substrate.
  • A bit contact 56 is formed in the interlayer insulator film 55 to reach one of each pair of source/drain diffused regions 54. A bit line 57 is formed on the interlayer insulator film 55 to be electrically connected to the bit contact 56. Furthermore, an interlayer insulator film 58 is deposited to cover the bit line 57 and the interlayer insulator film 55.
  • On the interlayer insulator film 58, a lower electrode 59 formed of a metal of a metal nitride, a capacitor dielectric film 60 formed of ZrO2, and an upper electrode 61 formed of a metal of a metal nitride, are continuously formed in the named order by the ALD apparatus. The lower electrode 59 is electrically connected to a capacitor contact 62 formed through the interlayer insulator films 58 and 55 to reach the other of each pair of source/drain diffused regions 54. A side wall 66 is formed on a side surface of each planar capacitor thus formed which is composed of the lower electrode 59, the capacitor dielectric film 60 and the upper electrode 61.
  • A common interconnection layer 63 is formed on the upper electrode 61 of each planar capacitor to interconnect the upper electrode 61 of the planar capacitors. An interlayer insulator film 64 is formed to cover the common interconnection layer 63, and a first metal layer 65 is formed on the interlayer insulator film 64 to constitute a first level metal interconnection.
  • Referring to FIG. 12, there is shown a diagrammatic sectional view of a box type capacitor to which the present invention can be applied. A device isolation region 72 is formed on a principal surface of a semiconductor substrate (silicon substrate) 71 to confirm a device formation region. In the device formation region, a gate electrode 73 is formed on a not-shown gate insulator film and a source/drain diffused region 74 having a cobalt silicide is formed in a surface region of the substrate at each side of the gate electrode. An interlayer insulator film 75 is formed to cover the gate electrode 73 and the principal surface of the substrate.
  • A bit contact 76 is formed in the interlayer insulator film 75 to reach one of each pair of source/drain diffused regions 74. A bit line 77 is formed on the interlayer insulator film 75 to be electrically connected to the bit contact 76. Furthermore, an interlayer insulator film 78 is deposited to cover the bit line 77 and the interlayer insulator film 75. A capacitor contact 82 is formed through the interlayer insulator films 78 and 75 to reach the other of each pair of source/drain diffused regions 74.
  • On the capacitor contact 82, a lower electrode 79 a of W (tungsten) is formed. To cover the lower electrode 79 a and the interlayer insulator film 78, a lower electrode 79 b formed of a metal of a metal nitride, a capacitor dielectric film 80 formed of ZrO2, and an upper electrode 81 formed of a metal of a metal nitride, are continuously formed in the named order by the ALD apparatus. Thus, the box type capacitor is composed of the lower electrodes 79 a and 79 b, the capacitor dielectric film 80 and the upper electrode 81.
  • On the upper electrode 81, an insulator film 86 is formed to isolate the upper electrode 81 and the lower electrode 79 from each other. On the an insulator film 86, a common interconnection layer 83 is formed to interconnect the upper electrode 81 b of the planar capacitors. An interlayer insulator film 84 is formed to cover the common interconnection layer 83, and a first metal layer 85 is formed on the interlayer insulator film 84 to constitute a first level metal interconnection.
  • Now, a fourth embodiment of the present invention will be described.
  • In this fourth embodiment, in a semiconductor device having a MIS thin film capacitor formed on an insulator film formed to over an uppermost interconnection layer, a capacitor dielectric film of the MIS thin film capacitor is formed by the ALD process which can carry out a film deposition at a low temperature and which makes the post-anneal in an oxidizing atmosphere unnecessary, and the MIS thin film capacitor is located to function as a decoupling capacitor for power supply lines.
  • Referring to FIG. 13, there is shown a diagrammatic sectional view of a part of a semiconductor device, for illustrating the fourth embodiment of the present invention.
  • An interlayer insulator film 103 is formed to cover an uppermost interconnection (ground line) 101, another uppermost interconnection (power supply line) 102 and an underlying interlayer insulator film. On the interlayer insulator film 103, a lower electrode 105, a capacitor dielectric film 106 and an upper electrode 107 are formed in the named order to constitute a decoupling capacitor 104. The lower electrode 105 is connected through a contact 108 to the uppermost interconnection (ground line) 101, and the upper electrode 107 is connected through a contact 109 to the uppermost interconnection (power supply line) 102.
  • Now, a method for forming the decoupling capacitor shown in FIG. 13 will be described.
  • In a logic device formed in a known fabricating process, on the interlayer insulator film 103, a lower electrode film is formed of at least one material selected from the group consisting of TiN, Ti, TaN, Ta, W, WN, Pt, Ir, Ru, by means of a sputtering process or a ALD process, and then, is patterned into a desired shape, so that the lower electrode 105 is formed at a position above the uppermost interconnection (ground line) 101 and is connected to the contact 108 reaching the uppermost interconnection (ground line) 101.
  • Thereafter, a capacitor dielectric film is deposited to cover the lower electrode 105 by use of the ALD process at a film deposition temperature of 200 to 400 degrees Celsius. This capacitor dielectric film is constituted of a single-layer film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), or alternatively, a multi-layer film formed of at least two materials selected from the group mentioned above. Then, the capacitor dielectric film is patterned into a desired shape to form the capacitor dielectric film 106.
  • Then, to cover the capacitor dielectric film 106, an upper electrode film is formed of at least one material selected from the group consisting of TiN, Ti, TaN, Ta, W, WN, Pt, Ir, Ru, by means of a sputtering process or a ALD process, and then, is patterned into a desired shape, so that the upper electrode 107 is formed to partially cover the capacitor dielectric film 106 and is connected to the contact 109 reaching the uppermost interconnection (power supply line) 102. Thus, the thin film capacitor functioning as the decoupling capacitor is formed in the semiconductor device.
  • In the embodiment shown in FIG. 13, the lower electrode is connected to the uppermost interconnection (ground line) and the upper electrode is connected to the uppermost interconnection (power supply line). However, the present invention is in no way limited to this fashion. It is a matter of course to persons skilled in the art that a similar advantage can be obtained in the case that the lower electrode is connected to the uppermost interconnection (power supply line) and the upper electrode is connected to the uppermost interconnection (ground line).
  • In addition, in the embodiment shown in FIG. 13, the thin film capacitor is formed over the uppermost interconnection of the semiconductor device to function as the decoupling capacitor. However, the thin film capacitor can be formed within the inside of the semiconductor device or on a lower surface of the semiconductor device.
  • As mentioned above, in the fourth embodiment, since a capacitor dielectric film having a high dielectric constant is formed by the ALD process which can carry out a film deposition at a low temperature and which makes the post-anneal in an oxidizing atmosphere unnecessary, the thin film capacitor can be formed in the semiconductor device with no characteristics deterioration attributable to oxidation of the interconnection layer and with no drop in yield of production.
  • Incorporation of the thin film capacitor in accordance with the present invention into the semiconductor device as the decoupling capacitor can overcome the problem mentioned hereinbefore of the conventional on-chip decoupling capacitor and can simultaneously realize a low inductance and a large capacitance which are advantages of the on-chip decoupling capacitor.
  • As mentioned above, in the MIM thin film capacitor in accordance with the present invention, since a capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), it is possible to reduce a leakage current and to increase a capacitance value.
  • Furthermore, in the MIM thin film capacitor in accordance with the present invention, since an anneal is carried out after a capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<X<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1−z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), it is possible to further reduce a leakage current and to further increase a capacitance value.
  • In the stacked MIM thin film capacitor in accordance with the present invention provided in a DRAM or a logic mixed DRAM, since a lower electrode, a capacitor dielectric film and an upper electrode are continuously formed in the ALD process, a silicide layer formed in a gate electrode and a source/drain diffused region is never deteriorated, and a sufficient capacitance value (a maximum capacitance value per a unitary area and a minimum leakage current value per a unitary area) can be ensured as a capacitor of each DRAM cell provided in a memory section.
  • Moreover, according to the present invention, since a thin film capacitor having a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<Y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), is formed over an uppermost interconnection layer in a semiconductor device, it is possible to realize a low-inductance, large-capacitance, one-chip decoupling capacitor, which meets with a speedup of an LSI.
  • The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims (14)

1-14. (Cancelled).
15. A method for fabricating a semiconductor device, comprising the steps of forming a lower electrode of a capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and, forming an upper electrode of said capacitor on the capacitor dielectric film, so that the capacitor is constituted of said lower electrode, said capacitor dielectric film and said upper electrode, wherein at a stage after formation of said capacitor dielectric film, a heat treatment is carried out at a temperature not lower than a film deposition temperature in the atomic layer deposition.
16. A method for fabricating a semiconductor device including a transistor having a gate electrode and source/drain diffused layers having a silicide of a refractory metal, the method comprising the steps of forming a lower electrode of a capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and, forming an upper electrode of said capacitor on said capacitor dielectric film, so that the capacitor is constituted of said lower electrode, said capacitor dielectric film and said upper electrode.
17. A method claimed in claim 16 wherein after formation of said capacitor dielectric film, a heat treatment is carried out at a temperature which is not lower than a film deposition temperature in the atomic layer deposition but which is not higher than a temperature where no aggregation of said silicide of refractory metal occurs in said gate electrode and said source/drain diffused layers.
18. A method claimed in claim 16 wherein after formation of said upper electrode, a heat treatment is carried out at a temperature which is not lower than a film deposition temperature in the atomic layer deposition but which is not higher than a temperature where no aggregation of said silicide of refractory metal occurs in said gate electrode and said source/drain diffused layers.
19. A method claimed in claim 16 wherein said capacitor constitutes a cell capacitor of each DRAM cell and wherein said lower electrode, said capacitor dielectric film and said upper electrode are continuously deposited in the same machine.
20. A method claimed in claim 16 wherein said cell capacitor of each DRAM cell is of a cylinder type, and wherein after the formation of said upper electrode, said lower electrode, said capacitor dielectric film and said upper electrode, which are positioned in an upper portion of the cylinder, are removed so that a cylinder type capacitor is formed, and said upper electrode charged into an inside of the cylinder is connected to a common interconnection.
21. A method for fabricating a semiconductor device having a capacitor of a MIM (metal-insulator-metal) structure formed on an insulator film formed on an interconnection layer, the method comprising the steps of forming a lower electrode of the capacitor, forming on said lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and then, forming an upper electrode on said capacitor dielectric film.
22. A method of fabricating a semiconductor device comprising forming source and drain regions of a transistor, forming a metal plug in contact with one of the source and drain regions of said transistor, forming a lower metal electrode of a capacitor in contact with said metal plug, forming a capacitor dielectric film on said lower metal electrode by atomic layer deposition (ALD), and forming an upper metal electrode on said capacitor dielectric film, said capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1) and (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and said capacitor dielectric film having a film thickness of 5 to 15 nm,
whereby said semiconductor device results in a better electrical connection between said capacitor and said transistor and in suppressing a change in leakage current between said lower metal electrode and said upper metal electrode of said capacitor against a change in temperature irrespective of a thinner dielectric film thickness.
23. The method as claimed in claim 22, wherein said upper electrode is formed by atomic layer deposition (ALD).
24. The method as claimed in claim 23, wherein said lower electrode is formed by atomic layer deposition (ALD).
25. A method of fabricating a semiconductor device comprising forming first and second diffusion regions of a transistor selectively in a semiconductor substrate, forming first and second metal silicide layers on respective surface portions of said first and second diffusion regions, covering said semiconductor substrate and said transistor with a first insulating layer, forming first and second holes in said first insulating layer to expose respective parts of said first and second metal silicide layers, filling said first and second holes with first and second metal plugs respectively, forming a bit line formed over said first insulating layer in contract with said first metal plug, forming a second insulating layer formed over said first insulating layer and said bit line, forming a third contact hole in said second insulating layer, filling said third hole with a third metal plug, and forming a lower metal electrode of a capacitor in contact with said third metal plug, forming a dielectric film on said lower metal electrode by atomic layer deposition (ALD), said dielectric film being made of a dielectric material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), and (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and forming an upper metal electrode on said dielectric film, whereby said semiconductor device results in a better electrical connection between said capacitor and said transistor without aggregation of said first and second metal silicide layers occurring and in suppressing a change in leakage current between said lower metal electrode and said upper metal electrode of said capacitor against a change in temperature.
26. The method as claimed in claim 25, wherein said upper electrode is formed by atomic layer deposition (ALD).
27. The method as claimed in claim 26, wherein said lower electrode is formed by atomic layer deposition (ALD).
US10/967,436 2001-06-13 2004-10-18 Semiconductor device having a thin film capacitor and method for fabricating the same Abandoned US20050051824A1 (en)

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US10/967,436 US20050051824A1 (en) 2001-06-13 2004-10-18 Semiconductor device having a thin film capacitor and method for fabricating the same
US11/637,147 US8169013B2 (en) 2001-06-13 2006-12-12 Metal-insulator-metal (MIM) capacitor having capacitor dielectric material selected from a group consisting of ZRO2, HFO2, (ZRX, HF1-X)O2 (0<x<1), (ZRy, Ti (O<y<1), (Hfz, Ti-z)O2 (O<z<1) and (Zrk, Ti1, Hfm)O2 (O<K, 1, m<1, K+1+m=1)
US11/928,460 US8815678B2 (en) 2001-06-13 2007-10-30 Method for fabricating a metal-insulator-metal (MIM) capacitor having capacitor dielectric layer formed by atomic layer deposition (ALD)
US14/332,687 US20140327064A1 (en) 2001-06-13 2014-07-16 Method for fabricating a metal-insulator-metal (mim) capacitor having capacitor dielectric layer formed by atomic layer deposition (ald)

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JP2001178539A JP3863391B2 (en) 2001-06-13 2001-06-13 Semiconductor device
JP2001-178539 2001-06-13
US10/170,813 US8212299B2 (en) 2001-06-13 2002-06-13 Semiconductor device having a thin film capacitor of a MIM (metal-insulator-metal) structure
US10/967,436 US20050051824A1 (en) 2001-06-13 2004-10-18 Semiconductor device having a thin film capacitor and method for fabricating the same

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US10/170,813 Expired - Fee Related US8212299B2 (en) 2001-06-13 2002-06-13 Semiconductor device having a thin film capacitor of a MIM (metal-insulator-metal) structure
US10/967,436 Abandoned US20050051824A1 (en) 2001-06-13 2004-10-18 Semiconductor device having a thin film capacitor and method for fabricating the same
US11/637,147 Active 2025-01-08 US8169013B2 (en) 2001-06-13 2006-12-12 Metal-insulator-metal (MIM) capacitor having capacitor dielectric material selected from a group consisting of ZRO2, HFO2, (ZRX, HF1-X)O2 (0<x<1), (ZRy, Ti (O<y<1), (Hfz, Ti-z)O2 (O<z<1) and (Zrk, Ti1, Hfm)O2 (O<K, 1, m<1, K+1+m=1)
US11/928,460 Expired - Lifetime US8815678B2 (en) 2001-06-13 2007-10-30 Method for fabricating a metal-insulator-metal (MIM) capacitor having capacitor dielectric layer formed by atomic layer deposition (ALD)
US13/538,638 Abandoned US20120261735A1 (en) 2001-06-13 2012-06-29 Semiconductor device having a thin film capacitor and method for fabricating the same
US14/332,687 Abandoned US20140327064A1 (en) 2001-06-13 2014-07-16 Method for fabricating a metal-insulator-metal (mim) capacitor having capacitor dielectric layer formed by atomic layer deposition (ald)

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US11/928,460 Expired - Lifetime US8815678B2 (en) 2001-06-13 2007-10-30 Method for fabricating a metal-insulator-metal (MIM) capacitor having capacitor dielectric layer formed by atomic layer deposition (ALD)
US13/538,638 Abandoned US20120261735A1 (en) 2001-06-13 2012-06-29 Semiconductor device having a thin film capacitor and method for fabricating the same
US14/332,687 Abandoned US20140327064A1 (en) 2001-06-13 2014-07-16 Method for fabricating a metal-insulator-metal (mim) capacitor having capacitor dielectric layer formed by atomic layer deposition (ald)

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Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050153518A1 (en) * 2004-01-09 2005-07-14 Samsung Electronics Co., Ltd. Method for forming capacitor using etching stopper film in semiconductor memory
US20050170665A1 (en) * 2003-04-17 2005-08-04 Fujitsu Limited Method of forming a high dielectric film
US20060097305A1 (en) * 2004-11-08 2006-05-11 Lee Kee-Jeung Capacitor with zirconium oxide and method for fabricating the same
US20060234500A1 (en) * 2005-04-15 2006-10-19 Park Jong B Method of forming capacitor of semiconductor device by successively forming a dielectric layer and a plate electrode in a single processing chamber
US20060240679A1 (en) * 2005-04-21 2006-10-26 Seung-Hwan Lee Method of manufacturing semiconductor device having reaction barrier layer
US20060281330A1 (en) * 2005-06-14 2006-12-14 Micron Technology, Inc. Iridium / zirconium oxide structure
US20070018224A1 (en) * 2005-07-20 2007-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Devices and methods for preventing capacitor leakage
FR2890982A1 (en) * 2005-09-21 2007-03-23 St Microelectronics Sa Formation of a dielectric layer on a carrier material by circulating a metal precursor gas with two stages of oxidation, notably for the realization of a condenser in an integrated circuit
US20070077759A1 (en) * 2005-10-05 2007-04-05 Elpida Memory, Inc. Method for forming dielectric film and method for manufacturing semiconductor device by using the same
US20080014247A1 (en) * 2006-06-30 2008-01-17 Nucryst Pharmaceuticals Metal-containing formulations and methods of use
US20080138503A1 (en) * 2004-12-23 2008-06-12 Hynix Semiconductor Inc. Method For Forming Dielectric Film And Method For Forming Capacitor In Semiconductor Device Using The Same
US20090075434A1 (en) * 2007-09-14 2009-03-19 Junker Kurt H Method of removing defects from a dielectric material in a semiconductor
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7825043B2 (en) 2005-11-28 2010-11-02 Hynix Semiconductor Inc. Method for fabricating capacitor in semiconductor device
US20100291763A1 (en) * 2009-05-18 2010-11-18 Hitachi-Kokusai Electric Inc. Method of manufacturing semiconductor device and substrate processing apparatus
US20110038094A1 (en) * 2008-04-16 2011-02-17 Renesas Electronics Corporation Capacitor
US20110057240A1 (en) * 2009-09-08 2011-03-10 Hynix Semiconductor Inc. Semiconductor device and method of manufacturing the same
US8154066B2 (en) 2004-08-31 2012-04-10 Micron Technology, Inc. Titanium aluminum oxide films
US8501563B2 (en) 2005-07-20 2013-08-06 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US20180122810A1 (en) * 2016-11-03 2018-05-03 Samsung Electronics Co., Ltd. Semiconductor device
US20190081096A1 (en) * 2017-09-12 2019-03-14 Panasonic Intellectual Property Management Co., Ltd. Capacitor including first electrode, dielectric layer, and second electrode, image sensor, and method for producing capacitor
US20190189357A1 (en) * 2017-12-15 2019-06-20 Micron Technology, Inc. Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100464007B1 (en) * 2002-01-30 2005-01-03 엘지전자 주식회사 Mim emitter of field emission device and manufacturing method thereof
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US7279392B2 (en) * 2003-08-04 2007-10-09 Samsung Electronics Co., Ltd. Thin film structure, capacitor, and methods for forming the same
US7425493B2 (en) * 2002-08-17 2008-09-16 Samsung Electronics Co., Ltd. Methods of forming dielectric structures and capacitors
US6784478B2 (en) * 2002-09-30 2004-08-31 Agere Systems Inc. Junction capacitor structure and fabrication method therefor in a dual damascene process
JP2004165559A (en) * 2002-11-15 2004-06-10 Toshiba Corp Semiconductor device
US7101813B2 (en) 2002-12-04 2006-09-05 Micron Technology Inc. Atomic layer deposited Zr-Sn-Ti-O films
JP4907839B2 (en) 2003-03-26 2012-04-04 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
KR100505680B1 (en) * 2003-03-27 2005-08-03 삼성전자주식회사 Method for manufacturing semiconductor memory device having ruthenium film and apparatus for manufacturing the ruthenium film
US7183186B2 (en) * 2003-04-22 2007-02-27 Micro Technology, Inc. Atomic layer deposited ZrTiO4 films
KR100532434B1 (en) * 2003-05-09 2005-11-30 삼성전자주식회사 Methods for manufacturing capacitor of semiconductor memory device
KR100725690B1 (en) * 2003-07-08 2007-06-07 마츠시타 덴끼 산교 가부시키가이샤 Semiconductor device and method for fabricating the same
CN1610117A (en) * 2003-10-17 2005-04-27 松下电器产业株式会社 Semiconductor device and producing method thereof
JP2005150416A (en) * 2003-11-17 2005-06-09 Hitachi Ltd Semiconductor integrated circuit device and its manufacturing method
KR100568256B1 (en) * 2003-12-11 2006-04-07 삼성전자주식회사 Method for cleaning fabrication apparatus of semiconductor device
CN1300855C (en) * 2003-12-19 2007-02-14 上海新傲科技有限公司 Preparing method for silicon substrate mixed structure grid media material on insulator
US7906393B2 (en) * 2004-01-28 2011-03-15 Micron Technology, Inc. Methods for forming small-scale capacitor structures
US7199001B2 (en) * 2004-03-29 2007-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming MIM capacitor electrodes
JP5235260B2 (en) * 2004-04-12 2013-07-10 三星電子株式会社 Method for manufacturing metal-insulator-metal capacitor with seed layer containing nitrogen
KR100604845B1 (en) 2004-04-12 2006-07-26 삼성전자주식회사 Metal-Insulator-Metal capacitor having insulating layer with nitrogen and method for manufacturing the same
FR2869325B1 (en) * 2004-04-27 2006-06-16 Commissariat Energie Atomique METHOD FOR DEPOSITING A THIN LAYER ON AN OXIDE LAYER OF A SUBSTRATE
JP4571836B2 (en) * 2004-07-23 2010-10-27 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
KR100713065B1 (en) * 2004-07-30 2007-05-02 주식회사 하이닉스반도체 Method for fabricating semiconductor memory device having cylinder type storage node
US7601649B2 (en) 2004-08-02 2009-10-13 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7081421B2 (en) 2004-08-26 2006-07-25 Micron Technology, Inc. Lanthanide oxide dielectric layer
JP4543378B2 (en) 2004-11-15 2010-09-15 エルピーダメモリ株式会社 Manufacturing method of semiconductor device
KR100647484B1 (en) * 2004-11-23 2006-11-23 삼성전자주식회사 method of forming a thin film layer, and method of forming a gate structure, capacitor and flash memory device using the same
KR100695887B1 (en) * 2004-12-09 2007-03-20 삼성전자주식회사 Method for forming a titanium nitride layer and method for forming a lower electrode of a MIM capacitor using the titanium nitride layer
KR100667633B1 (en) 2004-12-20 2007-01-12 삼성전자주식회사 Method of manufacturing a thin film layer, and method of manufacturing a gate structure, capacitor and flash memory device using the same
US7560395B2 (en) 2005-01-05 2009-07-14 Micron Technology, Inc. Atomic layer deposited hafnium tantalum oxide dielectrics
US7316962B2 (en) * 2005-01-07 2008-01-08 Infineon Technologies Ag High dielectric constant materials
JP4559866B2 (en) 2005-01-17 2010-10-13 パナソニック株式会社 Manufacturing method of semiconductor device
DE102005018029A1 (en) 2005-04-14 2006-10-26 Infineon Technologies Ag Method for producing an electrical component
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
KR100639219B1 (en) * 2005-05-27 2006-10-30 주식회사 하이닉스반도체 Method for forming capacitor of semiconductor device
KR100717813B1 (en) * 2005-06-30 2007-05-11 주식회사 하이닉스반도체 Capacitor with nano-mixed dielectric and method for manufacturing the same
KR100722988B1 (en) * 2005-08-25 2007-05-30 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same
KR100648860B1 (en) * 2005-09-08 2006-11-24 주식회사 하이닉스반도체 Dielectric and method for forming the same, semiconductor memory device having the dielectric and method for manufacturing the semiconductor memory device
KR100780650B1 (en) * 2006-02-28 2007-11-29 주식회사 하이닉스반도체 Capacitor in semiconductor device and method for using the same
CN100395891C (en) * 2006-03-30 2008-06-18 复旦大学 Capacitor of high-performance metal/insulator/metal structure and preparing method
US7605030B2 (en) 2006-08-31 2009-10-20 Micron Technology, Inc. Hafnium tantalum oxynitride high-k dielectric and metal gates
KR100809336B1 (en) * 2006-10-02 2008-03-05 삼성전자주식회사 Method for fabricating semiconductor device
US8203176B2 (en) 2007-03-08 2012-06-19 Renesas Electronics Corporation Dielectric, capacitor using dielectric, semiconductor device using dielectric, and manufacturing method of dielectric
WO2009002058A2 (en) * 2007-06-25 2008-12-31 Lg Chem, Ltd. Method for manufacturing capacitor of semiconductor
KR100815969B1 (en) 2007-06-26 2008-03-24 주식회사 동부하이텍 Metal insulator metal capacitor and method for manufacture thereof
JP2009059889A (en) 2007-08-31 2009-03-19 Elpida Memory Inc Capacitor and its manufacturing method
JP5133643B2 (en) 2007-09-28 2013-01-30 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP2009135216A (en) 2007-11-29 2009-06-18 Nec Electronics Corp Semiconductor device
JP2009212381A (en) * 2008-03-05 2009-09-17 Fujitsu Microelectronics Ltd Semiconductor device and manufacturing method therefor
KR101417728B1 (en) * 2008-03-12 2014-07-11 삼성전자주식회사 Semiconductor device using a zirconium carbon oxynitride insulation layer and method for manufacturing the same
JP5354944B2 (en) * 2008-03-27 2013-11-27 株式会社東芝 Semiconductor device and field effect transistor
CN102007591A (en) * 2009-01-15 2011-04-06 东京毅力科创株式会社 Capacitor and process for manufacturing capacitor
US8710669B2 (en) * 2009-05-20 2014-04-29 Nec Corporation Semiconductor device manufacture in which minimum wiring pitch of connecting portion wiring layer is less than minimum wiring pitch of any other wiring layer
US8310807B2 (en) 2009-06-12 2012-11-13 Micron Technology, Inc. Capacitors having dielectric regions that include multiple metal oxide-comprising materials
US8236372B2 (en) 2009-06-12 2012-08-07 Micron Technology, Inc. Methods of forming capacitors having dielectric regions that include multiple metal oxide-comprising materials
US8119492B2 (en) 2009-07-10 2012-02-21 United Microelectronics Corp. Dissolving precipates in alloy material in capacitor structure
KR20110064269A (en) * 2009-12-07 2011-06-15 삼성전자주식회사 Semiconductor device and method of fabricating the same, and semiconductor module, electronic circuit board and electronic system including the same
KR200457927Y1 (en) * 2010-02-04 2012-01-12 조정준 Flowerpot stand for self-assembly
JP2012104551A (en) * 2010-11-08 2012-05-31 Elpida Memory Inc Semiconductor storage device, and method of manufacturing the same
JP2013021012A (en) 2011-07-07 2013-01-31 Renesas Electronics Corp Semiconductor device manufacturing method
US9142607B2 (en) 2012-02-23 2015-09-22 Freescale Semiconductor, Inc. Metal-insulator-metal capacitor
TW201546804A (en) * 2014-02-05 2015-12-16 Conversant Intellectual Property Man Inc A DRAM memory device with manufacturable capacitor
JP2015179727A (en) 2014-03-19 2015-10-08 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit device and manufacturing method thereof
JP6294151B2 (en) * 2014-05-12 2018-03-14 東京エレクトロン株式会社 Deposition method
DE102015116495A1 (en) * 2015-09-29 2017-03-30 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor chip and method for producing an optoelectronic semiconductor chip
US9691871B1 (en) * 2015-12-18 2017-06-27 Stmicroelectronics (Crolles 2) Sas Process for forming a layer of equiaxed titanium nitride and a MOSFET device having a metal gate electrode including a layer of equiaxed titanium nitride
US10388721B2 (en) 2017-01-24 2019-08-20 International Business Machines Corporation Conformal capacitor structure formed by a single process
FR3063387B1 (en) 2017-02-24 2021-05-21 Commissariat Energie Atomique ELECTRONIC COMPONENT EQUIPPED WITH A TRANSISTOR AND PROHIBITED FINGERS TO FORM AT LEAST PART OF A CAPACITIVE COMPONENT WITHIN THE ELECTRONIC COMPONENT
CN110366778B (en) * 2017-04-04 2024-04-09 英特尔公司 Thin Film Transistor Embedded Dynamic Random Access Memory
CN109755244B (en) * 2017-11-06 2021-03-23 联华电子股份有限公司 Method for manufacturing embedded word line of dynamic random access memory
US20190259618A1 (en) * 2018-02-19 2019-08-22 Stmicroelectronics (Crolles 2) Sas Process for forming a layer of a work function metal for a mosfet gate having a uniaxial grain orientation
US10629428B2 (en) * 2018-03-09 2020-04-21 Globalfoundries Inc. Metal insulator metal capacitor devices
US11329047B2 (en) 2018-04-18 2022-05-10 Intel Corporation Thin-film transistor embedded dynamic random-access memory with shallow bitline
KR102084608B1 (en) * 2018-04-25 2020-03-04 한국과학기술연구원 Dielectric, semiconductor memory device including the dielectric and methods of manufacturing the same
US11450669B2 (en) 2018-07-24 2022-09-20 Intel Corporation Stacked thin-film transistor based embedded dynamic random-access memory
JP7197311B2 (en) 2018-09-03 2022-12-27 太陽誘電株式会社 Capacitor and capacitor manufacturing method
KR20220004253A (en) * 2020-07-03 2022-01-11 에스케이하이닉스 주식회사 Semiconductor device and method for fabricating the same
JPWO2022038450A1 (en) * 2020-08-19 2022-02-24
TW202210653A (en) * 2020-09-07 2022-03-16 日商半導體能源研究所股份有限公司 Metal oxide film, semiconductor device, and manufacturing method therefor

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5189503A (en) * 1988-03-04 1993-02-23 Kabushiki Kaisha Toshiba High dielectric capacitor having low current leakage
US6100200A (en) * 1998-12-21 2000-08-08 Advanced Technology Materials, Inc. Sputtering process for the conformal deposition of a metallization or insulating layer
US6153460A (en) * 1998-12-28 2000-11-28 Sharp Kabushiki Kaisha Method of fabricating semiconductor memory device
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US6207487B1 (en) * 1998-10-13 2001-03-27 Samsung Electronics Co., Ltd. Method for forming dielectric film of capacitor having different thicknesses partly
US6336049B1 (en) * 1998-07-08 2002-01-01 Nitto Denko Corporation Electrode structure for reducing irritation to the skin
US6420230B1 (en) * 2000-08-31 2002-07-16 Micron Technology, Inc. Capacitor fabrication methods and capacitor constructions
US6423632B1 (en) * 2000-07-21 2002-07-23 Motorola, Inc. Semiconductor device and a process for forming the same
US20020195683A1 (en) * 1999-08-14 2002-12-26 Kim Yeong-Kwan Semiconductor device and method for manufacturing the same
US6509601B1 (en) * 1998-07-31 2003-01-21 Samsung Electronics Co., Ltd. Semiconductor memory device having capacitor protection layer and method for manufacturing the same
US6551399B1 (en) * 2000-01-10 2003-04-22 Genus Inc. Fully integrated process for MIM capacitors using atomic layer deposition
US6580111B2 (en) * 2000-06-07 2003-06-17 Samsung Electronics Co., Ltd. Metal-insulator-metal capacitor
US6596583B2 (en) * 2000-06-08 2003-07-22 Micron Technology, Inc. Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
US6623985B1 (en) * 2000-03-13 2003-09-23 Oki Electric Industry Co., Ltd. Structure of and manufacturing method for semiconductor device employing ferroelectric substance

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1266247A (en) 1985-03-25 1990-02-27 Adrienne A. Tymiak Antibiotic prepared from lysobacter sp. sc 14,067
JP2524862B2 (en) 1990-05-01 1996-08-14 三菱電機株式会社 Semiconductor memory device and manufacturing method thereof
JPH0653408A (en) 1991-09-09 1994-02-25 Hitachi Ltd Mom capacitive element
JPH06151751A (en) 1992-11-13 1994-05-31 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JP3207978B2 (en) 1993-06-28 2001-09-10 康夫 垂井 Capacitor and method of forming the same
JPH0794600A (en) * 1993-06-29 1995-04-07 Mitsubishi Electric Corp Semiconductor device and fabrication thereof
JPH07161934A (en) 1993-12-06 1995-06-23 Hitachi Ltd Semiconductor device and its manufacture
JP3450463B2 (en) 1994-10-24 2003-09-22 株式会社日立製作所 Method for manufacturing semiconductor device
US6407420B1 (en) * 1996-12-20 2002-06-18 Hitachi, Ltd. Integrated circuit device having line width determined by side wall spacer provided in openings formed in insulating film for connection conductors
JPH11177085A (en) 1997-12-08 1999-07-02 Sony Corp Semiconductor device
JP3173451B2 (en) 1998-02-25 2001-06-04 日本電気株式会社 Semiconductor device and manufacturing method thereof
TW383494B (en) 1998-04-21 2000-03-01 United Microelectronics Corp Structure and manufacturing method for capacitors
TW403991B (en) 1998-06-16 2000-09-01 Samsung Electronics Co Ltd Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same
JP3718058B2 (en) * 1998-06-17 2005-11-16 株式会社ルネサステクノロジ Manufacturing method of semiconductor integrated circuit device
KR100275738B1 (en) 1998-08-07 2000-12-15 윤종용 Method for producing thin film using atomatic layer deposition
JP3869128B2 (en) * 1998-09-11 2007-01-17 株式会社ルネサステクノロジ Manufacturing method of semiconductor integrated circuit device
US6207561B1 (en) * 1998-09-29 2001-03-27 Texas Instruments Incorporated Selective oxidation methods for metal oxide deposition on metals in capacitor fabrication
KR100293713B1 (en) 1998-12-22 2001-07-12 박종섭 Method of manufacturing capacitor of memory element
JP2001024170A (en) * 1999-07-13 2001-01-26 Mitsubishi Electric Corp Semiconductor storage device and its manufacture
US6576053B1 (en) * 1999-10-06 2003-06-10 Samsung Electronics Co., Ltd. Method of forming thin film using atomic layer deposition method
SG99871A1 (en) 1999-10-25 2003-11-27 Motorola Inc Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6548343B1 (en) * 1999-12-22 2003-04-15 Agilent Technologies Texas Instruments Incorporated Method of fabricating a ferroelectric memory cell
US6335049B1 (en) * 2000-01-03 2002-01-01 Micron Technology, Inc. Chemical vapor deposition methods of forming a high K dielectric layer and methods of forming a capacitor
US7217615B1 (en) * 2000-08-31 2007-05-15 Micron Technology, Inc. Capacitor fabrication methods including forming a conductive layer
US6486080B2 (en) * 2000-11-30 2002-11-26 Chartered Semiconductor Manufacturing Ltd. Method to form zirconium oxide and hafnium oxide for high dielectric constant materials
JP2002222934A (en) * 2001-01-29 2002-08-09 Nec Corp Semiconductor device and manufacturing method thereof
US6617266B2 (en) * 2001-04-12 2003-09-09 Applied Materials, Inc. Barium strontium titanate annealing process
JP2002314072A (en) * 2001-04-19 2002-10-25 Nec Corp Semiconductor device with high dielectric thin film and manufacturing method therefor, and film-forming method for dielectric film
US6391713B1 (en) * 2001-05-14 2002-05-21 Silicon Integrated Systems Corp. Method for forming a dual damascene structure having capacitors
JP2002343790A (en) 2001-05-21 2002-11-29 Nec Corp Vapor-phase deposition method of metallic compound thin film and method for manufacturing semiconductor device
JP4911838B2 (en) * 2001-07-06 2012-04-04 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7425493B2 (en) * 2002-08-17 2008-09-16 Samsung Electronics Co., Ltd. Methods of forming dielectric structures and capacitors
JP4046588B2 (en) * 2002-10-10 2008-02-13 Ｎｅｃエレクトロニクス株式会社 Capacitor manufacturing method
JP4907839B2 (en) * 2003-03-26 2012-04-04 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP4502189B2 (en) * 2004-06-02 2010-07-14 ルネサスエレクトロニクス株式会社 Thin film forming method and semiconductor device manufacturing method

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5189503A (en) * 1988-03-04 1993-02-23 Kabushiki Kaisha Toshiba High dielectric capacitor having low current leakage
US6336049B1 (en) * 1998-07-08 2002-01-01 Nitto Denko Corporation Electrode structure for reducing irritation to the skin
US6509601B1 (en) * 1998-07-31 2003-01-21 Samsung Electronics Co., Ltd. Semiconductor memory device having capacitor protection layer and method for manufacturing the same
US6207487B1 (en) * 1998-10-13 2001-03-27 Samsung Electronics Co., Ltd. Method for forming dielectric film of capacitor having different thicknesses partly
US6100200A (en) * 1998-12-21 2000-08-08 Advanced Technology Materials, Inc. Sputtering process for the conformal deposition of a metallization or insulating layer
US6153460A (en) * 1998-12-28 2000-11-28 Sharp Kabushiki Kaisha Method of fabricating semiconductor memory device
US20020195683A1 (en) * 1999-08-14 2002-12-26 Kim Yeong-Kwan Semiconductor device and method for manufacturing the same
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US6551399B1 (en) * 2000-01-10 2003-04-22 Genus Inc. Fully integrated process for MIM capacitors using atomic layer deposition
US6623985B1 (en) * 2000-03-13 2003-09-23 Oki Electric Industry Co., Ltd. Structure of and manufacturing method for semiconductor device employing ferroelectric substance
US6580111B2 (en) * 2000-06-07 2003-06-17 Samsung Electronics Co., Ltd. Metal-insulator-metal capacitor
US6596583B2 (en) * 2000-06-08 2003-07-22 Micron Technology, Inc. Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
US6423632B1 (en) * 2000-07-21 2002-07-23 Motorola, Inc. Semiconductor device and a process for forming the same
US6420230B1 (en) * 2000-08-31 2002-07-16 Micron Technology, Inc. Capacitor fabrication methods and capacitor constructions

Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050170665A1 (en) * 2003-04-17 2005-08-04 Fujitsu Limited Method of forming a high dielectric film
US20050153518A1 (en) * 2004-01-09 2005-07-14 Samsung Electronics Co., Ltd. Method for forming capacitor using etching stopper film in semiconductor memory
US8541276B2 (en) 2004-08-31 2013-09-24 Micron Technology, Inc. Methods of forming an insulating metal oxide
US8154066B2 (en) 2004-08-31 2012-04-10 Micron Technology, Inc. Titanium aluminum oxide films
US7592217B2 (en) 2004-11-08 2009-09-22 Hynix Semiconductor Inc. Capacitor with zirconium oxide and method for fabricating the same
US20060097305A1 (en) * 2004-11-08 2006-05-11 Lee Kee-Jeung Capacitor with zirconium oxide and method for fabricating the same
US8084804B2 (en) * 2004-11-08 2011-12-27 Hynix Semiconductor Inc. Capacitor with zirconium oxide and method for fabricating the same
US8062943B2 (en) 2004-11-08 2011-11-22 Hynix Semiconductor Capacitor with zirconium oxide and method for fabricating the same
US20100084740A1 (en) * 2004-11-08 2010-04-08 Lee Kee-Jeung Capacitor with zirconium oxide and method for fabricating the same
US20100047989A1 (en) * 2004-11-08 2010-02-25 Lee Kee-Jeung Capacitor with zirconium oxide and method for fabricating the same
US20110027465A1 (en) * 2004-12-23 2011-02-03 Hynix Semiconductor Inc. Method for forming dielectric film and method for forming capacitor in semiconductor device using the same
US20080138503A1 (en) * 2004-12-23 2008-06-12 Hynix Semiconductor Inc. Method For Forming Dielectric Film And Method For Forming Capacitor In Semiconductor Device Using The Same
US8092862B2 (en) 2004-12-23 2012-01-10 Hynix Semiconductor Inc. Method for forming dielectric film and method for forming capacitor in semiconductor device using the same
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US8399365B2 (en) 2005-03-29 2013-03-19 Micron Technology, Inc. Methods of forming titanium silicon oxide
US8076249B2 (en) 2005-03-29 2011-12-13 Micron Technology, Inc. Structures containing titanium silicon oxide
US20060234500A1 (en) * 2005-04-15 2006-10-19 Park Jong B Method of forming capacitor of semiconductor device by successively forming a dielectric layer and a plate electrode in a single processing chamber
US20060240679A1 (en) * 2005-04-21 2006-10-26 Seung-Hwan Lee Method of manufacturing semiconductor device having reaction barrier layer
US20060281330A1 (en) * 2005-06-14 2006-12-14 Micron Technology, Inc. Iridium / zirconium oxide structure
US20100187589A1 (en) * 2005-07-20 2010-07-29 Kuo-Chi Tu Devices and methods for preventing capacitor leakage
US8501563B2 (en) 2005-07-20 2013-08-06 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US8487361B2 (en) 2005-07-20 2013-07-16 Taiwan Semiconductor Manufacturing Co., Ltd. Devices and methods for preventing capacitor leakage
US20070018224A1 (en) * 2005-07-20 2007-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Devices and methods for preventing capacitor leakage
US7745865B2 (en) * 2005-07-20 2010-06-29 Taiwan Semiconductor Manufacturing Co., Ltd. Devices and methods for preventing capacitor leakage
US8921914B2 (en) 2005-07-20 2014-12-30 Micron Technology, Inc. Devices with nanocrystals and methods of formation
FR2890982A1 (en) * 2005-09-21 2007-03-23 St Microelectronics Sa Formation of a dielectric layer on a carrier material by circulating a metal precursor gas with two stages of oxidation, notably for the realization of a condenser in an integrated circuit
US20070082502A1 (en) * 2005-09-21 2007-04-12 Stmicroelectronics S.A. Method for producing a dielectric layer on a carrier material and an integrated circuit comprising a capacitor incorporating a dielectric layer
US20070077759A1 (en) * 2005-10-05 2007-04-05 Elpida Memory, Inc. Method for forming dielectric film and method for manufacturing semiconductor device by using the same
US7825043B2 (en) 2005-11-28 2010-11-02 Hynix Semiconductor Inc. Method for fabricating capacitor in semiconductor device
US20080014247A1 (en) * 2006-06-30 2008-01-17 Nucryst Pharmaceuticals Metal-containing formulations and methods of use
US7776731B2 (en) * 2007-09-14 2010-08-17 Freescale Semiconductor, Inc. Method of removing defects from a dielectric material in a semiconductor
US20090075434A1 (en) * 2007-09-14 2009-03-19 Junker Kurt H Method of removing defects from a dielectric material in a semiconductor
US20110038094A1 (en) * 2008-04-16 2011-02-17 Renesas Electronics Corporation Capacitor
US20100291763A1 (en) * 2009-05-18 2010-11-18 Hitachi-Kokusai Electric Inc. Method of manufacturing semiconductor device and substrate processing apparatus
TWI416630B (en) * 2009-05-18 2013-11-21 Hitachi Int Electric Inc Method of manufacturing semiconductor device and substrate processing apparatus
KR101110557B1 (en) * 2009-09-08 2012-01-31 주식회사 하이닉스반도체 Semiconductor device and method for forming using the same
US20110057240A1 (en) * 2009-09-08 2011-03-10 Hynix Semiconductor Inc. Semiconductor device and method of manufacturing the same
US20180122810A1 (en) * 2016-11-03 2018-05-03 Samsung Electronics Co., Ltd. Semiconductor device
US10249627B2 (en) * 2016-11-03 2019-04-02 Samsung Electronics Co., Ltd. Semiconductor device
US20190081096A1 (en) * 2017-09-12 2019-03-14 Panasonic Intellectual Property Management Co., Ltd. Capacitor including first electrode, dielectric layer, and second electrode, image sensor, and method for producing capacitor
US11114481B2 (en) * 2017-09-12 2021-09-07 Panasonic Intellectual Property Management Co., Ltd. Capacitor including first electrode, dielectric layer, and second electrode, image sensor, and method for producing capacitor
US12094893B2 (en) 2017-09-12 2024-09-17 Panasonic Intellectual Property Management Co., Ltd. Capacitor including first electrode, dielectric layer, and second electrode, image sensor, and method for producing capacitor
US20190189357A1 (en) * 2017-12-15 2019-06-20 Micron Technology, Inc. Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb
US10650978B2 (en) * 2017-12-15 2020-05-12 Micron Technology, Inc. Methods of incorporating leaker devices into capacitor configurations to reduce cell disturb
US11404217B2 (en) 2017-12-15 2022-08-02 Micron Technology, Inc. Methods of incorporating leaker devices into capacitor configurations to reduce cell disturb, and capacitor configurations incorporating leaker devices
US11676768B2 (en) 2017-12-15 2023-06-13 Micron Technology, Inc. Methods of incorporating leaker devices into capacitor configurations to reduce cell disturb, and capacitor configurations incorporating leaker devices

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US20070152256A1 (en) 2007-07-05
US8212299B2 (en) 2012-07-03
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JP3863391B2 (en) 2006-12-27
CN1228850C (en) 2005-11-23
US8815678B2 (en) 2014-08-26
TW583727B (en) 2004-04-11
US20020190294A1 (en) 2002-12-19
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US20080064147A1 (en) 2008-03-13
KR20020094933A (en) 2002-12-18
DE10226381B4 (en) 2015-08-20
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CN1391283A (en) 2003-01-15
US20140327064A1 (en) 2014-11-06

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