US20040110525A1

US20040110525A1 - Systems and techniques for channel gain computations

Info

Publication number: US20040110525A1
Application number: US10/463,188
Authority: US
Inventors: Peter Black; Nagabhushana Sindhushayana; Raghu Challa; Rashid Attar
Original assignee: Individual
Current assignee: Infineon Technologies AG
Priority date: 2001-12-14
Filing date: 2003-06-16
Publication date: 2004-06-10
Also published as: WO2003052963A1; WO2003052963A9; TW200301046A; US6594501B2; AU2002357235A1; US20030114180A1

Abstract

Systems and techniques for controlling transmission power involve receiving a first to second channel power ratio, receiving a first to second channel power ratio, adjusting the power ratio if a combined power of a plurality of channels exceeds a threshold, the channels including the first and second channels, and computing gain of the first channel as a function of the power ratio.

Description

CROSS REFERENCE

This application is a continuation of Utility application Ser. No. 10/104,208 entitled “SYSTEMS AND TECHNIQUES FOR CHANNEL GAIN COMPUTATIONS” and filed on Mar. 20, 2002, which claims priority to Provisional Application No. 60/340,512, filed Dec. 14, 2001, entitled “Systems and Techniques for Channel Gain Computations” and is assigned to the assignee of the present application.[0001]

BACKGROUND

1. Field

The present invention relates to communications systems, and more specifically, to systems and techniques for controlling transmission power in a wireless communications system.

2. Background

Modern communications systems are designed to allow multiple users to access a common communications medium. Numerous multiple-access techniques are known in the art, such as time division multiple-access (TDMA), frequency division multiple-access (FDMA), space division multiple-access, polarization division multiple-access, code division multiple-access (CDMA), and other similar multi-access techniques. The multiple-access concept is a channel allocation methodology which allows multiple user access to a common communications link. The channel allocations can take on various forms depending on the specific multi-access technique. By way of example, in FDMA systems, the total frequency spectrum is divided into a number of smaller sub-bands and each user is given its own sub-band to access the communications link. Alternatively, in TDMA systems, each user is given the entire frequency spectrum during periodically recurring time slots. In CDMA systems, each user is given the entire frequency spectrum for all of the time but distinguishes its transmission through the use of a code.

In multi-access communications systems, techniques to reduce mutual interference between multiple users are often utilized to increase user capacity. By way of example, power control techniques can be employed to limit the transmission power of each user to that necessary to achieve a desired quality of service. This approach ensures that each user transmits only the minimum power necessary, but no higher, thereby making the smallest possible contribution to the total noise seen by other users. These power control techniques may become more complex in multi-access communications systems supporting users with multiple channel capability. In addition to limiting the transmission power of the user, the allocated power should be balanced between the multiple channels in a way that optimizes performance.

SUMMARY

In one aspect of the present invention, a method of controlling transmission power includes receiving a first to second channel power ratio, adjusting the power ratio if a combined power of a plurality of channels exceeds a threshold, the channels including the first and second channels, and computing gain of the first channel as a function of the power ratio.

In another aspect of the present invention, a computer readable media embodying a method of controlling transmission receives a first to second power ratio, adjusts the power ratio if a combined power of a plurality of channels exceeds a threshold, the channels including the first and second channels, and computes gain of the first channel as a function of the power ratio.

In yet another aspect of the invention, an apparatus including a transmitter gain control configured to receive a first to second channel power ratio, adjust the power ratio if a combined power of a plurality of channels exceeds a threshold, the channels including the first and second channels, compute gain of the first channel as a function of the power ratio, and a transmitter configured to apply the computed gain to the first channel, combine the channels, and apply a second gain to the combined channels.

In a further aspect of the present invention, an apparatus includes means for receiving a first to second power ratio, means for adjusting the power ratio if a combined power of a plurality of channels exceeds a threshold, the channels including the first and second channels, and means for computing gain of the first channel as a function of the power ratio.

It is understood that other aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein is shown and described only exemplary embodiments of the invention, simply by way of illustration. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present invention are illustrated by way of example, and not by way of limitation, in the accompanying drawings in which like reference numerals refer to similar elements: [0012]
FIG. 1 is a simplified functional block diagram of an exemplary CDMA communications system; [0013]
FIG. 2 is a functional block diagram of an exemplary subscriber station adapted for operation in a CDMA communications system; [0014]
FIG. 3 is a functional block diagram an exemplary transmitter gain control and transmitter from the subscriber station of FIG. 2; [0015]
FIG. 4 is a flow chart illustrating an exemplary back off algorithm implemented by the transmitter gain control of FIG. 3; and [0016]
FIG. 5 is a flow chart illustrating an alternative exemplary back off algorithm implemented by the transmitter gain control of FIG. 3.[0017]

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention can be practiced. The term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other embodiments. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the present invention. [0018]
In an exemplary embodiment of a communications system, a power control system can be used to increase the number of users that can be supported by the system. For those users with multi-channel capability, gain computation techniques can be employed to balance the relative transmission power between the channels. The gain computations can be performed through a power estimation process which controls the transmission power for one or more channels. In the event that the total transmission power exceeds the power limitations of the user, a systematic back off procedure can be used to reduce the gain of one or more channels. [0019]
Various aspects of these gain computation techniques will be described in the context of a CDMA communications system, however, those skilled in the art will appreciate that the techniques for gain computation of multiple channels are likewise suitable for use in various other communications environments. Accordingly, any reference to a CDMA communications system is intended only to illustrate the inventive aspects of the present invention, with the understanding that such inventive aspects have a wide range of applications. [0020]
CDMA is a modulation and multiple access scheme based on spread-spectrum communications. In a CDMA communications system, a large number of signals share the same frequency spectrum and, as a result, provide an increase in user capacity. This is achieved by transmitting each signal with a different pseudo-random noise (PN) code that modulates a carrier, and thereby, spreads the spectrum of the signal waveform. The transmitted signals are separated in the receiver by a correlator that uses a corresponding PN code to despread the desired signal=s spectrum. The undesired signals, whose PN codes do not match, are not despread in bandwidth and contribute only to noise. [0021]
FIG. 1 is a simplified functional block diagram of an exemplary CDMA communications system. A [0022] base station controller 102 can be used to provide an interface between a network 104 and all base stations dispersed throughout a geographic region. For ease of explanation, only one base station 106 is shown. The geographic region is generally subdivided into smaller regions known as cells. Each base station is configured to serve all subscriber stations in its respective cell. In some high traffic applications, the cell may be divided into sectors with a base station serving each sector. In the described exemplary embodiment, three subscriber stations 108 a-c are shown in communication with the base station 106. Each subscriber station 108 a-c may access the network, or communicate with other subscriber stations, through one or base stations under control of the base station controller 102.
A power control system can be employed to reduce mutual interference between the multiple subscriber stations. The power control system can be used to limit the transmission power over both the forward and reverse links to that necessary to achieve a desired quality of service. The forward link refers to transmissions from the base station to a subscriber station, and the reverse link refers to transmissions from a subscriber station to the base station. For the purposes of illustration, the gain computation techniques will be described with reference to the reverse link, however, as those skilled in the art will readily appreciate, these gain computation techniques are equally applicable to the forward link. [0023]
The reverse link transmission power is typically controlled with two power control loops. The first power control loop is an open loop control. The open control loop is designed to control the reverse link transmission power as a function of path loss, the effect of base station loading, and environmentally induced phenomena such as fast fading and shadowing. This open control loop estimation process is well known in CDMA communications systems. [0024]
The second power control loop is a closed loop control. The closed loop control has the function of correcting the open loop estimate to achieved a desired signal-to-noise ratio (SNR) at the base station. This can be achieved by measuring the reverse link transmission power at the base station and providing feedback to the subscriber station to adjust the reverse link transmission power. The feedback signal can be in the form of a reverse power control (RPC) command which is generated by comparing the measured reverse link transmission power at the base station with a power control set point. If the measured reverse link transmission power is below the set point, then an RPC up command is provided to the subscriber station to increase the reverse link transmission power. If the measured reverse link transmission power is above the set point, then an RPC down command is provided to the subscriber station to decrease the reverse link transmission power. [0025]
The open and closed loop controls may be used to control the transmission power of various reverse link channel structures. By way of example, in some CDMA communications systems, the reverse link waveform includes a traffic channel to carry voice and data services to the base station and a pilot channel used by the base station for coherent demodulation of the voice and data. In these systems, the open and closed loop controls can be used to control the reverse link power of the pilot channel. In order to optimize performance, the power of the pilot channel can then be balanced with the power of the traffic channel. Specifically, each channel can be spread with a unique orthogonal code generated by using Walsh functions. A gain can then applied to the traffic channel in order to maintain an optimal traffic to pilot channel power ratio. [0026]
This principle can be extended to additional channels in the reverse link waveform. In CDMA communications systems with a variable data rate, for example, a data rate control (DRC) channel containing a DRC message is generally supported by the reverse link transmission. In the variable data rate mode, the data rate of the forward link transmission is dictated by the DRC message. The DRC message is typically based on a carrier-to-interference (C/I) estimation performed at the subscriber station. This approach provides a mechanism for the base station to efficiently transmit the forward link data at the highest possible rate. An exemplary CDMA communications system supporting a variable data rate request scheme is a High Data Rate (HDR) communications system. The HDR communications system is typically designed to conform one or more standards such as the “cdma2000 High Rate Packet Data Air Interface Specification,” 3GPP2 C.S0024, Version 2, Oct. 27, 2000, promulgated by a consortium called “3[0027] ^rdGeneration Partnership Project,” the contents of the aforementioned standard being incorporated by reference herein.
In the described exemplary HDR communications system, the reverse link transmission may also support an acknowledgment (ACK) channel. The ACK channel is used to indicate to the base station that the subscriber station has successfully decoded a packet received over the forward link. This can be achieved by sending an ACK message over the ACK channel. [0028]
In these HDR communications systems, the power of the pilot channel can also be balanced with the power of the DRC and ACK channels. This process involves spreading each of the DRC and ACK channels with a unique orthogonal code generated by using Walsh functions. A DRC gain can then be applied to the DRC channel to maintain an optimal DRC to pilot channel power ratio. Similarly, an ACK gain can also be applied to the ACK channel to maintain an optimal ACK to pilot channel power ratio. [0029]
A functional block diagram of an exemplary subscriber station operating in an HDR communications system is shown in FIG. 2. The exemplary subscriber station includes a receiver and a transmitter both coupled to an [0030] antenna 202. The receiver includes an RF front end 204, a demodulator 206 and a decoder 208. The transmitter includes an encoder 209, a modulator 210, and shares the RF front end 204 with the receiver. The transmitter also includes a transmitter gain control 214 to control the reverse link transmission power in a manner to be discussed in greater detail later.
The RF [0031] front end 204 is coupled to the antenna 202. The receiver portion of the front end 204 downconverts, filters, amplifies and digitizes a signal received by the antenna 202. The receiver portion of the RF front end 204 also includes an AGC (not shown) to maximize the dynamic range of the digitized signal. The AGC can be utilized by the transmitter gain control 214 to compute the path loss between the base station and the subscriber station during the open loop power control estimation. The digitized signal from the receiver portion of the RF front end 204 can then be coupled to the demodulator 206 where it is quadrature demodulated with short PN codes, decovered by Walsh codes, and descrambled using a long PN code. The demodulated signal can then be provided to the decoder 208 for forward error correction. The demodulator 206 can also be used to extract the RPC command from the reverse link transmission and provide it to the transmitter gain control 214 for closed loop power control computations.
The transmitter includes the [0032] encoder 209 which typically provides convolution coding and interleaving of the reverse link traffic channel. The encoded traffic channel is provided to the modulator 210 where it is spread with a Walsh cover and amplified by a traffic channel gain (G_T) computed by the transmitter gain control 214. The pilot channel, DRC channel, and ACK channel are also provided to the modulator 210 where they are each spread with a different Walsh cover and amplified by respective channel gains (G_P), (G_D), and (G_A) computed by the transmitter gain control 214. The channels are then combined, spread with a long PN code and quadrature modulated with short PN codes. The quadrature modulated signal is provided to the transmitter portion of the RF front end 204 where it is upconverted, filtered, and amplified for over the air forward link transmission through the antenna 202. The amplification of the quadrature modulated signal in the transmitter portion of the RF front end 204 is controlled by an AGC signal from the transmitter gain control 214.
A functional block diagram of an exemplary [0033] transmitter gain control 214, modulator 210 and transmitter portion of the RF front end 204 is shown in FIG. 3. The transmitter gain control 214 includes a power and gain computation block 302 for computing the gains for the pilot, traffic, DRC, and ACK channels. The gain computations are based on predetermined power ratios for the traffic, DRC and ACK channels with respect to the pilot channel. A feedback loop can be used to reduce the channel gains under power limiting conditions by “throttling” or “backing off” the predetermined power ratios for the DRC and ACK channels. The feedback loop includes a limiter 304 and a power throttle block 306. The limiter 304 determines whether the total reverse link transmission power resulting from the predetermined power ratios exceeds the maximum power capability of the transmitter. The maximum power capability of the transmitter is limited by a variable gain amplifier (VGA) 308 and a power amplifier (not shown) in the RF front end 204. In the described exemplary embodiment, the power and gain computation block 302 also computes the total reverse link transmission power based on the predetermined power ratios and the estimated reverse link power for the pilot channel. If the resultant total reverse link transmission power exceeds the power capability of the transmitter; the power throttle block 306 is used to back off the power ratios for the DRC and ACK channels in a manner to be described in greater detail later.
The [0034] transmitter gain control 214 can be implemented with a variety of technologies including, by way of example, embedded communications software. The embedded communications software can be run on a programmable digital signal processor (DSP). Alternatively, the transmitter gain control 214 can be implemented with a general purpose processor running a software program, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof.
In the described exemplary embodiment, the power ratios for the traffic, DRC and ACK channels with respect to the pilot channel can be used to compute the channel gains. Accordingly, computational complexity can be reduced if the appropriate power ratios are first determined using the feedback loop before the gain computations are made. As explained above, the feedback loop is used to “throttle” or “back off” the predetermined power ratios of the DRC and ACK channels with respect to the pilot channel if the total reverse link transmission power exceeds the maximum power capability of the transmitter. The total reverse link transmission power can be computed by solving the following equation: [0035]
Total Power=Pilot Channel Power+10 log₁₀(1+P _T+β_D □P _D +βA □P _A) (1)
where: P[0036] _Tis the traffic to pilot channel power ratio;
P[0037] _Dis the DRC to pilot channel power ratio;
β[0038] _Dis a value used to back off the DRC power ratio;
P[0039] _Ais the ACK to pilot channel power ratio; and
β[0040] _Ais a value used to back off the ACK power ratio.
The “Pilot Channel Power” is estimated by two power control loops. An [0041] open loop control 310 generates an estimate of the required transmission power on the pilot channel based on the average value of the AGC from the receiver. The open loop estimate can then be computed by means well known in the art for nominal base station loading and Effective Radiated Power (ERP). Information about variations from the nominal base station loading and ERP can be communicated from the base station to the subscriber station and used to adjust the open loop estimate by means well known in the art.
A closed [0042] loop control 312 can be used to increment or decrement the current closed loop estimate based on the RPC commands recovered from the demodulator. The resultant closed loop estimate is summed with the open loop estimate by a summer 314. The sum of the open and closed loop estimates yields the total reverse link power for the pilot channel. This sum is provided to the power and gain computation block 302 where it is used as the “Pilot Channel Power” in equation (1).
The traffic to pilot channel power ratio P[0043] _Tcan be computed in a variety of fashions. In at least one embodiment, the traffic to pilot channel power ratio can be predetermined for each data rate supported by the reverse link transmission either by empirical analysis, simulation, experimentation, or any other means to achieve a desired quality of service. By way of example, in at least one simulation it has been shown that for a 9.6 k data rate, the traffic to pilot channel ratio should be between −2.25 db and 9 dB. If the data rate is increased to 38.4 k, the traffic to pilot channel power ratio should be between 3.75 dB and 15 dB. Those skilled in the art will readily be able to determine the appropriate traffic to pilot channel power ratio values for all data rates supported by their particular application. These predetermined power ratio values can be stored at the base station and transmitted to each subscriber station in its respective cell or sector over a forward link control channel. Alternatively, the predetermined power ratio values can be stored or computed at the subscriber station.
The DRC to pilot channel power ratio P[0044] _Dand the ACK to pilot channel ratio P_Acan also be computed in a variety of fashions. Similar to the traffic to pilot channel power ratio, the DRC and ACK power ratios can be predetermined either by empirical analysis, simulation, experimentation, or any other means to achieve a desired quality of service. In at least one embodiment of the exemplary HDR communications system, the DRC to pilot channel power ratio can take on values between −9 dB and 6 dB in 1 dB increments and the ACK to pilot channel power ratio can take on values between −3 dB and 6 dB also in 1 dB increments. These predetermined power ratio values can be stored at the base station and transmitted to each subscriber station in its respective cell or sector over the control channel. Alternatively, the predetermined power ratio values can be stored or computed at the subscriber station.
To compute the total reverse link transmission power from equation (1), the channel power ratio values can be converted into the linear domain as follows: [0045]
P _T=10^{(Traffic Power Ratio Value/10)} (2)
P _D=10^{(DRC Power Ratio Value/10)} (3)
P _A=10^{(ACK Power Ratio Value/10)} (4)
The [0046] power throttle block 306 is used to reduce the power ratios for the DRC and ACK channels under power limiting conditions. The power throttle block 306 can accomplish this by generating values β_Dand β_Aand feeding them back to the power and gain computation block 302 for scaling the DRC and ACK power ratios, respectively. The DRC and ACK values can be expressed in the linear domain respectively as:
β_D=10^{(−DRCbackoff/10)} (5)
β_A=10^{(−ACKbackoff/10)} (6)
From the above equations, one skilled in the art will readily appreciate that a 1 dB reduction in the DRC to pilot channel power ratio can be achieved by setting “DRCbackoff” in equation (5) to 1. A 2 dB reduction in the ACK to pilot channel power ratio can be achieved by setting “ACKbackoff” in equation (6) to 2. Thus, any incremental reduction scheme can be implemented depending on the particular design parameters and the specific communications application. [0047]
In the described exemplary embodiment, the “Total Power” in equation (1) is initially computed by the power and gain [0048] computation block 302 with the values β_Dand β_Aset to 1 so that the power ratios for each channel are set to their predetermined, optimal or desired values. The computed “Total Power” is provided to the limiter 304. The limiter 304 compares the computed “Total Power” to the maximum power capability of the transmitter. If the computed “Total Power” exceeds the power limitations of the transmitter, then the reverse link data rate can be lowered to reduce the total reverse link transmission power. In response to the reduced data rate, the power and gain computation block 302 selects a new predetermined traffic to pilot channel power ratio corresponding to the reduced data rate. The “Total Power” can then be recomputed by the power and gain computation block 302 and provided to the limiter 304 for comparison with the maximum power capability of the transmitter. This procedure continues until the computed “Total Power” comes within the power capability of the transmitter or the reverse link data rate is reduced to the lowest data rate supported by the communications system.
In the event that the “Total Power” computed by the power and gain [0049] computation block 302 exceeds the maximum power capability of the transmitter at the lowest data rate supported by the communications system, the limiter 304 can be used to ratchet the closed loop control 312 such that RPC up commands are ignored. This can be achieved by holding the current closed loop estimate constant in response to an RPC up command and reducing the current closed loop estimate in response to an RPC down command. In some embodiments, ratcheting can be supported at both ends of the transmitter power level such that RPC down commands are ignored if the reverse link transmission power is below a minimum operating threshold.
The [0050] limiter 304 also enables the power throttle block 306 to implement a “back off” algorithm to adjust the values β_Dand β_Ato systematically reduce the power ratios for one or both of the DRC and ACK channels until the “Total Power” computed by the power and gain computation block is within the maximum power capability of the transmitter. The manner in which the values β_Dand β_Aare reduced and the resultant incremental reduction in the power ratios of the channels may vary depending on the system application and the overall design constraints.
A flow chart illustrating an exemplary back off algorithm is shown in FIG. 4. Initially, the limiter is used to enable the back off algorithm in [0051] step 402. Once the back off algorithm is enabled, a DRC power loop 404 is entered into. In the DRC power loop 404, the DRC to pilot channel power ratio can backed off by 1 dB in step 406. This can be achieved by recomputing the DRC value β_Dwith the “DRCbackoff” in equation (5) at 1. Alternatively, the “DRCbackoff” in equation (5) can be set to any value to achieve a desired reduction in the DRC to pilot channel power ratio. In any event, the recomputed DRC value β_Dcan be fed back to the to the power and gain computation block. The “Total Power” can then be recomputed and provided to the limiter to determine whether the total reverse link transmission power is within the maximum power capability of the transmitter.
In [0052] step 408, the results from the limiter are provided to the gain throttle block. If the recomputed “Total Power” is within the maximum power capability of the transmitter, the power throttle block is disabled in step 410. Conversely, if the recomputed “Total Power” still exceeds the maximum power capability of the transmitter, then the power throttle block determines whether the DRC channel remains in the “on” state in step 412. The DRC channel is determined to be in the “on” state if the DRC β_Dis greater than 0, or some other minimum threshold value. If the DRC channel remains in the “on” state, then the algorithm loops back to step 406 and reduces the DRC to pilot channel power ratio another dB by setting the “DRCbackoff” in equation (5) to 2 which will result in a 2 dB reduction in the DRC to pilot channel ratio. The back off algorithm remains in the DRC power loop 404 until either the power throttle block is disabled in step 410 or the DRC value β_Dis reduced below the minimum threshold. Should the DRC value β_Dbe reduced below the minimum threshold, then the back off algorithm exits the DRC power gain loop 404 and enters an ACK power loop 416.
In the [0053] ACK power loop 416, the ACK to pilot channel power ratio can backed off by 1 dB in step 418. This can be achieved by recomputing the ACK value PA with the “ACKbackoff” in equation (6) at 1. Alternatively, the “ACKbackoff” in equation (6) can be set to any value to achieve a desired reduction in the ACK to pilot channel power ratio. In any event, the recomputed ACK value β_Acan be fed back to the to the power and gain computation block. The “Total Power” can then be recomputed and provided to the limiter 304 to determine whether the total reverse link transmission power is within the maximum power capability of the transmitter.
In [0054] step 420, the results from the limiter are provided to the gain throttle block. If the recomputed “Total Power” is within the maximum power capability of the transmitter, the power throttle block is disabled in step 424. Conversely, if the recomputed “Total Power” still exceeds the maximum power capability of the transmitter, then the power throttle block determines whether the ACK channel remains in the “on” state. The ACK channel is determined to be in the “on” state if the ACK value β_Ais greater than 0, or some other minimum threshold value. If the ACK channel remains in the “on” state, then the algorithm loops back to step 418 and reduces the ACK to pilot channel power ratio another dB by setting the “ACKbackoff” in equation (6) to 2 which will result in a 2 dB reduction in the ACK to pilot channel ratio. The back off algorithm remains in the ACK power loop 416 until either the power throttle block is disabled by the limiter in step 424 or the ACK value β_Ais reduced below the minimum threshold. Should the ACK value β_Abe reduced below the minimum threshold, then the back off algorithm is disabled by exiting the ACK power loop in step 424. In that event, other power reduction techniques can be employed to bring the total reverse link transmission power within the maximum power capability of the transmitter.
The exemplary embodiment of the back off algorithm described in connection with FIG. 4 may be computationally intensive depending on the predetermined power ratios for the DRC and ACK channels. By way of example, if the predetermined power ratios for the DRC and ACK channels are each set to the 6 dB maximum, there is a possibility that [0055] 16 passes through the DRC power loop and 10 passes through the ACK power loop might be required to back off the DRC and ACK power ratios. To reduce the potential computational complexity, an alternative back off algorithm may be implemented that computes the DRC value β_Din a single step, and if necessary, computes the ACK value β_Ain a single step. This can be achieved in a variety of ways. By way of example, equation (1) can be manipulated to solve for the value of interest by defining a total power to pilot channel power ratio and setting it to a value relating to the maximum power capability of the transmitter. This can be achieved by rewriting equation (1) in the linear domain as:
R=1+P _T +P _D +P _A (7)
R _M≧1+P _T+β_D □P _D+β_A □P _A (8)
where R represents the total power to pilot channel power ratio before enabling the back off algorithm, and R[0056] _Mis the maximum allowed value of R after computing the values β_Dand β_A.
A flow chart illustrating an exemplary algorithm utilizing equations (7) and (8) is shown in FIG. 5. In [0057] step 502, the total power to pilot channel power ratio R is computed. The computed power ratio is then compared to the maximum allowable total power to pilot channel power ratio R_Min step 504. If R≦R_M, then the DRC and ACK power ratios do not require back off. In that event, the values β_Dand β_Aare set to 1 by the power throttle block and fed back to the power and gain computation block in step 506. Conversely, if R is greater than R_M, the DRC value β_Dcan then be computed in step 508.
The DRC value β[0058] _Dcan be computed by setting the ACK value β_Ato 1 and solving for the DRC value β_Din equation (8). With the ACK value β_Aset to 1, equation (8) can be rewritten as:
β_D=(R _M−1−P _T −P _A)/P _D (9).
In [0059] step 510, the resultant DRC value computation is examined to determine whether it is positive. If β_D≧0, then the computed DRC value β_Dwill reduce the DRC to pilot channel power ratio to a level that will result in a “Total Power” computation within the maximum power capability of the transmitter. In that event, the ACK value β_Ais set to land fed back along with the computed DRC value β_Dto the power and gain computation block in step 512. Conversely, if the DRC value β_Dis negative, then the DRC channel is gated off by setting the DRC value β_Dto 0 in step 514.
Once the DRC channel is gated off, the ACK valve β[0060] _Avalue can be computed in step 516. The ACK value β_Acan be computed by setting the DRC value β_Dto 0 and solving for the ACK value β_Ain equation (8). With the DRC value β_Dset to 0, equation (8) can be rewritten as:
β_A=(R _M−1−P _T)/P _A (10).
In [0061] step 518, the resultant ACK value computation is examined to determine whether it is positive. If β_A≧0, then the computed ACK value β_Awill reduce the ACK to pilot channel power ratio to a level that will result in a “Total Power” computation by the power and gain computation block within the maximum power capability of the transmitter. In that event, the DRC value β_Dis set to 0 and fed back along with the computed ACK value β_Ato the power and gain computation block in step 520. Conversely, if the ACK value β_Ais negative, then the ACK channel is gated off by setting the ACK value β_Ato 0 in step 522.
Regardless of the back off algorithm implemented by the [0062] power throttle block 306, the power and gain computation block 302 will compute the gains for the traffic, DRC, ACK and pilot channels once the limiter 304 determines that the total reverse link transmission power is within the maximum power capability of the transmitter. Since the gains will be applied to their respective channels in the digital domain, it is advantageous to scale the gains to prevent an increase in the number of bits as the gain adjusted channels are added together in the modulator. This can be accomplished by setting the gains such that the sum of their squares equals 1 as follows:
G _P ² +G _T ² +G _D ² +G _A ²=1 (10)
Equation (10) can be resolved as follows for each channel gain: [0063]
G _p =1/{square root}{square root over (1+P _T +β _D ·P _D+β_A ·P _A)} (11)
G _T ={square root}{square root over (P_T)}/{square root}{square root over (1+P _T+β_D ·P _D +β _A ·P _A)} (12)
G _D ={square root}{square root over (β_D·P_D)}/{square root}{square root over (1 +P _T+β_D ·P _D+β_A P _A)} (13)
G _A ={square root}{square root over (β_A·P_A)}/{square root}{square root over (1 +P _T+β_D ·P _D+β_A P _A)} (14)
Referring back to FIG. 3, the channel gains computed by the power and gain [0064] computation block 302 can be coupled to the modulator 210. The modulator 210 includes a mixer 316 b which is used to spread the encoded traffic channel from the encoder with a Walsh function. The pilot, DRC and ACK channels are also provided to mixers 316 a, 316 c, and 316 d, respectively, where they are each spread with a different Walsh cover. The Walsh covered traffic, pilot, DRC and ACK channels are provided to gain elements 318 a-d, respectively, where their respective gains computed by the power and gain computation block 306 are applied. The output of the gain elements 318 a-d are provided to a summer 320 where they are combined with the pilot channel. The combined channels are then coupled to a mixer 322 where they are spread using the long PN code. The spread channels are then split into a complex signal having an in-phase (I) component and a quadrature phase (Q) component. The complex signal is quadrature modulated with the short PN codes by mixers 324 a and 324 b before being output to the transmitter portion of the RF front end 204.
A [0065] complex baseband filter 326 is positioned at the input to the RF front end 204 to reject out of band components of the quadrature modulated signal. The filtered complex signal is provided to quadrature mixers 328 a and 328 b where it is modulated onto a carrier waveform before being combined by a summer 330. The combined signal is then provided to the VGA 308 to control the power of the reverse link transmission through the antenna. An AGC signal from the power and gain computation block 302 is used to set the gain of the of the VGA 308. The AGC signal is based on the “Total Power” computed by the power and gain computation block 302 from equation (1).
Those skilled in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and algorithms have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention. [0066]
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. [0067]
The methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal. [0068]
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. [0069]

Claims

What is claimed is:

1. A method for reducing power ratios of a data rate control (DRC) channel and an acknowledgment (ACK) channel, comprising:

enabling a DRC power loop, wherein a DRC backoff value is reduced to incrementally reduce a DRC to pilot channel power ratio if a total power of traffic channels exceeds a maximum power capability of a transmitter; and

enabling a ACK power loop if the DRC backoff value is below a minimum threshold, wherein an ACK backoff value is reduced to incrementally reduce an ACK to pilot channel power ratio if the total power of traffic channels exceeds the maximum power capability of the transmitter.

2. Apparatus for reducing power ratios of a data rate control (DRC) channel and an acknowledgment (ACK) channel, comprising:

means for enabling a DRC power loop, wherein a DRC backoff value is reduced to incrementally reduce a DRC to pilot channel power ratio if a total power of traffic channels exceeds a maximum power capability of a transmitter; and

means for enabling a ACK power loop if the DRC backoff value is below a minimum threshold, wherein an ACK backoff value is reduced to incrementally reduce an ACK to pilot channel power ratio if the total power of traffic channels exceeds the maximum power capability of the transmitter.

3. A method for reducing power ratios of a data rate control (DRC) channel and an acknowledgment (ACK) channel, comprising:

computing a total power to pilot channel power ratio R;

comparing the ratio R to a maximum allowable total power to pilot channel power ratio R_M;

if R≦R_M, then:

setting a DRC backoff value and an ACK backoff value to 1; and

refraining from reducing a DRC power ratio and an ACK power ratio;

if R>R_M, then:

computing a new DRC backoff value;

determining whether the new DRC backoff value is positive or negative;

if the new DRC backoff value is positive, then:

setting a new ACK backoff value to 1;

using the new DRC backoff value and the new ACK backoff value to reduce the DRC power ratio;

if the new DRC backoff value is negative, then:

gating off the DRC channel;

computing a new ACK backoff value; and

using the new ACK backoff value to reduce the ACK power ratio.

4. Apparatus for adjusting power ratios of a data rate control (DRC) channel and an acknowledgment (ACK) channel, comprising:

a power and gain computation block means for computing a total power to pilot channel power ratio R;

a limiter means for comparing the ratio R to a maximum allowable total power to pilot channel power ratio R_M; and

a power throttle block means for implementing a power control algorithm, wherein the algorithm is for determining: