US20020064931A1 - Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure - Google Patents
Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure Download PDFInfo
- Publication number
- US20020064931A1 US20020064931A1 US09/609,626 US60962600A US2002064931A1 US 20020064931 A1 US20020064931 A1 US 20020064931A1 US 60962600 A US60962600 A US 60962600A US 2002064931 A1 US2002064931 A1 US 2002064931A1
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- United States
- Prior art keywords
- ball
- grid
- coating
- solder balls
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0379—Stacked conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
Definitions
- the present invention is in the field of semiconductor and printed-circuit-board (PCB) manufacturing including surface mount technologies (SMT), and pertains more particularly to methods and apparatus for applying protective coatings to structures meant for connection by BGA techniques.
- PCB printed-circuit-board
- SMT surface mount technologies
- BGA Ball-Grid-Array
- BGA technology provides several advantages over more mainstream technologies such as Fine-Pitch-Technology (FTP), and Pin-Grid-Array (PGA).
- FTP Fine-Pitch-Technology
- PGA Pin-Grid-Array
- One obvious advantage is that there are no leads that can be damaged during handling.
- Another obvious advantage is that the solder balls are typically self-centering on die pads. Still other advantages are smaller size, better thermal and electrical performances, better package yields, and so on.
- a non-conductive material such as a nitride layer.
- the die pads are exposed through the nitride layer by means of chemical etching, or by other known methods.
- the protective nitride layer is intended to protect the substrates from contaminants and damage.
- One problem with prior-art protective coatings such as a nitride layer is that it is ultra-thin and does not offer any protection to the die pads themselves nor to the connection points between solder balls in the die pads.
- an additional protective coating such as a protective polymer-based coating
- a protective polymer-based coating would offer a measure of protection not provided with prior-art coatings.
- die pads and soldered connections may also benefit logically from protection.
- a unique application process must be conceived. It is to such a process that the method and apparatus of the present invention is directed.
- a coating mold for forming a protective coating on a ball-grid-array assembly having solder balls extending above a base surface of the ball-grid-array assembly comprising a first portion having a substantially flat area for supporting the ball grid array assembly on a back surface; a second portion having a substantially flat compliant layer; an injection port passing through one or the other of the first and second portions; a vacuum pumping port passing through one or the other of the first and second portions; and a sealing mechanism for sealing the first portion to the second portion, enclosing the ball-grid-array assembly.
- the mold is characterized in that with the first portion closed on the second portion the compliant layer contacts the solder balls of the ball grid array, and a space is formed between the second portion and the base surface of the ball-grid-array.
- the sealing mechanism is an o-ring. Also in some embodiments there is a clamping or bolting mechanism for keeping the mold closed in process.
- the compliant layer is a flexible polymer material.
- a method for applying a protective coating to a ball-grid-array assembly having solder balls extending above a base surface comprising steps of (a) placing the ball-grid-array assembly, including solder balls, into a coating mold having a first surface for supporting the ball-grid-array assembly on a back surface and a second portion having a substantially flat compliant layer; (b) closing and sealing the mold such that the compliant layer contacts the balls of the ball grid array, leaving a space between the compliant layer and the base surface of the ball-grid -array assembly; (c) creating a vacuum in the space formed in step (b); (d) injecting a polymer-based coating into the space formed; and (e) curing the polymer material, such that, when opened the ball-grid-array assembly is coated while leaving an upper portion of each of the solder balls exposed.
- the mold closes on an o-ring seal.
- a method for providing a protective polymer coating to a ball-grid-array assembly, before placing solder balls on the die pads of the assembly comprising the steps of (a) overcoating the assembly with a polymer material; and (b) opening each die pad area to the die pad through the polymer material by a removal process to expose the die pads for placement of the solder balls.
- the removal process comprises laser machining.
- the removal process comprises chemical etching, and in yet another embodiment the removal process comprises physical etching.
- a method for providing a protective polymer coating to a ball-grid-array assembly, before placing solder balls on the die pads of the assembly comprising the steps of (a) screen printing photoresist onto the ball-grid-array assembly; (b) masking the ball-grid-array assembly to protect areas of photoresist over the die pads; (c) developing and removing the photoresist exposed through the mask, leaving the photoresist over the die pads as protective photoresist islands; (d) applying a protective coat to the ball-grid-array assembly to the thickness of the photoresist coating; and (e) developing and removing the remaining photoresist islands to expose the underlying die pads.
- a method for protecting and strengthening a ball-grid-array assembly having solder balls extending above a base surface comprising steps of (a) applying a protective material layer over the solder balls to a level at or above the level of the top of the solder balls, providing thereby a new upper surface for the assembly; (b) removing a portion of the new upper surface to an extent that a portion of each of the original solder balls is exposed as a flat region in a planar upper surface; and (c) applying new solder material over each of the flat exposed solder ball regions.
- step (b) removal is by machining.
- the protective material may be applied in a number of different ways, such as by screening, spraying, or dispense and spinning. There may also be an additional step for reflowing the new solder material.
- BGA Ball-Grid-Array
- FIG. 1A is a perspective view of a wafer with die pads according to prior art.
- FIG. 1B is an expanded and broken view of the wafer of FIG. 1A illustrating a die-pad exposed through a nitride coating.
- FIG. 2 is a broken view of a BGA assembly with a protective overcoat according to an embodiment of the present invention.
- FIG. 3A is a plan view of the wafer of FIG. 2 with a protective overcoat applied as a first step according to an embodiment of the present invention.
- FIG. 3B is a plan view of the coated wafer of FIG. 3A with coated areas removed in areas to expose the die pads.
- FIG. 3C is a plan view of the coated wafer of FIGS. 3A and 3B with solder balls in place according to a third step.
- FIG. 4 is a process diagram illustrating processing steps a through e for coating and creating die pad openings according to another embodiment of the present invention.
- FIG. 5A is a section view of a vacuum enhanced coating apparatus for applying a protective overcoat to a BGA assembly according to a preferred embodiment of the present invention.
- FIG. 5B is a detailed view of a portion of FIG. 5A.
- FIG. 1A is a idealized perspective view of a coated wafer 9 with die pads 11 according to the prior art art.
- wafer 9 is coated with a thin, protective layer that is nonconductive, such as a nitride layer 13 .
- Die pads 11 are illustrated in an array on wafer 9 .
- die pads 11 are nitride coated along with wafer 9 , which may be a rectangular substrate instead of an actual wafer. After nitride coating, die pads 11 are exposed by such as an etching process.
- FIG. 1B is an expanded and broken view of one pad 11 of FIG. 1A, shown in perspective, illustrating the pad exposed through the nitride layer.
- a die pad 11 can be seen recessed beneath the thickness of nitride coating 13 . It is noted herein, that die pad 11 is completely exposed, meaning that there is no protective layer above any of the land occupied by die pad 11 .
- a solder ball (not shown) is placed on die pad 11 , certain real estate of die pad 11 along with the soldered area between the ball and die pad 11 will be exposed, and therefore vulnerable to damage and contamination.
- a goal of the present invention is to provide a process that according to various embodiments, which are described in enabling detail below, may be used to successfully apply a protective coating layer in addition to the standard hard protective layer such as the nitride layer described above.
- FIG. 2 is a broken view of a portion of a BGA assembly 14 with a protective overcoat 17 according to an embodiment of the present invention.
- BGA assembly 14 exhibits 2 die pads 11 having solder balls 15 adhered thereto.
- a protective coating 17 is, in a preferred embodiment, a polymer-based coating such as a polyamide coating. In other embodiments, other polymer-based coatings may be used such as are known in the art and available to the inventor.
- This example illustrates a preferred embodiment, wherein protective coating 17 coats the substrate and the normally exposed area of each die pad 11 around solder balls 15 and also around the perimeter of each solder ball 15 .
- a nitride coating 13 which is illustrated in FIGS. 1A and B, is illustrated here as coating the substrate portion of assembly 14 with the coating extending up over the attached die pads. It may be assumed herein, that a portion of coating 13 has been removed by any one of several known methods in order to clear to an appropriate area on the upper surf aces of each die pad 11 for placement and reflow of solder balls 15 .
- Protective coating 17 is illustrated as over coating nitride layer 13 and encompassing the lower peripheral areas of solder balls 15 .
- a height dimension D illustrates the thickness of coating 17 , which may be anywhere from 1 to 3 mils thick in a preferred embodiment. Overcoat 17 functions to protect any exposed pad areas as well as a portion of solder balls 15 .
- FIG. 3A is a plan-broken view of wafer 14 of FIG. 2 with a protective overcoat applied as a first step according to an embodiment of the present invention.
- FIG. 3B is a plan-broken view of coated wafer 14 of FIG. 3A undergoing a process to expose covered die pads in a second step.
- FIG. 3C is a plan-broken view of coated wafer 14 of FIGS. 3A and 3C with solder balls in place according to a third step.
- the examples of FIGS. 3A, 3B, and 3 C illustrate a general 3-part process for the over coating wafer 14 , removing material to expose die pads, and then screening the solder balls into place for a re-flow operation.
- wafer 14 is illustrated with protective coating 17 already applied. It may be assumed herein, although not specifically illustrated, that die pads 11 of FIG. 2 and nitride coating 13 of FIG. 2 are present on wafer 14 before application of protective coating 17 .
- Coating 17 in a first step completely covers die pads 11 and nitride coating 13 .
- Coating 17 may be a Polyamide coating or a similar polymer-based coating as described above. Coating 17 may be applied by any one of several processes, such as by vacuum deposition process, a spin-on process, or by virtue of other known methods.
- protective coating 17 is partially removed over the land areas above each die pad attached to wafer 14 .
- This process may be a laser process, a plasma-etch process, or a chemical-etch process.
- a mask is used to protect portions of coating 17 not covering die pads. These portions are represented herein by element number 19 . Areas where material has been removed are represented herein by element number 21 . Once die pads are exposed, they are ready to accept solder balls.
- wafer 14 is illustrated with solder balls 15 screened in place and ready to be re-flowed onto the associated die pads.
- a re-flow process uses heat to effect the solder connections between balls 15 and associated die pads.
- the process described above with respect to FIGS. 3 A- 3 C may be used to according to one embodiment, to protect any BGA assembly.
- FIG. 4 is a process diagram illustrating processing steps a through e for coating and creating die pad openings according to another embodiment of the present invention.
- wafer 14 is coated with a photoresist coating represented herein by element number 23 .
- a photoresist coating represented herein by element number 23 .
- die pads ( 11 ) and a standard nitride layer ( 13 ) are present in this step.
- This photoresist process may be accomplished using a standard screen-printing technique. It is noted herein that photoresist 23 is applied before applying a protective coating ( 17 ).
- step b a masking technique is used to cover areas of photoresist that are directly over die pads ( 11 ).
- resist islands are formed as represented by element number 25 in this step. Resist islands 25 are present areas of photoresist left directly over die pads ( 11 ) after developing.
- step c protective coating 17 is applied at substantially the same thickness as photoresist 25 .
- This process of coating fills in the areas inbetween resist islands 25 , such areas representing real estate of wafer 14 not occupied by a die pad ( 11 ).
- step d a second masking technique is used to protect the areas coated with protective coating 17 in step c.
- resist islands 25 are chemically developed, and then etched away exposing associated die pads ( 11 ) leaving all other real estate untouched.
- step e solder balls 15 are screened in place over die pads ( 11 ) as described with reference to FIG. 3C.
- a re-flow operation to permanently attach solder balls 15 to die pads ( 11 ) may begin.
- FIG. 4 illustrates a process for applying protective coating 17 according to yet another embodiment of the present invention.
- FIG. 5A is a section view of a vacuum-application and coating apparatus 27 for applying protective overcoat 17 to a BGA assembly according to a preferred embodiment of the present invention.
- Vacuum-application and coating apparatus 27 hereinafter referred to as simply apparatus 27 , is provided and adapted to enable an automated coating process to be performed on a BGA assembly after re-flow.
- Apparatus 27 comprises an upper plate 29 , a lower plate 31 , and a vacuum seal 33 .
- both plate 29 and 31 are manufactured of stainless-steel or other durable metals. Plates 29 and 31 may be circular, or rectangular in shape. Other shapes may be employed as well.
- a BGA assembly 32 In operation a BGA assembly 32 , with solder balls in place, is enclosed by plate 29 and 31 fitted together using a seal 33 . It may be assumed herein that either plate 29 or plate 31 has an o-ring-style groove provided on its mating surface, generally around the perimeter, such that seal 33 may be properly retained and facilitated. In one embodiment, both mating surfaces of plates 29 and 31 may be grooved to facilitate seal 33 . In still another embodiment, a metallic sealing apparatus may be used instead of an o-ring.
- Plate 29 and 31 are fitted together over seal 33 to form apparatus 27 , and the plates may be held together by any of several methods, such as by bolts or by clamp mechanisms.
- a chamber formed within apparatus 27 after assembling contains at least one BGA assembly. In one embodiment, many BGA assemblies may be introduced into the formed chamber for processing. The height of an internal processing area formed within apparatus 27 after assembly is sufficient to accommodate the height of a BGA assembly without damaging the assembly.
- Plate 29 has a compliant layer of material, illustrated herein as compliant layer 37 affixed thereto and covering the area over the ball array of an enclosed part.
- This compliant layer 37 may be a rubberized material, a polymer-based material, or any other suitable material having compliant characteristics.
- the purpose of compliant layer 37 on plate 29 is to protect the upper portions of solder balls ( 15 ) of a BGA assembly or assemblies inserted into apparatus 27 for processing.
- the dimensions of the plates are such that, when the plates are closed, the compliant layer forms over the upper portion of each solder ball as may be seen in FIG. 5B.
- Upper plate 29 has an injection port 37 provided therethrough, which opens into the vacuum chamber formed within apparatus 27 .
- Port 37 is adapted to enable injection of an uncured protective coating material 17 , in liquid form, into the vacuum chamber during processing. In one embodiment, there may be more than 1 injection port 37 provided within plate 29 .
- Lower plate 31 has a vacuum port 35 providing therethrough, which opens into the vacuum chamber formed within apparatus 27 . Port 35 is adapted to connect a vacuum pumping apparatus (not shown) to enable a vacuum to be drawn within apparatus 27 . In one embodiment, there may be more than one vacuum port provided within plate 31 .
- At least one BGA assembly complete with re-flowed solder balls is placed onto the surface of plate 31 .
- Plate 29 is urged into to plate 31 over seal 33 and bolted or clamped together with the BGA assembly or assemblies inside.
- a vacuum is then drawn by virtue of port 35 .
- the protective coating 17 is injected through port(s) 37 to the internal chamber coating the inserted BGA assembly or assemblies.
- FIG. 5B is an expanded view of one edge of the assembly shown in FIG. 5A.
- wafer 14 is shown with one solder ball 15 .
- Compliant layer 37 forms over the top of solder ball 15 and protects the covered area of ball 15 from being coated with injected coating 17 , in a manner that, when released, the solder balls will be exposed on the coated parts.
- the top surface of solder ball 15 is required to be free of coating as this area is used for lead connection.
- the remaining real estate of wafer 14 and solder ball 15 is covered with protective coating 17 during this back-filling operation. after back-filling with the protective coating material in liquid form, the material is cured before the molds are opened.
- apparatus 27 may be manufactured of a size such as to facilitate the processing of a number of BGA assemblies simultaneously. In one embodiment apparatus 27 may process only a few assemblies, or perhaps one assembly at a time. Once processing is completed within apparatus 27 , BGA assemblies are removed from apparatus 27 by unbolting or unclamping apparatus and pulling apart plates 29 and 31 revealing completed BGA assemblies. A tracking operation may be used to remove excess coating.
- FIG. 6 a illustrates a wafer 41 with balls 45 placed and soldered to solder pads, with a nitride layer 43 in place, as is known in the art.
- FIG. 6 b shows the assembly of FIG. 6 a with a protective layer 47 applied according to embodiments to the present invention as described above.
- Layer 47 may be applied by screening, spraying, dispense and spinning, by backfilling, or in any of several other ways. Preferably, layer 47 completely covers all balls in the ball grid array.
- FIG. 6 c a machining operation is illustrated using a grinding or cutting wheel 49 to remove a portion of layer 47 and enough of each ball in the ball grid array that each ball is now exposed as a flat pad even with the upper machined surface of layer 47 .
- FIG. 6 d shows the assembly of FIG. 6 c completely planarized.
- solder material is applied over each exposed solder ball machined surface.
- FIG. 6 e illustrates a solder pad 51 in place over each solder ball in the assembly.
- Solder islands 51 may be applied by screen printing paste, by plating, or by direct solder ball attachment.
- the new solder material may have a melting point equal to that of the original solder balls, or a lower melting point.
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
A vacuum-application and coating apparatus for applying a protective coating to at least one ball-grid-array assembly is provided. The apparatus comprises an upper plate having at least one injection port forming the upper chamber wall, and a lower plate having at least one vacuum port forming the lower chamber wall of the vacuum-application and coating apparatus when assembled. A compliant layer of material is provided on the chamber-side surface of the upper plate and a sealing mechanism for enabling a vacuum seal is also provided. At least one ball-grid-array assembly is placed on the chamber surface of the lower plate during assembly of the vacuum-application and coating apparatus, which forms a vacuum chamber. The ball-grid-array assemblies held in the chamber are protected from receiving any coating on the upper portions of connected solder balls during processing by virtue of intimate contact between the solder balls and the compliant layer of material. In other aspects methods are provided for adding a protective coating to ball-grid-array assemblies and subsequently providing opening for access to the die pads. In another aspect a process is provided for completely encapsulating balls, then exposing a portion and applying a new grid array.
Description
- The present invention is in the field of semiconductor and printed-circuit-board (PCB) manufacturing including surface mount technologies (SMT), and pertains more particularly to methods and apparatus for applying protective coatings to structures meant for connection by BGA techniques.
- The field of integrated circuit interconnection and packaging is one of the most rapidly-evolving technologies associated with semiconductor manufacturing. As demand for devices that are smaller and more powerful continues to increase, pressures are put on manufacturers to develop better and more efficient ways to assemble and package IC products. One of the more recently developed methods for assembling and packaging IC products is known as Ball-Grid-Array (BGA) technology. Motorola™ inc. is one of the noted pioneers of BGA technology. Currently there are many companies that license BGA technology developed by Motorola™, and Motorola and other companies continue to develop BGA technology.
- BGA technology provides several advantages over more mainstream technologies such as Fine-Pitch-Technology (FTP), and Pin-Grid-Array (PGA). One obvious advantage is that there are no leads that can be damaged during handling. Another obvious advantage is that the solder balls are typically self-centering on die pads. Still other advantages are smaller size, better thermal and electrical performances, better package yields, and so on.
- In BGA technology, wafers or substrates are typically protected with a non-conductive material such as a nitride layer. The die pads are exposed through the nitride layer by means of chemical etching, or by other known methods. The protective nitride layer is intended to protect the substrates from contaminants and damage. One problem with prior-art protective coatings such as a nitride layer is that it is ultra-thin and does not offer any protection to the die pads themselves nor to the connection points between solder balls in the die pads.
- It has occurred in the inventor that an additional protective coating, such as a protective polymer-based coating, would offer a measure of protection not provided with prior-art coatings. For example, it is desired that in addition to protecting the substrates itself, die pads and soldered connections may also benefit logically from protection. However, in order to obtain the added, protective benefits from an additional coating, a unique application process must be conceived. It is to such a process that the method and apparatus of the present invention is directed.
- What is clearly needed is a method and apparatus for applying a protective overcoat to a Ball-Grid-Array (BGA) device such that exposed die-pad areas, soldered connections, and exposed areas of solder balls in the assembly are protected from exposure.
- In a preferred embodiment of the present invention a coating mold for forming a protective coating on a ball-grid-array assembly having solder balls extending above a base surface of the ball-grid-array assembly is provided, comprising a first portion having a substantially flat area for supporting the ball grid array assembly on a back surface; a second portion having a substantially flat compliant layer; an injection port passing through one or the other of the first and second portions; a vacuum pumping port passing through one or the other of the first and second portions; and a sealing mechanism for sealing the first portion to the second portion, enclosing the ball-grid-array assembly. The mold is characterized in that with the first portion closed on the second portion the compliant layer contacts the solder balls of the ball grid array, and a space is formed between the second portion and the base surface of the ball-grid-array.
- In some embodiments the sealing mechanism is an o-ring. Also in some embodiments there is a clamping or bolting mechanism for keeping the mold closed in process. Preferably the compliant layer is a flexible polymer material.
- In another aspect of the invention a method for applying a protective coating to a ball-grid-array assembly having solder balls extending above a base surface is provided, comprising steps of (a) placing the ball-grid-array assembly, including solder balls, into a coating mold having a first surface for supporting the ball-grid-array assembly on a back surface and a second portion having a substantially flat compliant layer; (b) closing and sealing the mold such that the compliant layer contacts the balls of the ball grid array, leaving a space between the compliant layer and the base surface of the ball-grid -array assembly; (c) creating a vacuum in the space formed in step (b); (d) injecting a polymer-based coating into the space formed; and (e) curing the polymer material, such that, when opened the ball-grid-array assembly is coated while leaving an upper portion of each of the solder balls exposed. In preferred embodiments of the method the mold closes on an o-ring seal.
- In yet another aspect of the invention a method for providing a protective polymer coating to a ball-grid-array assembly, before placing solder balls on the die pads of the assembly is provided, comprising the steps of (a) overcoating the assembly with a polymer material; and (b) opening each die pad area to the die pad through the polymer material by a removal process to expose the die pads for placement of the solder balls.
- In a preferred embodiment of this method, in step (b) the removal process comprises laser machining. In another embodiment the removal process comprises chemical etching, and in yet another embodiment the removal process comprises physical etching.
- In still another aspect of the invention a method for providing a protective polymer coating to a ball-grid-array assembly, before placing solder balls on the die pads of the assembly is provided, comprising the steps of (a) screen printing photoresist onto the ball-grid-array assembly; (b) masking the ball-grid-array assembly to protect areas of photoresist over the die pads; (c) developing and removing the photoresist exposed through the mask, leaving the photoresist over the die pads as protective photoresist islands; (d) applying a protective coat to the ball-grid-array assembly to the thickness of the photoresist coating; and (e) developing and removing the remaining photoresist islands to expose the underlying die pads.
- In yet another aspect of the invention a method for protecting and strengthening a ball-grid-array assembly having solder balls extending above a base surface is provided, comprising steps of (a) applying a protective material layer over the solder balls to a level at or above the level of the top of the solder balls, providing thereby a new upper surface for the assembly; (b) removing a portion of the new upper surface to an extent that a portion of each of the original solder balls is exposed as a flat region in a planar upper surface; and (c) applying new solder material over each of the flat exposed solder ball regions.
- In some embodiments, in step (b), removal is by machining. The protective material may be applied in a number of different ways, such as by screening, spraying, or dispense and spinning. There may also be an additional step for reflowing the new solder material.
- Now, for the first time a method and apparatus for applying a protective overcoat to a Ball-Grid-Array (BGA) is provided that protects exposed die-pad areas, soldered connections, and exposed areas of solder balls from exposure and damage.
- FIG. 1A is a perspective view of a wafer with die pads according to prior art.
- FIG. 1B is an expanded and broken view of the wafer of FIG. 1A illustrating a die-pad exposed through a nitride coating.
- FIG. 2 is a broken view of a BGA assembly with a protective overcoat according to an embodiment of the present invention.
- FIG. 3A is a plan view of the wafer of FIG. 2 with a protective overcoat applied as a first step according to an embodiment of the present invention.
- FIG. 3B is a plan view of the coated wafer of FIG. 3A with coated areas removed in areas to expose the die pads.
- FIG. 3C is a plan view of the coated wafer of FIGS. 3A and 3B with solder balls in place according to a third step.
- FIG. 4 is a process diagram illustrating processing steps a through e for coating and creating die pad openings according to another embodiment of the present invention.
- FIG. 5A is a section view of a vacuum enhanced coating apparatus for applying a protective overcoat to a BGA assembly according to a preferred embodiment of the present invention.
- FIG. 5B is a detailed view of a portion of FIG. 5A.
- FIG. 1A is a idealized perspective view of a coated
wafer 9 with diepads 11 according to the prior art art. The skilled artisan will recognize that the pads have been very much exaggerated in this view to be able to provide some detail. In this example ofprior art wafer 9 is coated with a thin, protective layer that is nonconductive, such as anitride layer 13. Diepads 11 are illustrated in an array onwafer 9. Typically, diepads 11 are nitride coated along withwafer 9, which may be a rectangular substrate instead of an actual wafer. After nitride coating, diepads 11 are exposed by such as an etching process. - FIG. 1B is an expanded and broken view of one
pad 11 of FIG. 1A, shown in perspective, illustrating the pad exposed through the nitride layer. In this detail, adie pad 11 can be seen recessed beneath the thickness ofnitride coating 13. It is noted herein, that diepad 11 is completely exposed, meaning that there is no protective layer above any of the land occupied bydie pad 11. When a solder ball (not shown) is placed ondie pad 11, certain real estate ofdie pad 11 along with the soldered area between the ball and diepad 11 will be exposed, and therefore vulnerable to damage and contamination. A goal of the present invention is to provide a process that according to various embodiments, which are described in enabling detail below, may be used to successfully apply a protective coating layer in addition to the standard hard protective layer such as the nitride layer described above. - FIG. 2 is a broken view of a portion of a
BGA assembly 14 with aprotective overcoat 17 according to an embodiment of the present invention. In this example of the present invention,BGA assembly 14 exhibits 2 diepads 11 havingsolder balls 15 adhered thereto. Aprotective coating 17 is, in a preferred embodiment, a polymer-based coating such as a polyamide coating. In other embodiments, other polymer-based coatings may be used such as are known in the art and available to the inventor. This example illustrates a preferred embodiment, whereinprotective coating 17 coats the substrate and the normally exposed area of each diepad 11 aroundsolder balls 15 and also around the perimeter of eachsolder ball 15. - A
nitride coating 13, which is illustrated in FIGS. 1A and B, is illustrated here as coating the substrate portion ofassembly 14 with the coating extending up over the attached die pads. It may be assumed herein, that a portion ofcoating 13 has been removed by any one of several known methods in order to clear to an appropriate area on the upper surf aces of each diepad 11 for placement and reflow ofsolder balls 15.Protective coating 17 is illustrated as overcoating nitride layer 13 and encompassing the lower peripheral areas ofsolder balls 15. A height dimension D illustrates the thickness ofcoating 17, which may be anywhere from 1 to 3 mils thick in a preferred embodiment.Overcoat 17 functions to protect any exposed pad areas as well as a portion ofsolder balls 15. - In practice of the present invention, the inventor has isolated three basic processes that are useful to successfully apply
protective coating 17 toBGA assembly 14. FIG. 3A is a plan-broken view ofwafer 14 of FIG. 2 with a protective overcoat applied as a first step according to an embodiment of the present invention. FIG. 3B is a plan-broken view ofcoated wafer 14 of FIG. 3A undergoing a process to expose covered die pads in a second step. FIG. 3C is a plan-broken view ofcoated wafer 14 of FIGS. 3A and 3C with solder balls in place according to a third step. The examples of FIGS. 3A, 3B, and 3C illustrate a general 3-part process for the overcoating wafer 14, removing material to expose die pads, and then screening the solder balls into place for a re-flow operation. - Referring now to FIG. 3A,
wafer 14 is illustrated withprotective coating 17 already applied. It may be assumed herein, although not specifically illustrated, that diepads 11 of FIG. 2 andnitride coating 13 of FIG. 2 are present onwafer 14 before application ofprotective coating 17.Coating 17 in a first step completely covers diepads 11 andnitride coating 13.Coating 17 may be a Polyamide coating or a similar polymer-based coating as described above.Coating 17 may be applied by any one of several processes, such as by vacuum deposition process, a spin-on process, or by virtue of other known methods. - Referring now to FIG. 3B,
protective coating 17 is partially removed over the land areas above each die pad attached towafer 14. This process may be a laser process, a plasma-etch process, or a chemical-etch process. In both the plasma-etch and chemical-etch processes, a mask is used to protect portions of coating 17 not covering die pads. These portions are represented herein byelement number 19. Areas where material has been removed are represented herein byelement number 21. Once die pads are exposed, they are ready to accept solder balls. - Referring now to FIG. 3C,
wafer 14 is illustrated withsolder balls 15 screened in place and ready to be re-flowed onto the associated die pads. A re-flow process uses heat to effect the solder connections betweenballs 15 and associated die pads. The process described above with respect to FIGS. 3A-3C may be used to according to one embodiment, to protect any BGA assembly. - FIG. 4 is a process diagram illustrating processing steps a through e for coating and creating die pad openings according to another embodiment of the present invention. In step a,
wafer 14 is coated with a photoresist coating represented herein byelement number 23. As described in FIG. 3A above, it may be assumed that die pads (11) and a standard nitride layer (13) are present in this step. This photoresist process may be accomplished using a standard screen-printing technique. It is noted herein thatphotoresist 23 is applied before applying a protective coating (17). - In step b, a masking technique is used to cover areas of photoresist that are directly over die pads (11). Through development of photoresist (23) with a protective mask applied, resist islands are formed as represented by
element number 25 in this step. Resistislands 25 are present areas of photoresist left directly over die pads (11) after developing. - In step c,
protective coating 17 is applied at substantially the same thickness asphotoresist 25. This process of coating fills in the areas inbetween resistislands 25, such areas representing real estate ofwafer 14 not occupied by a die pad (11). - In step d, a second masking technique is used to protect the areas coated with
protective coating 17 in step c. At this point in the process, resistislands 25 are chemically developed, and then etched away exposing associated die pads (11) leaving all other real estate untouched. In step e,solder balls 15 are screened in place over die pads (11) as described with reference to FIG. 3C. At this point of the process, a re-flow operation to permanently attachsolder balls 15 to die pads (11) may begin. The process represented herein by FIG. 4, illustrates a process for applyingprotective coating 17 according to yet another embodiment of the present invention. - FIG. 5A is a section view of a vacuum-application and
coating apparatus 27 for applyingprotective overcoat 17 to a BGA assembly according to a preferred embodiment of the present invention. Vacuum-application andcoating apparatus 27, hereinafter referred to as simplyapparatus 27, is provided and adapted to enable an automated coating process to be performed on a BGA assembly after re-flow.Apparatus 27 comprises anupper plate 29, alower plate 31, and avacuum seal 33. In a preferred embodiment bothplate Plates - In operation a BGA assembly32, with solder balls in place, is enclosed by
plate seal 33. It may be assumed herein that eitherplate 29 orplate 31 has an o-ring-style groove provided on its mating surface, generally around the perimeter, such thatseal 33 may be properly retained and facilitated. In one embodiment, both mating surfaces ofplates seal 33. In still another embodiment, a metallic sealing apparatus may be used instead of an o-ring. -
Plate seal 33 to formapparatus 27, and the plates may be held together by any of several methods, such as by bolts or by clamp mechanisms. A chamber formed withinapparatus 27 after assembling contains at least one BGA assembly. In one embodiment, many BGA assemblies may be introduced into the formed chamber for processing. The height of an internal processing area formed withinapparatus 27 after assembly is sufficient to accommodate the height of a BGA assembly without damaging the assembly. -
Plate 29 has a compliant layer of material, illustrated herein ascompliant layer 37 affixed thereto and covering the area over the ball array of an enclosed part. Thiscompliant layer 37 may be a rubberized material, a polymer-based material, or any other suitable material having compliant characteristics. The purpose ofcompliant layer 37 onplate 29 is to protect the upper portions of solder balls (15) of a BGA assembly or assemblies inserted intoapparatus 27 for processing. The dimensions of the plates are such that, when the plates are closed, the compliant layer forms over the upper portion of each solder ball as may be seen in FIG. 5B. -
Upper plate 29 has aninjection port 37 provided therethrough, which opens into the vacuum chamber formed withinapparatus 27.Port 37 is adapted to enable injection of an uncuredprotective coating material 17, in liquid form, into the vacuum chamber during processing. In one embodiment, there may be more than 1injection port 37 provided withinplate 29.Lower plate 31 has avacuum port 35 providing therethrough, which opens into the vacuum chamber formed withinapparatus 27.Port 35 is adapted to connect a vacuum pumping apparatus (not shown) to enable a vacuum to be drawn withinapparatus 27. In one embodiment, there may be more than one vacuum port provided withinplate 31. - In practice of the present invention, at least one BGA assembly complete with re-flowed solder balls is placed onto the surface of
plate 31.Plate 29 is urged into to plate 31 overseal 33 and bolted or clamped together with the BGA assembly or assemblies inside. A vacuum is then drawn by virtue ofport 35. Theprotective coating 17 is injected through port(s) 37 to the internal chamber coating the inserted BGA assembly or assemblies. - FIG. 5B is an expanded view of one edge of the assembly shown in FIG. 5A. In this expanded view,
wafer 14 is shown with onesolder ball 15.Compliant layer 37 forms over the top ofsolder ball 15 and protects the covered area ofball 15 from being coated with injectedcoating 17, in a manner that, when released, the solder balls will be exposed on the coated parts. The top surface ofsolder ball 15 is required to be free of coating as this area is used for lead connection. However, the remaining real estate ofwafer 14 andsolder ball 15 is covered withprotective coating 17 during this back-filling operation. after back-filling with the protective coating material in liquid form, the material is cured before the molds are opened. - It will be apparent to one with skill in the art that
apparatus 27 may be manufactured of a size such as to facilitate the processing of a number of BGA assemblies simultaneously. In oneembodiment apparatus 27 may process only a few assemblies, or perhaps one assembly at a time. Once processing is completed withinapparatus 27, BGA assemblies are removed fromapparatus 27 by unbolting or unclamping apparatus and pulling apartplates - In yet another embodiment of the invention for a method is provided for protecting a BGA assembly in a manner that increased strength is also provided. This method is illustrated herein with the aid of FIGS. 6a through 6 f. FIG. 6a illustrates a
wafer 41 withballs 45 placed and soldered to solder pads, with anitride layer 43 in place, as is known in the art. FIG. 6b shows the assembly of FIG. 6a with aprotective layer 47 applied according to embodiments to the present invention as described above.Layer 47 may be applied by screening, spraying, dispense and spinning, by backfilling, or in any of several other ways. Preferably,layer 47 completely covers all balls in the ball grid array. - In FIG. 6c a machining operation is illustrated using a grinding or cutting
wheel 49 to remove a portion oflayer 47 and enough of each ball in the ball grid array that each ball is now exposed as a flat pad even with the upper machined surface oflayer 47. FIG. 6d shows the assembly of FIG. 6c completely planarized. - After planarization, solder material is applied over each exposed solder ball machined surface. FIG. 6e illustrates a
solder pad 51 in place over each solder ball in the assembly.Solder islands 51 may be applied by screen printing paste, by plating, or by direct solder ball attachment. Preferably the new solder material may have a melting point equal to that of the original solder balls, or a lower melting point. - After the new solder material is applied, that material is re-flowed, such that the new ball grid array surface is created over the original. The original solder balls are now completely encapsulated in the material of
layer 47, and the original wafer surface and all of the elements of that surface are very well protected. Additionally, the new array is much more robust and strong than the original, because all stress points have now been redistributed away from the wafer surface. - It will be apparent to one with skill in the art that the method and apparatus of the present invention may be provided for a wide variety of shapes and sizes of BGA assemblies without departing from the spirit and scope of the present invention. Similarly, the method and apparatus of the present invention may be applied to BGA assemblies of varying materials. The method and apparatus of the present invention provides an automated and efficient way to apply an additional protective coating to BGA assemblies. The method and apparatus of the present invention should be afforded the broadest scope possible under examination. The spirit and scope of the present invention should be limited only by the claims that follow.
Claims (15)
1. A coating mold for forming a protective coating on a ball-grid-array assembly having solder balls extending above a base surface of the ball-grid-array assembly, comprising:
a first portion having a substantially flat area for supporting the ball grid array assembly on a back surface;
a second portion having a substantially flat compliant layer;
an injection port passing through one or the other of the first and second portions;
a vacuum pumping port passing through one or the other of the first and second portions; and
a sealing mechanism for sealing the first portion to the second portion, enclosing the ball-grid-array assembly;
characterized in that with the first portion closed on the second portion the compliant layer contacts the solder balls of the ball grid array, and a space is formed between the second portion and the base surface of the ball-grid-array.
2. The coating mold of claim 1 wherein the sealing mechanism is an o-ring.
3. The coating mold of claim 1 further comprising a clamping or bolting mechanism for keeping the mold closed in process.
4. The coating mold of claim 1 wherein the compliant layer is a flexible polymer material.
5. A method for applying a protective coating to a ball-grid-array assembly having solder balls extending above a base surface, comprising steps of:
(a) placing the ball-grid-array assembly, including solder balls, into a coating mold having a first surface for supporting the ball-grid-array assembly on a back surface and a second portion having a substantially flat compliant layer;
(b) closing and sealing the mold such that the compliant layer contacts the balls of the ball grid array, leaving a space between the compliant layer and the base surface of the ball-grid -array assembly;
(c) creating a vacuum in the space formed in step (b);
(d) injecting a polymer-based coating into the space formed; and
(e) curing the polymer material, such that, when opened the ball-grid-array assembly is coated while leaving an upper portion of each of the solder balls exposed.
6. The method of claim 5 wherein the mold closes on an o-ring seal.
7. A method for providing a protective polymer coating to a ball-grid-array assembly, before placing solder balls on the die pads of the assembly, comprising the steps of:
(a) overcoating the assembly with a polymer material; and
(b) opening each die pad area to the die pad through the polymer material by a removal process to expose the die pads for placement of the solder balls.
8. The method of claim 7 wherein, in step (b) the removal process comprises laser machining.
9. The method of claim 7 wherein the removal process comprises chemical etching.
10. The method of claim 7 wherein the removal process comprises physical etching.
11. A method for providing a protective polymer coating to a ball-grid-array assembly, before placing solder balls on the die pads of the assembly, comprising the steps of:
(a) screen printing photoresist onto the ball-grid-array assembly;
(b) masking the ball-grid-array assembly to protect areas of photoresist over the die pads;
(c) developing and removing the photoresist exposed through the mask, leaving the photoresist over the die pads as protective photoresist islands;
(d) applying a protective coat to the ball-grid-array assembly to the thickness of the photoresist coating; and
(e) developing and removing the remaining photoresist islands to expose the underlying die pads.
12. A method for protecting and strengthening a ball-grid-array assembly having solder balls extending above a base surface, comprising steps of:
(a) applying a protective material layer over the solder balls to a level at or above the level of the top of the solder balls, providing thereby a new upper surface for the assembly;
(b) removing a portion of the new upper surface to an extent that a portion of each of the original solder balls is exposed as a flat region in a planar upper surface; and
(c) applying new solder material over each of the flat exposed solder ball regions.
13. The method of claim 12 wherein, in step (b), removal is by machining.
14. The method of claim 12 wherein, in step (a) the protective material is applied by one of screening, spraying, or dispense and spinning.
15. The method of claim 12 comprising an additional step (d) for reflowing the new solder material.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
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US09/609,626 US20020064931A1 (en) | 2000-07-03 | 2000-07-03 | Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure |
US09/625,693 US6347947B1 (en) | 2000-07-03 | 2000-07-26 | Method and apparatus for protecting and strengthening electrical contact interfaces |
US09/752,116 US20020001981A1 (en) | 2000-07-03 | 2000-12-29 | Method and apparatus for protecting and strengthening electrical contact interfaces |
PCT/US2001/041200 WO2002003446A1 (en) | 2000-07-03 | 2001-06-28 | Method and apparatus for applying a protective over-coating to a ball-grid-array (bga) structure |
AU2001273651A AU2001273651A1 (en) | 2000-07-03 | 2001-06-28 | Method and apparatus for applying a protective over-coating to a ball-grid-array(bga) structure |
US09/915,708 US7104804B2 (en) | 2000-07-03 | 2001-07-25 | Method and apparatus for memory module circuit interconnection |
US10/047,858 US20020061665A1 (en) | 2000-07-03 | 2002-01-14 | Method and apparatus for vertically stacking and interconnecting ball grid array (BGA) electronic circuit devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US09/609,626 US20020064931A1 (en) | 2000-07-03 | 2000-07-03 | Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US09/625,693 Continuation-In-Part US6347947B1 (en) | 2000-07-03 | 2000-07-26 | Method and apparatus for protecting and strengthening electrical contact interfaces |
US09/915,708 Continuation-In-Part US7104804B2 (en) | 2000-07-03 | 2001-07-25 | Method and apparatus for memory module circuit interconnection |
Publications (1)
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US20020064931A1 true US20020064931A1 (en) | 2002-05-30 |
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US09/609,626 Abandoned US20020064931A1 (en) | 2000-07-03 | 2000-07-03 | Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure |
US09/625,693 Expired - Fee Related US6347947B1 (en) | 2000-07-03 | 2000-07-26 | Method and apparatus for protecting and strengthening electrical contact interfaces |
US09/752,116 Abandoned US20020001981A1 (en) | 2000-07-03 | 2000-12-29 | Method and apparatus for protecting and strengthening electrical contact interfaces |
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US09/625,693 Expired - Fee Related US6347947B1 (en) | 2000-07-03 | 2000-07-26 | Method and apparatus for protecting and strengthening electrical contact interfaces |
US09/752,116 Abandoned US20020001981A1 (en) | 2000-07-03 | 2000-12-29 | Method and apparatus for protecting and strengthening electrical contact interfaces |
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US (3) | US20020064931A1 (en) |
AU (1) | AU2001273651A1 (en) |
WO (1) | WO2002003446A1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2004008528A1 (en) * | 2002-07-12 | 2004-01-22 | Keteca Singapore (Pte) Ltd | Method and wafer for maintaining ultra clean bonding pads on a wafer |
US20040207068A1 (en) * | 2003-04-18 | 2004-10-21 | Leal George R. | Circuit device with at least partial packaging and method for forming |
US6921975B2 (en) | 2003-04-18 | 2005-07-26 | Freescale Semiconductor, Inc. | Circuit device with at least partial packaging, exposed active surface and a voltage reference plane |
US20050242425A1 (en) * | 2004-04-30 | 2005-11-03 | Leal George R | Semiconductor device with a protected active die region and method therefor |
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Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7382142B2 (en) * | 2000-05-23 | 2008-06-03 | Nanonexus, Inc. | High density interconnect system having rapid fabrication cycle |
US6812718B1 (en) | 1999-05-27 | 2004-11-02 | Nanonexus, Inc. | Massively parallel interface for electronic circuits |
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US20070245553A1 (en) * | 1999-05-27 | 2007-10-25 | Chong Fu C | Fine pitch microfabricated spring contact structure & method |
US6794751B2 (en) * | 2001-06-29 | 2004-09-21 | Intel Corporation | Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies |
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WO2008070673A2 (en) * | 2006-12-04 | 2008-06-12 | Nanonexus, Inc. | Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies |
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US11172580B2 (en) * | 2017-07-24 | 2021-11-09 | Rosemount Aerospace Inc. | BGA component masking dam and a method of manufacturing with the BGA component masking dam |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2511289B2 (en) * | 1988-03-30 | 1996-06-26 | 株式会社日立製作所 | Semiconductor device |
US6133534A (en) * | 1991-11-29 | 2000-10-17 | Hitachi Chemical Company, Ltd. | Wiring board for electrical tests with bumps having polymeric coating |
US5371654A (en) * | 1992-10-19 | 1994-12-06 | International Business Machines Corporation | Three dimensional high performance interconnection package |
US5810607A (en) * | 1995-09-13 | 1998-09-22 | International Business Machines Corporation | Interconnector with contact pads having enhanced durability |
SG45122A1 (en) * | 1995-10-28 | 1998-01-16 | Inst Of Microelectronics | Low cost and highly reliable chip-sized package |
KR0182073B1 (en) * | 1995-12-22 | 1999-03-20 | 황인길 | Semiconductor chip scale semiconductor package and manufacturing method thereof |
JP3224731B2 (en) * | 1996-02-05 | 2001-11-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Method of forming layer having high density pattern |
US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
JP3116273B2 (en) * | 1996-04-26 | 2000-12-11 | 日本特殊陶業株式会社 | Relay board, method of manufacturing the same, structure including board, relay board, and mounting board, connection body between board and relay board |
US5971734A (en) * | 1996-09-21 | 1999-10-26 | Anam Semiconductor Inc. | Mold for ball grid array semiconductor package |
US6160705A (en) * | 1997-05-09 | 2000-12-12 | Texas Instruments Incorporated | Ball grid array package and method using enhanced power and ground distribution circuitry |
US5972734A (en) * | 1997-09-17 | 1999-10-26 | Lsi Logic Corporation | Interposer for ball grid array (BGA) package |
US6097087A (en) * | 1997-10-31 | 2000-08-01 | Micron Technology, Inc. | Semiconductor package including flex circuit, interconnects and dense array external contacts |
US6118179A (en) * | 1999-08-27 | 2000-09-12 | Micron Technology, Inc. | Semiconductor component with external contact polymer support member and method of fabrication |
-
2000
- 2000-07-03 US US09/609,626 patent/US20020064931A1/en not_active Abandoned
- 2000-07-26 US US09/625,693 patent/US6347947B1/en not_active Expired - Fee Related
- 2000-12-29 US US09/752,116 patent/US20020001981A1/en not_active Abandoned
-
2001
- 2001-06-28 WO PCT/US2001/041200 patent/WO2002003446A1/en active Application Filing
- 2001-06-28 AU AU2001273651A patent/AU2001273651A1/en not_active Abandoned
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US20040207068A1 (en) * | 2003-04-18 | 2004-10-21 | Leal George R. | Circuit device with at least partial packaging and method for forming |
US6838776B2 (en) | 2003-04-18 | 2005-01-04 | Freescale Semiconductor, Inc. | Circuit device with at least partial packaging and method for forming |
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US20060192301A1 (en) * | 2004-04-30 | 2006-08-31 | Leal George R | Semiconductor device with a protected active die region and method therefor |
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Also Published As
Publication number | Publication date |
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WO2002003446A1 (en) | 2002-01-10 |
US6347947B1 (en) | 2002-02-19 |
US20020001981A1 (en) | 2002-01-03 |
AU2001273651A1 (en) | 2002-01-14 |
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