US20020000599A1

US20020000599A1 - Semiconductor device and manufacturing method thereof

Info

Publication number: US20020000599A1
Application number: US08/941,065
Authority: US
Inventors: Toshikazu Mizukoshi; Ikuo Kurachi
Original assignee: Oki Electric Industry Co Ltd
Current assignee: Oki Electric Industry Co Ltd
Priority date: 1997-05-08
Filing date: 1997-09-30
Publication date: 2002-01-03
Also published as: CN1199247A; TW365016B; KR19980086441A; KR100338275B1; US6383866B1; JPH10308498A; CN1136615C

Abstract

A Si₃N₄film and a side wall are provided on an electrode to obtain a Cs capacitor capable of enlarging an area of a memory cell contact of a DRAM, and a hole if formed penetrating an inter-layer film by a selective etching process. The Si₃N₄film and the side wall are left without being etched, and an area of the hole through which a substrate is exposed, is smaller than an upper portion area of the hole.

Description

BACKGROUND OF THE INVENTION

The present invention relates generally to a semiconductor device and a manufacturing method thereof and, more particularly, to a semiconductor device and a manufacturing method thereof, which have characteristics in terms of a structure of a capacitor and in terms of a method of manufacturing this capacitor.

A dynamic DRAM contains capacitors for storing information. These capacitors are arranged in matrix in a memory device, and among them a capacitor existing in a predetermined position is selected based on address information supplied from outside. The selected capacitor is supplied with information converted into an electric charge by a write control system.

When in a reading process, the capacitor in the predetermined is selected based on the address information, and the electric charge of the selected capacitor is read to a bit line previously charged by a read control system. This electric charge is amplified by a sense amplifier and then outputted to outside.

FIG. 2 is a diagram of one example of a DRAM memory cell mask pattern, showing a structure of the capacitors in the DRAM having a conventional COB structure. AC areas y 1 are formed obliquely in FIG. 2, and bit lines y2 extend in an X-direction while word lines y3 extend in a Y-direction. Hereinafter, mainly an X-directional structure and a manufacturing method thereof will be explained with reference to FIGS. 3, 5 and 7, while a Y-directional structure is shown in FIGS. 4, 6 and 8.

FIG. 3 shows an X-directional section in the middle of a process of manufacturing the capacitor illustrated in FIG. 2. FIG. 4 shows a Y-directional section in FIG. 2. Provided on a

substrate

51 composed of a semiconductor such as Si monocrystal or the like are a field oxide film 52 having a thickness on the order of 2000-4000 A and a MOS transistor (Tr) gate oxide film 53 having a thickness of approximately 50-150 A, which are formed normally by a LOCS (Local Oxidation of Silicon: Selective Oxidation) method.

After the

gate oxide film

53 and the field oxide film 52 have been formed, a plurality of electrodes 54 supplied with signals for capacitors are provided on these films. Then, insulating oxide films 55 are provided on both sides of these electrodes 54. The electrode 54 composed of polysilicon or polycide is formed in thickness of approximately 1000-2000 A and subjected to patterning in the Y-direction by ordinary photolithography and etching.

After the

electrodes

54 and the oxide films 55 have been formed, BPSG (borophosphosilicate glass) films 56 are formed thereon by a CVD (Chemical Vapor Deposition) method. This BPSG film 56 is formed with a hole 57 penetrating the BPSG film 56 and the gate oxide film 53, through which the substrate 51 is exposed. Provided also is an electrode 58 connected to the substrate 51 exposed through the hole 57. The electrode 58 composed of polysilicon and polycide is subjected to X-directional patterning by ordinary photolithography as well as by etching, and is thus formed.

Thereafter, as illustrated in FIG. 5, a

resist pattern

60 is formed by the ordinary photolithography, and a hole 61 is obtained (a Y-directional section is shown in FIG. 6) by etching. Next, as shown in FIG. 7, a polysilicon layer 62 that is approximately 5000-10000 A in thickness is provided as an electrode layer serving as one plate of the capacitor. Thereafter, a Si3N film 63 serving as a dielectric layer of the capacitor is formed in thickness on the order of 30-100 A on the surface of the electrode layer 62, and a polysilicon layer 64 serving as the other plate of the capacitor is formed in thickness of approximately 1000-2000 A on the Si3N film 63. The capacitor is thus completed. FIG. 8 illustrates a Y-directional section of this capacitor.

In the construction described above, however, an area of the

memory cell contact

61 of the DRAM can not be enlarged when reducing the device, and hence there arises a problem of causing an increase in the number of steps for enlarging the capacitor area. Another problem is that a hole margin of the photolithography of the memory cell contact is small.

It is a primary object of the present invention, which was contrived to obviate the problems given above, to provide a semiconductor device and a manufacturing method thereof, which are capable of enlarging an area of a DRAM memory cell contact.

It is another object of the present invention to provide a semiconductor device and a manufacturing method thereof, which are capable of increasing a hole margin of photolithography of a memory cell contact.

SUMMARY OF THE INVENTION

A semiconductor device according to the present invention comprises a semiconductor substrate, a gate electrode formed on the semiconductor substrate and extending in a first direction, a first protection layer formed along a side wall of the gate electrode as well as on the gate electrode and exhibiting an insulating property, an inter-layer insulating layer formed on the semiconductor substrate including the first protection layer, having an opening portion extending to the first protection layer and to the semiconductor substrate as well and exhibiting a selectivity for the first protection layer when in an etching process, and a capacitor formed inwardly of the opening portion.

The first protection layer may be, e.g., a nitride layer, and the inter-layer insulating layer may be, e.g., an oxide layer.

Further, the capacitor may be constructed of a first conductive layer connected to the semiconductor substrate and having a rugged surface, a capacitor insulating film formed on the first conductive layer, and a second conductive layer formed on the capacitor insulating film.

Alternatively, the inter-layer insulating layer may be constructed of a first insulating layer and a second insulating layer formed on the first insulating layer. The inter-layer insulating layer may contain a bit line provided between the first insulating layer and the second insulating layer and extending in a direction substantially orthogonal to the first direction, and a second protection layer provided on the bit line and along a side wall of the bit line and exhibiting a selectivity with respect to the inter-layer insulating layer when in an etching process and also an insulating property. The opening portion may extend to the second protection layer.

A semiconductor device manufacturing method according to the present invention is used for manufacturing the semiconductor device according to the present invention.

This manufacturing method comprises a step of forming a gate insulating film and a gate electrode extending in a first direction on a semiconductor substrate, a step of forming a protection layer exhibiting an insulating property on an upper portion of the gate electrode and along a side wall thereof, a step of forming a inter-layer insulating layer on the semiconductor substrate including the protection layer, a step of forming an opening portion extending to the protection layer and to the semiconductor substrate by selectively etching the inter-layer insulting layer, and a step of forming a capacitor inwardly of the opening portion.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the present invention will become apparent during the following discussion in conjunction with the accompanying drawings, in which: [0018]
FIG. 1 is a plan view showing a construction of the principal portion of a DRAM in accordance with a first embodiment of the present invention; [0019]
FIG. 2 is a plan view showing a construction of a prior art DRAM; [0020]
FIG. 3 is a sectional view showing steps of manufacturing the prior art DRAM; [0021]
FIG. 4 is a sectional view showing steps of manufacturing the prior art DRAM; [0022]
FIG. 5 is a sectional view showing the steps of manufacturing the prior art DRAM; [0023]
FIG. 6 is a sectional view showing the steps of manufacturing the prior art DRAM; [0024]
FIG. 7 is a sectional view showing a structure of the prior art DRAM; [0025]
FIG. 8 is a sectional view showing the structure of the prior art DRAM; [0026]
FIG. 9 is a sectional view showing a structure of the principal portion of a DRAM in a first embodiment of the present invention; [0027]
FIG. 10 is a sectional view showing the structure of the principal portion of the DRAM described above; [0028]
FIG. 11 is a sectional view showing manufacturing steps in a method of manufacturing the DRAM in a second embodiment of the present invention; [0029]
FIG. 12 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0030]
FIG. 13 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0031]
FIG. 14 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0032]
FIG. 15 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0033]
FIG. 16 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0034]
FIG. 17 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0035]
FIG. 18 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0036]
FIG. 19 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0037]
FIG. 20 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0038]
FIG. 21 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0039]
FIG. 22 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0040]
FIG. 23 is a sectional view showing a structure of the principal portion of the DRAM in a third embodiment of the present invention; [0041]
FIG. 24 is a sectional view showing the manufacturing steps in the method of manufacturing the DRAM in a fourth embodiment of the present invention; [0042]
FIG. 25 is a plan view showing a structure of the principal portion of the DRAM in a fifth embodiment of the present invention; [0043]
FIG. 26 is a sectional view showing the structure of the principal portion of the above DRAM; [0044]
FIG. 27 is a sectional view showing the structure of the principal portion of the DRAM; [0045]
FIG. 28 is a sectional view showing the manufacturing steps in the method of manufacturing the DRAM in a sixth embodiment of the present invention; [0046]
FIG. 29 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0047]
FIG. 30 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0048]
FIG. 31 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0049]
FIG. 32 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0050]
FIG. 33 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0051]
FIG. 34 is a sectional view showing the manufacturing steps in the method of manufacturing the above DRAM; [0052]
FIG. 35 is a sectional view showing a structure of the principal portion of the DRAM in a seventh embodiment of the present invention; and [0053]
FIG. 36 is a sectional view showing the manufacturing steps in the method of manufacturing the DRAM in an eighth embodiment of the present invention.[0054]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIGS. 1, 9 and [0055] 10 are views each illustrating a structure of capacitors of a DRAM in accordance with a first embodiment of the present invention. FIG. 1 is a top view of the DRAM. FIGS. 9 and 10 are views respectively schematically showing an X-X section and a Y-Y section.
Provided on a substrate (a semiconductor substrate) [0056] 1 are a field oxide film 2 for separation between elements and a gate oxide film 3 corresponding to a gate of a MOS (Metal Oxide Semiconductor) transistor (Tr). An electrode (a gate electrode) 4 is provided on this gate oxide film 3, and a Si₃N₄film (a protection layer) 5 is provided on the electrode 4. Further, side walls 6 are provided extending from a side surface of the electrode 4 to a side surface of the Si₃N₄film 5.
Formed further on the [0057] field oxide films 2, the Si₃N₄films 5 and the side walls 6 is a inter-layer film (an inter-layer insulating layer) 7 for separating these layers from layers formed thereon. This inter-layer film 7 is formed with a hole 8 through which the substrate 1 is exposed for a bit line contact. Provided moreover are an electrode 9 connected to the substrate 1 exposed from the hole 8, and an inter-layer film (an inter-layer insulating layer) 10 for separating the electrode 9 from a layer formed thereon. Note that the hole 8 and the electrode 9, as illustrated in FIGS. 1 and 9, do not exist on the X-X section in FIG. 1.
Then, a hole (an opening) [0058] 12 is formed penetrating the inter-layer films 10, 7. A hole 11 through which to expose a part of the substrate 1 that is not covered with the protection layers 5, 6, is formed in the bottom of the hole 12. A capacitor for accumulating an electric charge corresponding to data to be held, is formed inwardly of this hole 12.
This capacitor comprises an electrode (a first conductive layer) [0059] 13 so provided on a surface of the inter-layer film 10 as to extend from the hole 11 along the periphery of the hole 12, and connected to the substrate 1 exposed from the hole 11. The capacitor also comprises a capacitor insulating film 14 formed on the surface of this electrode 13, and an electrode (a second conductive layer) 15 further provided thereon. Namely, the hole 11 serves as a memory cell contact for connecting the substrate 1 to the electrode 13.
The [0060] substrate 1 is composed of monocrystal of silicon (Si). The field oxide film 2 is formed in thickness on the order of 2000-4000 A by an ordinary LOCOS (Local Oxidation of Silicon: selective oxidation) method. The gate oxide film 3 is approximately 50-150 A in thickness. The electrode 4 is composed of polysilicon or polycide and has a thickness of approximately 1000-3000 A. The side wall 6 is composed of Si₃N₄as in the case of the Si₃N₄film 5. The electrode 4 is covered in thickness of approximately 1000-3000 A with the side wall (Si₃N₄film) 6 and the Si₃N₄film 5. The inter-layer film 7 is composed of BPSG (borophosphosilicate glass: an oxide film to which boron and phosphorus are added) and is approximately 3000-5000 A thick. The electrode 9 is composed of polysilicon or polycide as in the case of the electrode 4 and has a width of approximately 1000-2000 A.
The [0061] inter-layer film 10 is composed BPSG as in the case of the inter-layer film 7 and has a thickness of approximately 3000-5000 A. The electrode 13 is composed of polysilicon having a thickness that is less than ½ the width of the hole 12. The hole 11 is formed by high selection ratio etching to selectively etch the inter BPSG layer films 7, 10 with respect to the Si₃N₄films 5, 6. Therefore, the Si₃N₄films 5, 6 are left on the bottom of the hole 11, and an aperture area of the hole 11 is smaller than an aperture area of the upper portion of the hole 12. A method of thus providing the protection layers (the Si₃N₄films 5, 6) and holding only the area covered with no protection layer, is called a self alignment.
As described above, according to the first embodiment, the aperture area of the memory cell contact (the hole [0062] 12) can be enlarged while keeping small the aperture area of the bottom surface (the hole 11) of the memory cell contact by use of the self alignment for forming the memory cell contact. Therefore, the memory cell contact can be provided on the gate electrode, whereby the side wall of the contact (the hole 12) can be used as a capacitor surface area. Accordingly, the surface area of the capacitor per unit chip area can be set larger than by the prior art. An occupying area on the chip can be reduced while keeping a capacity of the capacitor.
Further, the hole area of the [0063] hole 12 can be taken large, and hence a margin when holing the resist layer through a pattern transfer can be enlarged in the photolithography in the case of holing the memory cell contact.

Second Embodiment

A second embodiment of the present invention deals with a manufacturing method of manufacturing the DRAM having a construction shown in FIGS. 1, 9 and [0064] 10. FIGS. 11-22 show respective steps of this manufacturing method.
According to this manufacturing method, to start with, the [0065] field oxide film 2 having a thickness of approximately 2000-4000 A is formed on a Si monocrystal semiconductor substrate 1. This step generally involves the use of the LOCOS method. Thereafter, as illustrated in FIG. 11, the gate oxide film 3 of MOS-Tr is formed in thickness of approximately 50-150 A.
Next, a layer x[0066] 1, which is composed of polysilicon or polycide and will become an electrode 4 afterward, is formed in thickness on the order of 1000-3000 A on the field oxide film 2 and the gate oxide film 3 by the CVD (Chemical Vapor Deposition) method. Then, as shown in FIG. 12, a Si₃N₄layer x2, which will become a Si₃N₄film 5 afterward, is formed in thickness of approximately 1000-3000 A on this layer x1.
Thereafter, a photoresist layer x[0067] 3 is formed on the layer x2, and, when etching is executed by removing the photoresist excluding necessary patterns as illustrated in FIG. 13, the electrode 4 and the Si₃N₄film 5 are formed as shown in FIG. 14. Thereafter, as shown in FIG. 15, a Si₃N₄layer x4, which will become a side wall 6 afterward, is formed by the CVD method, and the etching process is executed. This etching is anisotropic etching exhibiting a high up-and-down directivity in FIG. 15. With this etching carried out, as indicated by a broken line in FIG. 16, the Si₃N₄layer x4 is uniformly etched in only the up-and-down direction, and the residual Si₃N₄layer x4 becomes the side wall 6.
Next, as shown in FIG. 17, a [0068] BPSG film 7 having a thickness of approximately 3000-5000 A is formed by the CVD method, and the surface is flatted by effecting a flow. Thereafter, a photoresist layer x5 is provided on the BPSG film 7, and, as illustrated in FIG. 18, there is removed the photoresist in a position x6 where a hole 8 is to be formed.
Thereafter, the [0069] hole 8 is formed by executing the etching process, and further a layer of polysilicon or polycide is formed by the CVD method. Moreover, when carrying out the patterning in the direction perpendicular to the sheet surface, i.e., in the direction horizontal to the surface of the substrate 1, as illustrated in FIG. 19, an electrode 9 is formed. Furthermore, a BPSG film 10 that is approximately 3000-5000 A in thickness is formed by the CVD method is formed on this electrode 9, and the surface is flatted by executing the flow.
Thereafter, a [0070] photoresist layer 11 is provided on this BPSG film 10, and, as shown in FIG. 20, a selective etching process is carried out by removing the photoresist in a position that will correspond to a prospective hole 12. In this selective etching process, oxide films (BPSG films 7, 10) are selectively etched with respect to nitride films (Si₃N₄films 5, 6), and therefore, as shown in FIG. 21, the Si₃N₄films 5, 6 are left on the bottom of the hole 12 formed without being etched. This etching process involves the use of a gas mixed with C4F2, CO, Ar and O2 or a gas to which CH2F2 and CHF3 are added. Note that a composition ratio of this gas is properly varied corresponding to a size (e.g., a width of the hole 12) of the device. The oxide films (the BPSG films 7, 10) are selectively etched with respect to the nitride films (the Si₃N₄films 5, 6) by executing the etching process using the gas described above.
A protection layer exhibiting a durability against the etching of the nitride film is formed, and, with the self alignment for forming the [0071] hole 11 by effecting the selective etching, the hole 12 is formed, whereby a width of the hole 11 can be set smaller than a width of the upper portion of the hole 12.
Moreover, an electrode layer of polysilicon having a thickness that is less than ½ the width of the [0072] hole 12, is formed by the CVD method, and unnecessary polysilicon is removed by the photolithography, with the result that an electrode 13 is formed as shown in FIG. 22.
Thereafter, an insulating film (a capacitor insulating film) [0073] 14 such as an oxide film and a nitride film is formed on the surface of the electrode 13 by thermal nitriding, thermal oxidation or the CVD method, etc., and finally an electrode 15 composed of polysilicon or the like is formed by the CVD method, etc. A DRAM is thereby completed with a structure illustrated in FIGS. 1, 9 and 10.
As stated above, in accordance with the second embodiment, the self alignment is used for forming the memory cell contact, thereby enabling the aperture area of the memory cell contact (the hole [0074] 12) to enlarge while keeping small the aperture area of the bottom surface (the hole 11) of the memory cell contact. Therefore, the memory cell contact can be provided on the gate electrode, whereby the side wall of the contact (the hole 12) can be used as a capacitor surface area. Accordingly, the surface area of the capacitor per unit chip area can be set larger than by the prior art.
Further, the aperture area of the [0075] hole 12 can be taken large, and hence it is feasible to enlarge the margin when holing the resists layer through the pattern transfer in the photolithography in the case of holing the memory cell contact.
Note that BPSG (borophosphosilicate glass: an oxide film to which boron and phosphorus are added) is used for the [0076] inter-layer films 7, 10 in the first and second embodiments discussed above, but the oxide films may also be used. In this case, the etching process with a high selectivity can be executed as in the case described above by changing the composition of the gas used for etching.

Third Embodiment

FIG. 23 is a view showing a structure of capacitors of the DRAM in accordance with a third embodiment of the present invention. FIG. 23 shows an X-X section in FIG. 1 and is, i.e., a sectional view corresponding to FIG. 9. In FIG. 23, the same or corresponding components as or to those in FIG. 9 are marked with the same numerals as those in FIG. 9. Further, a section corresponding to the Y-Y section is the same as FIG. 1 other than configurations of [0077] electrodes 13′, 15′ and is therefore omitted. Similarly, the plan view is the same as FIG. 1.
In the DRAM illustrated in FIGS. 1, 9 and [0078] 10, the electrode 13 of the capacitor has a flat surface. In the third embodiment, however, as shown in FIG. 23, the electrode 13′ has a rugged surface. This electrode 13′ is, as in the case of the electrode 13 shown in FIGS. 1, 9 and 10, composed of polysilicon and has a thickness that is less than ½ the width of the hole 12. A capacitor insulating film 14′ and an electrode 15′ also have rugged surfaces corresponding to the rugged surface of the electrode 13′.
The third embodiment exhibits the same effects as those in the first embodiment discussed above. Furthermore, the [0079] electrodes 13′, 15′ in the third embodiment are constructed to have the rugged surfaces, and it is therefore possible to have a larger surface area than by flatting the surfaces of those electrodes. This enables a further enlargement of the surface area of the capacitor per unit chip area.

Fourth Embodiment

A fourth embodiment of the present invention deals with a manufacturing method of manufacturing the DRAM having the construction shown in FIG. 22. According to this manufacturing method, to begin with, the same processes as the above steps shown in FIGS. [0080] 11-22, thereby obtaining a construction illustrated in FIG. 21.
Next, by using the CVD method, an electrode layer of polysilicon, etc. is formed in thickness that is less than ½ the width of the [0081] hole 12. On this occasion, after a flat layer has been formed by the ordinary CVD method, particles of, e.g., polysilicon, etc. are adhered onto this layer, thus forming a particled rough surface. Then, unnecessary polysilicon is removed by the photolithography, and thereupon, as shown in FIG. 24, the electrode 13′ having a rugged surface is formed.
Thereafter, when an insulating film (a capacitor insulating film) [0082] 14′ such as an oxide film and a nitride film is formed on the surface of the electrode 13′ by the thermal nitriding, the thermal oxidation or the CVD method, etc., the capacitor insulating film 14′ having a ruggedness corresponding to the ruggedness of the surface of the electrode 13′. Finally, an electrode 15 composed of polysilicon or the like is formed by the CVD method, and a DRAM having a structure shown in FIG. 23 is thereby completed.
The fourth embodiment exhibits the same effects as those in the second embodiment discussed above. Furthermore, the [0083] electrodes 13′, 15′ in the fourth embodiment are constructed to have the rugged surfaces, and it is therefore possible to have a larger surface area than by flatting the surfaces of those electrodes. This enables a further enlargement of the surface area of the capacitor per unit chip area.

Fifth Embodiment

FIGS. [0084] 25-27 are views showing a structure of capacitors of the DRAM in a fifth embodiment of the present invention. FIG. 25 is a top view of the DRAM. FIGS. 26 and 27 are views respectively schematically showing an X-X section and a Y-Y section.
In the DRAM with the construction shown in FIGS. 1, 9 and [0085] 10 or 23, the protection layer (the Si₃N₄films 5, 6, and the protection layer) is provided on only the electrode (the gate electrode) 4 of the lowest layer, and the memory cell contact (the hole 11) is holed based on the self alignment. In accordance with the fifth embodiment, however, a protection layer (Si₃N₄films 38, 39, and a second protection layer) is provided also on an electrode (a bit line) 37 of an upper layer, and a memory cell contact (a hole 41) is holed based on the self alignment.
Provided on a substrate (a semiconductor substrate) [0086] 31 are a field oxide film 2 for separation between elements and an electrode (a gate electrode) 33 formed on the field oxide film 32. An Si₃N₄film (a first protection layer) 34 is provided on this electrode 33, and a side wall 35 is provided extending from a side surface of the electrode 33 to a side surface of the Si₃N₄film 34.
Formed further on the Si[0087] ₃N₄film and the side wall 35 is an inter-layer film (an inter-layer insulating layer) 36 for separation from layers to be formed thereon. Formed on this inter-layer film 36 are an electrode (second signal line) 37, a Si₃N₄film (a second protection layer) 38 and a side wall 39, which have the same constructions as those of the electrode 4, the Si₃N₄film 5 and the side wall 6 that are shown in FIGS. 1, 9 and 10. Formed moreover on the Si₃N₄film 38 and the side wall 39 is an inter-layer film (an inter-layer insulating layer) 40 for separation from layers to be provided thereon. Note that the electrode 37 and the protection layers 38, 39, as illustrated in FIGS. 25 and 27, do not exist on the Y-Y section in FIG. 25.
Then, a hole (an opening) [0088] 42 is formed penetrating the inter-layer films 40, 36. A hole 41 through which to expose a part of a substrate 41 that is not covered with the protection layers 34, 35, is formed in the bottom of the hole 42. A capacitor for accumulating an electric charge corresponding to data to be held, is formed inwardly of this hole 42.
This capacitor comprises an electrode (a first conductive layer) [0089] 43 so provided on surfaces of the inter-layer films 36, 40 as to extend from the hole 41 along the periphery of the hole 42, and connected to the substrate 31 exposed from the hole 41. The capacitor also comprises a capacitor insulating film 44 formed on the surface of this electrode 33, and an electrode (a second conductive layer) 45 further provided thereon. Namely, the hole 41 serves as a memory cell contact for connecting the substrate 3 to the electrode 43.
The [0090] substrate 31 is composed of Si monocrystal. The field oxide film 32 is formed in thickness on the order of 2000-4000 A on this substrate 31 by the ordinary LOCOS method. The electrode 33 is composed of polysilicon or polycide and formed in thickness of approximately 1000-3000 A. The side wall 35 is composed of Si₃N₄as in the case of the Si₃N₄film 34, which have a thickness on the order of 1000-3000 A.
The [0091] inter-layer film 36 is composed of BPSG and is approximately 3000-5000 A in thickness. The electrode 37 is composed of polysilicon or polycide and has a thickness of approximately 1000-2000 A. This electrode 37 covered in thickness of approximately 1000-3000 A with the Si₃N₄film 38 and the Si₃N₄film 39 of the side wall. The inter-layer film 40 is composed of BPSG as in the case of the inter-layer film 36 and has a thickness of approximately 3000-5000 A. The electrode 43 is composed of polysilicon, etc. and has a thickness that is less than ½ the width of the hole 42.
The [0092] hole 41 is formed by high selection ratio etching to selectively etch the inter BPSG layer films 36, 40 with respect to the Si₃N₄films 38, 39. Further, this etching exhibits a high up-and-down directivity in FIG. 27, i.e., in the direction perpendicular to the sheet surface of FIG. 25, and, as illustrated in FIG. 26, the inter-layer film 36 covered with the Si₃N₄films 38, 39 are left without being etched. Therefore, an aperture area of the hole 41 is smaller than an aperture area of the upper portion of the hole 42.
As discussed above, in accordance with the fifth embodiment, the memory cell contact is formed involving the use of the self alignment, and it is therefore feasible to enlarge the aperture area of the memory cell contact (the hole [0093] 42) while keeping small the aperture area of the bottom surface (the hole 41) of the memory cell contact. The memory cell contact can be thereby formed on the gate electrode, and the side wall of the contact (the hole 42) can be used as a capacitor surface area by providing the gate electrode having a thickness less than ½ the width of the hole inwardly of the memory cell contact. Accordingly, the surface area of the capacitor per unit chip area can be set larger than by the prior art. An occupying area on the chip can be thereby reduced while keeping a capacity of the capacitor.
Further, the hole area of the [0094] hole 12 can be taken large, and hence a margin when holing the resist layer through a pattern transfer can be enlarged in the photolithography in the case of holing the memory cell contact.

Sixth Embodiment

A sixth embodiment of the present invention deals with a manufacturing method of manufacturing the DRAM having a construction shown in FIGS. [0095] 25-27. FIGS. 28-34 show respective steps of this manufacturing method.
According to this manufacturing method, to start with, a [0096] field oxide film 32 having a thickness of approximately 2000-4000 A is formed on a Si monocrystal semiconductor substrate 31. This step generally involves the use of the LOCOS method. Thereafter, as illustrated in FIG. 28, a gate oxide film x10 of MOS-Tr is formed in thickness of approximately 50-150 A.
Next, a layer x[0097] 11, which is composed of polysilicon or polycide and will become an electrode 33 afterward, is formed in thickness on the order of 1000-3000 A on the field oxide film 32 and the gate oxide film x10 by the CVD (Chemical Vapor Deposition) method. Then, as shown in FIG. 29, a Si₃N₄layer x12, which will become a Si₃N₄film 34 afterward, is formed in thickness of approximately 1000-3000 A on this layer x11.
Thereafter, the [0098] electrode 33, the Si₃N₄film 34 and the side wall 35 are formed by executing the same patterning process as those shown in FIG. 13-16. After this processing, as illustrated in FIG. 30, a BPSG film 36 is formed in thickness of approximately 3000-5000 A thereon by the CVD method, and the surface is flatted by effecting a flow.
Upon an end of flatting process, a layer of polysilicon or polycide and a Si[0099] ₃N₄layer are provided on the BPSG film 36. Then, by executing the same patterning process as the one described above, as shown in FIG. 31, an electrode 37, a Si₃N₄I film 38 and a side wall 39 are formed.
Thereafter, as shown in FIG. 32, a [0100] BPSG film 40 having a thickness of about 3000-5000 A is formed thereon by the CVD method, and the surface is flatted by effecting a flow. When the flatting process is ended, a photoresist layer x13 is provided on the BPSG film 40, and the photoresist of a portion corresponding to the hole 42 is removed.
After removing the photoresist, the selectivity etching is carried out. This selectivity etching is a process of selectively etching the oxide films (the [0101] BPSG films 36, 40) with respect to the nitride films (the Si₃N₄films 35, 36, 38, 39). Further, this etching exhibits a high directivity perpendicular to the sheet surface of FIG. 33, and, as shown in the Figure, the inter-layer film 36 covered with the Si₃N₄films 38, 39 is left without being etched. This etching process involves the use of a gas mixed with C₄F₈, CO, Ar, O₂, or a gas obtained by adding CH₂F₂, CHF₃thereto. Note that a composition ratio of this gas is properly varied corresponding to a size (e.g., a width of the hole) of the device. The oxide films (the BPSG films 7, 10) are selectively etched with respect to the nitride films (the Si₃N₄films 5, 6).
A protection layer exhibiting a durability against the etching of the nitride films (the Si[0102] ₃N₄films 38, 39) is formed, and, with the self alignment for forming the hole 41 by effecting the selective etching, the hole 42 is formed, whereby a width of the hole 41 can be set smaller than a width of the upper portion of the hole 12.
Thereafter, an electrode layer of polysilicon having a thickness less than ½ the width of the [0103] hole 12, is formed by the CVD method, and unnecessary polysilicon is removed by the photolithography, with the result that an electrode 43 is formed as shown in FIG. 34.
Thereafter, an insulating film (a capacitor insulating film) [0104] 44 such as an oxide film and a nitride film is formed on the surface of the electrode 43 by the thermal nitriding, the thermal oxidation or the CVD method, etc., and finally an electrode 45 composed of polysilicon or the like is formed by the CVD method, etc. A DRAM is thereby completed with a structure illustrated in FIGS. 25-27.
As mentioned above, in accordance with the sixth embodiment, the self alignment is used for forming the memory cell contact, thereby enabling the aperture area of the memory cell contact (the hole [0105] 12) to enlarge while keeping small the aperture area of the bottom surface (the hole 11) of the memory cell contact. Therefore, the gate electrode can be provided inwardly of the memory cell contact (the hole 12), whereby the side wall of the contact (the hole 12) can be used as a capacitor surface area. Accordingly, the surface area of the capacitor per unit chip area can be set larger than by the prior art.
Further, the aperture area of the [0106] hole 12 can be taken large, and hence it is feasible to enlarge the margin when holing the resists layer through the pattern transfer in the photolithography in the case of holing the memory cell contact.
Note that BPSG (borophosphosilicate glass: an oxide film to which boron and phosphorus are added) is used for the [0107] inter-layer films 36, 40 in the fifth and sixth embodiments discussed above, but the oxide films may also be used. In this case, the etching process with a high selectivity can be executed as in the case described above by changing the composition of the gas.

Seventh Embodiment

FIG. 35 is a view showing a structure of capacitors of the DRAM in accordance with a seventh embodiment of the present invention. FIG. 35 shows an X-X section in FIG. 25 and is, i.e., a sectional view corresponding to FIG. 26. In FIG. 35, the same or corresponding components as or to those in FIG. 26 are marked with the same numerals as those in FIG. 26. Further, a section corresponding to the Y-Y section is the same as FIG. 27 other than configurations of [0108] electrodes 43′, 45′ and is therefore omitted. Similarly, the plan view is the same as FIG. 25.
In the DRAM illustrated in FIGS. [0109] 25-27, the electrode 43 of the capacitor has a flat surface. In the seventh embodiment, however, as shown in FIG. 35, the electrode 43′ has a rugged surface. This electrode 43′ is, as in the case of the electrode 43 shown in FIGS. 25-27, composed of polysilicon and has a thickness less than ½ the width of the hole 42. A capacitor insulating film 44′ and an electrode 45′ also have rugged surfaces corresponding to the rugged surface of the electrode 43′.
The seventh embodiment exhibits the same effects as those in the fifth embodiment discussed above. Furthermore, the [0110] electrodes 43′, 45′ in this embodiment are constructed to have the rugged surfaces, and it is therefore possible to have a larger surface area than by flatting the surfaces of those electrodes. This enables a further enlargement of the surface area of the capacitor per unit chip area.

Eighth Embodiment

An eighth embodiment of the present invention deals with a manufacturing method of manufacturing the DRAM having the construction shown in FIG. 35. According to this manufacturing method, at first, the same processes as the above steps shown in FIGS. [0111] 28-33, thereby obtaining a construction illustrated in FIG. 33.
Next, by using the CVD method, an electrode layer of polysilicon, etc. is formed in thickness less than ½ the width of the [0112] hole 12. On this occasion, after a flat layer has been formed by the ordinary CVD method, particles of, e.g., polysilicon, etc. are adhered onto this layer, thus forming a particled rough surface. Then, unnecessary polysilicon is removed by the photolithography, and thereupon, as shown in FIG. 36, the electrode 43′ having a rugged surface is formed.
Thereafter, when an insulating film (a capacitor insulating film) [0113] 44′ such as an oxide film and a nitride film is formed on the surface of the electrode 43 by the thermal nitriding, the thermal oxidation or the CVD method, etc., the capacitor insulating film 44′ having a ruggedness corresponding to the ruggedness of the surface of the electrode 43′. Finally, an electrode 45 composed of polysilicon or the like is formed by the CVD method, and a capacitor having a structure shown in FIG. 35 is thereby completed.
The eighth embodiment exhibits the same effects as those in the sixth embodiment discussed above. Furthermore, the [0114] electrodes 43′, 45′ in the this embodiment are constructed to have the rugged surfaces, and it is therefore possible to have a larger surface area than by flatting the surfaces of those electrodes. This enables a further enlargement of the surface area of the capacitor per unit chip area.
Note that the protection layer is formed of the nitride film, and the intermediate layer is formed of BPSG in each embodiment discussed above. However, even when the protection layer is formed of the oxide film or a glass such as BPSG, the selection ratio of etching is adjusted by controlling a mixing ratio of the gas used for the etching process described above, thereby enabling a formation of the hole (the opening) an upper portion aperture area of which is larger than the area of the exposed substrate (the semiconductor substrate) in the same manner as the one described above. [0115]
According to the present invention, when forming the opening portion, the area of the upper portion of the hole can be set larger than the area of the semiconductor substrate that is exposed to the bottom of the hole. The capacitor is provided inwardly of this hole, whereby the area of the memory cell contact of the DRAM can be enlarged. Further, since the area of the upper portion of the hole can be enlarged, the aperture margin can be increased in the photolithography for the memory cell contact. [0116]
It is apparent that, in this invention, a wide range of different working modes can be formed based on the invention without deviating from the spirit and scope of the invention. This invention is not restricted by its specific working modes except being limited by the appended claims. [0117]

Claims

What is claimed is:

1. A semiconductor device comprising:

a semiconductor substrate;

a gate electrode formed on said semiconductor substrate and extending in a first direction;

a first protection layer formed along a side wall of said gate electrode as well as on said gate electrode, and exhibiting an insulating property;

an inter-layer insulating layer formed over said semiconductor substrate including said first protection layer, having an opening portion extending to said first protection layer and said semiconductor substrate as well, and exhibiting a selectivity for said first protection layer when in an etching process; and

a capacitor formed inwardly of said opening portion.

2. A semiconductor device according to claim 1, wherein said first protection layer is a nitride layer, and

said inter-layer insulating layer is an oxide layer.

3. A semiconductor device according to claim 1 or 2, wherein said capacitor is constructed of a first conductive layer connected to said semiconductor substrate and having a rugged surface;

a capacitor insulating film formed on said first conductive layer; and

a second conductive layer formed on said capacitor insulating film.

4. A semiconductor device according to any one of claims 1 through 3, wherein said inter-layer insulating layer is constructed of a first insulating layer and a second insulating layer formed on said first insulating layer,

said inter-layer insulating layer contains a bit line provided between said first insulating layer and said second insulating layer and extending in a direction substantially orthogonal to the first direction, and a second protection layer provided on said bit line and along a side wall of said bit line and exhibiting a selectivity with respect to said inter-layer insulating layer when in an etching process and also an insulating property, and

said opening portion extends to said second protection layer.

5. A method of manufacturing a semiconductor device, comprising:

a step of forming a gate insulating film and a gate electrode on a semiconductor substrate;

a step of forming a protection layer exhibiting an insulating property on an upper portion of said gate electrode and along a side wall thereof;

a step of forming an inter-layer insulating layer on said semiconductor substrate including said protection layer;

a step of forming an opening portion extending to said protection layer and to said semiconductor substrate by selectively etching said inter-layer insulting layer; and

a step of forming a capacitor inwardly of said opening portion.

6. A method of manufacturing a semiconductor device, comprising:

a step of forming a gate insulating film and a gate electrode extending in a first direction on a semiconductor substrate;

a step of forming a first protection layer exhibiting an insulating property on an upper portion of said gate electrode and along a side wall thereof;

a step of forming a first inter-layer insulating layer having a selectivity when in an etching process with respect to said first protection layer on said semiconductor substrate including said first protection layer;

a step of forming a bit line extending in a second direction substantially orthogonal to the first direction on said first inter-layer insulating layer;

a step of forming a second protection layer having the selectivity when in the etching process with respect to said first inter-layer insulating layer an upper portion of said bit line and along a side wall thereof;

a step of forming a second inter-layer insulating layer having the selectivity and an insulating property with respect to said first and second protection layers on sid first inter-layer insulating layer including said second protection layer;

a step of forming an opening portion extending to said first and second protection layers and said semiconductor substrate by selectively etching said first and second inter-layer insulating layers; and

a step of forming a capacitor inwardly of said opening portion.

7. A method of manufacturing a semiconductor device according to claim 5 or 6, wherein said capacitor forming step comprises:

a step of forming a conductive layer inwardly of said opening portion and forming a first conductive layer having a ruggedness by adhering conductive particles onto said conductive layer;

a step of forming capacitor insulating film on said first conductive layer; and

a step of forming a second conductive film on said capacitor insulating film.