[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

US12094939B2 - Semiconductor device having a gate electrode, an interlayer insulating film and a barrier metal provided in a trench - Google Patents

Semiconductor device having a gate electrode, an interlayer insulating film and a barrier metal provided in a trench Download PDF

Info

Publication number
US12094939B2
US12094939B2 US15/993,671 US201815993671A US12094939B2 US 12094939 B2 US12094939 B2 US 12094939B2 US 201815993671 A US201815993671 A US 201815993671A US 12094939 B2 US12094939 B2 US 12094939B2
Authority
US
United States
Prior art keywords
semiconductor
type
region
trench
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US15/993,671
Other versions
US20180358445A1 (en
Inventor
Yusuke Kobayashi
Naoyuki Ohse
Shinsuke Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Assigned to FUJI ELECTRIC CO., LTD. reassignment FUJI ELECTRIC CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HARADA, SHINSUKE, KOBAYASHI, YUSUKE, OHSE, NAOYUKI
Publication of US20180358445A1 publication Critical patent/US20180358445A1/en
Application granted granted Critical
Publication of US12094939B2 publication Critical patent/US12094939B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0869—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices

Definitions

  • Embodiments of the invention relate to a semiconductor device and a method of manufacturing a semiconductor device.
  • a vertical metal oxide semiconductor field effect transistor having a trench structure is fabricated (manufactured).
  • MOSFET metal oxide semiconductor field effect transistor
  • a trench structure formed orthogonally to a surface of a substrate enables the cell density per unit area to be increased to a greater extent than does a planar structure in which a channel is formed parallel to the surface of the substrate and therefore, the former enables the current density per unit area to be increased and is advantageous from an aspect of cost.
  • a trench structure is formed in a vertical MOSFET, the structure is such that inner walls of the trench are covered entirely by a gate insulating film to form the channel in a vertical direction and a portion of the gate insulating film at a bottom of the trench is near a drain electrode, whereby high electric field tends to be applied to the portion of the gate insulating film at the bottom of the trench.
  • a wide bandgap semiconductor material semiconductor material having a bandgap that is wider than that of silicon, e.g., silicon carbide (SiC)
  • SiC silicon carbide
  • a p + -type base region is provided between trenches, in a striped shape parallel to the trenches (for example, refer to Japanese Laid-Open Patent Publication No. 2009-260253).
  • a p + -type base region is provided at the bottom of the trench, in a striped shape parallel to the trench.
  • FIG. 12 is a cross-sectional view of a structure of a conventional silicon carbide semiconductor device.
  • the conventional silicon carbide semiconductor device depicted in FIG. 12 includes at a front surface (surface on a p-type base layer 1016 side) side of a semiconductor base (hereinafter, silicon carbide base) 200 containing silicon carbide, a MOS gate having a typical gate structure.
  • the silicon carbide base (semiconductor chip) 200 is formed by sequentially forming by epitaxial growth on an n + -type supporting substrate (hereinafter, n + -type silicon carbide substrate) 102 containing silicon carbide, silicon carbide layers constituting an n ⁇ -type drift layer 101 , an n-type region 1015 that is a current diffusion region, and the p-type base layer 1016 .
  • a first p + -type region 103 is selectively formed so as to entirely cover a bottom of a trench 1030 .
  • the first p + -type region 103 is provided at a depth not reaching the n ⁇ -type drift layer 101 .
  • Reference numerals 1017 , 1018 , 1019 , 1020 , 1021 , 1022 , 1025 , and 1028 are a first n + -type source region, a p + -type contact region, gate insulating film, a gate electrode, an interlayer insulating film, a source electrode pad, a barrier metal, and a source electrode, respectively.
  • a pn junction of the first p + -type region 103 and the n-type region 1015 is positioned deeper than the trench 1030 . Therefore, electric field concentrates at a boundary of the first p + -type region 103 and the n-type region 1015 , enabling electric field concentration at the bottom part of the trench 1030 to be mitigated.
  • a gate electrode and an interlayer insulating film are embedded in the trench, a top surface of the trench is planarized and at the top surface of the trench, the interlayer insulating film and a source contact region are made to be equal heights (for example, refer to Japanese Laid-Open Patent Publication No. 2016-040844, Japanese Laid-Open Patent Publication No. 2008-306095).
  • a semiconductor device includes a semiconductor substrate of a first semiconductor type; a first semiconductor layer of the first semiconductor type provided on a front surface of the semiconductor substrate; a second semiconductor layer of a second semiconductor type provided on a first side of the first semiconductor layer opposite a second side of the first semiconductor layer, the second side facing toward the semiconductor substrate; a first semiconductor region of the first semiconductor type selectively provided in second semiconductor layer, an impurity concentration of the first semiconductor region being higher than an impurity concentration of the semiconductor substrate; a trench penetrating the first semiconductor region and the second semiconductor layer, and reaching the first semiconductor layer; a gate electrode provided on the trench, via a gate insulating film; an interlayer insulating film provided on the gate electrode in the trench; a barrier metal provided on the interlayer insulating film in the trench; a first electrode in contact with the first semiconductor region, the second semiconductor layer, and the barrier metal; and a second electrode provided at a rear surface of the semiconductor substrate.
  • the first semiconductor region is constituted by an upper first semiconductor region and a lower first semiconductor region having respectively differing impurity concentrations determining conductivity.
  • the barrier metal contains TiN or Ti.
  • a thickness of the interlayer insulating film is at least 0.3 ⁇ m.
  • the semiconductor device further includes a second semiconductor region of the second semiconductor type selectively provided in the first semiconductor layer, the second semiconductor region being in contact with a bottom of the trench.
  • the second semiconductor region has a striped shape parallel to a width direction of the trench.
  • FIG. 1 is a cross-sectional view of a structure of a silicon carbide semiconductor device according to a first embodiment
  • FIG. 2 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture
  • FIG. 3 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture
  • FIG. 4 A is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture
  • FIG. 4 B is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture
  • FIG. 5 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture
  • FIG. 6 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture
  • FIG. 7 A is a cross-sectional view a structure of the silicon carbide semiconductor device according to a second embodiment, at cutting line X-X′ in FIG. 8 ;
  • FIG. 7 B is a cross-sectional view of the structure of the silicon carbide semiconductor device according to the second embodiment, at cutting line Y-Y′ in FIG. 8 ;
  • FIG. 7 C is a cross-sectional view of the structure of the silicon carbide semiconductor device according to the second embodiment, at cutting line Z-Z′ in FIG. 8 ;
  • FIG. 8 is a top view of the structure of the silicon carbide semiconductor device according to the second embodiment, at cutting line a-a′ in FIGS. 7 A to 7 C ;
  • FIG. 9 A is a cross-sectional view of the silicon carbide semiconductor device according to the second embodiment, at cutting line X-X′ in FIG. 8 during manufacture;
  • FIG. 9 B is a cross-sectional view of the silicon carbide semiconductor device according to the second embodiment, at cutting line Y-Y′ in FIG. 8 during manufacture;
  • FIG. 10 A is a cross-sectional view of the silicon carbide semiconductor device according to the second embodiment, at cutting line X-X′ in FIG. 8 during manufacture;
  • FIG. 10 B is a cross-sectional view of the silicon carbide semiconductor device according to the second embodiment, at cutting line Y-Y′ in FIG. 8 during manufacture;
  • FIG. 100 is a cross-sectional view of the silicon carbide semiconductor device according to the second embodiment, at cutting line Z-Z′ in FIG. 8 during manufacture;
  • FIG. 11 is a graph depicting a relationship of cell pitch and ON resistance of the silicon carbide semiconductor device according to the first to the fourth embodiments.
  • FIG. 12 is a cross-sectional view of a structure of a conventional silicon carbide semiconductor device.
  • the semiconductor device is configured using a semiconductor material (hereinafter, wide bandgap semiconductor material) that has a bandgap that is wider than a bandgap of silicon.
  • a semiconductor material hereinafter, wide bandgap semiconductor material
  • SiC silicon carbide
  • FIG. 1 is a cross-sectional view of a structure of the silicon carbide semiconductor device according to a first embodiment. In FIG. 1 , only two unit cells (function units of an element) are depicted, while other unit cells adjacent to these two unit cells are not depicted (similarly in FIGS. 7 A to 7 C ).
  • the silicon carbide semiconductor device according to the first embodiment depicted in FIG. 1 is a MOSFET that includes a MOS gate at a front surface (surface on a p-type base layer 16 side) side of a semiconductor base (silicon carbide base: semiconductor chip) 100 that contains silicon carbide.
  • the silicon carbide base 100 is formed by sequentially forming by epitaxial growth on an n + -type supporting substrate (n + -type silicon carbide substrate: semiconductor substrate of a first semiconductor type) 2 containing silicon carbide, silicon carbide layers respectively constituting an n ⁇ -type drift layer (first semiconductor layer of the first semiconductor type) 1 and a p-type base layer (second semiconductor layer of a second semiconductor type) 16 .
  • n + -type silicon carbide substrate semiconductor substrate of a first semiconductor type
  • silicon carbide layers respectively constituting an n ⁇ -type drift layer (first semiconductor layer of the first semiconductor type) 1 and a p-type base layer (second semiconductor layer of a second semiconductor type) 16 .
  • the MOS gate is constituted by the p-type base layer 16 , a first n + -type source region (first semiconductor region of the first semiconductor type) 17 , a second n + -type source region (first semiconductor region of the first semiconductor type) 24 , a p + -type contact region 18 , a trench 30 , a gate insulating film 19 , and a gate electrode 20 .
  • an n-type region 15 is provided so as to be in contact with the p-type base layer 16 .
  • the n-type region 15 is a current diffusing layer, a so-call current spreading layer (CSL) that reduces carrier spreading resistance.
  • the n-type region 15 for example, is provided uniformly along a direction (hereinafter, lateral direction) parallel to a base front surface (front surface of the silicon carbide base 100 ).
  • a first p + -type region 3 and a second p + -type region 4 are selectively provided.
  • the first p + -type region 3 is provided so as to be in contact with a bottom surface of the trench 30 described hereinafter.
  • the first p + -type region 3 is provided from a position deeper toward a drain electrode 29 than is an interface of the p-type base layer 16 and the n-type region 15 , to a depth not reaching an interface of the n-type region 15 and the n ⁇ -type drift layer 1 .
  • Provision of the first p + -type region 3 enables formation of a pn junction between the first p + -type region 3 and the n-type region 15 , near the bottom surface of the trench 30 .
  • the first p + -type region 3 is doped with, for example, aluminum and has an impurity concentration that is higher than an impurity concentration of the p-type base layer 16 .
  • a width of the first p + -type region 3 is equal to or wider than a width of the trench 30 .
  • Each first p + -type region 3 may partially extend toward adjacent trenches 30 , whereby the first p + -type regions 3 are connected.
  • the second p + -type region 4 is partially provided in a surface layer of the n-type region 15 , and a bottom of the second p + -type region 4 is in contact with the first p + -type region 3 (refer to FIG. 4 B ). Further, the second p + -type region 4 is in contact with a side wall of the trench 30 (refer to FIG. 7 C of a second embodiment).
  • the second p + -type region 4 is doped with, for example, aluminum and an impurity concentration of the second p + -type region 4 is higher than the impurity concentration of the p-type base layer 16 .
  • an n + -type source region and a p + -type contact region 18 are selectively provided so as to be in contact with each other.
  • the n + -type source region is constituted by a first n + -type source region 17 and a second n + -type source region 24 in contact with each other.
  • the first n + -type source region 17 is provided in a surface layer of the p-type base layer 16 .
  • the second n + -type source region 24 is provided at a position deeper toward the drain electrode 29 than is the first n + -type source region 17 , and a width of the second n + -type source region 24 is narrower than a width of the first n + -type source region 17 .
  • a depth of the p + -type contact region 18 may be, for example, equal to or deeper than a depth of the second n + -type source region 24 .
  • the first n + -type source region 17 has an impurity concentration that is lower than an impurity concentration of the second n + -type source region 24 , and has a type of impurity different from that of the second n + -type source region 24 .
  • the first n + -type source region 17 is implanted with phosphorus (P) or arsenic (As), and the second n + -type source region 24 is implanted with nitrogen (N 2 ). Provision of the first n + -type source region 17 and the second n + -type source region 24 enables a source region to be provided deeply, thereby enabling the trench 30 to be provided deeply.
  • the trench 30 penetrates the first n + -type source region 17 , the second n + -type source region 24 and the p-type base layer 16 from the base front surface, and reaches the n-type region 15 and the first p + -type region 3 .
  • the gate insulating film 19 is provided along side walls of the trench 30
  • the gate electrode 20 is provided on the gate insulating film 19 .
  • the gate electrode 20 is electrically connected at a non-depicted part to a gate pad (not depicted).
  • an interlayer insulating film 21 containing silicon dioxide (SiO 2 ) is provided in the trench 30 .
  • a thickness of the interlayer insulating film 21 may be 0.3 ⁇ m or greater. Provision of the interlayer insulating film 21 having this thickness or greater enables the gate electrode 20 and the source electrode 28 to be insulated.
  • a barrier metal 25 is provided that prevents diffusion of metal atoms, for example, nickel (Ni), from the source electrode 28 toward the gate electrode 20 .
  • the barrier metal 25 is formed by, for example, titanium nitride (TiN), Ti, etc.
  • the interlayer insulating film 21 and the barrier metal 25 are embedded, enabling the front surface of the silicon carbide base 100 to be planarized.
  • an Ni film 26 and a Ti film 27 are provided in order stated.
  • the Ni film 26 and the Ti film 27 constitute the source electrode (first electrode) 28 , are in contact with the n + -type source region 17 and the p + -type contact region 18 , and are electrically insulated from the gate electrode 20 by the interlayer insulating film 21 .
  • the source electrode pad 22 containing, for example, Al—Si is provided.
  • the drain electrode 29 second electrode
  • FIGS. 2 , 3 , 4 , 5 , and 6 are cross-sectional views of the silicon carbide semiconductor device according to the first embodiment during manufacture.
  • the n + -type silicon carbide substrate 2 constituting the n + -type drain region is prepared.
  • the n + -type silicon carbide substrate 2 is prepared having an impurity concentration in a range from 1 ⁇ 10 18 to 1 ⁇ 10 20 /cm 3 and a thickness in a range from 100 ⁇ m to 700 ⁇ m.
  • the n ⁇ -type drift layer 1 is formed by epitaxial growth.
  • conditions of the epitaxial growth for forming the n ⁇ -type drift layer 1 may be set so that an impurity concentration of the n ⁇ -type drift layer 1 is in a range from 3 ⁇ 10 15 to 5 ⁇ 10 16 /cm 3 , and a film thickness of the n ⁇ -type drift layer 1 in a range from about 5 ⁇ m to 40 ⁇ m.
  • the state up to here is depicted in FIG. 2 .
  • the first p + -type region 3 is selectively formed in a surface layer of the n ⁇ -type drift layer 1 .
  • a dose amount at the time of ion implantation for forming the first p + -type region 3 may be set so that an impurity concentration thereof is in a range from 1 ⁇ 10 17 to 1 ⁇ 10 19 /cm 3 , and a depth of the first p + -type region 3 is in a range from 0.1 ⁇ m to 1.0 ⁇ m, and a width of the first p + -type region 3 is in a range from 0.5 ⁇ m to 2.0 ⁇ m.
  • a lower n-type region 15 a is selectively formed in a surface layer of the n ⁇ -type drift layer 1 .
  • the lower n-type region 15 a is a part of the n-type region 15 .
  • a dose amount at the time of ion implantation for forming the lower n-type region 15 a may be set so that an impurity concentration of the lower n-type region 15 a is in a range from 1 ⁇ 10 16 to 1 ⁇ 10 18 /cm 3 , and a depth of the lower n-type region 15 a is in a range from 0.1 ⁇ m to 1.5 ⁇ m.
  • the state up to here is depicted in FIG. 3 .
  • an n-type region is formed by epitaxial growth.
  • conditions of the epitaxial growth for forming the n-type region may be set so that an impurity concentration of the n-type region is in a range from 3 ⁇ 10 16 to 5 ⁇ 10 16 /cm 3 , and a thickness of the n-type region is in a range from 0.3 ⁇ m to 0.6 ⁇ m.
  • the n-type region is formed by ion implantation described hereinafter and constitutes a part of the n-type region 15 .
  • the second p + -type region 4 is selectively formed in a surface layer of the n-type region.
  • a dose amount at the time of ion implantation for forming the second p + -type region 4 may be set so that an impurity concentration of the second p + -type region 4 is in a range from 1 ⁇ 10 17 to 1 ⁇ 10 19 /cm 3 , a depth of the second p + -type region 4 is in a range from 0.1 ⁇ m to 1.0 ⁇ m, and a width of the second p + -type region 4 is in a range from 0.5 ⁇ m to 2.0 ⁇ m.
  • an upper n-type region 15 b is selectively provided in the surface layer of the n-type region.
  • a dose amount at the time of ion implantation for forming the upper n-type region 15 b may be set so that an impurity concentration of the upper n-type region 15 b is in a range from 1 ⁇ 10 16 to 1 ⁇ 10 18 /cm 3 , and a depth of the upper n-type region 15 b is in a range from 0.1 ⁇ m to 1.5 ⁇ m.
  • the lower n-type region 15 a and the upper n-type region 15 b combined constitute the n-type region 15 .
  • the state up to here is depicted in FIGS. 4 A and 4 B .
  • FIGS. 4 A and 4 B are cross-sectional views at differing positions at a same at manufacturing stage.
  • the p-type base layer 16 is formed by epitaxial growth.
  • conditions of the epitaxial growth for forming the p-type base layer 16 may be set so that the impurity concentration of the p-type base layer 16 is in a range from 5 ⁇ 10 16 to 1 ⁇ 10 18 /cm 3 , and a thickness of the p-type base layer 16 is in a range from 0.7 ⁇ m to 2.1 ⁇ m.
  • the second n + -type source region 24 is selectively formed in the surface layer of the p-type base layer 16 .
  • a dose amount at the time of ion implantation for forming the second n + -type source region 24 may be set so that an impurity concentration of the second n + -type source region 24 is in a range from 1 ⁇ 10 17 to 1 ⁇ 10 19 /cm 3 , a depth of the second n + -type source region 24 is in a range from 0.6 ⁇ m to 1.1 ⁇ m, and a width of the second n + -type source region 24 is in a range from 240.5 ⁇ m to 1.5 ⁇ m.
  • the first n + -type source region 17 is selectively formed in the surface layer of the p-type base layer 16 .
  • a dose amount at the time of ion implantation for forming the first n + -type source region 17 may be set so that an impurity concentration of the first n + -type source region 17 is in a range from 1 ⁇ 10 18 to 1 ⁇ 10 20 /cm 3 , and a depth of the first n + -type source region 17 is in a range from 0.3 ⁇ m to 0.6 ⁇ m.
  • the p + -type contact region 18 is selectively formed in the surface layer of the p-type base layer 16 .
  • a dose amount at the time of ion implantation for forming the p + -type contact region 18 may be set so that an impurity concentration of the p + -type contact region 18 is in a range from 1 ⁇ 10 18 to 1 ⁇ 10 20 /cm 2 , and a depth of the p + -type contact region 18 is in a range from 0.3 ⁇ m to 0.6 ⁇ m.
  • the state up to here is depicted in FIG. 5 .
  • a carbon coating layer called a carbon cap is formed on a surface of the silicon carbide base 100 and activation annealing is performed.
  • the carbon cap is removed and by photolithography and etching, the trench 30 is formed penetrating the first n + -type source region 17 , the second n + -type source region 24 and the p-type base layer 16 , and reaching the n-type region 15 and the first p + -type region 3 .
  • isotropic etching for removing damage of the trenches 30 and hydrogen annealing for rounding the bottom part of the trenches 30 and openings of the trenches 30 may be performed. Either the isotropic etching or the hydrogen annealing may be performed. Alternatively, after the isotropic etching is performed, the hydrogen annealing may be performed.
  • the gate insulating film 19 is formed along an inner wall of the trench 30 .
  • the gate insulating film 19 may be formed by thermal oxidation by heat treatment in an oxygen atmosphere at a temperature of about 1200 degrees C.
  • the gate insulating film 19 may be formed by a deposition method such as by a chemical reaction like that for a high temperature oxide (HTO).
  • post oxidation annealing (POA) in an atmosphere containing hydrogen or water vapor may be performed.
  • poly-silicon is deposited so as to be embedded in the trenches 30 and is etched, whereby the poly-silicon remains in the trenches 30 , and forms the gate electrodes 20 . At this time, etching is performed so that the poly-silicon remains deeper than the surface of the silicon carbide base 100 .
  • SiO 2 is deposited and etched so as to be embedded on the poly-silicon in the trenches 30 , whereby the SiO 2 is left forming the interlayer insulating film 21 in the trenches 30 .
  • etching may be performed so that the SiO 2 is left up to the surface of the silicon carbide base 100 .
  • CMP chemical mechanical polishing
  • formation may be by etching by thickly stacking a resist.
  • the interlayer insulating film 21 is dry etched from the surface of the silicon carbide base 100 , to a predetermined depth of, for example, within 0.1 ⁇ m. The state up to here is depicted in FIG. 6 .
  • the barrier metal 25 for example, TiN is deposited so as to be embedded on the interlayer insulating film 21 in the trench 30 and by a CMP process, is left up to the surface of the silicon carbide base 100 .
  • the Ni film 26 is formed on the front surface side of the silicon carbide base 100 .
  • a silicon carbide semiconductor part the first n + -type source region 17 and the p + -type contact region 18
  • the Ni film 26 are caused to react and form a nickel silicide film, whereby an ohmic contact is formed with the silicon carbide semiconductor part.
  • the Ti film 27 is formed as the source electrode, and the source electrode pad 22 , which is an Al—Si film is formed.
  • the Ti film 27 is formed by a sputtering method, and the Al—Si film is formed by sputtering to a top of the Ti film 27 .
  • a metal film such as a nickel (Ni) film, a titanium (Ti) film, etc. is formed.
  • the metal film may be constituted by a combination of multiple Ni and Ti films.
  • annealing such as rapid thermal annealing (RTA) is performed to convert the metal film into a silicide and form an ohmic contact.
  • RTA rapid thermal annealing
  • a thick film constituted by a Ti film, an Ni film, and a gold (Au) film sequentially stacked in order stated is formed by electron beam (EB) deposition, etc., whereby the drain electrode 29 is formed.
  • EB electron beam
  • the gate electrode, the interlayer insulating film, and the barrier metal are embedded in the trench.
  • a thickness of the interlayer insulating film may be adjusted by a length of the trench and even when the cell pitch is reduced, insulation of the gate electrode and the source electrode may be ensured. Therefore, decreases in semiconductor device yield due to degradation of insulation between the gate electrode and the source electrode may be resolved.
  • the surface of the semiconductor base is flat, plating is facilitated and nickel silicide coverage also improves.
  • the mathematical area of contact between the first n + -type source region and the nickel silicide increases and the contact resistance decreases. Therefore, even when the cell pitch is 4.0 ⁇ m or less, for example, 1.5 ⁇ m, the ON resistance does not increase and there is no need to use a tungsten plug.
  • the first n + -type source region and the second n + -type source region are provided and formed by ion implanting P or As in the first n + -type source region, and implanting N 2 in the second n + -type source region.
  • the source region may be provided deeply, and the length of the trench may be increased. Therefore, the gate electrode, the interlayer insulating film, and the barrier metal may be embedded in the trench.
  • FIGS. 7 A, 7 B , and FIG. 7 C are cross-sectional views of a structure of the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 8 is a top view of the structure of the silicon carbide semiconductor device according to the second embodiment, at cutting line a-a′ in FIGS. 7 A to 7 C .
  • FIG. 7 A is a cross-sectional view at cutting line X-X′ in FIG. 8
  • FIG. 7 B is a cross-sectional view at cutting line Y-Y′ in FIG. 8
  • FIG. 7 C is a cross-sectional view at cutting line Z-Z′ in FIG. 8 .
  • the silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that positions and shapes of the first p + -type region 3 and the second p + -type region 4 in the n-type region 15 differ from those in the first embodiment.
  • the first p + -type region 3 is provided to be in contact with the n ⁇ -type drift layer 1 and the bottoms of the trenches 30 . Further, as depicted in FIG. 8 , the first p + -type region 3 has a striped shape along a width direction of the trenches 30 . Further, as depicted in FIG. 7 C , the second p + -type region 4 is selectively provided on an upper side (side toward the source electrode 28 ) of the first p + -type region 3 , between adjacent trenches 30 . Provision of the first p + -type region 3 in a striped shape along the width direction of the trenches 30 enables alignment deviations of the second p + -type region 4 and the trench 30 with the first p + -type region 3 to be prevented.
  • FIGS. 9 A, 9 B, 10 A, 10 B, and 10 C are cross-sectional views of the silicon carbide semiconductor device according to the second embodiment during manufacture.
  • the method of manufacturing the silicon carbide semiconductor device according to the second embodiment differs from the method of manufacturing the silicon carbide semiconductor device according to the first embodiment in the method of forming the first p + -type region 3 and the second p + -type region 4 .
  • the processes of preparing the n + -type silicon carbide substrate 2 to forming the n ⁇ -type drift layer 1 by epitaxial growth are sequentially performed (refer to FIG. 2 ).
  • the lower n-type region 15 a is formed by epitaxial growth.
  • conditions of the epitaxial growth for forming the lower n-type region 15 a may be set so that the impurity concentration of the lower n-type region 15 a is in a range from 1 ⁇ 10 16 to 1 ⁇ 10 18 /cm 3 , and the thickness of the lower n-type region 15 a is in a range from 0.1 ⁇ m to 1.5 ⁇ m.
  • the first p + -type region 3 having striped shaped is selectively formed in the surface layer of the lower n-type region 15 a .
  • a dose amount at the time of ion implantation for forming the first p + -type region 3 may be set so that the impurity concentration of the first p + -type region 3 is in a range from 1 ⁇ 10 17 to 1 ⁇ 10 19 /cm 3 , the depth of the first p + -type region 3 is in a range from 0.1 ⁇ m to 1.5 ⁇ m, and the width of the first p + -type region 3 is in a range from 0.5 ⁇ m to 2.0 ⁇ m.
  • FIGS. 9 A and 9 B The state up to here is depicted in FIGS. 9 A and 9 B .
  • FIG. 9 A is a cross-sectional view at cutting line X-X′ in FIG. 8 ; and
  • FIG. 9 B is a cross-sectional view at cutting line Y-Y′ in FIG. 8 .
  • the upper n-type region 15 b is formed by epitaxial growth.
  • conditions of the epitaxial growth for forming the upper n-type region 15 b may be set so that the impurity concentration of the upper n-type region 15 b is in a range from 1 ⁇ 10 16 to 1 ⁇ 10 18 /cm 3 , and a thickness of the upper n-type region 15 b is in a range from 0.3 ⁇ m to 0.6 ⁇ m.
  • the lower n-type region 15 a and the upper n-type region 15 b combined constitute the n-type region 15 .
  • the second p + -type region 4 is selectively formed in the surface layer of the upper n-type region 15 b .
  • a dose amount at the time of ion implantation for forming the second p + -type region 4 may be set so that the impurity concentration of the second p + -type region 4 is in a range from 1 ⁇ 10 17 to 1 ⁇ 10 19 /cm 3 , the depth of the second p + -type region 4 is in a range from 0.1 ⁇ m to 1.0 ⁇ m, and the width of the second p + -type region 4 is in a range from 0.5 ⁇ m to 2.0 ⁇ m.
  • FIGS. 10 A to 10 C The state up to here is depicted in FIGS. 10 A to 10 C .
  • FIG. 10 A is a cross-sectional view at cutting line X-X′ in FIG. 8 ;
  • FIG. 10 B is a cross-sectional view at cutting line Y-Y′ in FIG. 8 ;
  • FIG. 100 is a cross-sectional view at cutting line Z-Z′ in FIG. 8 .
  • the first p + -type region is provided in a striped shape along the width direction of the trenches. As a result, alignment deviations of the first p + -type region and the trenches may be prevented. Therefore, since there is no need to form the first p + -type region excessively large for alignment, the cell pitch of the semiconductor device may be reduced.
  • FIG. 11 is a graph depicting a relationship of cell pitch and ON resistance of the silicon carbide semiconductor device according to the first and the second embodiments.
  • FIG. 11 depicts results of simulation where a thickness of the n + -type silicon carbide substrate 2 is assumed to be 150 ⁇ m, a drain current density Jc is assumed to be 300 A/cm 2 , and forward voltage Vth is assumed to be 5V.
  • a horizontal axis represents the cell pitch of the silicon carbide semiconductor device in units of ⁇ m, while a vertical axis represents ON resistance (RonA) per unit active area in units of m ⁇ cm 2 .
  • RonA ON resistance
  • the ON resistance decreases as the cell pitch decreases.
  • the present invention enables a silicon carbide semiconductor device having a cell pitch of less than 4 ⁇ m to be provided and thus, may provide a silicon carbide semiconductor device having a lower ON resistance.
  • the gate electrode, the interlayer insulating film, and the barrier metal are embedded in the trench.
  • the thickness of the interlayer insulating film may be adjusted by the length of the trench and even when the cell pitch is reduced, insulation of the gate electrode and the source electrode may be ensured. Therefore, decreases in semiconductor device yield due to degradation of insulation between the gate electrode and the source electrode may be resolved.
  • the surface of the semiconductor base is flat, plating is facilitated and nickel silicide coverage also improves.
  • the mathematical area of contact between the first n + -type source region (first semiconductor region of the first semiconductor type) and the nickel silicide increases and the contact resistance decreases. Therefore, even when the cell pitch is 4.0 ⁇ m or less, for example, 1.5 ⁇ m, the ON resistance does not increase and there is no need to use a tungsten plug.
  • the first n + -type source region and the second n + -type source region are provided and formed by ion implanting P or As in the first n + -type source region, and implanting N 2 in the second n + -type source region.
  • the source region may be provided deeply, and the length of the trench may be increased. Therefore, the gate electrode, the interlayer insulating film, and the barrier metal may be embedded in the trench.
  • the semiconductor device and the method of manufacturing a semiconductor device according to the embodiments of the invention achieve an effect in that without increases in the ON resistance, the cell pitch may be made less than 4.0 ⁇ m and the reliability is high.
  • the semiconductor device and the method of manufacturing a semiconductor device according to the embodiments of the present invention are useful for power semiconductor devices used in power converting equipment and power supply devices such as in various types of industrial machines, and are particularly suitable for silicon carbide semiconductor devices having a trench gate structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

At a front surface of a silicon carbide base, an n−-type drift layer, a p-type base layer, a first n+-type source region, a second n+-type source region, and a trench that penetrates the first and the second n+-type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided in the trench on the gate electrode, and a barrier metal is provided in the trench on the interlayer insulating film.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2017-114766, filed on Jun. 9, 2017, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION 1. Field of the Invention
Embodiments of the invention relate to a semiconductor device and a method of manufacturing a semiconductor device.
2. Description of the Related Art
Conventionally, in a power semiconductor element, to facilitate reductions in element ON resistance, a vertical metal oxide semiconductor field effect transistor (MOSFET) having a trench structure is fabricated (manufactured). In the vertical MOSFET, a trench structure formed orthogonally to a surface of a substrate enables the cell density per unit area to be increased to a greater extent than does a planar structure in which a channel is formed parallel to the surface of the substrate and therefore, the former enables the current density per unit area to be increased and is advantageous from an aspect of cost.
Nonetheless, when a trench structure is formed in a vertical MOSFET, the structure is such that inner walls of the trench are covered entirely by a gate insulating film to form the channel in a vertical direction and a portion of the gate insulating film at a bottom of the trench is near a drain electrode, whereby high electric field tends to be applied to the portion of the gate insulating film at the bottom of the trench. In particular, with a wide bandgap semiconductor material (semiconductor material having a bandgap that is wider than that of silicon, e.g., silicon carbide (SiC)), an ultra-high voltage element is fabricated and therefore, adverse effects on the gate insulating film at the bottom of the trench significantly reduce reliability.
According to a technique proposed as a method to solve such problems, in a vertical MOSFET with a trench structure having a striped planar pattern, a p+-type base region is provided between trenches, in a striped shape parallel to the trenches (for example, refer to Japanese Laid-Open Patent Publication No. 2009-260253). According to another proposed technique, a p+-type base region is provided at the bottom of the trench, in a striped shape parallel to the trench.
FIG. 12 is a cross-sectional view of a structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device depicted in FIG. 12 includes at a front surface (surface on a p-type base layer 1016 side) side of a semiconductor base (hereinafter, silicon carbide base) 200 containing silicon carbide, a MOS gate having a typical gate structure. The silicon carbide base (semiconductor chip) 200 is formed by sequentially forming by epitaxial growth on an n+-type supporting substrate (hereinafter, n+-type silicon carbide substrate) 102 containing silicon carbide, silicon carbide layers constituting an n−-type drift layer 101, an n-type region 1015 that is a current diffusion region, and the p-type base layer 1016.
In the n-type region 1015, a first p+-type region 103 is selectively formed so as to entirely cover a bottom of a trench 1030. The first p+-type region 103 is provided at a depth not reaching the n−-type drift layer 101. Reference numerals 1017, 1018, 1019, 1020, 1021, 1022, 1025, and 1028 are a first n+-type source region, a p+-type contact region, gate insulating film, a gate electrode, an interlayer insulating film, a source electrode pad, a barrier metal, and a source electrode, respectively.
In a vertical MOSFET having the structure depicted in FIG. 12 , a pn junction of the first p+-type region 103 and the n-type region 1015 is positioned deeper than the trench 1030. Therefore, electric field concentrates at a boundary of the first p+-type region 103 and the n-type region 1015, enabling electric field concentration at the bottom part of the trench 1030 to be mitigated.
According to one technique, in a trench-type vertical MOSFET, a gate electrode and an interlayer insulating film are embedded in the trench, a top surface of the trench is planarized and at the top surface of the trench, the interlayer insulating film and a source contact region are made to be equal heights (for example, refer to Japanese Laid-Open Patent Publication No. 2016-040844, Japanese Laid-Open Patent Publication No. 2008-306095).
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a semiconductor device includes a semiconductor substrate of a first semiconductor type; a first semiconductor layer of the first semiconductor type provided on a front surface of the semiconductor substrate; a second semiconductor layer of a second semiconductor type provided on a first side of the first semiconductor layer opposite a second side of the first semiconductor layer, the second side facing toward the semiconductor substrate; a first semiconductor region of the first semiconductor type selectively provided in second semiconductor layer, an impurity concentration of the first semiconductor region being higher than an impurity concentration of the semiconductor substrate; a trench penetrating the first semiconductor region and the second semiconductor layer, and reaching the first semiconductor layer; a gate electrode provided on the trench, via a gate insulating film; an interlayer insulating film provided on the gate electrode in the trench; a barrier metal provided on the interlayer insulating film in the trench; a first electrode in contact with the first semiconductor region, the second semiconductor layer, and the barrier metal; and a second electrode provided at a rear surface of the semiconductor substrate.
In the embodiment, the first semiconductor region is constituted by an upper first semiconductor region and a lower first semiconductor region having respectively differing impurity concentrations determining conductivity.
In the embodiment, the barrier metal contains TiN or Ti.
In the embodiment, a thickness of the interlayer insulating film is at least 0.3 μm.
In the embodiment, the semiconductor device further includes a second semiconductor region of the second semiconductor type selectively provided in the first semiconductor layer, the second semiconductor region being in contact with a bottom of the trench.
In the embodiment, the second semiconductor region has a striped shape parallel to a width direction of the trench.
Objects, features, and advantages of the present invention are specifically set forth in or will become apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view of a structure of a silicon carbide semiconductor device according to a first embodiment;
FIG. 2 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture;
FIG. 3 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture;
FIG. 4A is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture;
FIG. 4B is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture;
FIG. 5 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture;
FIG. 6 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment during manufacture;
FIG. 7A is a cross-sectional view a structure of the silicon carbide semiconductor device according to a second embodiment, at cutting line X-X′ in FIG. 8 ;
FIG. 7B is a cross-sectional view of the structure of the silicon carbide semiconductor device according to the second embodiment, at cutting line Y-Y′ in FIG. 8 ;
FIG. 7C is a cross-sectional view of the structure of the silicon carbide semiconductor device according to the second embodiment, at cutting line Z-Z′ in FIG. 8 ;
FIG. 8 is a top view of the structure of the silicon carbide semiconductor device according to the second embodiment, at cutting line a-a′ in FIGS. 7A to 7C;
FIG. 9A is a cross-sectional view of the silicon carbide semiconductor device according to the second embodiment, at cutting line X-X′ in FIG. 8 during manufacture;
FIG. 9B is a cross-sectional view of the silicon carbide semiconductor device according to the second embodiment, at cutting line Y-Y′ in FIG. 8 during manufacture;
FIG. 10A is a cross-sectional view of the silicon carbide semiconductor device according to the second embodiment, at cutting line X-X′ in FIG. 8 during manufacture;
FIG. 10B is a cross-sectional view of the silicon carbide semiconductor device according to the second embodiment, at cutting line Y-Y′ in FIG. 8 during manufacture;
FIG. 100 is a cross-sectional view of the silicon carbide semiconductor device according to the second embodiment, at cutting line Z-Z′ in FIG. 8 during manufacture;
FIG. 11 is a graph depicting a relationship of cell pitch and ON resistance of the silicon carbide semiconductor device according to the first to the fourth embodiments; and
FIG. 12 is a cross-sectional view of a structure of a conventional silicon carbide semiconductor device.
 DETAILED DESCRIPTION OF THE INVENTION
First, problems associated with the related arts will be described. With the described conventional structure, making a cell pitch less than 4.0 μm is difficult. To reduce the cell pitch, a distance X between adjacent source electrodes 1028 depicted in FIG. 12 or a distance Y between a source electrode 1028 and the trench 1030 has to be reduced.
For example, when X is reduced, contact holes become narrower. Therefore, coverage for aluminum (Al) constituting the source electrode pad 1022 degrades and plating becomes difficult. Further, nickel silicide coverage of the source electrode 1028 degrades and contact resistance increases. Further, coverage for the barrier metal 1025 degrades and reliability decreases. While use of a tungsten (W) plug may circumvent these problems, W has high resistivity and therefore, ON resistance may increase.
On the other hand, when Y is decreased, a distance between the gate electrode 1020 and the source electrode 1028 decreases and therefore, Al and poly-silicon (Poly-Si) constituting the gate electrode 1020 have a higher risk of shorting. The poly-silicon and nickel silicide constituting the source electrode 1028 also have a higher risk of shorting. As a result, insulation between the gate electrode 1020 and the source electrode 1028 degrades, whereby yield of the semiconductor device may decrease.
Embodiments of a semiconductor device and a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. Additionally, + or − appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or −. In the description of the embodiments below and the accompanying drawings, main portions that are identical will be given the same reference numerals and will not be repeatedly described.
The semiconductor device according to embodiments of the present invention is configured using a semiconductor material (hereinafter, wide bandgap semiconductor material) that has a bandgap that is wider than a bandgap of silicon. Here, a structure of a semiconductor device (silicon carbide semiconductor device) that uses, for example, silicon carbide (SiC) as a wide bandgap semiconductor material will be described as an example. FIG. 1 is a cross-sectional view of a structure of the silicon carbide semiconductor device according to a first embodiment. In FIG. 1 , only two unit cells (function units of an element) are depicted, while other unit cells adjacent to these two unit cells are not depicted (similarly in FIGS. 7A to 7C). The silicon carbide semiconductor device according to the first embodiment depicted in FIG. 1 is a MOSFET that includes a MOS gate at a front surface (surface on a p-type base layer 16 side) side of a semiconductor base (silicon carbide base: semiconductor chip) 100 that contains silicon carbide.
The silicon carbide base 100 is formed by sequentially forming by epitaxial growth on an n+-type supporting substrate (n+-type silicon carbide substrate: semiconductor substrate of a first semiconductor type) 2 containing silicon carbide, silicon carbide layers respectively constituting an n−-type drift layer (first semiconductor layer of the first semiconductor type) 1 and a p-type base layer (second semiconductor layer of a second semiconductor type) 16. The MOS gate is constituted by the p-type base layer 16, a first n+-type source region (first semiconductor region of the first semiconductor type) 17, a second n+-type source region (first semiconductor region of the first semiconductor type) 24, a p+-type contact region 18, a trench 30, a gate insulating film 19, and a gate electrode 20. In particular, in a surface layer on a source side (side toward a source electrode 28) of the n−-type drift layer 1, an n-type region 15 is provided so as to be in contact with the p-type base layer 16. The n-type region 15 is a current diffusing layer, a so-call current spreading layer (CSL) that reduces carrier spreading resistance. The n-type region 15, for example, is provided uniformly along a direction (hereinafter, lateral direction) parallel to a base front surface (front surface of the silicon carbide base 100).
In the n-type region 15, a first p+-type region 3 and a second p+-type region 4 (not depicted) are selectively provided. The first p+-type region 3 is provided so as to be in contact with a bottom surface of the trench 30 described hereinafter. The first p+-type region 3 is provided from a position deeper toward a drain electrode 29 than is an interface of the p-type base layer 16 and the n-type region 15, to a depth not reaching an interface of the n-type region 15 and the n−-type drift layer 1. Provision of the first p+-type region 3 enables formation of a pn junction between the first p+-type region 3 and the n-type region 15, near the bottom surface of the trench 30. The first p+-type region 3 is doped with, for example, aluminum and has an impurity concentration that is higher than an impurity concentration of the p-type base layer 16.
Further, a width of the first p+-type region 3 is equal to or wider than a width of the trench 30. Each first p+-type region 3 may partially extend toward adjacent trenches 30, whereby the first p+-type regions 3 are connected. With such a structure, holes generated at the time of avalanche breakdown at a junction of the first p+-type region 3 and the n-type region 15 are efficiently migrated to the source electrode 28, whereby load on the gate insulating film 19 is reduced and reliability is increased.
The second p+-type region 4 is partially provided in a surface layer of the n-type region 15, and a bottom of the second p+-type region 4 is in contact with the first p+-type region 3 (refer to FIG. 4B). Further, the second p+-type region 4 is in contact with a side wall of the trench 30 (refer to FIG. 7C of a second embodiment). The second p+-type region 4 is doped with, for example, aluminum and an impurity concentration of the second p+-type region 4 is higher than the impurity concentration of the p-type base layer 16.
In the p-type base layer 16, an n+-type source region and a p+-type contact region 18 are selectively provided so as to be in contact with each other. The n+-type source region is constituted by a first n+-type source region 17 and a second n+-type source region 24 in contact with each other. The first n+-type source region 17 is provided in a surface layer of the p-type base layer 16. The second n+-type source region 24 is provided at a position deeper toward the drain electrode 29 than is the first n+-type source region 17, and a width of the second n+-type source region 24 is narrower than a width of the first n+-type source region 17. A depth of the p+-type contact region 18 may be, for example, equal to or deeper than a depth of the second n+-type source region 24.
The first n+-type source region 17 has an impurity concentration that is lower than an impurity concentration of the second n+-type source region 24, and has a type of impurity different from that of the second n+-type source region 24. For example, the first n+-type source region 17 is implanted with phosphorus (P) or arsenic (As), and the second n+-type source region 24 is implanted with nitrogen (N2). Provision of the first n+-type source region 17 and the second n+-type source region 24 enables a source region to be provided deeply, thereby enabling the trench 30 to be provided deeply.
The trench 30 penetrates the first n+-type source region 17, the second n+-type source region 24 and the p-type base layer 16 from the base front surface, and reaches the n-type region 15 and the first p+-type region 3. In the trench 30, the gate insulating film 19 is provided along side walls of the trench 30, and the gate electrode 20 is provided on the gate insulating film 19. The gate electrode 20 is electrically connected at a non-depicted part to a gate pad (not depicted).
In the trench 30, at a position (closer to the source electrode 28 than is the gate electrode 20) farther from the drain electrode 29 than is the gate electrode 20, for example, an interlayer insulating film 21 containing silicon dioxide (SiO2) is provided. A thickness of the interlayer insulating film 21 may be 0.3 μm or greater. Provision of the interlayer insulating film 21 having this thickness or greater enables the gate electrode 20 and the source electrode 28 to be insulated. Further, in the trench 30, at a position (closer to the source electrode 28 than is the interlayer insulating film 21) farther from the drain electrode 29 than is the interlayer insulating film 21, a barrier metal 25 is provided that prevents diffusion of metal atoms, for example, nickel (Ni), from the source electrode 28 toward the gate electrode 20. The barrier metal 25 is formed by, for example, titanium nitride (TiN), Ti, etc.
In the trench 30, the interlayer insulating film 21 and the barrier metal 25 are embedded, enabling the front surface of the silicon carbide base 100 to be planarized. At the entire front surface, an Ni film 26 and a Ti film 27 are provided in order stated. The Ni film 26 and the Ti film 27 constitute the source electrode (first electrode) 28, are in contact with the n+-type source region 17 and the p+-type contact region 18, and are electrically insulated from the gate electrode 20 by the interlayer insulating film 21. On the source electrode 28, the source electrode pad 22 containing, for example, Al—Si is provided. At a rear surface (rear surface of the n+-type silicon carbide substrate 2 constituting an n+-type drain region) of the silicon carbide base 100, the drain electrode 29 (second electrode) is provided.
A method of manufacturing the silicon carbide semiconductor device according to the first embodiment will be described. FIGS. 2, 3, 4, 5, and 6 are cross-sectional views of the silicon carbide semiconductor device according to the first embodiment during manufacture. First, the n+-type silicon carbide substrate 2 constituting the n+-type drain region is prepared. For example, as the n+-type silicon carbide substrate 2, the n+-type silicon carbide substrate 2 is prepared having an impurity concentration in a range from 1×1018 to 1×1020/cm3 and a thickness in a range from 100 μm to 700 μm.
Next, on a front surface of the n+-type silicon carbide substrate 2, the n−-type drift layer 1 is formed by epitaxial growth. For example, conditions of the epitaxial growth for forming the n−-type drift layer 1 may be set so that an impurity concentration of the n−-type drift layer 1 is in a range from 3×1015 to 5×1016/cm3, and a film thickness of the n−-type drift layer 1 in a range from about 5 μm to 40 μm. The state up to here is depicted in FIG. 2 .
Next, by photolithography and ion implantation of a p-type impurity, for example, Al, the first p+-type region 3 is selectively formed in a surface layer of the n−-type drift layer 1. For example, a dose amount at the time of ion implantation for forming the first p+-type region 3 may be set so that an impurity concentration thereof is in a range from 1×1017 to 1×1019/cm3, and a depth of the first p+-type region 3 is in a range from 0.1 μm to 1.0 μm, and a width of the first p+-type region 3 is in a range from 0.5 μm to 2.0 μm.
Next, by photolithography and ion implantation of an n-type impurity, for example, N2, a lower n-type region 15 a is selectively formed in a surface layer of the n−-type drift layer 1. The lower n-type region 15 a is a part of the n-type region 15. For example, a dose amount at the time of ion implantation for forming the lower n-type region 15 a may be set so that an impurity concentration of the lower n-type region 15 a is in a range from 1×1016 to 1×1018/cm3, and a depth of the lower n-type region 15 a is in a range from 0.1 μm to 1.5 μm. The state up to here is depicted in FIG. 3 .
Next, on the first p+-type region 3 and the lower n-type region 15 a, an n-type region is formed by epitaxial growth. For example, conditions of the epitaxial growth for forming the n-type region may be set so that an impurity concentration of the n-type region is in a range from 3×1016 to 5×1016/cm3, and a thickness of the n-type region is in a range from 0.3 μm to 0.6 μm. The n-type region is formed by ion implantation described hereinafter and constitutes a part of the n-type region 15.
Next, by photolithography and ion implantation of a p-type impurity, for example, Al, the second p+-type region 4 is selectively formed in a surface layer of the n-type region. For example, a dose amount at the time of ion implantation for forming the second p+-type region 4 may be set so that an impurity concentration of the second p+-type region 4 is in a range from 1×1017 to 1×1019/cm3, a depth of the second p+-type region 4 is in a range from 0.1 μm to 1.0 μm, and a width of the second p+-type region 4 is in a range from 0.5 μm to 2.0 μm.
Next, by photolithography and ion implantation of an n-type impurity, for example, N2, an upper n-type region 15 b is selectively provided in the surface layer of the n-type region. For example, a dose amount at the time of ion implantation for forming the upper n-type region 15 b may be set so that an impurity concentration of the upper n-type region 15 b is in a range from 1×1016 to 1×1018/cm3, and a depth of the upper n-type region 15 b is in a range from 0.1 μm to 1.5 μm. The lower n-type region 15 a and the upper n-type region 15 b combined constitute the n-type region 15. The state up to here is depicted in FIGS. 4A and 4B. FIGS. 4A and 4B are cross-sectional views at differing positions at a same at manufacturing stage.
Next, on the second p+-type region 4 and the n-type region 15, the p-type base layer 16 is formed by epitaxial growth. For example, conditions of the epitaxial growth for forming the p-type base layer 16 may be set so that the impurity concentration of the p-type base layer 16 is in a range from 5×1016 to 1×1018/cm3, and a thickness of the p-type base layer 16 is in a range from 0.7 μm to 2.1 μm.
Next, by photolithography and ion implantation of an n-type impurity, for example, N2, the second n+-type source region 24 is selectively formed in the surface layer of the p-type base layer 16. For example, a dose amount at the time of ion implantation for forming the second n+-type source region 24 may be set so that an impurity concentration of the second n+-type source region 24 is in a range from 1×1017 to 1×1019/cm3, a depth of the second n+-type source region 24 is in a range from 0.6 μm to 1.1 μm, and a width of the second n+-type source region 24 is in a range from 240.5 μm to 1.5 μm.
Next, by photolithography and ion implantation of an n-type impurity, for example, P, the first n+-type source region 17 is selectively formed in the surface layer of the p-type base layer 16. For example, a dose amount at the time of ion implantation for forming the first n+-type source region 17 may be set so that an impurity concentration of the first n+-type source region 17 is in a range from 1×1018 to 1×1020/cm3, and a depth of the first n+-type source region 17 is in a range from 0.3 μm to 0.6 μm.
Next, by photolithography and ion implantation of a p-type impurity, for example, Al, the p+-type contact region 18 is selectively formed in the surface layer of the p-type base layer 16. For example, a dose amount at the time of ion implantation for forming the p+-type contact region 18 may be set so that an impurity concentration of the p+-type contact region 18 is in a range from 1×1018 to 1×1020/cm2, and a depth of the p+-type contact region 18 is in a range from 0.3 μm to 0.6 μm. The state up to here is depicted in FIG. 5 .
Next, to reduce surface roughness of the silicon carbide base 100, a carbon coating layer called a carbon cap is formed on a surface of the silicon carbide base 100 and activation annealing is performed. Next, the carbon cap is removed and by photolithography and etching, the trench 30 is formed penetrating the first n+-type source region 17, the second n+-type source region 24 and the p-type base layer 16, and reaching the n-type region 15 and the first p+-type region 3. Further, after trench etching, isotropic etching for removing damage of the trenches 30 and hydrogen annealing for rounding the bottom part of the trenches 30 and openings of the trenches 30 may be performed. Either the isotropic etching or the hydrogen annealing may be performed. Alternatively, after the isotropic etching is performed, the hydrogen annealing may be performed.
Next, along an inner wall of the trench 30, the gate insulating film 19 is formed. The gate insulating film 19 may be formed by thermal oxidation by heat treatment in an oxygen atmosphere at a temperature of about 1200 degrees C. The gate insulating film 19 may be formed by a deposition method such as by a chemical reaction like that for a high temperature oxide (HTO). After formation of the gate insulating film 19, post oxidation annealing (POA) in an atmosphere containing hydrogen or water vapor may be performed. Next, for example, poly-silicon is deposited so as to be embedded in the trenches 30 and is etched, whereby the poly-silicon remains in the trenches 30, and forms the gate electrodes 20. At this time, etching is performed so that the poly-silicon remains deeper than the surface of the silicon carbide base 100.
Next, for example, SiO2 is deposited and etched so as to be embedded on the poly-silicon in the trenches 30, whereby the SiO2 is left forming the interlayer insulating film 21 in the trenches 30. At this time, etching may be performed so that the SiO2 is left up to the surface of the silicon carbide base 100. Further, in place of etching, a chemical mechanical polishing (CMP) process may be used, or formation may be by etching by thickly stacking a resist. Next, the interlayer insulating film 21 is dry etched from the surface of the silicon carbide base 100, to a predetermined depth of, for example, within 0.1 μm. The state up to here is depicted in FIG. 6 .
Next, as the barrier metal 25, for example, TiN is deposited so as to be embedded on the interlayer insulating film 21 in the trench 30 and by a CMP process, is left up to the surface of the silicon carbide base 100. Next, for example, by a sputtering method, the Ni film 26 is formed on the front surface side of the silicon carbide base 100. Next, for example, by sintering (heat treatment) at 800 degrees C. to 1000 degrees C., a silicon carbide semiconductor part (the first n+-type source region 17 and the p+-type contact region 18) and the Ni film 26 are caused to react and form a nickel silicide film, whereby an ohmic contact is formed with the silicon carbide semiconductor part.
Next, on the nickel silicide film, the Ti film 27 is formed as the source electrode, and the source electrode pad 22, which is an Al—Si film is formed. For example, the Ti film 27 is formed by a sputtering method, and the Al—Si film is formed by sputtering to a top of the Ti film 27.
Next, at the rear surface of the n+-type silicon carbide substrate 2, by sputtering deposition at a contact part of the drain electrode 29, a metal film such as a nickel (Ni) film, a titanium (Ti) film, etc. is formed. The metal film may be constituted by a combination of multiple Ni and Ti films. Thereafter, annealing such as rapid thermal annealing (RTA) is performed to convert the metal film into a silicide and form an ohmic contact. Thereafter, for example, a thick film constituted by a Ti film, an Ni film, and a gold (Au) film sequentially stacked in order stated is formed by electron beam (EB) deposition, etc., whereby the drain electrode 29 is formed. In this manner, the MOSFET depicted in FIG. 1 is completed.
As described, according to the first embodiment, the gate electrode, the interlayer insulating film, and the barrier metal are embedded in the trench. As a result, a thickness of the interlayer insulating film may be adjusted by a length of the trench and even when the cell pitch is reduced, insulation of the gate electrode and the source electrode may be ensured. Therefore, decreases in semiconductor device yield due to degradation of insulation between the gate electrode and the source electrode may be resolved. Further, since the surface of the semiconductor base is flat, plating is facilitated and nickel silicide coverage also improves. Further, the mathematical area of contact between the first n+-type source region and the nickel silicide increases and the contact resistance decreases. Therefore, even when the cell pitch is 4.0 μm or less, for example, 1.5 μm, the ON resistance does not increase and there is no need to use a tungsten plug.
Further, in the first embodiment, as the source region, the first n+-type source region and the second n+-type source region are provided and formed by ion implanting P or As in the first n+-type source region, and implanting N2 in the second n+-type source region. As a result, the source region may be provided deeply, and the length of the trench may be increased. Therefore, the gate electrode, the interlayer insulating film, and the barrier metal may be embedded in the trench.
A structure of the silicon carbide semiconductor device according to the second embodiment will be described. FIGS. 7A, 7B, and FIG. 7C are cross-sectional views of a structure of the silicon carbide semiconductor device according to the second embodiment. FIG. 8 is a top view of the structure of the silicon carbide semiconductor device according to the second embodiment, at cutting line a-a′ in FIGS. 7A to 7C. Here, FIG. 7A is a cross-sectional view at cutting line X-X′ in FIG. 8 ; FIG. 7B is a cross-sectional view at cutting line Y-Y′ in FIG. 8 ; and FIG. 7C is a cross-sectional view at cutting line Z-Z′ in FIG. 8 .
The silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that positions and shapes of the first p+-type region 3 and the second p+-type region 4 in the n-type region 15 differ from those in the first embodiment.
The first p+-type region 3, as depicted in FIG. 7A, is provided to be in contact with the n−-type drift layer 1 and the bottoms of the trenches 30. Further, as depicted in FIG. 8 , the first p+-type region 3 has a striped shape along a width direction of the trenches 30. Further, as depicted in FIG. 7C, the second p+-type region 4 is selectively provided on an upper side (side toward the source electrode 28) of the first p+-type region 3, between adjacent trenches 30. Provision of the first p+-type region 3 in a striped shape along the width direction of the trenches 30 enables alignment deviations of the second p+-type region 4 and the trench 30 with the first p+-type region 3 to be prevented.
A method of manufacturing the silicon carbide semiconductor device according to the second embodiment will be described. FIGS. 9A, 9B, 10A, 10B, and 10C are cross-sectional views of the silicon carbide semiconductor device according to the second embodiment during manufacture. The method of manufacturing the silicon carbide semiconductor device according to the second embodiment, for example, differs from the method of manufacturing the silicon carbide semiconductor device according to the first embodiment in the method of forming the first p+-type region 3 and the second p+-type region 4. For example, first, similarly to the first embodiment, the processes of preparing the n+-type silicon carbide substrate 2 to forming the n−-type drift layer 1 by epitaxial growth are sequentially performed (refer to FIG. 2 ).
Next, on the n−-type drift layer 1, the lower n-type region 15 a is formed by epitaxial growth. For example, conditions of the epitaxial growth for forming the lower n-type region 15 a may be set so that the impurity concentration of the lower n-type region 15 a is in a range from 1×1016 to 1×1018/cm3, and the thickness of the lower n-type region 15 a is in a range from 0.1 μm to 1.5 μm.
Next, by photolithography and ion implantation of a p-type impurity, for example, Al, the first p+-type region 3 having striped shaped is selectively formed in the surface layer of the lower n-type region 15 a. For example, a dose amount at the time of ion implantation for forming the first p+-type region 3 may be set so that the impurity concentration of the first p+-type region 3 is in a range from 1×1017 to 1×1019/cm3, the depth of the first p+-type region 3 is in a range from 0.1 μm to 1.5 μm, and the width of the first p+-type region 3 is in a range from 0.5 μm to 2.0 μm. The state up to here is depicted in FIGS. 9A and 9B. FIG. 9A is a cross-sectional view at cutting line X-X′ in FIG. 8 ; and FIG. 9B is a cross-sectional view at cutting line Y-Y′ in FIG. 8 .
Next, on the lower n-type region 15 a and the first p+-type region 3, the upper n-type region 15 b is formed by epitaxial growth. For example, conditions of the epitaxial growth for forming the upper n-type region 15 b may be set so that the impurity concentration of the upper n-type region 15 b is in a range from 1×1016 to 1×1018/cm3, and a thickness of the upper n-type region 15 b is in a range from 0.3 μm to 0.6 μm. The lower n-type region 15 a and the upper n-type region 15 b combined constitute the n-type region 15.
Next, by photolithography and ion implantation of a p-type impurity, for example, Al, the second p+-type region 4 is selectively formed in the surface layer of the upper n-type region 15 b. For example, a dose amount at the time of ion implantation for forming the second p+-type region 4 may be set so that the impurity concentration of the second p+-type region 4 is in a range from 1×1017 to 1×1019/cm3, the depth of the second p+-type region 4 is in a range from 0.1 μm to 1.0 μm, and the width of the second p+-type region 4 is in a range from 0.5 μm to 2.0 μm. The state up to here is depicted in FIGS. 10A to 10C. FIG. 10A is a cross-sectional view at cutting line X-X′ in FIG. 8 ; FIG. 10B is a cross-sectional view at cutting line Y-Y′ in FIG. 8 ; and FIG. 100 is a cross-sectional view at cutting line Z-Z′ in FIG. 8 .
Thereafter, similarly in the first embodiment, the process of forming the p-type base layer 16 by epitaxial growth and subsequent processes are sequentially performed, whereby the MOSFET depicted in FIGS. 7A to 7C is completed.
As described, according to the second embodiment, effects similar to those of the first embodiment may be obtained. Further, in the second embodiment, the first p+-type region is provided in a striped shape along the width direction of the trenches. As a result, alignment deviations of the first p+-type region and the trenches may be prevented. Therefore, since there is no need to form the first p+-type region excessively large for alignment, the cell pitch of the semiconductor device may be reduced.
FIG. 11 is a graph depicting a relationship of cell pitch and ON resistance of the silicon carbide semiconductor device according to the first and the second embodiments. FIG. 11 depicts results of simulation where a thickness of the n+-type silicon carbide substrate 2 is assumed to be 150 μm, a drain current density Jc is assumed to be 300 A/cm2, and forward voltage Vth is assumed to be 5V. A horizontal axis represents the cell pitch of the silicon carbide semiconductor device in units of μm, while a vertical axis represents ON resistance (RonA) per unit active area in units of mΩcm2. According to FIG. 11 , for cell pitches of 4 μm or greater, which may be realized by a conventional technique and for cell pitches less than 4 μm, which may be realized by the present invention, the ON resistance decreases as the cell pitch decreases. The present invention enables a silicon carbide semiconductor device having a cell pitch of less than 4 μm to be provided and thus, may provide a silicon carbide semiconductor device having a lower ON resistance.
In the embodiments of the present invention, various modifications within a range not deviating from the spirit of the invention are possible. For example, in the embodiments, dimensions, impurity concentrations, etc. of regions may be variously changed according to required specifications. Further, while a MOSFET has been described as an example in the embodiments, without limitation hereto, wide application to various types of silicon carbide semiconductor devices that conduct and interrupt current by gate driving control based on a predetermined gate threshold voltage is possible. For example, an insulated gate bipolar transistor (IGBT), etc. may be given as a silicon carbide semiconductor device under gate driving control. In the embodiments, while description has been given taking, as an example, a case where silicon carbide is used as a wide bandgap semiconductor material, application to another wide bandgap semiconductor material other than silicon carbide such as, for example, gallium nitride (GaN) is possible. Further, in the embodiments, while a first conductivity type is assumed to be an n-type and a second conductivity type is assumed to be a p-type, the invention is similarly implemented when the first conductivity type is a p-type and the second conductivity type is an n-type.
According to the embodiments, the gate electrode, the interlayer insulating film, and the barrier metal are embedded in the trench. As a result, the thickness of the interlayer insulating film may be adjusted by the length of the trench and even when the cell pitch is reduced, insulation of the gate electrode and the source electrode may be ensured. Therefore, decreases in semiconductor device yield due to degradation of insulation between the gate electrode and the source electrode may be resolved. Further, since the surface of the semiconductor base is flat, plating is facilitated and nickel silicide coverage also improves. Further, the mathematical area of contact between the first n+-type source region (first semiconductor region of the first semiconductor type) and the nickel silicide increases and the contact resistance decreases. Therefore, even when the cell pitch is 4.0 μm or less, for example, 1.5 μm, the ON resistance does not increase and there is no need to use a tungsten plug.
Further, in the first embodiment, as the source region, the first n+-type source region and the second n+-type source region are provided and formed by ion implanting P or As in the first n+-type source region, and implanting N2 in the second n+-type source region. As a result, the source region may be provided deeply, and the length of the trench may be increased. Therefore, the gate electrode, the interlayer insulating film, and the barrier metal may be embedded in the trench.
The semiconductor device and the method of manufacturing a semiconductor device according to the embodiments of the invention achieve an effect in that without increases in the ON resistance, the cell pitch may be made less than 4.0 μm and the reliability is high.
As described, the semiconductor device and the method of manufacturing a semiconductor device according to the embodiments of the present invention are useful for power semiconductor devices used in power converting equipment and power supply devices such as in various types of industrial machines, and are particularly suitable for silicon carbide semiconductor devices having a trench gate structure.
Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.

Claims (7)

What is claimed is:
1. A semiconductor device, comprising:
a semiconductor substrate of a first semiconductor type;
a first semiconductor layer of the first semiconductor type provided on a front surface of the semiconductor substrate;
a second semiconductor layer of a second semiconductor type provided on a first side of the first semiconductor layer opposite a second side of the first semiconductor layer, the second side facing toward the semiconductor substrate;
a first semiconductor region of the first semiconductor type that is selectively provided in the second semiconductor layer, that is constituted by an upper first semiconductor region and a lower first semiconductor region in which the upper first semiconductor region has a width that is wider than that of the lower first semiconductor region, and that has an impurity concentration that is higher than that of the semiconductor substrate;
a trench having a length that penetrates the first semiconductor region and the second semiconductor layer, and reaches the first semiconductor layer;
a gate insulating film provided in the trench;
a gate electrode provided in the trench on the gate insulating film;
an interlayer insulating film that is provided only in the trench to cover the gate electrode, that is formed of SiO2, and that has a thickness that is adjusted based on the length of the trench;
a barrier metal layer containing Ti and selectively provided only in the trench and disposed on and in direct contact with the interlayer insulating film so as to substantially completely cover the interlayer insulating film;
a first electrode that is flat and completely covers the semiconductor substrate, that is constituted by a Ni film provided on the semiconductor substrate and a Ti film provided on the Ni film, and that contacts the first semiconductor region, the second semiconductor layer, and the barrier metal layer;
a source electrode pad containing Al—Si provided on the first electrode; and
a second electrode provided at a rear surface of the semiconductor substrate,
wherein the semiconductor device has a cell pitch of less than 4.0μm so that ON resistance decreases as cell pitch decreases.
2. The semiconductor device according to claim 1, wherein the upper first semiconductor region and the lower first semiconductor region have differing impurity concentrations determining conductivity.
3. The semiconductor device according to claim 1, wherein the interlayer insulating film has a thickness of at least 0.3 μm.
4. The semiconductor device according to claim 1, further comprising a second semiconductor region of the second semiconductor type selectively provided in the first semiconductor layer, the second semiconductor region being in contact with a bottom of the trench.
5. The semiconductor device according to claim 4, wherein the trench has a width direction and the second semiconductor region has a striped shape parallel to the width direction of the trench.
6. The semiconductor device according to claim 2, wherein the upper first semiconductor region has an impurity concentration that ranges from 1×1018 to 1×1020/cm3, and wherein the lower first semiconductor region has an impurity concentration that ranges from 1×1017 to 1×1019/cm3.
7. The semiconductor device according to claim 1, further comprising a contact region of the second conductivity type selectively provided in the second semiconductor layer and in direct contact with the upper first semiconductor region but not in direct contact with the lower first semiconductor region, wherein the contact region has an impurity concentration that is higher than that of the second semiconductor layer.
US15/993,671 2017-06-09 2018-05-31 Semiconductor device having a gate electrode, an interlayer insulating film and a barrier metal provided in a trench Active 2039-06-07 US12094939B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017114766A JP6950290B2 (en) 2017-06-09 2017-06-09 Semiconductor devices and manufacturing methods for semiconductor devices
JP2017-114766 2017-06-09

Publications (2)

Publication Number Publication Date
US20180358445A1 US20180358445A1 (en) 2018-12-13
US12094939B2 true US12094939B2 (en) 2024-09-17

Family

ID=64564306

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/993,671 Active 2039-06-07 US12094939B2 (en) 2017-06-09 2018-05-31 Semiconductor device having a gate electrode, an interlayer insulating film and a barrier metal provided in a trench

Country Status (2)

Country Link
US (1) US12094939B2 (en)
JP (1) JP6950290B2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7180425B2 (en) * 2019-02-06 2022-11-30 住友電気工業株式会社 Silicon carbide semiconductor device
JP7563180B2 (en) * 2019-02-13 2024-10-08 住友電気工業株式会社 Silicon carbide semiconductor chip and silicon carbide semiconductor device
JP6992021B2 (en) * 2019-03-18 2022-01-13 株式会社東芝 Semiconductor devices, inverter circuits, drives, vehicles, and elevators
JP2021012995A (en) * 2019-07-09 2021-02-04 トヨタ自動車株式会社 Trench gate type semiconductor device
WO2021038699A1 (en) * 2019-08-26 2021-03-04 株式会社デンソー Semiconductor device and method for manufacture thereof
JP7388197B2 (en) * 2020-01-07 2023-11-29 株式会社デンソー Manufacturing method of trench gate type switching element
CN112820648B (en) * 2020-12-31 2023-08-01 扬州扬杰电子科技股份有限公司 Gallium nitride metal oxide semiconductor transistor and preparation method thereof
JP7476132B2 (en) * 2021-03-23 2024-04-30 株式会社東芝 Semiconductor device, inverter circuit, drive device, vehicle, and elevator
JP7563356B2 (en) 2021-10-05 2024-10-08 株式会社デンソー Silicon carbide semiconductor device
CN117397043A (en) * 2021-12-27 2024-01-12 富士电机株式会社 Semiconductor device with a semiconductor device having a plurality of semiconductor chips
CN118610234A (en) * 2024-07-29 2024-09-06 凌锐半导体(上海)有限公司 Embedded interlayer dielectric layer structure and preparation method thereof

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008306095A (en) 2007-06-11 2008-12-18 Rohm Co Ltd Semiconductor device
US20090212359A1 (en) * 2008-02-23 2009-08-27 Force Mos Technology Co. Ltd. Trenched mosfet with trenched source contact
US20090236612A1 (en) 2008-03-24 2009-09-24 Fuji Electric Device Technology Co., Ltd. Silicon carbide mos semiconductor device
JP2009260253A (en) 2008-03-26 2009-11-05 Rohm Co Ltd Semiconductor device and method for manufacturing the same
US20110079844A1 (en) * 2009-10-01 2011-04-07 Force Mos Technology Co. Ltd. Trench mosfet with high cell density
US20110169075A1 (en) 2010-01-14 2011-07-14 Force Mos Technology Co. Ltd. Trench mosfet with ultra high cell density and manufacture thereof
US7989293B2 (en) * 2009-02-24 2011-08-02 Maxpower Semiconductor, Inc. Trench device structure and fabrication
US20120146090A1 (en) * 2010-12-14 2012-06-14 Alpha And Omega Semiconductor Incorporated Self aligned trench mosfet with integrated diode
US20140141585A1 (en) 2008-03-03 2014-05-22 Fuji Electric Co., Ltd. Trench gate type semiconductor device and method of producing the same
US20160247910A1 (en) * 2013-10-02 2016-08-25 Denso Corporation Silicon carbide semiconductor device
US20160359026A1 (en) 2015-06-03 2016-12-08 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US20170084699A1 (en) * 2015-09-17 2017-03-23 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US20170352730A1 (en) * 2015-01-27 2017-12-07 Mitsubishi Electric Corporation Semiconductor device
US20190109227A1 (en) * 2017-10-05 2019-04-11 Fuji Electric Co., Ltd. Semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2956682C (en) * 2014-08-05 2018-09-11 Luminara Worldwide, Llc Electric lighting devices

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008306095A (en) 2007-06-11 2008-12-18 Rohm Co Ltd Semiconductor device
US20090212359A1 (en) * 2008-02-23 2009-08-27 Force Mos Technology Co. Ltd. Trenched mosfet with trenched source contact
JP2016040844A (en) 2008-03-03 2016-03-24 富士電機株式会社 Trench gate semiconductor device manufacturing method
US20140141585A1 (en) 2008-03-03 2014-05-22 Fuji Electric Co., Ltd. Trench gate type semiconductor device and method of producing the same
US20090236612A1 (en) 2008-03-24 2009-09-24 Fuji Electric Device Technology Co., Ltd. Silicon carbide mos semiconductor device
JP2009231545A (en) 2008-03-24 2009-10-08 Fuji Electric Device Technology Co Ltd Silicon carbide mos semiconductor device
JP2009260253A (en) 2008-03-26 2009-11-05 Rohm Co Ltd Semiconductor device and method for manufacturing the same
US20110024831A1 (en) 2008-03-26 2011-02-03 Rohm Co., Ltd. Semiconductor device, and method for manufacturing the same
US7989293B2 (en) * 2009-02-24 2011-08-02 Maxpower Semiconductor, Inc. Trench device structure and fabrication
US20110079844A1 (en) * 2009-10-01 2011-04-07 Force Mos Technology Co. Ltd. Trench mosfet with high cell density
US20110169075A1 (en) 2010-01-14 2011-07-14 Force Mos Technology Co. Ltd. Trench mosfet with ultra high cell density and manufacture thereof
US20120146090A1 (en) * 2010-12-14 2012-06-14 Alpha And Omega Semiconductor Incorporated Self aligned trench mosfet with integrated diode
US20160247910A1 (en) * 2013-10-02 2016-08-25 Denso Corporation Silicon carbide semiconductor device
US20170352730A1 (en) * 2015-01-27 2017-12-07 Mitsubishi Electric Corporation Semiconductor device
US20160359026A1 (en) 2015-06-03 2016-12-08 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
JP2016225566A (en) 2015-06-03 2016-12-28 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of the same
US20170084699A1 (en) * 2015-09-17 2017-03-23 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
US20190109227A1 (en) * 2017-10-05 2019-04-11 Fuji Electric Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
US20180358445A1 (en) 2018-12-13
JP2019003967A (en) 2019-01-10
JP6950290B2 (en) 2021-10-13

Similar Documents

Publication Publication Date Title
US12094939B2 (en) Semiconductor device having a gate electrode, an interlayer insulating film and a barrier metal provided in a trench
US10403749B2 (en) Method of manufacturing semiconductor device
US10002952B2 (en) Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
US11552172B2 (en) Silicon carbide device with compensation layer and method of manufacturing
US10770582B2 (en) Semiconductor device
US10008592B1 (en) Semiconductor device
US10283591B2 (en) Silicon carbide semiconductor device and method of manufacturing the silicon carbide semiconductor device
US11437508B2 (en) Semiconductor device
US20140209999A1 (en) Semiconductor device
US11322607B2 (en) Semiconductor device
US10629725B2 (en) Semiconductor device having semiconductor regions with an interval therebetween in a gate pad region
JP7155641B2 (en) semiconductor equipment
US20240047572A1 (en) Semiconductor device with improved breakdown voltage
US20240145589A1 (en) Semiconductor device
US10388725B2 (en) Semiconductor device and method of manufacturing semiconductor device
US20190165162A1 (en) Semiconductor device and method of manufacturing a semiconductor device
US20230326960A1 (en) Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
US10665668B2 (en) Silicon carbide semiconductor device and method of manufacturing a silicon carbide semiconductor device
JP2023096841A (en) Semiconductor device and method for manufacturing the same
US20190245079A1 (en) Semiconductor device and method of manufacturing semiconductor device
US20210280707A1 (en) Semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: FUJI ELECTRIC CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KOBAYASHI, YUSUKE;OHSE, NAOYUKI;HARADA, SHINSUKE;SIGNING DATES FROM 20180515 TO 20180521;REEL/FRAME:045944/0270

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: ADVISORY ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE AFTER FINAL ACTION FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: ADVISORY ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STCV Information on status: appeal procedure

Free format text: NOTICE OF APPEAL FILED

STCV Information on status: appeal procedure

Free format text: APPEAL BRIEF (OR SUPPLEMENTAL BRIEF) ENTERED AND FORWARDED TO EXAMINER

STCV Information on status: appeal procedure

Free format text: EXAMINER'S ANSWER TO APPEAL BRIEF MAILED

STCV Information on status: appeal procedure

Free format text: ON APPEAL -- AWAITING DECISION BY THE BOARD OF APPEALS

STCV Information on status: appeal procedure

Free format text: BOARD OF APPEALS DECISION RENDERED

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

ZAAA Notice of allowance and fees due

Free format text: ORIGINAL CODE: NOA

ZAAB Notice of allowance mailed

Free format text: ORIGINAL CODE: MN/=.

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE