US11894064B2

US11894064B2 - Sub-block mode for non-volatile memory

Info

Publication number: US11894064B2
Application number: US17/583,570
Authority: US
Inventors: Xiang Yang
Original assignee: SanDisk Technologies LLC
Current assignee: SanDisk Technologies LLC
Priority date: 2022-01-25
Filing date: 2022-01-25
Publication date: 2024-02-06
Also published as: US20230238062A1

Abstract

The memory device includes a block with a plurality of memory cells arranged in a plurality of data word lines, which are arranged in sub-blocks that are not separated from one another by physical joints or by dummy word lines. A controller is configured to erase the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks. The controller reads data of the edge one word lines of the unselected sub-blocks adjacent the selected sub-block and stores this data in a temporary location external of the block before erasing the memory cells of the selected sub-block. The controller then re-programs the data that is being temporarily stored back into the memory cells of the edge word lines of the unselected sub-blocks after erase of the selected sub-block is completed.

Description

BACKGROUND

1. Field

The present technology relates to the operation of memory devices and, more particularly, to erasing operations to allow multiple sub-blocks, which are not separated by physical joints or dummy word lines, to be independently operated within a single block.

2. Related Art

Some modern types of cryptocurrencies rely on storage, rather than computational power, in mining. In some examples, mining these cryptocurrencies involves storing so-called “plots,” which can be approximately 100 GB in size, into a memory device, such as a solid state drive (SSD) or a hard disk drive (HDD). The mining operation may include a large number of program/erase cycles to repeatedly program and erase plots. In one mining technique, a high SSD memory device, such as of the type having a flash NAND array architecture, may be utilized for temporary storage for one or more plots until those plots are copied to a relatively slower HDD for long term storage.

Such SSDs may be provided as internal, semiconductor, integrated circuits in computers or other electronic devices. In a flash NAND array architecture, memory cells may be arranged in a plurality of blocks, each of which includes a matrix of rows and columns of memory cells. With an increasing demand for memory density, the number of rows of memory cells (also known as word lines) in each block has been increasing. However, while memory cells are typically programmed at the word line level, they are generally erased at the block level. This makes things difficult if you only want to erase a portion of the memory cells in a block. To guard against this, in some memory devices, each block may be segmented into a plurality of sub-blocks that are separated from one another either by physical joints or by dummy word lines.

SUMMARY

An aspect of the present disclosure is related to a method of operating a memory device. The method includes the step of preparing a block that includes a plurality of memory cells arranged in a plurality of data word lines. The data word lines are arranged in a plurality of sub-blocks, and at least some of the plurality of sub-blocks are not separated from one another by physical joints or by dummy word lines. The method continues with the step of receiving an instruction to erase the memory cells of a selected sub-block of the plurality of sub-blocks. The method proceeds with the step of reading data of at least edge one word line of at least one unselected sub-block of the plurality of sub-blocks. The at least one edge word line is located immediately adjacent the selected sub-block. The method continues with the step of storing the data in a temporary location external of the block. The method proceeds with the step of erasing the selected sub-block. The method continues with the step of re-programing the data to the memory cells of the at least one edge word line after erase of the selected sub-block is completed.

According to another aspect of the present disclosure, during the step of erasing the selected sub-block, a partial inhibit voltage is applied to a control gate of the at least one edge word line.

According to yet another aspect of the present disclosure, during the step of erasing the selected sub-block, a first voltage is applied to the control gates of the word lines of the selected sub-block, and an inhibit voltage is applied to the control gates of the word lines of the unselected sub-blocks other than the at least one edge word line. The partial inhibit voltage is between the first voltage and the inhibit voltage.

According to still another aspect of the present disclosure, the first voltage is zero Volts or is less than one Volt.

According to a further aspect of the present disclosure, the block includes a plurality of tiers, and each tier includes a plurality of sub-blocks that are not separated from one another by dummy word lines.

According to yet a further aspect of the present disclosure, the step of reading the data of the at least one edge word line and storing the data in a temporary location external of the block is further defined as reading data of an edge word line of an upper unselected block on one side of the selected block and reading data of an edge word line of a lower unselected block on an opposite side of the selected block from the upper unselected block, and the data from both of these edge word lines is stored in the temporary location.

According to still a further aspect of the present disclosure, the temporary location is DRAM or data latches.

According to another aspect of the present disclosure, the memory cells of the block contain no greater than two bits of data per memory cell.

Another aspect of the present disclosure is related to a memory device. The memory device includes a block with a plurality of memory cells arranged in a plurality of data word lines. The data word lines are arranged in a plurality of sub-blocks that are not separated from one another by physical joints or by dummy word lines. A controller is configured to erase the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks. The controller is further configured to read data of at least edge one word line of at least one unselected sub-block, the at least one edge word line being located immediately adjacent the selected sub-block. The controller is also configured to store the data in a temporary location external of the block and then erase the memory cells of the selected sub-block. The controller is then configured to re-program the data to the memory cells of the at least one edge word line of the at least one unselected sub-block after erase of the selected sub-block is completed.

According to another aspect of the present disclosure, while erasing the memory cells of the selected sub-block, the controller is configured to apply a partial inhibit voltage to a control gate of the at least one edge word line.

According to yet another aspect of the present disclosure, while erasing the memory cells of the selected sub-block, the controller applies a first voltage to the control gates of the word lines of the selected sub-block and applies an inhibit voltage to the control gates of the word lines of the unselected sub-blocks other than the edge word lines. The partial inhibit voltage is between the first voltage and the inhibit voltage.

According to yet a further aspect of the present disclosure, the controller is further configured to read data of both an edge word line of an upper unselected block on one side of the selected block and an edge word line of a lower unselected block on an opposite side of the selected block from the upper unselected block and is further configured to store the data from both edge word lines in the temporary location.

According to another aspect of the present disclosure, the controller is configured to program no more than two bits of data into each memory cell.

Yet another aspect of the present disclosure is related to an apparatus that includes a block containing a plurality of memory cells, which are arranged in a plurality of data word lines. The data word lines are arranged in a plurality of sub-blocks that are not separated from one another by physical joints or by dummy word lines. The apparatus further includes an erasing means for erasing the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks. The erasing means is further configured to read data of at least edge one word line of at least one unselected sub-block and store the data in a temporary location external of the block. The erasing means is also configured to erase the memory cells of the selected sub-block and re-program the data to the memory cells of the at least one edge word line.

According to another aspect of the present disclosure, while erasing the memory cells of the selected sub-block, the erasing means is configured to apply a partial inhibit voltage to a control gate of the at least one edge word line.

According to yet another aspect of the present disclosure, while erasing the memory cells of the selected sub-block, the erasing means applies a first voltage to the control gates of the word lines of the selected sub-block and applies an inhibit voltage to the control gates of the word lines of the unselected sub-blocks other than the edge word lines. The partial inhibit voltage is between the first voltage and the inhibit voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

A more detailed description is set forth below with reference to example embodiments depicted in the appended figures. Understanding that these figures depict only example embodiments of the disclosure and are, therefore, not to be considered limiting of its scope. The disclosure is described and explained with added specificity and detail through the use of the accompanying drawings in which:

FIG. 1A is a block diagram of an example memory device;

FIG. 1B is a block diagram of an example control circuit;

FIG. 2 depicts blocks of memory cells in an example two-dimensional configuration of the memory array of FIG. 1A;

FIG. 3A and FIG. 3B depict cross-sectional views of example floating gate memory cells in NAND strings;

FIG. 4A and FIG. 4B depict cross-sectional views of example charge-trapping memory cells in NAND strings;

FIG. 5 depicts an example block diagram of the sense block SB1 of FIG. 1 ;

FIG. 6A is a perspective view of a set of blocks in an example three-dimensional configuration of the memory array of FIG. 1 ;

FIG. 6B depicts an example cross-sectional view of a portion of one of the blocks of FIG. 6A;

FIG. 6C depicts a plot of memory hole diameter in the stack of FIG. 6B;

FIG. 6D depicts a close-up view of region 722 of the stack of FIG. 6B;

FIG. 7A depicts a top view of an example word line layer WLL0 of the stack of FIG. 6B;

FIG. 7B depicts a top view of an example top dielectric layer DL19 of the stack of FIG. 6B;

FIG. 8 schematically depicts an example memory block including a plurality of sub-blocks that are separated from one another by dummy word lines;

FIG. 9 schematically depicts an example sub-block being erased and an adjacent sub-block not being erased;

FIG. 10 schematically depicts an example block constructed according to an example embodiment of the present disclosure;

FIG. 11 is a flow chart illustrating the steps of erasing the memory cells of a selected sub-block of a plurality of sub-blocks within a block;

FIG. 12A schematically depicts the example block of FIG. 10 prior to an erase operation;

FIG. 12B schematically depicts the example block of FIG. 12A while the data stored in a pair of edge word lines is read;

FIG. 12C schematically depicts the example block of FIG. 12A during erase of a selected sub-block of the plurality of sub-blocks; and

FIG. 12D schematically depicts the example block of FIG. 12A after the data is re-programmed to the pair of edge word lines.

DETAILED DESCRIPTION

Techniques are provided for operating a non-volatile memory device in a sub-block mode that may be optimized for use in the mining of certain types of cryptocurrencies. As discussed in further detail below, these techniques of the present disclosure allow a single memory block to be broken up into a number of sub-blocks without the need to separate those sub-blocks by joints consisting of dummy word lines. Thus, memory density is improved as compared to memory devices that have sub-blocks which are separated by joints, and this memory density improvement is realized without the performance costs that may typically come without dividing a block into multiple sub-blocks.

Although the mining of cryptocurrencies is discussed throughout the present disclosure, it should be appreciated that the erase techniques discussed as follows may find uses outside of the mining of cryptocurrencies.

Turning now to FIG. 1A, a block diagram is provided of an example memory device that is capable of performing the erase techniques summarized above and discussed in more detail below. The memory device 100 may include one or more memory die 108. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read/write circuits 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read/write circuits 128 include multiple sense blocks SB1, SB2, . . . SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable storage card) as the one or more memory die 108. Commands and data are transferred between the host 140 and controller 122 via a data bus 120, and between the controller and the one or more memory die 108 via lines 118.

The memory structure 126 can be two-dimensional or three-dimensional. The memory structure 126 may comprise one or more array of memory cells including a three-dimensional array. The memory structure 126 may comprise a monolithic three-dimensional memory structure in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates. The memory structure 126 may comprise any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

The control circuitry 110 cooperates with the read/write circuits 128 to perform memory operations on the memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations.

A storage region 113 may, for example, be provided for programming parameters. The programming parameters may include a program voltage, a program voltage bias, position parameters indicating positions of memory cells, contact line connector thickness parameters, a verify voltage, and/or the like. The position parameters may indicate a position of a memory cell within the entire array of NAND strings, a position of a memory cell as being within a particular NAND string group, a position of a memory cell on a particular plane, and/or the like. The contact line connector thickness parameters may indicate a thickness of a contact line connector, a substrate or material that the contact line connector is comprised of, and/or the like.

The on-chip address decoder 114 provides an address interface between that used by the host or a memory controller to the hardware address used by the

decoders

124 and 132. The power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. It can include drivers for word lines, SGS and SGD transistors, and source lines. The sense blocks can include bit line drivers, in one approach. An SGS transistor is a select gate transistor at a source end of a NAND string, and an SGD transistor is a select gate transistor at a drain end of a NAND string.

In some embodiments, some of the components can be combined. In various designs, one or more of the components (alone or in combination), other than memory structure 126, can be thought of as at least one control circuit which is configured to perform the actions described herein. For example, a control circuit may include any one of, or a combination of, control circuitry 110, state machine 112, decoders 114/132, power control module 116, sense blocks SBb, SB2, . . . , SBp, read/write circuits 128, controller 122, and so forth.

The control circuits can include a programming circuit configured to perform a program and verify operation for one set of memory cells, wherein the one set of memory cells comprises memory cells assigned to represent one data state among a plurality of data states and memory cells assigned to represent another data state among the plurality of data states; the program and verify operation comprising a plurality of program and verify iterations; and in each program and verify iteration, the programming circuit performs programming for the one selected word line after which the programming circuit applies a verification signal to the selected word line. The control circuits can also include a counting circuit configured to obtain a count of memory cells which pass a verify test for the one data state. The control circuits can also include a determination circuit configured to determine, based on an amount by which the count exceeds a threshold, if a programming operation is completed.

For example, FIG. 1B is a block diagram of an example control circuit 150 which comprises a programming circuit 151, a counting circuit 152, and a determination circuit 153.

The off-chip controller 122 may comprise a processor 122 c, storage devices (memory) such as ROM 122 a and RAM 122 b and an error-correction code (ECC) engine 245. The ECC engine can correct a number of read errors which are caused when the upper tail of a Vth distribution becomes too high. However, uncorrectable errors may exist in some cases. The techniques provided herein reduce the likelihood of uncorrectable errors.

The storage device(s) 122 a, 122 b comprise, code such as a set of instructions, and the processor 122 c is operable to execute the set of instructions to provide the functionality described herein. Alternately or additionally, the processor 122 c can access code from a storage device 126 a of the memory structure 126, such as a reserved area of memory cells in one or more word lines. For example, code can be used by the controller 122 to access the memory structure 126 such as for programming, read and erase operations. The code can include boot code and control code (e.g., set of instructions). The boot code is software that initializes the controller 122 during a booting or startup process and enables the controller 122 to access the memory structure 126. The code can be used by the controller 122 to control one or more memory structures 126. Upon being powered up, the processor 122 c fetches the boot code from the ROM 122 a or storage device 126 a for execution, and the boot code initializes the system components and loads the control code into the RAM 122 b. Once the control code is loaded into the RAM 122 b, it is executed by the processor 122 c. The control code includes drivers to perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

Generally, the control code can include instructions to perform the functions described herein including the steps of the flowcharts discussed further below and provide the voltage waveforms including those discussed further below.

In one embodiment, the host is a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors, one or more processor readable storage devices (RAM, ROM, flash memory, hard disk drive, solid state memory) that store processor readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input/output interfaces and/or one or more input/output devices in communication with the one or more processors.

Other types of non-volatile memory in addition to NAND flash memory can also be used.

Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.

The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse or phase change material, and optionally a steering element, such as a diode or transistor. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.

Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a set of series-connected transistors comprising memory cells and SG transistors.

A NAND memory array may be configured so that the array is composed of multiple memory strings in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be otherwise configured. The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-y direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements is formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

A three-dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the z-direction is substantially perpendicular and the x- and y-directions are substantially parallel to the major surface of the substrate).

As a non-limiting example, a three-dimensional memory structure may be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements. The columns may be arranged in a two-dimensional configuration, e.g., in an x-y plane, resulting in a three-dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array.

By way of non-limiting example, in a three-dimensional array of NAND strings, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-y) memory device level. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three-dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.

Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or have intervening layers between memory device levels.

Then again, two-dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three-dimensional memory arrays. Further, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.

FIG. 2 illustrates

blocks

200, 210 of memory cells in an example two-dimensional configuration of the memory array 126 of FIG. 1 . The memory array 126 can include many

such blocks

200, 210. Each

example block

200, 210 includes a number of NAND strings and respective bit lines, e.g., BL0, BL1, . . . which are shared among the blocks. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gates of the drain select gates are connected via a common SGD line. The NAND strings are connected at their other end to a source-side select gate (SGS) which, in turn, is connected to a common source line 220. One hundred and twelve word lines, for example, WL0-WL111, extend between the SGSs and the SGDs. In some embodiments, the memory block may include more or fewer than one hundred and twelve word lines. For example, in some embodiments, a memory block includes one hundred and sixty-four word lines. In some cases, dummy word lines, which contain no user data, can also be used in the memory array adjacent to the select gate transistors. Such dummy word lines can shield the edge data word line from certain edge effects.

One type of non-volatile memory which may be provided in the memory array is a floating gate memory, such as of the type shown in FIGS. 3A and 3B. However, other types of non-volatile memory can also be used. As discussed in further detail below, in another example shown in FIGS. 4A and 4B, a charge-trapping memory cell uses a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

In another approach, NROM cells are used. Two bits, for example, are stored in each NROM cell, where an ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

FIG. 3A illustrates a cross-sectional view of example floating

gate memory cells

300, 310, 320 in NAND strings. In this Figure, a bit line or NAND string direction goes into the page, and a word line direction goes from left to right. As an example, word line 324 extends across NAND strings which include

respective channel regions

306, 316 and 326. The memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305 and the channel region 306. The memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315 and the channel region 316. The memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325 and the channel region 326. Each

memory cell

300, 310, 320 is in a different respective NAND string. An inter-poly dielectric (IPD) layer 328 is also illustrated. The

control gates

302, 312, 322 are portions of the word line. A cross-sectional view along contact line connector 329 is provided in FIG. 3B.

The

control gate

302, 312, 322 wraps around the floating

gate

304, 314, 321, increasing the surface contact area between the

control gate

302, 312, 322 and floating

gate

304, 314, 321. This results in higher IPD capacitance, leading to a higher coupling ratio which makes programming and erase easier. However, as NAND memory devices are scaled down, the spacing between neighboring

cells

300, 310, 320 becomes smaller so there is almost no space for the

control gate

302, 312, 322 and the IPD layer 328 between two adjacent floating

gates

302, 312, 322.

As an alternative, as shown in FIGS. 4A and 4B, the flat or

planar memory cell

400, 410, 420 has been developed in which the

control gate

402, 412, 422 is flat or planar; that is, it does not wrap around the floating gate and its only contact with the charge storage layer 428 is from above it. In this case, there is no advantage in having a tall floating gate. Instead, the floating gate is made much thinner. Further, the floating gate can be used to store charge, or a thin charge trap layer can be used to trap charge. This approach can avoid the issue of ballistic electron transport, where an electron can travel through the floating gate after tunneling through the tunnel oxide during programming.

FIG. 4A depicts a cross-sectional view of example charge-trapping

memory cells

400, 410, 420 in NAND strings. The view is in a word line direction of

memory cells

400, 410, 420 comprising a flat control gate and charge-trapping regions as a two-dimensional example of

memory cells

400, 410, 420 in the memory cell array 126 of FIG. 1 . Charge-trapping memory can be used in NOR and NAND flash memory device. This technology uses an insulator such as an SiN film to store electrons, in contrast to a floating-gate MOSFET technology which uses a conductor such as doped polycrystalline silicon to store electrons. As an example, a word line 424 extends across NAND strings which include

respective channel regions

406, 416, 426. Portions of the word line provide

control gates

402, 412, 422. Below the word line is an IPD layer 428, charge-trapping

layers

404, 414, 421, polysilicon layers 405, 415, 425, and tunneling

layers

409, 407, 408. Each charge-

trapping layer

404, 414, 421 extends continuously in a respective NAND string. The flat configuration of the control gate can be made thinner than a floating gate. Additionally, the memory cells can be placed closer together.

FIG. 4B illustrates a cross-sectional view of the structure of FIG. 4A along contact line connector 429. The NAND string 430 includes an SGS transistor 431,

example memory cells

400, 433, . . . 435, and an SGD transistor 436. Passageways in the IPD layer 428 in the SGS and

SGD transistors

431, 436 allow the control gate layers 402 and floating gate layers to communicate. The control gate 402 and floating gate layers may be polysilicon and the tunnel oxide layer may be silicon oxide, for instance. The IPD layer 428 can be a stack of nitrides (N) and oxides (O) such as in a N—O—N—O—N configuration.

The NAND string may be formed on a substrate which comprises a p-type substrate region 455, an n-type well 456 and a p-type well 457. N-type source/drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6 and sd7 are formed in the p-type well. A channel voltage, Vch, may be applied directly to the channel region of the substrate.

FIG. 5 illustrates an example block diagram of the sense block SB1 of FIG. 1 . In one approach, a sense block comprises multiple sense circuits. Each sense circuit is associated with data latches. For example, the

example sense circuits

550 a, 551 a, 552 a, and 553 a are associated with the data latches 550 b, 551 b, 552 b, and 553 b, respectively. In one approach, different subsets of bit lines can be sensed using different respective sense blocks. This allows the processing load which is associated with the sense circuits to be divided up and handled by a respective processor in each sense block. For example, a sense circuit controller 560 in SB1 can communicate with the set of sense circuits and latches. The sense circuit controller 560 may include a pre-charge circuit 561 which provides a voltage to each sense circuit for setting a pre-charge voltage. In one possible approach, the voltage is provided to each sense circuit independently, e.g., via the data bus and a local bus. In another possible approach, a common voltage is provided to each sense circuit concurrently. The sense circuit controller 560 may also include a pre-charge circuit 561, a memory 562 and a processor 563. The memory 562 may store code which is executable by the processor to perform the functions described herein. These functions can include reading the

latches

550 b, 551 b, 552 b, 553 b which are associated with the

sense circuits

550 a, 551 a, 552 a, 553 a, setting bit values in the latches and providing voltages for setting pre-charge levels in sense nodes of the

sense circuits

550 a, 551 a, 552 a, 553 a. Further example details of the sense circuit controller 560 and the

sense circuits

550 a, 551 a, 552 a, 553 a are provided below.

In some embodiments, a memory cell may include a flag register that includes a set of latches storing flag bits. In some embodiments, a quantity of flag registers may correspond to a quantity of data states. In some embodiments, one or more flag registers may be used to control a type of verification technique used when verifying memory cells. In some embodiments, a flag bit's output may modify associated logic of the device, e.g., address decoding circuitry, such that a specified block of cells is selected. A bulk operation (e.g., an erase operation, etc.) may be carried out using the flags set in the flag register, or a combination of the flag register with the address register, as in implied addressing, or alternatively by straight addressing with the address register alone.

FIG. 6A is a perspective view of a set of blocks 600 in an example three-dimensional configuration of the memory array 126 of FIG. 1 . On the substrate are example blocks BLK0, BLK1, BLK2, BLK3 of memory cells (storage elements) and a peripheral area 604 with circuitry for use by the blocks BLK0, BLK1, BLK2, BLK3. For example, the circuitry can include voltage drivers 605 which can be connected to control gate layers of the blocks BLK0, BLK1, BLK2, BLK3. In one approach, control gate layers at a common height in the blocks BLK0, BLK1, BLK2, BLK3 are commonly driven. The substrate 601 can also carry circuitry under the blocks BLK0, BLK1, BLK2, BLK3, along with one or more lower metal layers which are patterned in conductive paths to carry signals of the circuitry. The blocks BLK0, BLK1, BLK2, BLK3 are formed in an intermediate region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuitry. Each block BLK0, BLK1, BLK2, BLK3 comprises a stacked area of memory cells, where alternating levels of the stack represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposing tiered sides from which vertical contacts extend upward to an upper metal layer to form connections to conductive paths. While four blocks BLK0, BLK1, BLK2, BLK3 are illustrated as an example, two or more blocks can be used, extending in the x- and/or y-directions.

In one possible approach, the length of the plane, in the x-direction, represents a direction in which signal paths to word lines extend in the one or more upper metal layers (a word line or SGD line direction), and the width of the plane, in the y-direction, represents a direction in which signal paths to bit lines extend in the one or more upper metal layers (a bit line direction). The z-direction represents a height of the memory device.

FIG. 6B illustrates an example cross-sectional view of a portion of one of the blocks BLK0, BLK1, BLK2, BLK3 of FIG. 6A. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers comprise two SGD layers, two SGS layers and four dummy word line layers DWLD0, DWLD1, DWLS0 and DWLS1, in addition to data word line layers (word lines) WL0-WL111. The dielectric layers are labelled as DL0-DL116. Further, regions of the stack 610 which comprise NAND strings NS1 and NS2 are illustrated. Each NAND string encompasses a

memory hole

618, 619 which is filled with materials which form memory cells adjacent to the word lines. A region 622 of the stack 610 is shown in greater detail in FIG. 6D and is discussed in further detail below.

The 610 stack includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of a source line SL. NS1 has a source-end 613 at a bottom 614 of the stack and a drain-end 615 at a top 616 of the stack 610. Contact line connectors (e.g., slits, such as metal-filled slits) 617, 620 may be provided periodically across the stack 610 as interconnects which extend through the stack 610, such as to connect the source line to a particular contact line above the stack 610. The

contact line connectors

617, 620 may be used during the formation of the word lines and subsequently filled with metal. A portion of a bit line BL0 is also illustrated. A conductive via 621 connects the drain-end 615 to BL0.

FIG. 6C illustrates a plot of memory hole diameter in the stack of FIG. 6B. The vertical axis is aligned with the stack of FIG. 6B and illustrates a width (wMH), e.g., diameter, of the

memory holes

618 and 619. The word line layers WL0-WL111 of FIG. 6A are repeated as an example and are at respective heights z0-z111 in the stack. In such a memory device, the memory holes which are etched through the stack have a very high aspect ratio. For example, a depth-to-diameter ratio of about 25-30 is common. The memory holes may have a circular cross-section. Due to the etching process, the memory hole width can vary along the length of the hole. Typically, the diameter becomes progressively smaller from the top to the bottom of the memory hole. That is, the memory holes are tapered, narrowing at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate so that the diameter becomes slightly wider before becoming progressively smaller from the top to the bottom of the memory hole.

Due to the non-uniformity in the width of the memory hole, the programming speed, including the program slope and erase speed of the memory cells can vary based on their position along the memory hole, e.g., based on their height in the stack. With a smaller diameter memory hole, the electric field across the tunnel oxide is relatively stronger, so that the programming and erase speed is relatively higher. One approach is to define groups of adjacent word lines for which the memory hole diameter is similar, e.g., within a defined range of diameter, and to apply an optimized verify scheme for each word line in a group. Different groups can have different optimized verify schemes.

FIG. 6D illustrates a close-up view of the region 622 of the stack 610 of FIG. 6B. Memory cells are formed at the different levels of the stack at the intersection of a word line layer and a memory hole. In this example,

SGD transistors

680, 681 are provided above

dummy memory cells

682, 683 and a data memory cell MC. A number of layers can be deposited along the sidewall (SW) of the memory hole 630 and/or within each word line layer, e.g., using atomic layer deposition. For example, each column (e.g., the pillar which is formed by the materials within a memory hole 630) can include a charge-trapping layer or film 663 such as SiN or other nitride, a tunneling layer 664, a polysilicon body or channel 665, and a dielectric core 666. A word line layer can include a blocking oxide/block high-k material 660, a metal barrier 661, and a conductive metal 662 such as Tungsten as a control gate. For example,

control gates

690, 691, 692, 693, and 694 are provided. In this example, all of the layers except the metal are provided in the memory hole 630. In other approaches, some of the layers can be in the control gate layer. Additional pillars are similarly formed in the different memory holes. A pillar can form a columnar active area (AA) of a NAND string.

When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer which is associated with the memory cell. These electrons are drawn into the charge-trapping layer from the channel, and through the tunneling layer. The Vth of a memory cell is increased in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel.

Each of the memory holes 630 can be filled with a plurality of annular layers comprising a blocking oxide layer, a charge trapping layer 663, a tunneling layer 664 and a channel layer. A core region of each of the memory holes 630 is filled with a body material, and the plurality of annular layers are between the core region and the word line in each of the memory holes 630.

The NAND string can be considered to have a floating body channel because the length of the channel is not formed on a substrate. Further, the NAND string is provided by a plurality of word line layers above one another in a stack, and separated from one another by dielectric layers.

FIG. 7A illustrates a top view of an example word line layer WL0 of the stack 610 of FIG. 6B. As mentioned, a three-dimensional memory device can comprise a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates of the SG transistors and memory cells. The layers used for the SG transistors are SG layers and the layers used for the memory cells are word line layers. Further, memory holes are formed in the stack and filled with a charge-trapping material and a channel material. As a result, a vertical NAND string is formed. Source lines are connected to the NAND strings below the stack and bit lines are connected to the NAND strings above the stack.

A block BLK in a three-dimensional memory device can be divided into sub-blocks, where each sub-block comprises a NAND string group which has a common SGD control line. For example, see the SGD lines/control gates SGD0, SGD1, SGD2 and SGD3 in the sub-blocks SBa, SBb, SBc and SBd, respectively. Further, a word line layer in a block can be divided into regions. Each region is in a respective sub-block and can extend between contact line connectors (e.g., slits) which are formed periodically in the stack to process the word line layers during the fabrication process of the memory device. This processing can include replacing a sacrificial material of the word line layers with metal. Generally, the distance between contact line connectors should be relatively small to account for a limit in the distance that an etchant can travel laterally to remove the sacrificial material, and that the metal can travel to fill a void which is created by the removal of the sacrificial material. For example, the distance between contact line connectors may allow for a few rows of memory holes between adjacent contact line connectors. The layout of the memory holes and contact line connectors should also account for a limit in the number of bit lines which can extend across the region while each bit line is connected to a different memory cell. After processing the word line layers, the contact line connectors can optionally be filed with metal to provide an interconnect through the stack.

In this example, there are four rows of memory holes between adjacent contact line connectors. A row here is a group of memory holes which are aligned in the x-direction. Moreover, the rows of memory holes are in a staggered pattern to increase the density of the memory holes. The word line layer or word line is divided into regions WL0 a, WL0 b, WL0 c and WL0 d which are each connected by a contact line 713. The last region of a word line layer in a block can be connected to a first region of a word line layer in a next block, in one approach. The contact line 713, in turn, is connected to a voltage driver for the word line layer. The region WL0 a has

example memory holes

710, 711 along a contact line 712. The region WL0 b has

example memory holes

714, 715. The region WL0 c has

example memory holes

716, 717. The region WL0 d has

example memory holes

718, 719. The memory holes are also shown in FIG. 7B. Each memory hole can be part of a respective NAND string. For example, the

memory holes

710, 714, 716 and 718 can be part of NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

Each circle represents the cross-section of a memory hole at a word line layer or SG layer. Example circles shown with dashed lines represent memory cells which are provided by the materials in the memory hole and by the adjacent word line layer. For example,

memory cells

720, 721 are in WL0 a,

memory cells

724, 725 are in WL0 b,

memory cells

726, 727 are in WL0 c, and

memory cells

728, 729 are in WL0 d. These memory cells are at a common height in the stack.

Contact line connectors (e.g., slits, such as metal-filled slits) 701, 702, 703, 704 may be located between and adjacent to the edges of the regions WL0 a-WL0 d. The

contact line connectors

701, 702, 703, 704 provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, where the conductive line is connected to a voltage driver in a peripheral region of the memory device.

FIG. 7B illustrates a top view of an example top dielectric layer DL116 of the stack of FIG. 6B. The dielectric layer is divided into regions DL116 a, DL116 b, DL116 c and DL116 d. Each region can be connected to a respective voltage driver. This allows a set of memory cells in one region of a word line layer being programmed concurrently, with each memory cell being in a respective NAND string which is connected to a respective bit line. A voltage can be set on each bit line to allow or inhibit programming during each program voltage.

The region DL116 a has the

example memory holes

710, 711 along a contact line 712, which is coincident with a bit line BL0. A number of bit lines extend above the memory holes and are connected to the memory holes as indicated by the “X” symbols. BL0 is connected to a set of memory holes which includes the

memory holes

711, 715, 717, 719. Another example bit line BL1 is connected to a set of memory holes which includes the

memory holes

710, 714, 716, 718. The contact line connectors (e.g., slits, such as metal-filled slits) 701, 702, 703, 704 from FIG. 7A are also illustrated, as they extend vertically through the stack. The bit lines can be numbered in a sequence BL0-BL23 across the DL19 layer in the x-direction.

Different subsets of bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, BL20 are connected to memory cells in a first row of cells at the right-hand edge of each region. BL2, BL6, BL10, BL14, BL18, BL22 are connected to memory cells in an adjacent row of cells, adjacent to the first row at the right-hand edge. BL3, BL7, BL11, BL15, BL19, BL23 are connected to memory cells in a first row of cells at the left-hand edge of each region. BL1, BL5, BL9, BL13, BL17, BL21 are connected to memory cells in an adjacent row of memory cells, adjacent to the first row at the left-hand edge.

The use of SSDs in the mining of certain types of cryptocurrencies may include a very high frequency of programming and erasing data in comparison to most consumer uses of SSDs. This is particularly pronounced if the SSD is employed as a high-speed buffer for generating plots of data that are later moved to long-term storage on another storage device, e.g., an HDD. This high frequency of programming and erasing the data on an SSD can shorten the SSDs operating life. Two such limiting factors to an SSD's operating life are the number of program-erase cycles (the number of times a memory cell is programmed and then erased) a memory block experiences and also the number of programmed data states that each memory cell may be programmed to (e.g., one, three, seven, or fifteen programmed data states which correspond with one, two, three, or four bits of data respectively) during each program-erase cycle. More specifically, with each program-erase cycle, a dielectric layer of each memory cell may degrade very slightly and leak electrons. Over a large number of program-erase cycles, especially where multiple bits of data are stored in each memory cell, the degrading dielectric layer can impair data retention. This is because the more bits per memory cell, the larger the programming voltage must be employed to program the memory cells to the highest data states, and larger programming voltages damage the dielectric layer more than small programming voltages. Thus, one approach to maximizing endurance is to utilize SLC (one bit per memory cell) or MLC (two bits per memory cell) rather than TLC (three bits per memory cell) or QLC (four bits per memory cell).

Additionally, there is an ever-increasing trend for increased block sizes with each block having an increasing number of word lines. From a system management size, such a large block size may not be desirable as it may impair performance every time data needs to be internally transferred. One known approach is to break the block up into a plurality of sub-blocks so that portions of the block can be individually erased and programmed without impacting other portions of the block. Techniques for breaking up a block into a plurality of sub-blocks are discussed in U.S. Pat. Nos. 10,157,680 and 10,726,920, both of which are herein incorporated by reference.

In some cases, the sub-blocks may be distinct tiers of a block that are separated from one another by a physical joint, which may include one or more tier select gate transistors. In other cases, a single block or tier may be divided into two or more sub-blocks without any tier select gate transistors or other physical joints separating the sub-blocks but rather with dummy joints comprising dummy word lines separating the sub-blocks. For example, turning now to FIG. 8 , an exemplary block 800 that has been divided into four sub-blocks (labeled as SB0, SB1, SB2, and SB3) is schematically shown. Each sub-block SB0-SB3 includes a plurality of data word lines that include memory cells that can be programmed to contain bits of data. Between each set of adjacent sub-blocks, the block includes a dummy joint, which includes pair of dummy word lines 802 containing memory cells that are not configured to be programmed to contain bits of data. Specifically, one dummy joint is located between sub-blocks SB0 and SB1; another dummy joint is located between sub-blocks SB1 and SB2; and yet another dummy joint is located between sub-blocks SB2 and SB3. The presence of the dummy word lines 802 reduces the total number of data word lines in the block 800, thereby reducing the memory density of the memory block. The illustrated block 800 includes four strings (Str0, Str1, Str2, Str3), each extending from an SGS to an SGD. In other embodiments, the block includes other numbers of strings, and those strings could have various configurations, e.g., U-shaped configurations.

The purpose of the dummy word lines 802 is to provide a bias gradient, or buffer, during an erase operation when a selected sub-block is being erased and an unselected sub-block adjacent the selected sub-block is not being erased. For example, with reference to FIG. 9 , when a targeted sub-block SB3 is being erased, a channel bias VERA is applied to the bit lines coupled with the strings of the block 800. Simultaneously, a very low erase voltage (e.g., 0-1 V) is applied to the control gates of the word lines of the targeted sub-block SB3 to effectuate erase of the memory cells of the selected sub-block SB3, and a higher inhibit voltage (e.g., VERA-5 V) is applied to the control gates of the word lines of the unselected sub-block SB2 to inhibit erase of the memory cells of the unselected sub-block SB2. In order to ensure an adequate erase speed of a boundary word line (i.e., the data word line of the selected sub-block SB3 nearest the unselected sub-block SB2), a gradient voltage (e.g., VER-13 V) is applied to the control gates of the dummy word lines 802. Thus, the gradient voltage applied to the dummy word lines is between the erase voltage applied to the word lines of the selected block SB3 and the inhibit voltage applied to the word lines of the unselected block SB2.

Turning now to FIG. 10 , an exemplary tier 1000 of a memory block is generally shown. As illustrated, the tier 1000 includes a plurality of sub-blocks (SB0, SB1, SB2, SB3) that are not separated with either dummy word lines or physical joints. Rather, the word lines of one sub-block are immediately adjacent the word lines of the next sub-block. The dummy word lines 1002 are only found between the uppermost sub-block SB3 and the SGDs and between the lowermost sub-block SB0 and the SGS. Thus, no physical or dummy word joints separate the sub-blocks SB0-SB3 from one another. In this illustrative example, the tier 1000 includes twenty data word lines WL0-WL19, which are separated into four sub-blocks (SB0, SB1, SB2, SB3) of five word lines each. In other embodiments, the tier may include fewer or more word lines, and those word lines could be divided into any suitable number of sub-blocks, each containing any suitable number of word lines. It should also be appreciated that the memory block may include any suitable number of strings and may include additional tiers, which each includes multiple sub-blocks, and those tiers (but not the sub-blocks within those tiers) may be separated from one another by physical joints.

The tier 1000 of FIG. 10 is able to operate effectively without any of the sub-blocks by following the erase techniques discussed below. Turning now to FIGS. 11 and 12A-D, a flow chart depicting the steps of an exemplary embodiment of an erase technique according to the present disclosure is generally shown in FIG. 11 , and FIG. 12 schematically shows these steps being sequentially performed on the above-discussed tier 1000 of a memory block. At step 1100, a command is received to the memory device to erase one sub-block of a tier that includes multiple sub-blocks. In the example of FIG. 12A, a command is received to erase only sub-block SB2, and SB0, SB1, and SB3 are not to be erased.

At decision step 1102, it is determined if an edge word line of an adjacent upper sub-block contains data. As illustrated in FIG. 12B, in this example, the adjacent upper sub-block is sub-block SB3, and it is determined if the memory cells of edge word line WL15 contain data.

If the answer at decision step 1102 is yes, then at step 1104, the data of the edge word line of the upper sub-block is read and copied to DRAM included in the memory device, to a temporary data latch, or to any suitable location where this data can temporarily be held. In the example of FIG. 12B, the data of the memory cells of word line WL15 is copied to the temporary location external of the tier 1000. The process then proceeds to step 1106. If the answer at decision step 1102 is no or if there is no adjacent upper sub-block, then the process skips step 1104 and proceeds directly from decision step 1102 to step 1106.

At decision step 1106, it is determined if an edge word line of an adjacent lower sub-block contains data. As illustrated in FIG. 12B, in this example, sub-block SB1 is the adjacent lower sub-block, and it is determined if the memory cells of edge word line WL9 contain data.

If the answer at decision step 1106 is yes, then at step 1108, the data of the edge word line of the lower sub-block is read and copied to DRAM included in the memory device, to a temporary data latch, or to any suitable location where this data can temporarily be held. In the example of FIG. 12B, the data of edge word line WL9 of sub-block SB1 is copied to the temporary location. The process then proceeds to step 1110. If the answer at decision step 1106 is no or if there is no adjacent lower sub-block, then the process skips step 1108 and proceeds directly from decision step 1106 to step 1110.

At step 1110, the control gates of the upper and/or lower edge word lines are biased to a relatively strong erase condition, i.e., a partial inhibit voltage. In an example embodiment, the partial inhibit voltage is VERA minus thirteen Volts (VERA-13 V), and this partial inhibit voltage is applied to the control gates of edge word lines WL9 and WL15.

Simultaneous to step 1110, at step 1112, the selected sub-block is erased. In the example of FIG. 12C, during the erase operation, the erase voltage VERA is applied to the bit lines coupled with the strings of the tier. In an example embodiment, VERA is twenty Volts (20 V). A very low erasing voltage (for example, 0.5 V) is applied to the control gates of the word lines of the selected block to effectuate erase of all memory cells of the selected block. Also during the erase operation, an erase inhibit voltage (for example, VERA-5 V) is applied to the control gates of all word lines of all unselected blocks except the edge word lines that are immediately adjacent the selected block i.e., the edge word lines that receive the partial inhibit voltage. In the example of FIG. 12C, the erase inhibit voltage is applied to the control gates of WL0-WL8 and WL16-WL19. The erase operation may include one or more erase pulses to decrease the threshold voltages of the memory cells of the selected block to an erased state. The partial inhibit voltage, which is applied to the upper and/or lower edge word lines during the erase operation, is between the very low erasing voltage and the erase inhibit voltage. The erase operation may also include an erase verify operation and may include additional erase pulses until erase verify is passed.

By maintaining the edge word lines of the adjacent unselected sub-blocks at the partial inhibit voltage rather than the inhibit voltage, the erase of the edge word lines of the selected sub-block is not impaired. However, because the edge word lines of the unselected blocks are held at the partial inhibit voltage rather than the inhibit voltage, the threshold voltages of the memory cells of these edge word lines will fall some from their respective data states, but not fall fully to the erased state. In other words, the data stored in the memory cells of the edge word lines is corrupted, albeit temporarily as discussed below.

At step 1114, the controller retrieves the data from the edge word lines of the upper and lower unselected blocks from the temporary location. At step 1116, the controller re-programs the data from the edge word line of the upper unselected block back into the edge word line of the upper unselected block and re-programs the data from the edge word line of the lower unselected block back into the edge word line of the lower unselected block. In the example of FIG. 12 , the data of WL9 is re-programmed back into WL9, and the data of WL15 is re-programmed back into WL15. Because each memory cell of WL9 and WL15 has only had its threshold voltage fall and will be programmed back to its original threshold voltage, the edge word lines do not have to be erased prior to re-programming as is commonly required prior to programming data. The re-programming operation may include the application of one or more programming pulses to the control gates of the edge word lines followed by one or more verify pulses.

At step 1116, the erase operation is completed. The selected sub-block can then be programmed again with new data.

The erase techniques of the subject disclosure allow for a low-cost sub-block mode, which can be used for low unselected sub-block program-erase disturb applications like the mining of certain types of cryptocurrencies. Further, these erase techniques improve reliability by allowing a physical tier that has some defects to continue to operate as one or more sub-blocks, thereby improving block management and manufacture yield.

The several aspects of the present disclosure may be embodied in the form of an apparatus, system, method, or computer program process. Therefore, aspects of the present disclosure may be entirely in the form of a hardware embodiment or a software embodiment (including but not limited to firmware, resident software, micro-code, or the like), or may be a combination of both hardware and software components that may generally be referred to collectively as a “circuit,” “module,” “apparatus,” or “system.” Further, various aspects of the present disclosure may be in the form of a computer program process that is embodied, for example, in one or more non-transitory computer-readable storage media storing computer-readable and/or executable program code.

Additionally, various terms are used herein to refer to particular system components. Different companies may refer to a same or similar component by different names and this description does not intend to distinguish between components that differ in name but not in function. To the extent that various functional units described in the following disclosure are referred to as “modules,” such a characterization is intended to not unduly restrict the range of potential implementation mechanisms. For example, a “module” could be implemented as a hardware circuit that includes customized very-large-scale integration (VLSI) circuits or gate arrays, or off-the-shelf semiconductors that include logic chips, transistors, or other discrete components. In a further example, a module may also be implemented in a programmable hardware device such as a field programmable gate array (FPGA), programmable array logic, a programmable logic device, or the like. Furthermore, a module may also, at least in part, be implemented by software executed by various types of processors. For example, a module may comprise a segment of executable code constituting one or more physical or logical blocks of computer instructions that translate into an object, process, or function. Also, it is not required that the executable portions of such a module be physically located together, but rather, may comprise disparate instructions that are stored in different locations and which, when executed together, comprise the identified module and achieve the stated purpose of that module. The executable code may comprise just a single instruction or a set of multiple instructions, as well as be distributed over different code segments, or among different programs, or across several memory devices, etc. In a software, or partial software, module implementation, the software portions may be stored on one or more computer-readable and/or executable storage media that include, but are not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based system, apparatus, or device, or any suitable combination thereof. In general, for purposes of the present disclosure, a computer-readable and/or executable storage medium may be comprised of any tangible and/or non-transitory medium that is capable of containing and/or storing a program for use by or in connection with an instruction execution system, apparatus, processor, or device.

Similarly, for the purposes of the present disclosure, the term “component” may be comprised of any tangible, physical, and non-transitory device. For example, a component may be in the form of a hardware logic circuit that is comprised of customized VLSI circuits, gate arrays, or other integrated circuits, or is comprised of off-the-shelf semiconductors that include logic chips, transistors, or other discrete components, or any other suitable mechanical and/or electronic devices. In addition, a component could also be implemented in programmable hardware devices such as field programmable gate arrays (FPGA), programmable array logic, programmable logic devices, etc. Furthermore, a component may be comprised of one or more silicon-based integrated circuit devices, such as chips, die, die planes, and packages, or other discrete electrical devices, in an electrical communication configuration with one or more other components via electrical conductors of, for example, a printed circuit board (PCB) or the like. Accordingly, a module, as defined above, may in certain embodiments, be embodied by or implemented as a component and, in some instances, the terms module and component may be used interchangeably.

Where the term “circuit” is used herein, it includes one or more electrical and/or electronic components that constitute one or more conductive pathways that allow for electrical current to flow. A circuit may be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, the circuit components may provide a return pathway for the electrical current. By contrast, in an open-looped configuration, the circuit components therein may still be regarded as forming a circuit despite not including a return pathway for the electrical current. For example, an integrated circuit is referred to as a circuit irrespective of whether the integrated circuit is coupled to ground (as a return pathway for the electrical current) or not. In certain exemplary embodiments, a circuit may comprise a set of integrated circuits, a sole integrated circuit, or a portion of an integrated circuit. For example, a circuit may include customized VLSI circuits, gate arrays, logic circuits, and/or other forms of integrated circuits, as well as may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In a further example, a circuit may comprise one or more silicon-based integrated circuit devices, such as chips, die, die planes, and packages, or other discrete electrical devices, in an electrical communication configuration with one or more other components via electrical conductors of, for example, a printed circuit board (PCB). A circuit could also be implemented as a synthesized circuit with respect to a programmable hardware device such as a field programmable gate array (FPGA), programmable array logic, and/or programmable logic devices, etc. In other exemplary embodiments, a circuit may comprise a network of non-integrated electrical and/or electronic components (with or without integrated circuit devices). Accordingly, a module, as defined above, may in certain embodiments, be embodied by or implemented as a circuit.

It will be appreciated that example embodiments that are disclosed herein may be comprised of one or more microprocessors and particular stored computer program instructions that control the one or more microprocessors to implement, in conjunction with certain non-processor circuits and other elements, some, most, or all of the functions disclosed herein. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), in which each function or some combinations of certain of the functions are implemented as custom logic. A combination of these approaches may also be used. Further, references below to a “controller” shall be defined as comprising individual circuit components, an application-specific integrated circuit (ASIC), a microcontroller with controlling software, a digital signal processor (DSP), a field programmable gate array (FPGA), and/or a processor with controlling software, or combinations thereof.

Further, the terms “program,” “software,” “software application,” and the like as may be used herein, refer to a sequence of instructions that is designed for execution on a computer-implemented system. Accordingly, a “program,” “software,” “application,” “computer program,” or “software application” may include a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of specific instructions that is designed for execution on a computer system.

Additionally, the terms “couple,” “coupled,” or “couples,” where may be used herein, are intended to mean either a direct or an indirect connection. Thus, if a first device couples, or is coupled to, a second device, that connection may be by way of a direct connection or through an indirect connection via other devices (or components) and connections.

Regarding, the use herein of terms such as “an embodiment,” “one embodiment,” an “exemplary embodiment,” a “particular embodiment,” or other similar terminology, these terms are intended to indicate that a specific feature, structure, function, operation, or characteristic described in connection with the embodiment is found in at least one embodiment of the present disclosure. Therefore, the appearances of phrases such as “in one embodiment,” “in an embodiment,” “in an exemplary embodiment,” etc., may, but do not necessarily, all refer to the same embodiment, but rather, mean “one or more but not all embodiments” unless expressly specified otherwise. Further, the terms “comprising,” “having,” “including,” and variations thereof, are used in an open-ended manner and, therefore, should be interpreted to mean “including, but not limited to . . . ” unless expressly specified otherwise. Also, an element that is preceded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the subject process, method, system, article, or apparatus that includes the element.

The terms “a,” “an,” and “the” also refer to “one or more” unless expressly specified otherwise. In addition, the phrase “at least one of A and B” as may be used herein and/or in the following claims, whereby A and B are variables indicating a particular object or attribute, indicates a choice of A or B, or both A and B, similar to the phrase “and/or.” Where more than two variables are present in such a phrase, this phrase is hereby defined as including only one of the variables, any one of the variables, any combination (or sub-combination) of any of the variables, and all of the variables.

Further, where used herein, the term “about” or “approximately” applies to all numeric values, whether or not explicitly indicated. These terms generally refer to a range of numeric values that one of skill in the art would consider equivalent to the recited values (e.g., having the same function or result). In certain instances, these terms may include numeric values that are rounded to the nearest significant figure.

In addition, any enumerated listing of items that is set forth herein does not imply that any or all of the items listed are mutually exclusive and/or mutually inclusive of one another, unless expressly specified otherwise. Further, the term “set,” as used herein, shall be interpreted to mean “one or more,” and in the case of “sets,” shall be interpreted to mean multiples of (or a plurality of) “one or more,” “ones or more,” and/or “ones or mores” according to set theory, unless expressly specified otherwise.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or be limited to the precise form disclosed. Many modifications and variations are possible in light of the above description. The described embodiments were chosen to best explain the principles of the technology and its practical application to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the technology is defined by the claims appended hereto.

Claims

What is claimed is:

1. A method of operating a memory device, comprising the steps of:

preparing a block that includes a plurality of memory cells arranged in a plurality of data word lines, the plurality of data word lines being arranged in a plurality of sub-blocks, at least some of the plurality of sub-blocks being not separated from one another by physical joints or by dummy word lines;

receiving an instruction to erase the memory cells of a selected sub-block of the plurality of sub-blocks;

reading data of at least one edge word line of at least one unselected sub-block of the plurality of sub-blocks, the at least one edge word line being located immediately adjacent the selected sub-block;

storing the data in a temporary location external of the block;

erasing the selected sub-block; and

re-programing the data to the memory cells of the at least one edge word line after erase of the selected sub-block is completed.

2. The method as set forth in claim 1, wherein during the step of erasing the selected sub-block, a partial inhibit voltage is applied to a control gate of the at least one edge word line.

3. The method as set forth in claim 2, wherein during the step of erasing the selected sub-block, a first voltage is applied to the control gates of the word lines of the selected sub-block and an inhibit voltage is applied to the control gates of the word lines of the unselected sub-blocks other than the at least one edge word line, and wherein the partial inhibit voltage is between the first voltage and the inhibit voltage.

4. The method as set forth in claim 3, wherein the first voltage is zero Volts or is less than one Volt.

5. The method as set forth in claim 1, wherein the block includes a plurality of tiers and wherein each tier includes a plurality of sub-blocks that are not separated from one another by dummy word lines.

6. The method as set forth in claim 1, wherein the step of reading the data of the at least one edge word line and storing the data in a temporary location external of the block is further defined as reading data of an edge word line of an upper unselected block on one side of the selected block and reading data of an edge word line of a lower unselected block on an opposite side of the selected block from the upper unselected block and wherein the data from both edge word lines is stored in the temporary location.

7. The method as set forth in claim 1, wherein the temporary location is DRAM or data latches.

8. The method as set forth in claim 1, wherein the memory cells of the block contain no greater than two bits of data per memory cell.

9. A memory device, comprising:

a block including a plurality of memory cells arranged in a plurality of data word lines, the plurality of data word lines being arranged in a plurality of sub-blocks which are not separated from one another by physical joints or by dummy word lines;

a controller configured to erase the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks, the controller being further configured to:

read data of at least one edge word line of at least one unselected sub-block, the at least one edge word line being located immediately adjacent the selected sub-block;

store the data in a temporary location external of the block;

erase the memory cells of the selected sub-block; and

re-program the data to the memory cells of the at least one edge word line of the at least one unselected sub-block after erase of the selected sub-block is completed.

10. The memory device as set forth in claim 9, wherein while erasing the memory cells of the selected sub-block, the controller is configured to apply a partial inhibit voltage to a control gate of the at least one edge word line.

11. The memory device as set forth in claim 10, wherein while erasing the memory cells of the selected sub-block, the controller applies a first voltage to the control gates of the word lines of the selected sub-block and applies an inhibit voltage to the control gates of the word lines of the unselected sub-blocks other than the edge word lines and wherein the partial inhibit voltage is between the first voltage and the inhibit voltage.

12. The memory device as set forth in claim 11, wherein the first voltage is zero Volts or is less than one Volt.

13. The memory device as set forth in claim 9, wherein the block includes a plurality of tiers and wherein each tier includes a plurality of sub-blocks that are not separated from one another by dummy word lines.

14. The memory device as set forth in claim 9, wherein the controller is further configured to read data of both an edge word line of an upper unselected block on one side of the selected block and an edge word line of a lower unselected block on an opposite side of the selected block from the upper unselected block and is further configured to store the data from both edge word lines in the temporary location.

15. The memory device as set forth in claim 9, wherein the temporary location is DRAM or data latches.

16. The memory device as set forth in claim 9, wherein the controller is configured to program no more than two bits of data into each memory cell.

17. An apparatus, comprising:

an erasing means for erasing the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks, the erasing means being further configured to:

read data of at least one edge word line of at least one unselected sub-block;

store the data in a temporary location external of the block;

erase the memory cells of the selected sub-block; and

re-program the data to the memory cells of the at least one edge word line.

18. The apparatus as set forth in claim 17, wherein while erasing the memory cells of the selected sub-block, the erasing means is configured to apply a partial inhibit voltage to a control gate of the at least one edge word line.

19. The apparatus as set forth in claim 18, wherein while erasing the memory cells of the selected sub-block, the erasing means applies a first voltage to the control gates of the word lines of the selected sub-block and applies an inhibit voltage to the control gates of the word lines of the unselected sub-blocks other than the edge word lines and wherein the partial inhibit voltage is between the first voltage and the inhibit voltage.

20. The apparatus as set forth in claim 19, wherein the first voltage is zero Volts or is less than one Volt.