US10276730B2 - Stacked Schottky diode - Google Patents
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- US10276730B2 US10276730B2 US15/812,446 US201715812446A US10276730B2 US 10276730 B2 US10276730 B2 US 10276730B2 US 201715812446 A US201715812446 A US 201715812446A US 10276730 B2 US10276730 B2 US 10276730B2
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- 239000004065 semiconductor Substances 0.000 claims abstract description 117
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 26
- -1 GaAs compound Chemical class 0.000 claims description 23
- 239000002019 doping agent Substances 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 150000002736 metal compounds Chemical class 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66212—Schottky diodes
Definitions
- the invention relates to a stacked Schottky diode.
- High-blocking Schottky diodes made of SiC are known from Josef Lutz et al., Semiconductor Power Devices, Springer Verlag, 2011, ISBN 978-3-642-11124-2, p. 238.
- a Schottky diode having an epitaxial layer structure comprising GaAs with an n + substrate and a layer comprising nickel for forming the Schottky contact is known from “GaAs Power Devices,” Chapter 3, pp. 22-26 by German Ashkinazi, ISBN 965-7094-19-4.
- a stacked Schottky diode which has a stack with a top side and a bottom side.
- the stack comprises at least three semiconductor layers and a first connection contact layer, which is materially connected to the bottom side of the stack, and a second connection contact layer connected to the top side of the stack.
- the second connection contact layer comprises a metal or a metal compound or is formed of a metal or a metal compound, wherein the second terminal contact layer forms a Schottky contact, and wherein the second connection contact layer is disposed in a partial region of the top side and the second connection contact layer is bounded by edges.
- a first semiconductor layer formed as an n + layer is placed on the bottom side of the stack, wherein the first semiconductor layer has a dopant concentration of at least 10 19 N/cm ⁇ 3 and a layer thickness between 50 ⁇ m and 400 ⁇ m.
- the first semiconductor layer comprises a GaAs compound or is formed of a GaAs compound.
- a second semiconductor layer formed as an n ⁇ layer is placed on the first semiconductor layer.
- the second semiconductor layer has a dopant concentration between 10 12 and 10 16 N/cm ⁇ 3 and a layer thickness between 10 ⁇ m and 300 ⁇ m, and comprises a GaAs compound or is formed of a GaAs compound.
- a third semiconductor layer formed as a p + layer, is placed on the second semiconductor layer.
- the third semiconductor layer has a dopant concentration between 10 12 and 10 16 N/cm ⁇ 3 and a layer thickness between 10 nm and 10 ⁇ m, and comprises a GaAs compound or is formed of a GaAs compound.
- the stack has a plurality of p + regions, each spaced apart from one another.
- the p + regions are formed as ribs running parallel to the top side of the stack and have a dopant concentration of 5 ⁇ 10 17 to 5 ⁇ 10 20 N/cm ⁇ 3 and extend from the top side of the stack into the second semiconductor layer.
- All edges of the second connection contact layer can run within the p + regions.
- connection contact layer can be referred to as the anode and the first connection contact layer as the cathode.
- first connection contact layer forms an ohmic contact and the second connection contact layer a metal-semiconductor junction.
- connection contact layers in order to bond, for example, the Schottky diode.
- the Schottky contact can be completely shielded from penetration of the high electrical field by means of the very thin low-doped p layer as the third semiconductor layer and the p + regions which are formed at the edges and preferably below the second contact connection layer.
- the ribs are relatively close together, so that only relatively narrow n ⁇ layer regions remain between adjacent ribs.
- blocking voltages of the Schottky diode can be easily reached in a range between 200 V and 600 V and also above 600 V. Fast switching times can be achieved in conjunction with the effective mass of GaAs substantially smaller in comparison with silicon.
- the Schottky diode of the invention is thus particularly suited as a freewheeling diode in the field of power electronics, preferably in the case of switching power supply units and converters.
- the second connection contact layer is preferably quadrangular or circular and preferably covers more than 30%, most preferably more than 50% of the area of the semiconductor layer on the top of the stack.
- the stack can be formed monolithically.
- Monolithic semiconductor structures are fabricated by means of epitaxial production processes such as LPE or MOVPE.
- the three indicated semiconductor layers can be arranged in the indicated sequence and are materially connected to one another.
- the p + regions are produced by implantation, wherein all regions, except for the rib-shaped regions to be formed, are previously covered by a masking step on the top side.
- the distance between two directly adjacent p + regions is between 3 ⁇ m and 30 ⁇ m.
- connection contact layer completely covers all other p + regions except for the regions arranged along the edges.
- a fourth semiconductor layer formed as an n ⁇ layer, is placed on the third semiconductor layer, wherein the fourth semiconductor layer has a dopant concentration between of 10 12 N/cm ⁇ 3 and 10 16 N/cm ⁇ 3 and a layer thickness between 0.005 ⁇ m and 10 ⁇ m and comprises a GaAs compound or is formed of a GaAs compound.
- the fourth semiconductor layer is formed on the top side of the stack and the p + regions extend through the fourth semiconductor layer.
- the second contact layer covers the top side of the stack only partially.
- the first contact layer covers the bottom side of the stack completely or except for a narrow edge region of less than 1 mm.
- the stacked layer structure formed of the p ⁇ layer, the n ⁇ layer, and the n + layer, has a semiconductor bond formed between the n ⁇ layer and the p ⁇ layer.
- semiconductor bond can be used synonymously with the term ‘wafer bond’.
- the layer structure has a first partial stack, comprising the p ⁇ layer, and a second partial stack, comprising the n + layer and the n ⁇ layer. The first partial stack and the second partial stack are each formed monolithically.
- the p ⁇ layer can have a doping of less than 10 13 N/cm ⁇ 3 or a doping between 10 13 N/cm ⁇ 3 and 10 15 N/cm ⁇ 3 .
- the p ⁇ layer is thinned before or after the bonding by a grinding process to a thickness between 10 ⁇ m and 300 ⁇ m.
- a first partial stack is provided, wherein the first partial stack comprises the p ⁇ layer, and further a second stack is provided, wherein the second partial stack comprises the n ⁇ layer and the n + layer, and the first partial stack is connected to the second stack by a wafer bonding process.
- the second stack is formed in which the n ⁇ layer can be formed proceeding from an n ⁇ substrate; in this case the n ⁇ substrate or the n ⁇ layer will be or is connected to the second stack by a wafer bonding process.
- the n ⁇ substrate or the n ⁇ layer is thinned to the desired thickness.
- the thickness of the n ⁇ layer is within a range between 50 ⁇ m and 250 ⁇ m.
- the doping of the n ⁇ layer can be in a range between 10 13 N/cm ⁇ 3 and 10 15 N/cm ⁇ 3 .
- An advantage of the wafer bonding is that thick n ⁇ layers can be easily produced. A longer deposition process during epitaxy is not necessary as a result. The number of stacking errors can also be reduced by means of the bonding.
- the n ⁇ layer has a doping greater than 10 10 N/cm ⁇ 3 and less than 10 13 N/cm ⁇ 3 . Because the doping is extremely low, the n ⁇ layer can also be understood as an intrinsic layer.
- the n + layer is produced on the n ⁇ substrate or the n ⁇ layer in a range between 10 18 N/cm ⁇ 3 and less than 5 ⁇ 10 19 N/cm ⁇ 3 .
- the thinning of the n ⁇ substrate or the n ⁇ layer occurs for example by means of a CMP step, i.e., by means of chemical mechanical polishing.
- an auxiliary layer is deposited on the front side of the diode structure.
- the rear side of the diode structure can then be thinned and placed on a carrier.
- the front side is then removed.
- the surface of the n + layer and the surface of the p ⁇ layer are metallized in order to form and electrically connect the Schottky diode.
- the cathode of the semiconductor diode is materially connected to a base formed as a heat sink after the metallization.
- the anode is formed on the surface of the diode on the p ⁇ layer.
- the p ⁇ intermediate layer comprises: a thickness between 10 ⁇ m and 25 ⁇ m and a thickness between 40 ⁇ m and 90 ⁇ m for the n ⁇ layer results in a blocking voltage of about 900 V.
- the p ⁇ intermediate layer comprises: a thickness between 25 ⁇ m and 35 ⁇ m and a thickness between 40 ⁇ m and 70 ⁇ m for the n ⁇ layer results in a blocking voltage of about 1200 V.
- the p ⁇ intermediate layer comprises: a thickness between 35 ⁇ m and 50 ⁇ m and a thickness between 70 ⁇ m and 150 ⁇ m for the n ⁇ layer results in a blocking voltage of about 1500 V.
- the diodes described above in the first to third embodiments can be also be designated as punch-through diodes in regard to the formation of the space charge regions.
- the p ⁇ intermediate layer comprises: a thickness between 10 ⁇ m and 25 ⁇ m and a thickness between 60 ⁇ m and 110 ⁇ m for the n ⁇ layer.
- the p ⁇ intermediate layer comprises: a thickness between 10 ⁇ m and 25 ⁇ m and a thickness between 70 ⁇ m and 140 ⁇ m for the n ⁇ layer.
- the p ⁇ intermediate layer comprises: a thickness between 35 ⁇ m and 50 ⁇ m and a thickness between 80 ⁇ m and 200 ⁇ m for the n ⁇ layer.
- the diodes described above in the fourth to sixth embodiments can also be designated as “non-reach-through” diodes in regard to the formation of space charge regions.
- FIG. 1 shows a schematic view of an embodiment of the invention of a stacked Schottky diode
- FIG. 2 shows a schematic view of an embodiment of the invention of a stack of a stacked Schottky diode
- FIG. 3 shows a schematic view of an embodiment of the invention of a stacked Schottky diode
- FIG. 4 shows a top view of an embodiment of the Schottky diode of the invention in FIG. 3 .
- FIG. 1 shows a view of a first embodiment, a stacked Schottky diode 10 having a stack 30 having at least three semiconductor layers 20 , 22 , 24 , with a top side 32 and a bottom side 34 , a first connection contact layer 40 materially connected to the bottom side 34 of the stack 30 and a metallic second connection contact layer 50 , materially connected to a partial area of top side 32 of the stack, for forming a Schottky contact.
- First semiconductor layer 20 of stack 30 is placed as an n + layer on bottom side 34 of stack 30 and has a dopant concentration of at least 10 19 N/cm ⁇ 3 and a layer thickness between 50 ⁇ m and 400 ⁇ m.
- Second semiconductor layer 22 of stack 30 is placed on first semiconductor layer 20 and is materially connected to first semiconductor layer 20 .
- Second semiconductor layer 22 is formed as an n ⁇ layer and has a dopant concentration in a range of 10 12 to 10 16 cm ⁇ 3 and a layer thickness of 10 ⁇ m to 300 ⁇ m.
- Third semiconductor layer 24 of stack 30 is formed as a p ⁇ layer and is materially connected to second semiconductor layer 22 .
- Third semiconductor layer 24 has a dopant concentration in a range of 10 12 -10 16 cm ⁇ 3 and a layer thickness of 0.01 ⁇ m to 10 ⁇ m.
- All three semiconductor layers 20 , 22 , 24 comprise a GaAs compound.
- Stack 30 additionally has two p + regions 60 , 62 .
- the two p + regions 60 , 62 each have a dopant concentration of 5 ⁇ 10 18 to 5 ⁇ 10 20 cm ⁇ 3 and are formed as ribs spaced apart from one another, wherein each p + region 60 , 62 , therefore each rib, extends in a direction perpendicular to top side 32 of stack 30 from top side 32 of stack 30 into n ⁇ layer 22 and forms a strip in a first direction parallel to top side 32 of stack 30 .
- second connection contact layer 50 covers a part of top side 32 of stack 30 , wherein the part comprises a first surface region, located between the two p + regions 60 , 62 , and in each case only one partial region, adjacent to the first surface region, of the two p + regions, and second connection contact layer 50 is materially connected to third semiconductor layer 24 .
- FIG. 2 A further embodiment of a stack 30 of a Schottky diode 10 of the invention is shown in the diagram of FIG. 2 . Only the differences from the illustration in FIG. 1 will be explained below.
- Stack 30 has a fourth semiconductor layer 26 .
- Fourth semiconductor layer 26 is formed as an n ⁇ layer with a dopant concentration of 1012-1016 cm ⁇ 3 and a layer thickness of 0.005 ⁇ m to 10 ⁇ m and also comprises a GaAs compound.
- the n ⁇ layer is materially connected to the underlying p ⁇ layer and forms the top side of the stack.
- the p + region extends in each case through the n ⁇ layer.
- a further embodiment of a Schottky diode 10 of the invention is shown as a side view or as a top view in the diagrams in FIGS. 3 and 4 , respectively. Only the differences from the illustration in FIG. 1 will be explained below.
- the Schottky diode has seven rib-shaped p + regions 60 . 1 to 60 . 7 spaced apart from one another.
- the part of surface 32 which part is materially connected to second connection contact layer 50 in order to form a Schottky contact, extends from first p + region 60 . 1 up to seventh p + region 60 . 7 , wherein first p + region 60 . 1 and seventh p + region 60 . 7 are each covered only partially by the metal layer.
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Abstract
Description
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DE102016013542.5 | 2016-11-14 | ||
DE102016013542.5A DE102016013542A1 (en) | 2016-11-14 | 2016-11-14 | Stacked Schottky diode |
DE102016013542 | 2016-11-14 |
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US20180138321A1 US20180138321A1 (en) | 2018-05-17 |
US10276730B2 true US10276730B2 (en) | 2019-04-30 |
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EP (1) | EP3321972B1 (en) |
JP (1) | JP6570599B2 (en) |
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DE (1) | DE102016013542A1 (en) |
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US10847626B2 (en) | 2017-12-21 | 2020-11-24 | 3-5 Power Electronics GmbH | Stacked III-V semiconductor component |
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DE102019000166B4 (en) * | 2019-01-14 | 2022-08-04 | Tdk-Micronas Gmbh | device semiconductor structure |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US549655A (en) | 1895-11-12 | Contact device for electric railways | ||
US5017976A (en) | 1988-12-02 | 1991-05-21 | Kabushiki Kaisha Toshiba | Semiconductor device having intermediate layer for pinching off conductive path during reverse bias application |
DE4036222A1 (en) | 1990-11-14 | 1992-05-21 | Bosch Gmbh Robert | METHOD FOR THE PRODUCTION OF SEMICONDUCTOR ELEMENTS, IN PARTICULAR DIODES |
WO2000074130A1 (en) | 1999-05-28 | 2000-12-07 | Advanced Power Devices, Inc. | Discrete schottky diode device with reduced leakage current |
JP2005045212A (en) | 2003-07-04 | 2005-02-17 | Matsushita Electric Ind Co Ltd | Schottky barrier diode and manufacturing method thereof |
EP1947700A2 (en) | 2007-01-19 | 2008-07-23 | Cree, Inc. | Low voltage diode with reduced parasitic resistance and method for fabricating |
US20090289262A1 (en) * | 2008-05-21 | 2009-11-26 | Cree, Inc. | Junction barrier schottky diodes with current surge capability |
US8415671B2 (en) * | 2010-04-16 | 2013-04-09 | Cree, Inc. | Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices |
US8841683B2 (en) * | 2011-03-03 | 2014-09-23 | Kabushiki Kaisha Toshiba | Semiconductor rectifier device |
US20150236104A1 (en) | 2012-08-30 | 2015-08-20 | Kabushiki Kaisha Toshiba | Semiconductor device |
DE102015204138A1 (en) | 2015-03-09 | 2016-09-15 | Robert Bosch Gmbh | Semiconductor device with a trench MOS-barrier Schottky diode |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3005302C2 (en) * | 1980-02-13 | 1985-12-12 | Telefunken electronic GmbH, 7100 Heilbronn | Varactor or mixer diode |
JPH01257370A (en) * | 1988-04-07 | 1989-10-13 | Sanken Electric Co Ltd | Schottky barrier semiconductor device |
US7061067B2 (en) * | 2003-07-04 | 2006-06-13 | Matsushita Electric Industrial Co., Ltd. | Schottky barrier diode |
-
2016
- 2016-11-14 DE DE102016013542.5A patent/DE102016013542A1/en not_active Withdrawn
-
2017
- 2017-11-10 EP EP17001845.1A patent/EP3321972B1/en active Active
- 2017-11-13 JP JP2017218542A patent/JP6570599B2/en active Active
- 2017-11-14 US US15/812,446 patent/US10276730B2/en active Active
- 2017-11-14 CN CN201711124875.2A patent/CN108074987B/en active Active
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US549655A (en) | 1895-11-12 | Contact device for electric railways | ||
US5017976A (en) | 1988-12-02 | 1991-05-21 | Kabushiki Kaisha Toshiba | Semiconductor device having intermediate layer for pinching off conductive path during reverse bias application |
DE68918062T2 (en) | 1988-12-02 | 1995-03-02 | Toshiba Kawasaki Kk | Semiconductor device with an intermediate layer for constricting a current path during reverse bias. |
DE4036222A1 (en) | 1990-11-14 | 1992-05-21 | Bosch Gmbh Robert | METHOD FOR THE PRODUCTION OF SEMICONDUCTOR ELEMENTS, IN PARTICULAR DIODES |
WO1992009099A1 (en) * | 1990-11-14 | 1992-05-29 | Robert Bosch Gmbh | Method of manufacturing semiconductor elements, in particular diodes |
WO2000074130A1 (en) | 1999-05-28 | 2000-12-07 | Advanced Power Devices, Inc. | Discrete schottky diode device with reduced leakage current |
JP2005045212A (en) | 2003-07-04 | 2005-02-17 | Matsushita Electric Ind Co Ltd | Schottky barrier diode and manufacturing method thereof |
EP1947700A2 (en) | 2007-01-19 | 2008-07-23 | Cree, Inc. | Low voltage diode with reduced parasitic resistance and method for fabricating |
US20090289262A1 (en) * | 2008-05-21 | 2009-11-26 | Cree, Inc. | Junction barrier schottky diodes with current surge capability |
US8415671B2 (en) * | 2010-04-16 | 2013-04-09 | Cree, Inc. | Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices |
US8841683B2 (en) * | 2011-03-03 | 2014-09-23 | Kabushiki Kaisha Toshiba | Semiconductor rectifier device |
US20150236104A1 (en) | 2012-08-30 | 2015-08-20 | Kabushiki Kaisha Toshiba | Semiconductor device |
DE102015204138A1 (en) | 2015-03-09 | 2016-09-15 | Robert Bosch Gmbh | Semiconductor device with a trench MOS-barrier Schottky diode |
US9941381B2 (en) | 2015-03-09 | 2018-04-10 | Robert Bosch Gmbh | Semiconductor device having a trench MOS barrier Schottky diode |
Non-Patent Citations (6)
Title |
---|
"GaAs Power Devices", Chapter 3, pp. 22-27 by German Ashkinazi, ISGN 965-7094-19-4. |
Hadizad P et al: "High voltage GaAs rectifiers for high frequency, high power density switching applications", Power Modulator Symposium, 1996., Twenty-Second International Boca Raton, FL, USA Jun. 25-27, 1, New York, NY, USA, IEEE, US, Jun. 25, 1996 (Jun. 25, 1996), pp. 35-38, XP010205246, DOI: 10.1109/MODSYM.1996.564443, ISBN: 978-0-7803-3076-4. |
HADIZAD P., OMMEN J., SALIH A., VARADARAJAN S., SLOCUMB R., ROBLES E., WOLK M., THERO C.: "High voltage GaAs rectifiers for high frequency, high power density switching applications", POWER MODULATOR SYMPOSIUM, 1996., TWENTY-SECOND INTERNATIONAL BOCA RATON, FL, USA 25-27 JUNE 1996, NEW YORK, NY, USA,IEEE, US, 25 June 1996 (1996-06-25) - 27 June 1996 (1996-06-27), US, pages 35 - 38, XP010205246, ISBN: 978-0-7803-3076-4, DOI: 10.1109/MODSYM.1996.564443 |
Josef Lutz et al., "Semiconductor Power Devices", Springer Verlag, 2011, ISBN 978-3-642-11124-2, pp. 238-239. |
Mori M et al: "A novel soft and fast recovery diode (SFD) with thin p-layer formed by Al-Si electrode", Power Semiconductor Devices and ICS, 1991. ISPSD '91., Proceedings of the 3rd International Symposium on Baltimore, MD, USA Apr. 22-24, 1, New York, N.Y. USA, IEEE, US, Apr. 22, 1991 (Apr. 22, 1991), pp. 113-117, XP010044304, DOI: 10.1109/ISPD.1991.146079, ISBN: 978-0-7803-0009-5. |
MORI M., YASUDA Y., SAKURAI N., SUGAWARA Y.: "A novel soft and fast recovery diode (SFD) with thin p-layer formed by Al-Si electrode", POWER SEMICONDUCTOR DEVICES AND ICS, 1991. ISPSD '91., PROCEEDINGS OF THE 3RD INTERNATIONAL SYMPOSIUM ON BALTIMORE, MD, USA 22-24 APRIL 1991, NEW YORK, NY, USA,IEEE, US, 22 April 1991 (1991-04-22) - 24 April 1991 (1991-04-24), US, pages 113 - 117, XP010044304, ISBN: 978-0-7803-0009-5, DOI: 10.1109/ISPSD.1991.146079 |
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US10847626B2 (en) | 2017-12-21 | 2020-11-24 | 3-5 Power Electronics GmbH | Stacked III-V semiconductor component |
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JP6570599B2 (en) | 2019-09-04 |
EP3321972B1 (en) | 2020-01-15 |
JP2018082173A (en) | 2018-05-24 |
CN108074987A (en) | 2018-05-25 |
DE102016013542A1 (en) | 2018-05-17 |
US20180138321A1 (en) | 2018-05-17 |
CN108074987B (en) | 2021-01-12 |
EP3321972A1 (en) | 2018-05-16 |
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