TWM607620U - Write driving circuit - Google Patents

Abstract

This creation proposes a novel architecture write drive circuit, which is composed of a first PMOS transistor (P71), a first NMOS transistor (M71), a second NMOS transistor (M72), and a third NMOS transistor. Crystal (M73), a second PMOS transistor (Mcap), a first inverter (INV71), a second inverter (INV72), an input data (Din), a row of decoder output signals (Y) , A first delay circuit (Delay 1), a second delay circuit (Delay 1), and a first high power supply voltage (VDDH1), wherein the source and drain of the second PMOS transistor (Mcap) The poles are connected together to form a capacitor, and when the write drive circuit is in an inactive state, the second PMOS transistor (Mcap) is in an ON state, thereby increasing the capacitance of the capacitor. The write drive circuit is designed to be lower than the ground voltage in the first stage of writing logic 0 to accelerate the speed of writing logic 0, and in the second stage of writing logic 0, it is pulled back to ground The voltage level of the voltage is used to reduce the write interference of the half-selected cell. Moreover, the write drive circuit is designed to be higher than the power supply voltage of the memory cell when writing logic 1 to increase the memory cell. The initial instantaneous voltage of the storage node of the cell for writing, thereby increasing the speed of writing logic 1.

Description

Write drive circuit

This creation is related to a write driving circuit, especially a type that can be used for single port or dual port static random access memory (SRAM) or dynamic Random access memory (Dynamic Random Access Memory, referred to as DRAM) and has both high-speed write logic 1, high-speed write logic 0, and write drive circuit with low write interference.

Single-port or dual-port static random access memory (SRAM) or dynamic random access memory (DRAM) is composed of multiple rows of memory cell and multiple rows of memory cell, each row of memory cell and each A row of memory cell includes a plurality of memory cells, each memory cell has a storage node for storing data, each row of memory cell is controlled by a corresponding character line, and each row of memory cells The cell is connected to the corresponding bit line. The conventional single-port static random access memory (SRAM) unit cell is shown in Figure 1. Among them, PMOS transistors (P1) and (P2) are called load transistors, and NMOS transistors (M1) And (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL and BLB are respectively It is a bit line and a complementary bit line. Because the single-port SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial instant of the read operation ) Another driving transistor is turned on, and the initial instantaneous voltage (V _AR ) of storage node A must satisfy equation (1):

V _AR =V _DD ×(R _M1 )/(R _M1 +R _M3 )<V _TM2 (1) to prevent half-selected cell disturbance during reading, where V _AR stands for storage node Read the initial instantaneous voltage of A, R _M1 and R _M3 respectively represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply voltage and the NMOS transistor (M2) The threshold voltage, which results in the current drive capability ratio (ie, cell ratio) between the drive transistor and the access transistor is usually set between 2.2 and 3.5.

Next, we discuss the single-port and dual-port architecture of static random access memory (SRAM). The 6T static random access memory (SRAM) cell in Figure 1 is a single-port static random access memory (SRAM) cell. An example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, reading and writing are achieved through the same pair of bit lines, so only reading can be performed at the same time Or write operation. Therefore, when you want to design a dual-port static random access memory cell with simultaneous read and write capabilities, you need to add two more access transistors and another pair of bit lines ( Please refer to the circuit shown in Figure 2, where WBL and WBLB are bit line pairs for writing, RBL and RBLB are bit line pairs for reading, WWL is a word line for writing, and RWL is a character for reading. line).

In the static random access memory, in order to efficiently drive the bit line (BL) and the complementary bit line (BLB), a write driving circuit must be provided. So far, many high-performance write driver circuit technologies have been proposed, such as the "Low active power write driver with reduced-power boost circuit" proposed in Patent Document 1 (US10199090B2, granted to Apple Incorporation on February 5, 108) , Its designated representative The figure is shown in Figure 3 (same as US10199090B2, Figure 3), and the corresponding operation sequence diagram is shown in Figure 4 (same as US10199090B2, Figure 5); and as shown in Patent Document 2 "Capacitive lines and multi- Voltage negative bitline write assist driver" (US10332570B1, granted to ADVANCED MICRO DEVICES Incorporation on June 25, 108), its designated representative diagram is shown in Figure 5 (same as US10332570B1 Figure 2), and the corresponding operation sequence diagram is 6 Figure (same as US10332570B1, Figure 3) is shown; Figure 4 (same as US10199090B2, Figure 5) and Figure 6 (same as US10332570B1, Figure 3) shows that these patent documents are in order to increase the speed of writing logic 0 , The bit line voltage level after the writing logic 0 period is designed to be lower than the ground voltage, but the speed of writing logic is mainly determined by the writing period before, and these patent documents lack the method to improve the writing logic 1. The speed mechanism, so there is still room for improvement.

In view of this, the main purpose of this creation is to propose a write drive circuit with a novel architecture, which is designed to be lower than the ground voltage in the first stage of writing logic 0 to accelerate the speed of writing logic 0 , And pull back to the voltage level of the ground voltage in the second stage of writing logic 0 to alleviate the write disturbance of the half-selected cell.

The secondary purpose of this creation is to propose a write drive circuit with a novel architecture, which is designed to be higher than the power supply voltage of the SRAM cell when writing logic 1 to increase the initial instant of writing to the storage node of the SRAM cell Voltage to increase the speed of writing logic 1.

Another purpose of this creation is to propose a write drive circuit with a novel architecture. When the write drive circuit is in a non-enabled state, the PMOS transistor used to form a capacitor in the write drive circuit is designed to be turned on (ON). ) State to increase the capacitance value of the capacitor, thereby enhancing the capacitive coupling effect.

This creation proposes a novel architecture write drive circuit, which is composed of a first PMOS transistor (P71), a first NMOS transistor (M71), a second NMOS transistor (M72), and a third NMOS transistor. Crystal (M73), a second PMOS transistor (Mcap), a first inverter (INV71), a second inverter (INV72), an input data (Din), a row of decoder output signals (Y) , A first delay circuit (Delay 1), a second delay circuit (Delay 1), and a first high power supply voltage (VDDH1), wherein the source and drain of the second PMOS transistor (Mcap) The poles are connected together to form a capacitor, and when the write drive circuit is in an inactive state, the second PMOS transistor (Mcap) is in an ON state, thereby increasing the capacitance of the capacitor. The write drive circuit is designed to be lower than the ground voltage in the first stage of writing logic 0 to accelerate the speed of writing logic 0, and in the second stage of writing logic 0, it is pulled back to ground The voltage level of the voltage is used to reduce the write interference of the half-selected cell. Moreover, the write drive circuit is designed to be higher than the power supply voltage of the memory cell when writing logic 1 to increase the memory cell. The initial instantaneous voltage of the storage node of the cell for writing, thereby increasing the speed of writing logic 1.

P71: The first PMOS transistor

M71: The first NMOS transistor

M72: Second NMOS transistor

M73: The third NMOS transistor

Mcap: second PMOS transistor

INV71: the first inverter

INV72: second inverter

Din: input data

Delay 1: The first delay circuit

Delay 2: The second delay circuit

Y: Line decoder output signal

VDDH1: The first high power supply voltage

GND: Ground voltage

C _BL : Parasitic capacitance

BL: bit line

BLB: Complementary bit line

M1...M4: NMOS transistor

P1...P2: PMOS transistor

WBL, WBLB: bit line pair for writing

RBL, RBLB: bit line pair for reading

WWL: Character line for writing

RWL: Character line for reading

VDD: power supply voltage

Figure 1 is a schematic diagram showing the circuit of a conventional 6T single-port static random access memory cell;

Figure 2 is a schematic diagram showing the circuit of a conventional 8T dual-port static random access memory cell;

Figure 3 is a schematic diagram showing the circuit in Figure 3 of US10199090B2;

Figure 4 shows the operation sequence diagram of Figure 5 of US10199090B2;

Figure 5 is a schematic diagram showing the circuit in Figure 2 of US10332570B1;

Figure 6 shows the operation sequence diagram of Figure 3 of US10332570B1;

Figure 7 shows the write drive circuit of the preferred embodiment of the present invention;

Figure 8 is a schematic diagram showing the circuit diagram of the writing drive circuit in the first stage of writing logic 0;

Figure 9 is a schematic circuit diagram showing the second stage of writing logic 0 in the writing drive circuit of this authoring;

Figure 10 is a schematic diagram showing the circuit of the writing logic 1 in the writing drive circuit of the present invention.

According to the above-mentioned purpose, this author proposes a novel architecture write drive circuit, as shown in Figure 7, which is composed of a first PMOS transistor (P71), a first NMOS transistor (M71), and a second NMOS transistor (M72), a third NMOS transistor (M73), a second PMOS transistor (Mcap), a first inverter (INV71), a second inverter (INV72), an input data (Din), a row of decoder output signal (Y), a first delay circuit (Delay 1), a second delay circuit (Delay 2), and a first high power supply voltage (VDDH1), wherein the first delay circuit The source and drain of the two PMOS transistors (Mcap) are connected together to form a capacitor, and the second PMOS transistor (Mcap) is turned on (ON) when the write drive circuit is in a non-enabled state State, thereby increasing the capacitance value of the capacitor, thereby enhancing the capacitive coupling effect.

The source, gate, and drain of the first PMOS transistor (P71) are respectively connected to the first high power supply voltage (VDDH1), the output of the first inverter (INV71), and the first NMOS transistor. The drain of the crystal (M71), the source, gate and drain of the first NMOS transistor (M71) are respectively connected to the drain of the third NMOS transistor (M73) and the first inverter ( INV71) output and the drain of the first PMOS transistor (P71), the first The source, gate and drain of the two NMOS transistors (M72) are respectively connected to the ground voltage, the output of the first delay circuit (Delay 1) and the drain of the first PMOS transistor (P71), the second The source, gate and drain of the three NMOS transistors (M73) are respectively connected to the ground voltage, the output of the second inverter (INV72) and the source of the first NMOS transistor (M71), the The input of the first inverter (INV71) is for receiving the input data (Din), and the output is connected to the gate of the first PMOS transistor (P71) and the gate of the first NMOS transistor (M71) And the input of the first delay circuit (Delay 1), the input of the second inverter (INV72) is for receiving the row decoder output signal (Y), and the output is connected to the second delay circuit (Delay 2). ) Input and the gate of the third NMOS transistor (M73), the source and drain of the second PMOS transistor (Mcap) are connected together to form a capacitor (Cap), and in the write drive When the circuit is in a non-enable state, the second PMOS transistor (Mcap) is in an ON state to increase the capacitance of the capacitor. One end of the capacitor (Cap) (that is, the second PMOS transistor ( The source and drain of the Mcap connected together are connected to the output of the second delay circuit (Delay 2), and the other end of the capacitor (Cap) (that is, the gate of the second PMOS transistor (Mcap) ) Is connected to the source of the first NMOS transistor (M71) and the drain of the third NMOS transistor (M73), wherein the drain of the first PMOS transistor (P71), the drain of the first NMOS transistor The drain of the crystal (M71) and the drain of the second NMOS transistor (M72) are jointly connected to the corresponding bit line (BL), and the corresponding bit line (BL) is the first to write logic 0 The stage is designed to be lower than the voltage level of the ground voltage to accelerate the speed of writing logic 0, and when writing logic 1, it is designed to be higher than the power supply voltage (VDD) of the memory cell. A high power supply voltage (VDDH1) voltage level to accelerate the speed of writing logic 1.

Whether the write drive circuit is enabled or not is determined by the logic level of the row decoder output signal (Y). When the row decoder output signal (Y) is at a logic low level, the write drive The circuit is in an inactive state, and when the row decoder output signal (Y) is at a logic high level, the write drive circuit is in an enabled state. When the output signal (Y) of the row decoder is at the low logic level of the inactive state, the output of the second inverter (INV72) is at the high logic level. On the one hand, the third NMOS transistor (M73) is turned on, and the other On the one hand, after the delay time provided by the second delay circuit (Delay 2), one end of the capacitor (Cap) (that is, the source and drain of the second PMOS transistor (Mcap) connected together) is charged, because The turned-on third NMOS transistor (M73) makes the other end of the capacitor (Cap) (that is, the gate of the second PMOS transistor (Mcap)) the ground voltage, and one end of the capacitor (Cap) ( That is, the source and drain of the second PMOS transistor (Mcap) connected together will maintain the voltage level of the power supply voltage (VDD) due to the charging of the capacitor (Cap).

The write drive circuit adopts a two-stage operation when writing logic 0 in the enabled state. In the first stage of the write drive circuit being enabled, the row decoder output signal (Y) at the logic high level makes the The output of the second inverter (INV72) is at a logic low level. On the one hand, the third NMOS transistor (M73) is turned off (OFF), and on the other hand, it is provided by the second delay circuit (Delay 2). After the delay time, one end of the capacitor (Cap) is quickly discharged to the ground voltage. At this time, the input data (Din) is at a logic low level, so that the output of the first delay circuit (Delay 1) is at a logic high level. Then the first NMOS transistor (M71) is turned on, and the first PMOS transistor (P71) is turned off (OFF), so the voltage level of the corresponding bit line (BL) is at the level of the write drive circuit The first stage of writing logic 0 satisfies equation (2):

V _BL1 = -VDD×Cap/(Cap+C _BL ) (2)

Wherein, V _BL1 represents the voltage level of the corresponding bit line (BL) in the first stage of writing logic 0. _{The absolute value of V BL1} is designed to be smaller than the threshold voltage of the access transistor of the memory cell, for example Can be designed to be -100mV, -150mV or -200mV, VDD is the voltage level of the power supply voltage (VDD) of the memory cell, and Cap and C _BL respectively represent the capacitance value of the capacitor (Cap) and the corresponding The parasitic capacitance value of the bit line (BL).

It is worth noting here that in the first stage of enabling the write drive circuit, the second NMOS transistor (M71) is in the OFF state. Figure 8 shows the first stage of the write drive circuit being enabled. A schematic diagram of the circuit of the first stage; wherein the delay time provided by the first delay circuit (Delay 1) is designed to be greater than the delay time provided by the second delay circuit (Delay 2), and the second delay circuit (Delay 2) _{2) It is used to ensure that the voltage level (V BL1} ) of the corresponding bit line (BL) in the first stage of writing logic 0 can be effectively provided to the corresponding bit line (BL), and it can also be required , The second delay circuit (Delay 2) is omitted.

When the input data (Din) at the logic low level has passed the delay time provided by the first inverter (INV71) and the first delay circuit (Delay 1), the write drive circuit enters the enabled second At this time, since the second NMOS transistor (M72) is in the on state, the voltage level of the corresponding bit line (BL) satisfies the equation ( 3):

V _BL2 =0 (3)

Wherein, V _BL2 represents the voltage level of the corresponding bit line (BL) in the second stage of writing logic 0; Figure 9 shows the circuit of the write drive circuit in the second stage of writing logic 0 Schematic. The sum of the time of the first phase and the second phase of writing logic 0 is the time when the corresponding character line is in the enabled state. It is worth noting here that the second NMOS transistor (M72) is used to ensure that the corresponding bit line (BL) can be effectively charged to _{the voltage level (V BL2) in the second stage of writing logic 0} The ground voltage.

The write drive circuit is designed to be higher than the memory cell when writing logic 1 The power supply voltage (VDD) can increase the initial instantaneous voltage of the storage node of the memory cell, thereby increasing the speed of writing logic 1. When the write drive circuit is writing logic 1, the input data (Din) at a logic high level makes the output of the first inverter (INV71) a logic low level, so on the one hand, the first PMOS transistor is turned on (P71) On the other hand, the first NMOS transistor (M71) is turned off (OFF), so the voltage level of the corresponding bit line (BL) is satisfied when the write drive circuit writes logic 1 Equation (4):

V _BL =VDDH1 (4)

Wherein, V _BL represents the voltage level of the corresponding bit line (BL) in writing logic 1, VDDH1 is the voltage level of the first high power supply voltage (VDDH1), where the first high power supply voltage The voltage level of (VDDH1) is designed to be higher than the voltage level of the power supply voltage (VDD) of the memory cell, for example, it can be designed to be 100mV, 150mV higher than the power supply voltage (VDD) of the memory cell Or 200mV; Fig. 10 shows the schematic diagram of the write-in driving circuit in writing logic 1. The time for writing logic 1 is the time when the corresponding word line is in the enabled state. It is worth noting here that the first PMOS transistor (P71) is used to ensure that the corresponding bit line (BL) can provide a higher voltage level than the memory during the _{writing of the logic 1 voltage level (V BL)} The first high power supply voltage (VDDH1) of the voltage level of the power supply voltage (VDD) of the bulk cell to the corresponding bit line (BL).

【Creative Effect】

The write drive circuit proposed in this creation has the following functions:

(1) Increase the speed of writing logic 0: The writing drive circuit is designed to be lower than the ground voltage in the first stage of writing logic 0 to accelerate the speed of writing logic 0. Logic 0 The second stage is to pull back to the voltage level of the ground voltage to reduce the write interference of the half-selected cell;

(2) Increase the speed of writing logic 1: The writing drive circuit is designed to be higher than the power supply voltage of the memory cell when writing logic 1, so as to increase the initial instant of writing to the storage node of the memory cell Voltage to increase the speed of writing logic 1.

P71: The first PMOS transistor

M71: The first NMOS transistor

M72: Second NMOS transistor

M73: The third NMOS transistor

Mcap: second PMOS transistor

INV71: the first inverter

INV72: second inverter

Din: input data

Delay 1: The first delay circuit

Delay 2: The second delay circuit

Y: Line decoder output signal

VDDH1: The first high power supply voltage

GND: Ground voltage

BL: bit line

C _BL : Parasitic capacitance

Claims (10)

A write drive circuit for random access memory. The random access memory system is composed of a plurality of rows of memory cell and a plurality of rows of memory cell, each row of memory cell and each row of memory cell Each cell includes a plurality of memory cells. Each memory cell has a storage node for storing data. Each row of the memory cell is provided with a write drive circuit. The write drive circuit is composed of a first PMOS circuit. Crystal (P71), a first NMOS transistor (M71), a second NMOS transistor (M72), a third NMOS transistor (M73), a second PMOS transistor (Mcap), a first inverter (INV71), a second inverter (INV72), an input data (Din), a row of decoder output signal (Y), a first delay circuit (Delay 1), a second delay circuit (Delay 1) And a first high power supply voltage (VDDH1); Wherein, the source, gate and drain of the first PMOS transistor (P71) are respectively connected to the first high power supply voltage (VDDH1), the output of the first inverter (INV71) and the first The drain of NMOS transistor (M71); The source, gate and drain of the first NMOS transistor (M71) are respectively connected to the drain of the third NMOS transistor (M73), the output of the first inverter (INV71) and the first The drain of PMOS transistor (P71); The source, gate and drain of the second NMOS transistor (M72) are respectively connected to the ground voltage, the output of the first delay circuit (Delay 1) and the drain of the first PMOS transistor (P71); The source, gate and drain of the third NMOS transistor (M73) are respectively connected to the ground voltage, the output of the second inverter (INV72) and the source of the first NMOS transistor (M71) ； The input of the first inverter (INV71) is for receiving the input data (Din), and the output is connected Connected to the gate of the first PMOS transistor (P71), the gate of the first NMOS transistor (M71) and the input of the first delay circuit (Delay 1); The input of the second inverter (INV72) is for receiving the row decoder output signal (Y), and the output is connected to the input of the second delay circuit (Delay 2) and the third NMOS transistor (M73) Gate The source and drain of the second PMOS transistor (Mcap) are connected together to form a capacitor (Cap), and when the write drive circuit is in a non-enabled state, the second PMOS transistor (Mcap) In an ON state, the capacitance value of the capacitor can be effectively increased by the capacitive coupling effect. One end of the capacitor (Cap) (that is, the source and the source of the second PMOS transistor (Mcap) connected together The drain) is connected to the output of the second delay circuit (Delay 2), and the other end of the capacitor (Cap) (that is, the gate of the second PMOS transistor (Mcap)) is connected to the first NMOS circuit The source of the crystal (M71) and the drain of the third NMOS transistor (M73); Wherein, the drain of the first PMOS transistor (P71), the drain of the first NMOS transistor (M71), and the drain of the second NMOS transistor (M72) are connected to the corresponding bit line ( BL), the corresponding bit line (BL) in the first stage of writing logic 0 is designed to be lower than the voltage level of the ground voltage to accelerate the speed of writing logic 0, while writing logic 1 When it is designed to be higher than the voltage level of the first high power supply voltage (VDDH1) of the power supply voltage (VDD) of the random access memory, to accelerate the speed of writing logic 1; Wherein, the corresponding bit line (BL) is pulled back to the ground voltage in the second stage of writing logic 0 to alleviate the write interference of the half-selected memory cell; Wherein, the sum of the time of the first stage and the second stage of writing logic 0 is equal to the time when the corresponding character line is in the enabled state, and the time of writing logic 1 is also equal to the corresponding character line. can State time Wherein, the second NMOS transistor (M72) is used to ensure that the voltage level of the corresponding bit line (BL) in the second stage of writing logic 0 can be effectively charged to the ground voltage; Wherein, the first PMOS transistor (P71) is used to ensure that the corresponding bit line (BL) can provide a higher voltage than the power supply voltage of the random access memory during the writing of the logic 1 voltage level The first high power supply voltage (VDDH1) at the voltage level of (VDD) to the corresponding bit line (BL). The write drive circuit described in item 1 of the scope of patent application, wherein the write drive circuit satisfies the following equation in the first stage of writing logic 0: V _BL1 =-VDD×Cap/(Cap+C _BL ) Wherein, V _BL1 represents the voltage level of the corresponding bit line (BL) in the first stage of writing logic 0, and the _{absolute value of V BL1} is designed to be smaller than the threshold voltage of the access transistor of the memory cell. VDD is the voltage level of the power supply voltage (VDD) of the random access memory, and Cap and C _BL respectively represent the capacitance value of the capacitor (Cap) and the parasitic capacitance value of the corresponding bit line (BL) ; And Wherein, the second delay circuit (Delay 2) is used to ensure that the voltage level (V _BL1 ) of the corresponding bit line (BL) in the first stage of writing logic 0 can be effectively provided to the corresponding bit Line (BL). In the write drive circuit described in item 2 of the scope of patent application, the voltage level of the corresponding bit line (BL) in the first stage of writing logic 0 is designed to be -100mV. According to the write drive circuit described in item 2 of the scope of patent application, the voltage level of the corresponding bit line (BL) in the first stage of writing logic 0 is designed to be -150mV. The write drive circuit described in item 2 of the scope of patent application, wherein the corresponding bit line (BL) The voltage level in the first stage of writing logic 0 is designed to be -200mV. In the write drive circuit described in claim 1, wherein the delay time provided by the first delay circuit (Delay 1) is designed to be greater than the delay time provided by the second delay circuit (Delay 2). For the write drive circuit described in item 1 of the scope of patent application, the second delay circuit (Delay 2) can be omitted as required. The write drive circuit described in the first item of the scope of patent application, wherein the first high power supply voltage (VDDH1) is designed to be higher than the power supply voltage (VDD) of the random access memory by 100 mV quasi. The write drive circuit described in the first item of the scope of patent application, wherein the first high power supply voltage (VDDH1) is designed to be higher than the power supply voltage (VDD) of the random access memory by 150mV quasi. The write drive circuit described in the first item of the scope of patent application, wherein the first high power supply voltage (VDDH1) is designed to be 200mV higher than the power supply voltage (VDD) of the random access memory quasi.

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