TWM594242U - Amplifier circuits with voltage interpolation function and driving device - Google Patents

Abstract

An amplifier circuit with voltage interpolation function includes a plurality of input pairs configured to receive a first voltage and a second voltage and coupled to a voltage output terminal via an output stage. The input pairs include at least a first input pair and a second input pair. The first input pair is coupled between a ground node and a pair of terminals and includes at least a first transistor pair. The size of the first transistor pair corresponds to a first ratio. The second input pair is coupled between the ground node and the pair of terminals and includes at least a second transistor pair. The size of the second transistor pair corresponds to a second ratio. The second ratio does not equal to the first ratio and is a multiple of the first ratio. The voltage output at the voltage output terminal is a result obtained by interpolating the first voltage and the second voltage according to the first ratio and the second ratio.

Description

Amplifier circuit and driving device with voltage interpolation function

This creation relates to an amplifier circuit with a voltage interpolation function, especially an amplifier circuit that uses multiple input pairs to perform voltage interpolation according to unequal ratios at the input stage of the amplifier circuit to improve resolution.

As the size and resolution of the liquid crystal panel increase, the area occupied by the display driver chip layout becomes larger and larger. Among them, the 6-bit digital-to-analog converter is a design that is generally recognized as having better chip area utilization. However, the 6-bit image resolution has been unable to meet the image resolution requirements of larger LCD panels. For example, the image resolution requirements of today's large-size LCD panels have reached 10 bits. To meet the requirement of at least 10-bit image resolution and upgrade a 6-bit digital-to-analog converter to a 10-bit digital-to-analog converter, the digital-to-analog converter will occupy a large circuit area, making The chip area utilization rate will drop significantly.

Therefore, while improving image resolution, how to reduce the wafer area and production cost has become a very important issue in the industry.

One purpose of this creation is to provide an amplifier circuit to effectively reduce the chip area and improve the image resolution.

Another purpose of this creation is to provide an amplifier circuit for a driving device of a liquid crystal display to effectively reduce the chip area and improve the image resolution.

An embodiment of the present invention provides an amplifier circuit with a voltage interpolation function, which includes a plurality of input pairs for receiving a first voltage and a second voltage, and is coupled to a voltage output terminal through an output stage. The input pair includes at least a first input pair and a second input pair. The first input pair is coupled between a ground point and a pair of nodes, and includes at least a first pair of transistors. The size of the first pair of transistors corresponds to the first ratio. The second input pair is coupled between the ground point and the pair of nodes, and includes at least a second pair of transistors. The size of the second pair of transistors corresponds to a second ratio, where the second ratio is not equal to the first ratio, the second The ratio is a multiple of the first ratio, and the voltage output by the voltage output terminal is an interpolation result of the first voltage and the second voltage weighted by one of the first ratio and the second ratio.

Another embodiment of the present invention provides an amplifier circuit with a voltage interpolation function, which includes a plurality of input pairs for receiving a first voltage and a second voltage, and is coupled to a voltage output terminal through an output stage. The input pair includes at least a first input pair, a second input pair, and a third input pair. The first input pair is coupled between a ground point and a pair of nodes, and includes at least a first pair of transistors. The size of the first pair of transistors corresponds to the first ratio. The second input pair is coupled between the ground point and the pair of nodes, and includes at least a second pair of transistors. The size of the second pair of transistors corresponds to the second ratio. The third input pair is coupled between the ground point and the pair of nodes, and includes at least a third pair of transistors. The size of the third pair of transistors corresponds to the third ratio. The first ratio, the second ratio, and the third ratio are not equal to each other, and the voltage output by the voltage output terminal is an interpolation result of the first voltage and the second voltage weighted by one of the first ratio, the second ratio, and the third ratio.

Another embodiment of the present invention provides a driving device for a liquid crystal display, including the above amplifier circuit, wherein the amplifier circuit is integrated into the driving device.

FIG. 1 is a schematic circuit diagram showing an example of an amplifier circuit with voltage interpolation function according to the first embodiment of the present creation. The amplifier circuit 100 is used to generate an output voltage Vo according to the interpolation of the two input voltages VIH and VIL, which includes an input stage 110 and an output stage 120. The input stage 110 includes a plurality of input pairs, such as input pairs 111-0 to 111-4, for receiving input voltages VIH and VIL. The input pairs 111-0 to 111-4 are coupled between the ground point and a pair of nodes A and B, coupled to the output stage 120 through the nodes A and B, and coupled to the voltage output of the amplifier circuit 100 through the output stage 120端Vout. The output stage 120 is coupled to the nodes A and B and the voltage output terminal Vout, which is used to convert the single-ended voltage form to the voltage output terminal Vout according to the differential current output by the input stage 110, and provide the circuit for the subsequent stage Enough drive current. The input pairs 111-0 to 111-4 respectively include a first input terminal and a second input terminal. The first input terminal is coupled to a pair of switching devices for selecting bits according to the corresponding one, for example, selecting bits E>0>~E>4>, to selectively receive the input voltage VIH or VIL, and the second input terminal It is coupled to the voltage output terminal Vout for receiving the feedback output voltage Vo.

公式(1)

公式(2)

公式(3)

公式(4)

公式(5)

公式(6)

公式(7) According to the first embodiment of the present invention, the input pairs 111-0 to 111-4 may include a pair of transistors, and the output current of each pair of transistors is equal to the respective transconductance (gm) and the first input The product of the voltage VIH or VIL received at the terminal is shown in the following formula (2)~formula (6). Among them, the square of the transduction gm is proportional to the product of the input terminal size (W/L) of each pair of transistors and the amount of current I supplied, as shown in the following formula (1). The output voltage Vo of the output stage 120 is equal to the product of the sum of the output currents of all input pairs 111-0 to 111-4 and the equivalent output impedance Ro (not shown), as shown in the following formula (7). That is, the output voltage Vo can be determined by the ratio of the input terminal size (W/L) of each pair of transistors to the amount of current supplied.

Formula 1)

Formula (2)

Formula (3)

Formula (4)

Formula (5)

Formula (6)

Formula (7)

~

分別代表輸入對111-0~111-4的輸出電流，

~

分別代表輸入對111-0~111-4的轉導，

代表各輸入對於第一輸入端所接收的電壓，即VIH或VIL。 among them

~

Represent the output current of input pair 111-0~111-4,

~

Represent the input transduction of 111-0~111-4,

Represents the voltage received by each input for the first input, namely VIH or VIL.

According to the first embodiment of the present creation, the input pairs 111-0 to 111-4 may include a pair of transistors, respectively, and the size of each pair of transistors has a multiple relationship (or, when considering some process errors, it is generally a multiple relationship) ), the transistor pair is used to generate corresponding currents according to different ratios, so that the transistor pair has a multiple relationship (or generally multiple relationship). For example, you can enter the W/L ratio of a pair of transistors included in 111-0 as the basic size unit, that is, the aspect ratio of the pair of transistors can be set to 1 unit, enter The current I generated for 111-0 is also set as the basic current unit. The size of other input pairs 111-1~111-4 can be flexibly selected or designed according to the basic size unit.

As in the example shown in FIG. 1, the size of the input pair 111-1 can be designed to be the same as the input pair 111-0. That is, the pair of transistors included in the input pair 111-1 may also have an aspect ratio of 1 unit. Therefore, the size of the transistor pair included in the input pair 111-1 may correspond to a first ratio, where the first ratio is 1, and the current generated by the transistor pair is 1*I. In the embodiment of the present invention, the ratio represents the ratio of the size of the transistor pair to the above basic size unit. Similarly, the size of the transistor pair included in input pair 111-0 also corresponds to the first ratio.

The size of the input pair 111-2 can be designed to be twice the input pair 111-0. That is, the pair of transistors included in the input pair 111-2 may have an aspect ratio of 2 units. Therefore, the size of the transistor pair included in the input pair 111-2 may correspond to a second ratio, in which case the second ratio is 2, and the magnitude of the current generated by the transistor pair is 2*I.

The size of the input pair 111-3 can be designed to be four times the input pair 111-0. That is, the pair of transistors included in the input pair 111-3 may have an aspect ratio of 4 units. Therefore, the size of the transistor pair included in the input pair 111-3 may correspond to a third ratio, where the third ratio is 4, and the current generated by the transistor pair is 4*I.

The size of the input pair 111-4 can be designed to be eight times the input pair 111-0. That is, the pair of transistors included in the input pair 111-4 may have an aspect ratio of 8 units. Therefore, the size of the transistor pair included in the input pair 111-4 may correspond to a fourth ratio, in which case the fourth ratio is 8, and the current generated by the transistor pair is 8*I.

In the embodiment of the present invention, the input pairs 111-0 to 111-4 in the input stage 110 may weight the input voltage VIH and VIL according to an unequal ratio, and output the voltage Vo at the voltage output terminal Vout, that is, The input voltage VIH and VIL are weighted by one of the unequal ratio interpolation results as the output voltage Vo. Among them, in this embodiment, the fourth ratio is greater than the third ratio, the third ratio is greater than the second ratio, the second ratio is greater than the first ratio, and the fourth ratio is a multiple of the third ratio, and the third ratio is the second ratio The multiple, the fourth ratio, the third ratio and the second ratio are all multiples of the first ratio.

公式(8) As in the example shown in FIG. 1, the input stage 110 can use the input pairs 111-0 to 111-4 to respectively weight the input voltage VIH or VIL according to the ratios of 1, 1, 2, 4, 8, etc. to generate an interpolation result. In order to realize 4-bit voltage interpolation, the sum of the ratio values is the number of interpolation voltages. More specifically, the input stage 110 can use the input pair 111-0~111-4 to weight the input voltage VIH or VIL according to the unequal ratio to generate 16 different levels of voltage, of which 16=1+1+ 2+4+8, which is the 4th power of 2, to realize 4-bit voltage interpolation. The relationship between the output voltage Vo and the input voltage VIH or VIL, and the unequal ratio can be indicated by the following equivalent formula (8).

Formula (8)

~

表示選擇位元E>0>~E>4>的反相信號，其中於第1、2圖所示之範例中，若用以接收選擇位元E>0>~E>4>的接收端額外繪製了圓圈，代表實際輸入該電路的信號將會是選擇位元的反相信號(例如，

~

之其中一者)，若用以接收選擇位元E>0>~E>4>的接收端並未繪製圓圈，代表實際輸入該電路的信號為選擇位元(例如，E>0>~E>4>之其中一者)。於本創作之實施例中，可藉由於接收端設置一反相器或其他類似功能的電路實施將選擇位元反相的操作。 In formula (8),

~

Represents the inverted signal of the selection bit E>0>~E>4>, in the example shown in Figures 1 and 2, if it is used to receive the receiving end of the selection bit E>0>~E>4> An extra circle is drawn, indicating that the signal actually input to the circuit will be the inverted signal of the selected bit (for example,

~

One of them), if the receiver used to receive the selected bit E>0>~E>4> is not drawn with a circle, it means that the signal actually input to the circuit is the selected bit (for example, E>0>~E >4> one of them). In the embodiment of the present invention, the operation of inverting the selected bit can be implemented by a circuit provided with an inverter or other similar functions at the receiving end.

It is worth noting that the above ratios are for illustration only, not for limiting the scope of this creation. According to the embodiment of the present invention, the selection of the ratio depends on the required number of interpolation voltages, and can be flexibly combined and changed. For example, to achieve 5-bit voltage interpolation, an input pair can be added, and the size of the transistor pair included in this input pair can be designed to be 16 times the basic size unit (ie, the corresponding ratio 16), or two additional input pairs can be added, and the size of the transistor pairs contained in the two input pairs can be designed to be 8 times the basic size unit (ie, the corresponding ratio is 8).

Compared with the prior art, the amplifier circuit 100 of the present invention can use fewer transistor pairs to achieve the same voltage interpolation function, thereby greatly reducing the number of control signal traces and switching devices required by the amplifier circuit, which is effective Reduce the area of the circuit layout.

FIG. 2 is a schematic circuit diagram showing an example of an amplifier circuit with voltage interpolation function according to the second embodiment of the present creation. The amplifier circuit 200 is used to generate an output voltage Vo according to the interpolation of the two input voltages VIH and VIL, which includes an input stage 210 and an output stage 220. The input stage 210 includes a plurality of input pairs, for example, input pairs 211-0 to 211-4, for receiving input voltages VIH and VIL. The input pair 211-0~211-4 are coupled between the ground point and a pair of nodes C and D, are coupled to the output stage 220 through the nodes C and D, and are coupled to the voltage output of the amplifier circuit 200 through the output stage 220端Vout. The output stage 220 is coupled to the nodes C, D and the voltage output terminal Vout. It is used to convert the single-ended voltage output to the voltage output terminal Vout according to the differential current output by the input stage 210 and provide it to the subsequent stage circuit. Enough drive current.

The input pairs 211-0 to 211-4 respectively include two pairs of transistors, and each pair of transistors may include a first input terminal and a second input terminal. More specifically, the first input of one pair of transistors of each input pair is used to receive the voltage VIH, the first input of the other pair of transistors is used to receive the voltage VIL, and the second input of each pair of transistors The terminal is coupled to the voltage output terminal Vout for receiving the feedback output voltage Vo. In addition, each input pair 211-0~211-4 is further coupled to a pair of switching devices for selecting bits according to the corresponding one, for example, selecting bits E>0>~E>4>, selectively based on all The required input voltage VIH or VIL generates the corresponding current.

According to the second embodiment of the present invention, the input pairs 211-0 to 211-4 can include two pairs of transistors, and the output current of each pair of transistors is equal to the respective transconductance (gm) and the first input The product of the voltage received at the terminal (a person skilled in this art can make adaptive adjustments based on the above formula (2)~formula (6) to derive the corresponding formula). Among them, the first input terminal of one pair of transistors of each input pair is used to receive the input voltage VIH, and the first input terminal of the other pair of transistors is used to receive the input voltage VIL. Wherein, the square of the transduction gm is proportional to the product of the input terminal size (W/L) of each pair of transistors and the amount of current I supplied, as shown in the above formula (1). The output voltage Vo of the output stage 220 is equal to the product of the sum of the output currents of all input pairs 211-0~211-4 and the equivalent output impedance Ro (not shown) (a person skilled in this art can use the above formula (7) Make adaptive adjustments and derive the corresponding formula). That is, the output voltage Vo can be determined by the ratio of the input terminal size (W/L) of each pair of transistors to the amount of current supplied.

According to the second embodiment of the present creation, the size of the transistor pairs included in the input pair 211-0~211-4 may have a multiple relationship (or, when considering some process errors, the multiple relationship is generally a multiple relationship), The crystal pairs are used to generate corresponding currents according to different ratios, so that the transistor pairs have a multiple relationship (or generally multiple relationships). For example, the two pairs of transistors included in the input pair 211-0 can have the same aspect ratio, and the aspect ratio of the two pairs of transistors can be set as the basic size unit, that is, the two pairs of transistors The aspect ratio can be set to 1 unit, and the current I generated by the input pair 211-0 is also set to the base current unit. The size of other input pairs 211-1~211-4 can be flexibly selected or designed according to the basic size unit.

As in the example shown in FIG. 2, the size of the input pair 211-1 can be designed to be the same as the input pair 211-0. That is, the two pairs of transistors included in the input pair 211-1 may also have an aspect ratio of 1 unit. Therefore, the size of the two transistor pairs included in the input pair 211-1 may correspond to a first ratio, where the first ratio is 1, and the current generated by the transistor pair is 1*I. In the embodiment of the present invention, the ratio represents the ratio of the size of the transistor pair to the above basic size unit. Similarly, the size of the transistor pair included in the input pair 211-0 also corresponds to the first ratio.

The size of the input pair 211-2 can be designed to be twice that of the input pair 211-0. That is, the two pairs of transistors included in the input pair 211-2 may have an aspect ratio of 2 units. Therefore, the size of the transistor pair included in the input pair 211-2 may correspond to a second ratio, where the second ratio is 2, and the current generated by the transistor pair is 2*I.

The size of the input pair 211-3 can be designed to be four times that of the input pair 211-0. That is, the two pairs of transistors included in the input pair 211-3 may have an aspect ratio of 4 units. Therefore, the size of the transistor pair included in the input pair 211-3 may correspond to a third ratio, in which case the third ratio is 4, and the current generated by the transistor pair is 4*I.

The size of the input pair 211-4 can be designed to be eight times that of the input pair 211-0. That is, the two pairs of transistors included in the input pair 211-4 may have an aspect ratio of 8 units. Therefore, the size of the transistor pair included in the input pair 211-4 may correspond to a fourth ratio, where the fourth ratio is 8, and the current generated by the transistor pair is 8*I.

In the embodiment of the present invention, the input pairs 211-0 to 211-4 in the input stage 210 may weight the input voltage VIH and VIL according to an unequal ratio, and output the voltage Vo at the voltage output terminal Vout, that is, The input voltage VIH and VIL are weighted by one of the unequal ratio interpolation results as the output voltage Vo. Among them, in this embodiment, the fourth ratio is greater than the third ratio, the third ratio is greater than the second ratio, the second ratio is greater than the first ratio, and the fourth ratio is a multiple of the third ratio, and the third ratio is the second ratio The multiple, the fourth ratio, the third ratio and the second ratio are all multiples of the first ratio.

As in the example shown in Figure 2, the input stage 210 can use the input pair 211-0~211-4 to weight the input voltage VIH or VIL respectively according to the ratio of 1, 1, 2, 4, 8 etc. to generate an interpolation result, To achieve 4-bit voltage interpolation, the sum of the ratio values is the number of interpolation voltages. More specifically, the input stage 210 can use the input pair 211-0~211-4 to weight the input voltage VIH or VIL according to the unequal ratio to generate 16 different levels of voltage, of which 16=1+1+ 2+4+8, which is the 4th power of 2, to realize 4-bit voltage interpolation. The relationship between the output voltage Vo and the input voltage VIH or VIL, and the unequal ratio can be the same as the equivalent formula (8) listed above.

It is worth noting that the above ratios are for illustration only, not for limiting the scope of this creation. According to the embodiment of the present invention, the selection of the ratio depends on the required number of interpolation voltages, and can be flexibly combined and changed. For example, to achieve 5-bit voltage interpolation, an input pair can be added, and the size of the transistor pair included in this input pair can be designed to be 16 times the basic size unit (ie, the corresponding ratio 16), or two additional input pairs can be added, and the size of the transistor pairs contained in the two input pairs can be designed to be 8 times the basic size unit (ie, the corresponding ratio is 8).

Compared with the prior art, the amplifier circuit 200 of the present invention can use fewer transistor pairs to achieve the same voltage interpolation function, thereby greatly reducing the number of control signal traces and switching devices required by the amplifier circuit, which is effective Reduce the area of the circuit layout.

FIG. 3 is a schematic diagram showing an embodiment of a driving device for a liquid crystal display according to an embodiment of the present creation. The amplifier circuit 100/200 of this creation can be integrated into a driving device of a liquid crystal display. The driving device 300 may include a digital-to-analog converter 310, an amplifier circuit 320, and ^2N reference voltage traces 330. The reference voltage trace 330 is used to provide 2 ^N Gamma reference voltages generated by a reference voltage generating circuit (not shown). The digital-to-analog converter 310 is coupled to the reference voltage trace 330, and is used to switch out two adjacent reference voltages V1 and V2 from 2 ^N Jiama reference voltages according to a digital image signal S_DATA, where V1 and V2 can provide The amplifier circuit 320 serves as the aforementioned input voltages VIH and VIL. The amplifier circuit 320 can be implemented by the amplifier circuit 100/200 of FIG. 1 or FIG. 2 to generate an output voltage Vo corresponding to the interpolation result according to the reference voltages V1 and V2 output by the digital-to-analog converter 310 .

Therefore, by the amplifier circuit 320 with interpolation function performing voltage interpolation according to its input voltage to generate 2 ^K interpolation voltages, the driving device 300 will eventually be equivalent to generating 2 ^(N+K) Jiama reference voltages, Where 2 ^K is the sum of the size ratio values of the transistor pairs of the input stage of the amplifier circuit. Compared with the prior art, the amplifier circuit 320 of the present invention can use fewer transistor pairs to achieve the same voltage interpolation function, thereby greatly reducing the number of control signal traces and switching devices required by the amplifier circuit, which is effective Reduce the area of the circuit layout. In addition, the transistors in the input stage of the amplifier circuit of the invention can be operated in the same operation region (for example, saturation region), so compared with the prior art, the invention also has the advantage of easy design. In addition, the voltage value interpolated by the method of this creation can have better linearity, for example, integral nonlinearity (INL) and differential nonlinearity (DNL) can perform well For traditional technology. In addition, since this design uses transistors with unequal ratios for size design, the amplifier circuit has larger-sized components, which can relatively weaken the effect of random mismatch between components and components on the overall circuit. The above is only the preferred embodiment of this creation, and all changes and modifications made in accordance with the scope of the patent application of this creation shall fall within the scope of this creation.

100, 200, 320: amplifier circuit 110, 210: input stage 111-0, 111-1, 111-2, 111-3, 111-4, 211-0, 211-1, 211-2, 211-3, 211-4: Input pair 120, 220: Output stage 300: Drive device 310: Digital-to-analog converter 330: Reference voltage traces A, B, C, D: Nodes E>0>, E>1>, E>2>,E>3>,E>4>: select bit I, I _111-0 , I _111-1 , I _111-2 , I _111-3 , I _111-4 : current S_DATA: digital image signal V1 , V2, VIH, VIL, Vo: voltage Vout: voltage output

FIG. 1 is a schematic circuit diagram showing an example of an amplifier circuit with voltage interpolation function according to the first embodiment of the present creation. FIG. 2 is a schematic circuit diagram showing an example of an amplifier circuit with voltage interpolation function according to the second embodiment of the present creation. FIG. 3 is a schematic diagram showing an embodiment of a driving device for a liquid crystal display according to an embodiment of the present creation.

100: amplifier circuit

110: input level

111-0, 111-1, 111-2, 111-3, 111-4: input pair

120: output stage

A, B: Node

E<0>, E<1>, E<2>, E<3>, E<4>: select bit

I, I _111-0 , I _111-1 , I _111-2 , I _111-3 , I _111-4 : current

VIH, VIL, Vo: voltage

Vout: voltage output

Claims (12)

An amplifier circuit with voltage interpolation function, including: A plurality of input pairs are used to receive a first voltage and a second voltage. The input pairs are coupled to a voltage output terminal through an output stage. The input pairs include at least: A first input pair, coupled between a ground point and a pair of nodes, including at least a first pair of transistors, the size of the first pair of transistors corresponding to a first ratio; and A second input pair, coupled between the ground point and the pair of nodes, includes at least a second pair of transistors, the size of the second pair of transistors corresponds to a second ratio, wherein the second ratio and the The first ratio is not equal, the second ratio is a multiple of the first ratio, and a voltage output from the voltage output terminal is the weighted weight of the first voltage and the second voltage through the first ratio and the second ratio An interpolation result. The amplifier circuit as described in item 1 of the patent application scope further includes: A third input pair, including at least a third pair of transistors, the size of the third pair of transistors corresponds to a third ratio, wherein the third ratio is not equal to the second ratio, the third ratio is the third A ratio and a multiple of the second ratio, and the voltage output by the voltage output terminal is the interpolation of the first voltage and the second voltage through a weighting of the first ratio, the second ratio, and the third ratio result. The amplifier circuit as described in item 1 of the patent application scope, wherein the first input pair further includes: A first input terminal for selectively receiving the first voltage or the second voltage according to a first selection bit; and A second input terminal, coupled to the voltage output terminal, And where the second input pair further includes: A first input terminal for selectively receiving the first voltage or the second voltage according to a second selection bit; and A second input terminal is coupled to the voltage output terminal. The amplifier circuit as described in item 1 of the patent application scope, wherein the first pair of transistors includes: A first input terminal for receiving the first voltage; and A second input terminal, coupled to the voltage output terminal, and The first input pair further includes a third pair of transistors, the size of the third pair of transistors corresponds to the first ratio, and includes: A first input terminal for receiving the second voltage; and A second input terminal is coupled to the voltage output terminal. The amplifier circuit as described in item 1 of the patent application scope, wherein the second pair of transistors includes: A first input terminal for receiving the first voltage; and A second input terminal, coupled to the voltage output terminal, and The second input pair further includes a fourth pair of transistors, the size of the fourth pair of transistors corresponds to the second ratio, and includes: A first input terminal for receiving the second voltage; and A second input terminal is coupled to the voltage output terminal. An amplifier circuit with voltage interpolation function, including: A plurality of input pairs are used to receive a first voltage and a second voltage. The input pairs are coupled to a voltage output terminal through an output stage. The input pairs include at least: A first input pair, coupled between a ground point and a pair of nodes, including at least a first pair of transistors, the size of the first pair of transistors corresponding to a first ratio; A second input pair, coupled between the ground point and the pair of nodes, including at least one second pair of transistors, the size of the second pair of transistors corresponding to a second ratio; and A third input pair, coupled between the ground point and the pair of nodes, includes at least a third pair of transistors, the size of the third pair of transistors corresponds to a third ratio, wherein the first ratio, the The second ratio and the third ratio are not equal to each other, and the voltage output by the voltage output terminal is one of the weighting of the first voltage and the second voltage through the first ratio, the second ratio, and the third ratio Interpolate the result. The amplifier circuit as described in item 6 of the patent application range, wherein the third ratio is greater than the second ratio, the second ratio is greater than the first ratio, and the third ratio and the second ratio are the ratio of the first ratio multiple. The amplifier circuit as described in item 6 of the patent application scope, wherein the first input pair further includes: A first input terminal for selectively receiving the first voltage or the second voltage according to a first selection bit; and A second input terminal, coupled to the voltage output terminal, The second input pair further includes: A first input terminal for selectively receiving the first voltage or the second voltage according to a second selection bit; and A second input terminal, coupled to the voltage output terminal, and The third input pair further includes: A first input terminal for selectively receiving the first voltage or the second voltage according to a third selection bit; and A second input terminal is coupled to the voltage output terminal. The amplifier circuit as described in item 6 of the patent application scope, wherein the first pair of transistors includes: A first input terminal for receiving the first voltage; and A second input terminal, coupled to the voltage output terminal, and The first input pair further includes a fourth pair of transistors, the size of the fourth pair of transistors corresponds to the first ratio, and includes: A first input terminal for receiving the second voltage; and A second input terminal is coupled to the voltage output terminal. The amplifier circuit as described in item 6 of the patent application scope, wherein the second pair of transistors includes: A first input terminal for receiving the first voltage; and A second input terminal, coupled to the voltage output terminal, and The second input pair further includes a fifth pair of transistors, the size of the fifth pair of transistors corresponds to the second ratio, and includes: A first input terminal for receiving the second voltage; and A second input terminal is coupled to the voltage output terminal. The amplifier circuit as described in item 6 of the patent application scope, wherein the third pair of transistors includes: A first input terminal for receiving the first voltage; and A second input terminal, coupled to the voltage output terminal, and The third input pair further includes a sixth pair of transistors, the size of the sixth pair of transistors corresponds to the third ratio, and includes: A first input terminal for receiving the second voltage; and A second input terminal is coupled to the voltage output terminal. A driving device for a liquid crystal display includes an amplifier circuit as described in patent application scope 1 or 6, wherein the amplifier circuit is integrated into the driving device.

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