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TWM558999U - 發光封裝元件 - Google Patents

發光封裝元件 Download PDF

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Publication number
TWM558999U
TWM558999U TW106218341U TW106218341U TWM558999U TW M558999 U TWM558999 U TW M558999U TW 106218341 U TW106218341 U TW 106218341U TW 106218341 U TW106218341 U TW 106218341U TW M558999 U TWM558999 U TW M558999U
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Taiwan
Prior art keywords
lead frame
frame unit
light
adhesive layer
emitting package
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TW106218341U
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English (en)
Inventor
黃嘉能
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長華科技股份有限公司
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Application filed by 長華科技股份有限公司 filed Critical 長華科技股份有限公司
Priority to TW106218341U priority Critical patent/TWM558999U/zh
Publication of TWM558999U publication Critical patent/TWM558999U/zh
Priority to US15/977,252 priority patent/US10424694B2/en
Priority to DE202018104349.8U priority patent/DE202018104349U1/de
Priority to JP2018004372U priority patent/JP3219881U/ja
Priority to KR2020180005507U priority patent/KR200493123Y1/ko

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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62Protection against overvoltage, e.g. fuses, shunts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483Containers
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
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Abstract

本新型提供一種發光封裝元件,包含一導線架單元,及一預成形膠層。該導線架單元具有一周面,該預成形膠層包覆該導線架的周面,並令該導線架單元的該頂面及該底面對外裸露,具有一與該導線架單元的周面相對應的外表面、一與該導線架單元的底面共平面的下表面,及多條自該下表面向下形成並延伸貫通該外表面的接點溝槽,且該接點溝槽反向該外表面的一端與該導線架單元連通。該發光封裝元件側面外觀無金屬,且利用延伸貫通至該外表面的接點溝槽還可更易於後續封裝時的焊錫檢測。

Description

發光封裝元件
本新型是有關於一種封裝元件,特別是指一種發光封裝元件。
發光二極體因其具有體積小、高效能、壽命長、低耗能反應素度快等優點,因此,已廣為取代傳統光源,成為新一代的照明光源,而廣泛應用於不同領域。所以,如何提供更快速且可靠度更高的發光封裝元件,是技術領域者不斷發展的方向之一。
其中,利用四方平面無引腳導線架(QFN)進行半導體晶片封裝,雖然可將電連接點向下延伸設置在封裝元件底面,而達到高密度小體積封裝的優點,然而,也因為電連接點在封裝元件底部,因此,當要將封裝元件進行後續電連接的過程,會有無法由目視檢測方式快速檢出該封裝元件於電連接前的吃錫是否完全或是電連接是否完全的缺點。
因此,本新型之目的,即在提供一種方便使用並易於檢測的發光封裝元件。
於是,本新型的發光封裝元件,包含一導線架單元、一預成形膠層,及一發光單元。
該導線架單元具有一用於承載該半導體晶片的頂面、一反向該頂面的底面,及一分別連接該頂面及該底面的周面。
該預成形膠層包覆該導線架單元的周面,並令該導線架單元的該頂面及該底面對外裸露,具有一對應該導線架單元的該周面的外表面、一與該導線架單元的該底面共平面的下表面,及多條自該下表面向下形成並延伸貫通該外表面的接點溝槽。每一條接點溝槽反向該外表面的一端與該導線架單元連通,且該導線架單元不會裸露出該預成形膠層的該外表面。
該發光單元設置於該導線架單元的頂面。
本新型之功效在於:利用該預成形膠層包覆該導線架單元,並於該預成形膠層的該下表面形成與該導線架單元連通並延伸貫通該外表面的接點溝槽(Solder Seen Terminal,SST),不僅可令該發光封裝元件整體側面外觀無金屬,且藉由該接點溝槽的吃錫狀況還可更易於該發光封裝元件後續的焊錫檢測。
參閱圖1~3,本新型發光封裝元件的一第一實施例包含一導線架單元2、一預成形膠層3,及一發光單元4。
該導線架單元2是由銅、銅系合金或鐵鎳合金等至少一種導電材料構成,具有一用於承載該發光單元4的頂面211、一反向該頂面211的底面212,及一分別連接該頂面211及該底面212的周面213。
具體的說,該導線架單元2具有至少兩個彼此成一間隙間隔的接觸電極21,該等接觸電極21的頂面即為該導線架單元2的該頂面211,而該等接觸電極21的底面及周面即分別為該導線架單元2的該底面212及該周面213,且至少一個該接觸電極21的頂面211為用於設置該發光單元4。要說明的是該等接觸電極21的數量可視該發光單元4的極性及數量而至少為兩個或多個,於本實施例中,是以該導線架單元2具有兩個接觸電極21為例作說明。
該預成形膠層3包覆該等接觸電極21的周面213並延伸至該等接觸電極21的部分頂面211,以令該等接觸電極21的至少部分頂面211對外裸露,而將該等接觸電極21外露於該預成形膠層3的頂面211定義出一個可供設置該等發光單元4的設置區35。
詳細的說,該預成形膠層3與該導線架單元2為直接接觸接合,具有一對應該導線架單元2的周面213的外表面31、一對應該導線架單元2的該頂面211的上表面32、一與該導線架單元2的該底面212共平面的下表面33,及多條自該下表面33向下形成並延伸貫通該外表面31的接點溝槽(Solder Seen Terminal,SST)34,且每一個接觸電極21與至少一條接點溝槽34相連通。每一條接點溝槽34反向該外表面31的一端與相應的該接觸電極21連通,而令該接觸電極21具有自該接點溝槽34裸露的外露面214。其中,該外露面214可以是朝向該接觸電極21方向凹陷的內凹弧面,或是傾斜平面,而可易於導引位於該接觸電極21的該底面212的流體或膠態物質(例如導電膠或焊料)的溢流方向。於圖3中該外露面214是以朝向該接觸電極21方向凹陷的內凹弧面為例表示。
該發光單元4包括至少一個發光件41,該發光件41可選自發光二極體或雷射二極體等發光元件,於本實施例中,該發光單元4是以具有一個發光件41為例,該發光件41設置於該設置區35的其中一個接觸電極21的該頂面211並藉由導線42與另一個接觸電極21電連接。
由圖1可明顯看出,本新型該發光封裝元件的該等導線架單元2不會裸露出該預成形膠層3的該外表面31,因此可令該發光封裝元件的側面無金屬外露,且具有多個可用以檢視吃錫的接點溝槽34。
於一些實施例中,該預成形膠層3至少於位在該等接觸電極21的該頂面211的部分具有光反射性,因此,設置於該設置區35的該發光單元4,還可藉由該預成形膠層3達成光的多重反射,而提升該發光單元4的光取出率。
參閱圖4,茲將前述該發光封裝元件的該第一實施例的製作說明如下。
首先提供一由銅、銅系合金或鐵鎳合金等至少一種導電材料構成的基片,利用蝕刻方式將該基片不必要的部分蝕刻移除,而得到如圖4(a)所示的導線架半成品100A。
該導線架半成品100A具有一個外框101,多個位於該外框101內彼此間隔且概成陣列排列的接觸電極21,及多個連接部102。該等接觸電極21具有該頂面211及相對該頂面211的底面212,該等連接部102分佈於該等接觸電極21間,並自該等接觸電極21鄰近該底面212的底部連接任相鄰的兩個接觸電極21,以及與該外框101相鄰的該等接觸電極21,而令該等接觸電極21與該外框101可連接成一體不分散。
接著,將該導線架半成品100A夾設於一模具(圖未示)中,用模注方式於該等接觸電極21及該等接觸電極21與該外框101之間的間隙填注一選自環氧樹脂等絕緣高分子的高分子封裝材料,並讓該高分子封裝材料延伸並覆蓋該等接觸電極21的部分頂面211,固化後形成該預成形膠層3,而得到如圖4(b)的結構。圖4(c)是將圖4(b)翻面後的背視圖。
然後,利用蝕刻移除該等連接部102,即可於該預成形膠層3底部形成該等接點溝槽34,並同時令該等接觸電極21彼此獨立不相連接(如圖4(d)所示)。
接著,將4(d)翻回正面,於該等接觸電極21裸露出之該頂面211分別設置該等發光件41,並利用該等導線42將該等發光件4分別與相應的接觸電極21電連接,即可得到如4(e)所示之封裝結構。
最後,配合參閱圖4、5,圖5為沿圖4(e)的V-V割線的剖視圖。其中兩兩緊鄰的接觸電極21即為一個導線架單元2,定義任相鄰的兩個導線架單元2間的間隙及導線架單元2與該外框101之間的間隙為切割道X,將封裝完成後的封裝結構(如圖4(e))沿著該等切割線X進行切單,即可得到如圖1所示的發光封裝元件。
要說明的是,該預成形膠層3可藉由模具設計,如前所述於單一製程一體形成;或是也可利用不同模具,先形成一包覆該等接觸電極21的周面213並與該等接觸電極21的頂面211及底面212共平面的下膠部,再於該下膠部的上表面及該等接觸電極21的部分頂面212形成一頂膠部後,而得到該預成形膠層3。當該預成形膠層3是於不同製程形成,則該下膠部與該頂膠部可以是由相同或不同的高分子封裝材料(例如環氧樹脂或矽膠)所構成。此外,於形成該預成形膠層3,或是形成該頂膠部時,可以利用在高分子封裝材料中添加光反射粒子,如此,成形後即可令該預成形膠層3整體或該頂膠部具有光反射性,從而提升該等發光件41的出光效率。由於前述用於形成該預成形膠層3的相關模具設計及光反射粒子材料為本技術領域者所週知,故不再多加贅述。
參閱圖6、7,本新型發光封裝元件的一第二實施例,其結構與該第一實施例大致相同,不同處在於該第二實施例還包含一封裝膠層5,且該預成形膠層3的該上表面32與該導線架單元2的該頂面211共平面。
詳細的說,該第二實施例的該預成形膠層3的該上表面32及該下表面33分別與該等接觸電極21的該頂面211及該底面212共平面而成一平板狀。該發光件41會設置於其中一個接觸電極21的頂面211並藉由導線42電連接,該封裝膠層5則會覆蓋該等接觸電極21的該頂面211、該預成形膠層3的該上表面32及該發光單元4。其中,該封裝膠層5可選自矽膠、環氧樹脂等可透光的封裝材料,或是也可再進一步包含螢光材料。由於該封裝材料為本技術領域周知故不再多加贅述。
前述該第二實施例的製作與該第一實施例雷同,不同處在於:形成該預成形膠層3時為控制令該預成形膠層3的該上表面32與該導線架單元2的該頂面211共平面,且於完成該等發光單元4的打線連接後,再形成覆蓋該等接觸電極21的頂面211、該預成形膠層3的該上表面32及該等發光單元4,且不覆蓋該外框101的該封裝膠層5,最後再進行切單,即可得到如圖6所示的發光封裝元件。
由圖1、6可明顯看出,本新型該發光封裝元件利用讓該預成形膠層3包覆該導線架單元2,因此,無論何種封裝方式,該發光封裝元件的側面均無金屬外露。此外,還會具有多個形成於該下表面33並與該外表面31連通的接點溝槽34,因此,當後續要將該發光封裝元件進行電連接,例如要與電路板(圖未示)電連接時,即可透過檢視該等接點溝槽34的吃錫狀況,而快速確認該發光封裝元件的電連接狀態。
又要說明的是,於一些實施例中,本新型該等接觸電極21的該等外露面214,及該導線架單元2的表面(頂面211、底面212)也可以在形成該預成形膠層3之後進行鍍膜製程,而於該導線架單元2的表面形成異於該導線架單元2構成材料的導電鍍層。該導電鍍層可選自金屬或合金材料(例如鎳、鈀、銀或金等金屬或合金),且可以是單層或多層,而可用於提升後續與其它電路板電連接、焊錫或是打線製程的可靠度。
配合參閱圖8~11,圖8~11是以該第一實施例所示的該發光封裝元件為例說明。具體的說,例如,可在形成該預成形膠層3後進行鍍膜,於該等接觸電極21的該底面212形成一第一導電鍍層61,或同時在該等接觸電極21的該底面212及未被該預成形膠層3包覆的該頂面211分別形成第一導電鍍層61及第二導電鍍層62,而形成如圖8、9所示之結構。
或是,利用鍍膜製程的配合,也可得到如圖10所示,具有分別形成於該等接觸電極21的底面212及該等接觸電極21的外露面214的第一導電鍍層61及第三導電鍍層63的發光封裝元件,或是得到如圖11所示,具有同時形成於該等接觸電極21的底面212、頂面211、及該等外露面214的第一導電鍍層61、第二導電鍍層42,及第三導電鍍層43的發光封裝元件。由圖8~11可明顯看出,該等接觸電極21被該預成形膠層3包覆的位置均不會形成其它導電鍍層。
藉由該導電鍍層可加強該導線架單元2與該預成形膠層3、導線42、或是後續用於封裝的高分子封裝材料的密著性或可靠性。
綜上所述,本新型該發光封裝元件利用讓該預成形膠層3包覆該等接觸電極21的周面213,因此,該發光封裝元件的側面外觀不會有金屬外露。此外,藉由於該成形膠層3的該底面313形成延伸貫通至該外表面31的該等接點溝槽34,因此可透過目測檢視該等接點溝槽34的爬錫狀況,而快速得知該發光封裝元件的電連接狀態,故確實可達成本新型之目的。
惟以上所述者,僅為本新型之實施例而已,當不能以此限定本新型實施之範圍,凡是依本新型申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本新型專利涵蓋之範圍內。
2‧‧‧導線架單元
21‧‧‧接觸電極
211‧‧‧頂面
212‧‧‧底面
213‧‧‧周面
214‧‧‧外露面
3‧‧‧預成形膠層
31‧‧‧外表面
32‧‧‧上表面
33‧‧‧下表面
34‧‧‧接點溝槽
35‧‧‧設置區
4‧‧‧發光單元
41‧‧‧發光件
42‧‧‧導線
5‧‧‧封裝膠層
61‧‧‧第一導電鍍層
62‧‧‧第二導電鍍層
63‧‧‧第三導電鍍層
100A‧‧‧導線架半成品
101‧‧‧外框
102‧‧‧連接部
X‧‧‧切割道
本新型之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中: 圖1是說明本新型發光封裝元件第一實施例的俯視示意圖; 圖2是說明該第一實施例的背面仰視示意圖; 圖3是圖1的剖視示意圖; 圖4說明該第一實施例的製作流程示意圖 說明該實施例具單一個導線架單元的結構示意圖; 圖5,圖4(e)中V-V割線的剖視示意圖,輔助說明該第一實施例的製作流程; 圖6是說明本新型發光封裝元件第二實施例的俯視示意圖; 是說明該實施例的外露面還具有第一導電鍍層的結構示意圖; 圖7是圖6的剖視示意圖; 圖8是說明該第一實施例具有第一導電鍍層的結構示意圖; 圖9是說明該第一實施例具有第一、二導電鍍層的結構示意圖; 圖10是說明該第一實施例具有第一、三導電鍍層的結構示意圖;及 圖11是說明該第一實施例具有第一、二、三導電鍍層的結構示意圖。

Claims (11)

  1. 一種發光封裝元件,包含:一導線架單元,該導線架單元具有一用於承載該半導體晶片的頂面及一反向該頂面的底面,及一分別連接該頂面及該底面的周面;及一預成形膠層,包覆該導線架單元的周面,並令該導線架單元的該頂面及該底面對外裸露,具有一對應該導線架單元的該周面的外表面、一與該導線架單元的該底面共平面的下表面,及多條自該下表面向下形成並延伸貫通該外表面的接點溝槽,每一條接點溝槽反向該外表面的一端與該導線架單元連通,且該導線架單元不會裸露出該預成形膠層的該外表面;及一發光單元,設置於該導線架單元的頂面。
  2. 如請求項1所述的發光封裝元件,其中,該導線架單元具有至少兩個彼此成一間隙間隔的接觸電極,該等接觸電極的頂面及底面即分別為該導線架單元的頂面及底面,該預成形膠層還填覆該等間隙,且每一個接觸電極與至少一條接點溝槽相連通。
  3. 如請求項2所述的發光封裝元件,其中,該預成形膠層延伸至該等接觸電極的部分頂面,令每一個接觸電極的至少部份表面露出,並將該等接觸電極外露於該預成形膠層的頂面定義出一個設置區,且該發光單元設置於該設置區。
  4. 如請求項3所述的發光封裝元件,其中,該預成形膠層至少位在該等接觸電極的頂面的部分具有光反射性。
  5. 如請求項2所述的發光封裝元件,其中,該預成形膠層還具有一上表面,該上表面與該下表面反向並與該導線架單元的該頂面共平面,該發光封裝元件還包含一可透光的封裝層,且該封裝層覆蓋該導線架單元的頂面、該預成形膠層的該上表面,及該發光單元。
  6. 如請求項1所述的發光封裝元件,其中,該導線架單元自該等接點溝槽裸露的表面為一內凹弧面。
  7. 如請求項1所述的發光封裝元件,其中,該導線架單元的材料選自銅、鐵鎳合金,或銅系合金。
  8. 如請求項1所述的發光封裝元件,其中,該導線架單元的底面還具有一與該導線架單元的材料不同的第一導電鍍層。
  9. 如請求項8所述的發光封裝元件,其中,該導線架單元未被該預成形膠層包覆的該頂面還具有一與該導線架單元的材料不同的第二導電鍍層。
  10. 如請求項8或9項所述的發光封裝元件,其中,該導線架單元自該等接點溝槽裸露的表面還具有一與該導線架單元的材料不同的第三導電鍍層。
  11. 如請求項1所述的發光封裝元件,其中,該導線架單元與該預成形膠層為直接接觸接合。
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