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TWI839913B - Method for manufacturing micro fluid pump - Google Patents

Method for manufacturing micro fluid pump Download PDF

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Publication number
TWI839913B
TWI839913B TW111140483A TW111140483A TWI839913B TW I839913 B TWI839913 B TW I839913B TW 111140483 A TW111140483 A TW 111140483A TW 111140483 A TW111140483 A TW 111140483A TW I839913 B TWI839913 B TW I839913B
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Taiwan
Prior art keywords
substrate
layer
manufacturing
bonding
etching
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TW111140483A
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Chinese (zh)
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TW202418977A (en
Inventor
莫皓然
張正明
戴賢忠
黃翊展
韓永隆
林宗義
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研能科技股份有限公司
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Priority to TW111140483A priority Critical patent/TWI839913B/en
Priority to CN202311075076.6A priority patent/CN117923417A/en
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Publication of TWI839913B publication Critical patent/TWI839913B/en
Publication of TW202418977A publication Critical patent/TW202418977A/en

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00119Arrangement of basic structures like cavities or channels, e.g. suitable for microfluidic systems
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00047Cavities
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349Creating layers of material on a substrate
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523Etching material
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00Assembling of devices or systems from individually processed components
    • B81C3/001Bonding of two components
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04BPOSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS
    • F04B17/00Pumps characterised by combination with, or adaptation to, specific driving engines or motors
    • F04B17/03Pumps characterised by combination with, or adaptation to, specific driving engines or motors driven by electric motors
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04BPOSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS
    • F04B19/00Machines or pumps having pertinent characteristics not provided for in, or of interest apart from, groups F04B1/00 - F04B17/00
    • F04B19/006Micropumps

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Analytical Chemistry (AREA)
  • Dispersion Chemistry (AREA)
  • Reciprocating Pumps (AREA)
  • Micromachines (AREA)

Abstract

A method for manufacturing micro fluid pump is disclose and includes steps of: providing a first substrate; etching an upper surface of the first substrate to form at least one first groove; etching the upper surface of the first substrate to form a second groove, and the first groove is located under the bottom of the second groove; depositing a first binding layer on the surfaces of the at least one first groove and the second groove; providing a third substrate; depositing a second binding layer on the surface of the third substrate; patterned etching the second binding layer; and providing a second substrate and binding the second substrate with the patterned-etched second binding layer of the third substrate.

Description

微型流體泵浦的製造方法Manufacturing method of micro fluid pump

本案係關於一種微型流體泵浦的製造方法,尤指一種透過半導體製程來製作微型流體泵浦的製造方法。 This case is about a method for manufacturing a microfluid pump, especially a method for manufacturing a microfluid pump through a semiconductor process.

隨著科技的日新月異,流體輸送裝置的應用上亦愈來愈多元化,舉凡工業應用、生醫應用、醫療保健、電子散熱等等,甚至近來熱門的穿戴式裝置皆可見它的踨影,可見傳統的泵浦已漸漸有朝向裝置微小化、流量極大化的趨勢,而微機電泵浦能夠將流體輸送裝置的尺寸大幅度地縮小,故微機電泵浦明顯為當下微型化之流體輸送裝置的主要發展方向。 With the rapid development of technology, the application of fluid transport devices is becoming more and more diversified, including industrial applications, biomedical applications, healthcare, electronic heat dissipation, etc., and even the popular wearable devices can be seen. It can be seen that traditional pumps have gradually tended towards miniaturization of devices and maximum flow rate, and MEMS pumps can greatly reduce the size of fluid transport devices. Therefore, MEMS pumps are obviously the main development direction of miniaturized fluid transport devices at present.

請參考第5圖所示,第5圖為先前技術微型流體泵浦90,包含第一基板901、第一接著層902、第二基板903及壓電組件904。第一基板901係為矽基材,具有複數個第一流體通道9011,該些第一流體通道9011呈錐形;第一接著層902係為氧化矽,定義出第二流體通道9021,並疊設於第一基板901上;第二基板903疊設第一接著層902上,包含由下而上依序堆疊之矽結構層9031、第二接著層9035、矽薄化層9037;矽結構層9031具有一個穿孔9032、振動部9033及固定部9034;第二接著層9035係為氧化矽,具有共振腔室9036;矽薄化層9037具有一個致動部9038、外周部9039、連接部903A以及第三流體通道903B,其中致動部9038的外環之外周部9039與連接部903A連接,並具有第三流體通道903B;壓電 組件904疊設於矽薄化層9037的致動部9038上,壓電組件904包含依序堆疊於致動部9038上方之下電極層9041、壓電層9042、絕緣層9043及上電極層9044。 Please refer to FIG. 5 , which shows a prior art microfluidic pump 90 , including a first substrate 901 , a first bonding layer 902 , a second substrate 903 and a piezoelectric component 904 . The first substrate 901 is a silicon substrate having a plurality of first fluid channels 9011, which are conical in shape; the first connecting layer 902 is silicon oxide, defines a second fluid channel 9021, and is stacked on the first substrate 901; the second substrate 903 is stacked on the first connecting layer 902, and includes a silicon structure layer 9031, a second connecting layer 9035, and a silicon thinning layer 9037 stacked in order from bottom to top; the silicon structure layer 9031 has a through hole 9032, a vibration portion 9033, and a fixing portion 9034; the second connecting layer 9035 is silicon oxide. , having a resonance chamber 9036; the silicon thin layer 9037 has an actuating portion 9038, a peripheral portion 9039, a connecting portion 903A and a third fluid channel 903B, wherein the peripheral portion 9039 of the outer ring of the actuating portion 9038 is connected to the connecting portion 903A and has a third fluid channel 903B; the piezoelectric component 904 is stacked on the actuating portion 9038 of the silicon thin layer 9037, and the piezoelectric component 904 includes a lower electrode layer 9041, a piezoelectric layer 9042, an insulating layer 9043 and an upper electrode layer 9044 stacked in sequence above the actuating portion 9038.

先前技術在第一流體通道9011製程上,由於晶圓的晶向造成錐狀的濕蝕刻角度太大,且改用乾蝕刻也有深寬比太高的問題,其製程難度高,且流阻又大;再者,第一接著層902所定義出的第二流體通道9021要夠厚,然而要生成較厚的氧化矽並不容易,且會有明顯的應力問題,造成與第二基板903接合時較易發生剝離(peeling)。 In the prior art, the taper wet etching angle of the first fluid channel 9011 is too large due to the crystal orientation of the wafer, and the aspect ratio is too high when dry etching is used. The process is difficult and the flow resistance is large. Furthermore, the second fluid channel 9021 defined by the first bonding layer 902 must be thick enough, but it is not easy to generate thicker silicon oxide, and there will be obvious stress problems, which makes it easier to peel when bonding with the second substrate 903.

本案之主要目的在於提供一種微機電泵浦的製造方法,以半導體製程用於製造的微米等級的微機電泵浦,俾改善其結構在製程上的良率及流體輸送效率。 The main purpose of this case is to provide a method for manufacturing micro-electromechanical pumps, using semiconductor processes to manufacture micron-scale micro-electromechanical pumps, so as to improve the process yield and fluid transport efficiency of the structure.

為達上述目的,本案之較廣義實施態樣為提供一種微型流體泵浦的製造方法,包含:步驟1.準備一第一基板;步驟2.蝕刻該第一基板的一上表面,形成至少一第一凹槽;步驟3.蝕刻該第一基板的該上表面,形成一第二凹槽,其中該至少一第一凹槽位於該第二凹槽的底部;步驟4.沉積一第一接著層於該第一基板之該至少一第一凹槽及該第二凹槽的表面上;步驟5.準備一第三基板;步驟6.沉積一第二接著層於該第三基板的表面上;步驟7.圖案化蝕刻該第二接著層;步驟8.準備一第二基板,將該第二基板與該第三基板之圖案化蝕刻的該第二接著層相互結合;步驟9.移除部分的該第二基板;步驟10.圖案化蝕刻該第二基板;步驟11.將該第一基板具有該至少一第一凹槽及該第二凹槽的表面與該第二基板相互結合;步驟12.移除部分的該第三基板;步驟13.依序沉積一下電極層及一壓電層於該第三基板上;步驟14.圖案化蝕刻該下電極層及 該壓電層;步驟15.沉積一絕緣層,並圖案化蝕刻該絕緣層;步驟16.沉積一上電極層,並圖案化蝕刻該上電極層;步驟17.圖案化蝕刻該絕緣層及該第三基板;步驟18.圖案化蝕刻該第一基板的一下表面;步驟19.蝕刻該第一接著層。 To achieve the above-mentioned purpose, the general implementation of the present invention is to provide a method for manufacturing a microfluidic pump, comprising: step 1. preparing a first substrate; step 2. etching an upper surface of the first substrate to form at least one first groove; step 3. etching the upper surface of the first substrate to form a second groove, wherein the at least one first groove is located at the bottom of the second groove; step 4. depositing a first bonding layer on the surface of the at least one first groove and the second groove of the first substrate; step 5. preparing a third substrate; step 6. depositing a second bonding layer on the surface of the third substrate; step 7. pattern etching the second bonding layer; step 8. preparing a second substrate, bonding the second substrate and the patterned second bonding layer of the third substrate to each other; The layers are bonded to each other; step 9. removing a portion of the second substrate; step 10. patterning and etching the second substrate; step 11. bonding the surface of the first substrate having the at least one first groove and the second groove to the second substrate; step 12. removing a portion of the third substrate; step 13. sequentially depositing a lower electrode layer and a piezoelectric layer on the third substrate; step 1 4. Patterning the lower electrode layer and the piezoelectric layer; Step 15. Depositing an insulating layer and patterning the insulating layer; Step 16. Depositing an upper electrode layer and patterning the upper electrode layer; Step 17. Patterning the insulating layer and the third substrate; Step 18. Patterning the lower surface of the first substrate; Step 19. Etching the first connecting layer.

10、20、30:微型流體泵浦 10, 20, 30: Micro fluid pump

101、201、301:第一基板 101, 201, 301: first substrate

1011、2011、3011:流體通槽 1011, 2011, 3011: Fluid channel

101A、201A、301A:第一凹槽 101A, 201A, 301A: First groove

101B、201B、301B:第二凹槽 101B, 201B, 301B: Second groove

1012、2012、3012:第一流體通道 1012, 2012, 3012: first fluid channel

102、202、302:第一接著層 102, 202, 302: First layer

103、203、303:第二基板 103, 203, 303: Second substrate

1031、2031、3031:穿孔 1031, 2031, 3031: Perforation

1032、2032、3032:振動部 1032, 2032, 3032: Vibration part

1033、2033、3033:固定部 1033, 2033, 3033: Fixed part

104、204、304:第二流體通道 104, 204, 304: Second fluid channel

105、205、305:第二接著層 105, 205, 305: Second layer

3051:下層 3051: Lower level

3052:多晶矽層 3052: Polycrystalline silicon layer

3053:上層 3053: Upper level

106、206、306:第三基板 106, 206, 306: Third substrate

1061、2061、3061:共振腔室 1061, 2061, 3061: Resonance chamber

1062、2062、3062:第三流體通道 1062, 2062, 3062: Third fluid channel

1063、2063、3063:致動部 1063, 2063, 3063: Actuator

1064、2064、3064:連接部 1064, 2064, 3064: Connection part

1065、2065、3065:外周部 1065, 2065, 3065: Periphery

107、207、307:壓電組件 107, 207, 307: Piezoelectric components

1071、2071、3071:下電極層 1071, 2071, 3071: lower electrode layer

1072、2072、3072:壓電層 1072, 2072, 3072: piezoelectric layer

1073、2073、3073:絕緣層 1073, 2073, 3073: Insulation layer

1074、2074、3074:上電極層 1074, 2074, 3074: upper electrode layer

90:微型流體泵浦 90: Micro fluid pump

901:第一基板 901: First substrate

9011:第一流體通道 9011: First fluid channel

902:第一接著層 902: First layer

9021:第二流體通道 9021: Second fluid channel

903:第二基板 903: Second substrate

9031:矽結構層 9031: Silicon structural layer

9032:穿孔 9032:Piercing

9033:振動部 9033: Vibration Department

9034:固定部 9034:Fixed part

9035:第二接著層 9035: Second layer

9036:共振腔室 9036:Resonance Chamber

9037:矽薄化層 9037:Silicon thinning layer

9038:致動部 9038: Actuator

9039:外周部 9039: Periphery

903A:連接部 903A:Connection part

903B:第三流體通道 903B: Third fluid channel

904:壓電組件 904: Piezoelectric components

9041:下電極層 9041: Lower electrode layer

9042:壓電層 9042: Piezoelectric layer

9043:絕緣層 9043: Insulation layer

9044:上電極層 9044: Upper electrode layer

S1~S19:步驟 S1~S19: Steps

第1A圖至第1C圖為本案之微型流體泵浦的製造方法的步驟流程圖。 Figures 1A to 1C are flow charts of the steps of manufacturing the microfluidic pump of this case.

第2A圖至第2S圖為本案之微型流體泵浦的製造方法之第一實施例步驟示意圖。 Figures 2A to 2S are schematic diagrams of the first embodiment of the manufacturing method of the microfluid pump of this case.

第3A圖至第3T圖為本案之微型流體泵浦的製造方法之第二實施例步驟示意圖。 Figures 3A to 3T are schematic diagrams of the steps of the second embodiment of the manufacturing method of the microfluidic pump of this case.

第4A圖至第4S圖為本案之微型流體泵浦的製造方法之第三實施例步驟示意圖。 Figures 4A to 4S are schematic diagrams of the steps of the third embodiment of the manufacturing method of the microfluid pump of this case.

第5圖為先前技術中微型流體泵浦的示意圖。 Figure 5 is a schematic diagram of a microfluid pump in the prior art.

體現本案特徵與優點的實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化,其皆不脫離本案的範圍,且其中的說明及圖示在本質上當作說明之用,而非用以限制本案。 The embodiments that embody the features and advantages of this case will be described in detail in the following description. It should be understood that this case can have various variations in different forms, all of which do not deviate from the scope of this case, and the descriptions and diagrams therein are essentially for illustrative purposes, not for limiting this case.

請參閱第2S圖,係為本案之微型流體泵浦之第一實施例,微型流體泵浦10包含第一基板101、第一接著層102、第二基板103、第二接著層105、第三基板106及壓電組件107。第一基板101設有流體通槽1011以及至少一第一流體通道1012,其中流體通槽1011為深槽狀;第一基板101、第一接著層102、第二基板103依序由下而上疊設,並定義出第二流體通道104,第二流體通道104頂端設有穿孔1031,穿孔1031係位於第二基板103的中心,穿孔1031的外圍由振動部1032環繞,振動部1032由固定部 1033環繞;第二基板103、第二接著層105、第三基板106依序由下而上疊設,並定義出共振腔室1061;第三基板106更包含至少一第三流體通道1062、致動部1063、連接部1064與外周部1065,其中外周部1065環設於致動部1063的外圍,外周部1065並透過連接部1064耦接致動部1063,第三流體通道1062則貫通第三基板106,使第三流體通道1062、共振腔室1061得透過穿孔1031依序連通第二流體通道104、第一流體通道1012、流體通槽1011;壓電組件107疊設於致動部1063之上,包含下電極層1071、壓電層1072、絕緣層1073及上電極層1074。 Please refer to FIG. 2S , which is a first embodiment of the microfluid pump of the present invention. The microfluid pump 10 includes a first substrate 101 , a first connecting layer 102 , a second substrate 103 , a second connecting layer 105 , a third substrate 106 and a piezoelectric component 107 . The first substrate 101 is provided with a fluid groove 1011 and at least one first fluid channel 1012, wherein the fluid groove 1011 is in the shape of a deep groove; the first substrate 101, the first connecting layer 102, and the second substrate 103 are stacked in sequence from bottom to top, and define a second fluid channel 104, the top of the second fluid channel 104 is provided with a through hole 1031, the through hole 1031 is located at the center of the second substrate 103, the outer periphery of the through hole 1031 is surrounded by a vibrating portion 1032, and the vibrating portion 1032 is surrounded by a fixing portion 1033; the second substrate 103, the second connecting layer 105, and the third substrate 106 are stacked in sequence from bottom to top, and define a resonance chamber 1061; the third substrate 106 further includes It includes at least one third fluid channel 1062, an actuating portion 1063, a connecting portion 1064 and a peripheral portion 1065, wherein the peripheral portion 1065 is arranged around the periphery of the actuating portion 1063, and the peripheral portion 1065 is coupled to the actuating portion 1063 through the connecting portion 1064. The third fluid channel 1062 passes through the third substrate 106, so that the third fluid channel 1062 and the resonance chamber 1061 can be connected to the second fluid channel 104, the first fluid channel 1012, and the fluid through slot 1011 in sequence through the through hole 1031; the piezoelectric component 107 is stacked on the actuating portion 1063, and includes a lower electrode layer 1071, a piezoelectric layer 1072, an insulating layer 1073 and an upper electrode layer 1074.

請參閱第1A圖至第1C圖及第2A圖至第2S圖,如第2A圖所示,步驟1.準備一第一基板101。值得注意的是,第一基板101係為矽基材(Si),厚度為270~430μm,但不以此為限。 Please refer to Figures 1A to 1C and Figures 2A to 2S. As shown in Figure 2A, step 1. prepare a first substrate 101. It is worth noting that the first substrate 101 is a silicon substrate (Si) with a thickness of 270~430μm, but not limited to this.

如第2B圖所示,步驟2.蝕刻第一基板101的一上表面,形成至少一第一凹槽101A。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。 As shown in FIG. 2B, step 2. Etching an upper surface of the first substrate 101 to form at least one first groove 101A. It is worth noting that this etching method can be physical or chemical etching.

如第2C圖所示,步驟3.蝕刻第一基板101的上表面,形成第二凹槽101B,其中第一凹槽101A位於第二凹槽101B的底部。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。 As shown in FIG. 2C, step 3. Etching the upper surface of the first substrate 101 to form a second groove 101B, wherein the first groove 101A is located at the bottom of the second groove 101B. It is worth noting that this etching method can be physical or chemical etching.

如第2D圖所示,步驟4.沉積第一接著層102於第一基板101之至少一第一凹槽101A及第二凹槽101B的表面上。值得注意的是,第一接著層102係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於第一基板101的表面,第一接著層102係為氧化矽,厚度範圍為1~5μm。 As shown in FIG. 2D, step 4. depositing the first bonding layer 102 on the surface of at least one first groove 101A and the second groove 101B of the first substrate 101. It is worth noting that the first bonding layer 102 is formed on the surface of the first substrate 101 by physical vapor deposition or chemical vapor deposition or thermal oxidation. The first bonding layer 102 is silicon oxide with a thickness range of 1~5μm.

如第2E圖所示,步驟5.準備第三基板106。值得注意的是,第三基板106可以是一絕緣層上覆矽(Silicon On Insulator,SOI)晶圓,但不以此為限。 As shown in FIG. 2E, step 5. prepare the third substrate 106. It is worth noting that the third substrate 106 can be a silicon on insulator (SOI) wafer, but is not limited thereto.

如第2F圖所示,步驟6.沉積第二接著層105於第三基板106的表面上。值得注意的是,第二接著層105係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於第三基板106的表面,第二接著層105的厚度範圍為1-5μm。 As shown in FIG. 2F, step 6. depositing the second bonding layer 105 on the surface of the third substrate 106. It is worth noting that the second bonding layer 105 is formed on the surface of the third substrate 106 by physical vapor deposition or chemical vapor deposition or thermal oxidation, and the thickness of the second bonding layer 105 ranges from 1 to 5 μm.

如第2G圖所示,步驟7.圖案化蝕刻第二接著層105。值得注意的是,經步驟7.圖案化蝕刻第二接著層105後,產生一共振腔室1061。 As shown in FIG. 2G, step 7. pattern etching the second connecting layer 105. It is worth noting that after step 7. pattern etching the second connecting layer 105, a resonant chamber 1061 is generated.

如第2H圖所示,步驟8.準備第二基板103,將第二基板103與第三基板106之圖案化蝕刻的第二接著層105相互結合。值得注意的是,第二基板103可以是一絕緣層上覆矽(SOI)晶圓,但不以此為限。 As shown in FIG. 2H, step 8. prepare the second substrate 103, and bond the second substrate 103 and the patterned second bonding layer 105 of the third substrate 106 to each other. It is worth noting that the second substrate 103 can be a silicon-on-insulation layer (SOI) wafer, but is not limited thereto.

如第2I圖所示,步驟9.移除部分的第二基板103。值得注意的是,經步驟9.移除部分的第二基板103剩餘的厚度範圍為1-5μm。 As shown in Figure 2I, step 9. removes part of the second substrate 103. It is worth noting that the remaining thickness of the second substrate 103 after step 9. removes part of the second substrate 103 is in the range of 1-5μm.

如第2J圖所示,步驟10.圖案化蝕刻第二基板103。值得注意的是,經步驟10.圖案化蝕刻第二基板103後,第二基板103區分為一穿孔1031、一振動部1032及一固定部1033。 As shown in FIG. 2J, step 10. patterning and etching the second substrate 103. It is worth noting that after step 10. patterning and etching the second substrate 103, the second substrate 103 is divided into a through hole 1031, a vibration portion 1032 and a fixed portion 1033.

如第2K圖所示,步驟11.將第一基板101具有至少一第一凹槽101A及第二凹槽101B的表面與第二基板103相互結合。值得注意的是,將第二基板103接合第三基板106的順序優先於將第二基板103接合第一基板101。其中,基板接合的順序係考量避免在接合時產生接合不良(Poor Bonding)所造成微型流體泵浦10的良率問題,因此先將第二基板103與第三基板106接合後再與第一基板101接合可以提升接合良率。 As shown in FIG. 2K, step 11. The surface of the first substrate 101 having at least one first groove 101A and a second groove 101B is bonded to the second substrate 103. It is worth noting that the order of bonding the second substrate 103 to the third substrate 106 is prior to bonding the second substrate 103 to the first substrate 101. The order of bonding the substrates is considered to avoid the yield problem of the microfluid pump 10 caused by poor bonding during bonding. Therefore, bonding the second substrate 103 to the third substrate 106 first and then to the first substrate 101 can improve the bonding yield.

如第2L圖所示,步驟12.移除部分的第三基板106。值得注意的是,經步驟12.移除部分的第三基板106剩餘的厚度範圍為5-20μm。 As shown in Figure 2L, step 12. removes part of the third substrate 106. It is worth noting that the remaining thickness of the third substrate 106 after the part of the third substrate 106 is removed in step 12. ranges from 5 to 20 μm.

如第2M圖所示,步驟13.依序沉積下電極層1071及壓電層1072於第三基板106上。 As shown in Figure 2M, step 13. Sequentially deposit the lower electrode layer 1071 and the piezoelectric layer 1072 on the third substrate 106.

如第2N圖所示,步驟14.圖案化蝕刻下電極層1071及壓電層1072。 As shown in Figure 2N, step 14. Patterning and etching the lower electrode layer 1071 and the piezoelectric layer 1072.

如第2O圖所示,步驟15.沉積絕緣層1073,並圖案化蝕刻絕緣層1073。 As shown in FIG. 20, step 15. depositing an insulating layer 1073 and patterning and etching the insulating layer 1073.

如第2P圖所示,步驟16.沉積上電極層1074,並圖案化蝕刻上電極層1074。 As shown in FIG. 2P, step 16. depositing the upper electrode layer 1074 and patterning and etching the upper electrode layer 1074.

如第2Q圖所示,步驟17.圖案化蝕刻絕緣層1073及第三基板106。值得注意的是,經步驟17.圖案化蝕刻絕緣層1073及第三基板106後,產生至少一第三流體通道1062,第三基板106區分為致動部1063、至少一外周部1065,其中,至少一連接部1064連接致動部1063與外周部1065,至少一第三流體通道1062亦介於致動部1063與外周部1065之間。此外,值得注意的是,位於第三基板106之致動部1063上的下電極層1071、壓電層1072、絕緣層1073及上電極層1074係為壓電組件107。另外,值得注意的是,壓電層1072為圓形設置於第三基板106之致動部1063上方,使致動部1063亦呈圓形。 As shown in FIG. 2Q, step 17. patterning the insulating layer 1073 and the third substrate 106. It is worth noting that after step 17. patterning the insulating layer 1073 and the third substrate 106, at least one third fluid channel 1062 is generated, and the third substrate 106 is divided into an actuating portion 1063 and at least one peripheral portion 1065, wherein at least one connecting portion 1064 connects the actuating portion 1063 and the peripheral portion 1065, and at least one third fluid channel 1062 is also between the actuating portion 1063 and the peripheral portion 1065. In addition, it is worth noting that the lower electrode layer 1071, the piezoelectric layer 1072, the insulating layer 1073 and the upper electrode layer 1074 located on the actuating portion 1063 of the third substrate 106 are the piezoelectric component 107. In addition, it is worth noting that the piezoelectric layer 1072 is circularly disposed above the actuating portion 1063 of the third substrate 106, so that the actuating portion 1063 is also circular.

如第2R圖所示,步驟18.圖案化蝕刻第一基板101的一下表面。 As shown in FIG. 2R, step 18. patterning and etching the lower surface of the first substrate 101.

如第2S圖所示,步驟19.蝕刻第一接著層102。即完成微型流體泵浦10的製作。 As shown in FIG. 2S, step 19. Etch the first bonding layer 102. The production of the microfluid pump 10 is completed.

值得注意的是,如第2S圖所示之流體通槽1011為分段蝕刻,解決了先前技術的蝕刻角度過大或高深寬比蝕刻問題,並且降低了流體流通第一流體通道1012的流阻。此外,第一接著層102係為氧化矽,但厚度調整為1~5μm,可以避免與第二基板103接合所造成的應力剝離問題。另外,第二流體通道104則以蝕刻第一基板101來定義出。 It is worth noting that the fluid channel 1011 shown in FIG. 2S is segmented etching, which solves the problem of excessive etching angle or high aspect ratio etching in the previous technology, and reduces the flow resistance of the fluid flowing through the first fluid channel 1012. In addition, the first connecting layer 102 is silicon oxide, but the thickness is adjusted to 1~5μm, which can avoid the stress peeling problem caused by bonding with the second substrate 103. In addition, the second fluid channel 104 is defined by etching the first substrate 101.

再者,值得注意的是,如第2S圖所示之第二基板103係為矽結構層,可以由SOI晶片轉移而來,厚度為1~5μm,但不以此為限,第二基板103的厚度可視設計需求加以調整。第二基板103區分為穿孔1031、振動部 1032及固定部1033三個區域,穿孔1031位於中心位置,振動部1032位於穿孔1031的周邊區域,固定部1033位於第二基板103的周緣區域。 Furthermore, it is worth noting that the second substrate 103 shown in FIG. 2S is a silicon structure layer, which can be transferred from an SOI chip, and has a thickness of 1 to 5 μm, but is not limited thereto. The thickness of the second substrate 103 can be adjusted according to design requirements. The second substrate 103 is divided into three areas: a through hole 1031, a vibration part 1032, and a fixed part 1033. The through hole 1031 is located at the center, the vibration part 1032 is located at the peripheral area of the through hole 1031, and the fixed part 1033 is located at the peripheral area of the second substrate 103.

另外,值得注意的是,如第2S圖所示之第二接著層105係為氧化矽,厚度為1~5μm。第一接著層102的厚度可以等於第二接著層105的厚度,其厚度可以是1.1μm,但不以此為限,第一接著層102的厚度與第二接著層105的厚度亦可以不相等,可視設計需求加以調整。第二接著層105堆疊於第二基板103上方。 In addition, it is worth noting that the second bonding layer 105 shown in FIG. 2S is silicon oxide with a thickness of 1 to 5 μm. The thickness of the first bonding layer 102 can be equal to the thickness of the second bonding layer 105, which can be 1.1 μm, but is not limited thereto. The thickness of the first bonding layer 102 and the thickness of the second bonding layer 105 can also be unequal and can be adjusted according to design requirements. The second bonding layer 105 is stacked on the second substrate 103.

除此,值得注意的是,如第2S圖所示之第三基板106係為矽結構層,可以由SOI晶片轉移而來,厚度為10~20μm,但不以此為限,第三基板106的厚度可視設計需求加以調整;第三基板106堆疊於第二接著層105上方,形成共振腔室1061;第三基板106具有致動部1063及外周部1065,致動部1063的外環具有第三流體通道1062及連接部1064,連接部1064係用以連接致動部1063與外周部1065。 In addition, it is worth noting that the third substrate 106 shown in FIG. 2S is a silicon structure layer, which can be transferred from an SOI chip, and has a thickness of 10~20μm, but is not limited thereto. The thickness of the third substrate 106 can be adjusted according to design requirements; the third substrate 106 is stacked on the second bonding layer 105 to form a resonance chamber 1061; the third substrate 106 has an actuating portion 1063 and a peripheral portion 1065, and the outer ring of the actuating portion 1063 has a third fluid channel 1062 and a connecting portion 1064, and the connecting portion 1064 is used to connect the actuating portion 1063 and the peripheral portion 1065.

值得注意的是,第二基板103、第三基板106可以是單晶矽、多晶矽或非晶矽。第二基板103、第三基板106也可以使用沉積或薄化製程而來。 It is worth noting that the second substrate 103 and the third substrate 106 can be single crystal silicon, polycrystalline silicon or amorphous silicon. The second substrate 103 and the third substrate 106 can also be made using a deposition or thinning process.

壓電組件107更包含下電極層1071、壓電層1072、絕緣層1073及上電極層1074。壓電層1072疊設於下電極層1071上;絕緣層1073鋪設於壓電層1072之部分表面上及下電極層1071之部分表面上,其中絕緣層1073為電性絕緣;上電極層1074疊設於絕緣層1073上以及壓電層1072未設有絕緣層1073之其餘表面上。值得注意的是,壓電層1072為圓形設置於第三基板106之致動部1063上方,使致動部1063亦呈圓形。此外,值得注意的是,壓電層1072的直徑為140~500μm,但不以此為限,壓電層1072的直徑,可視微型流體泵浦10整體大小加以調整。另外,值得注意的是, 壓電層1072與致動部1063的直徑比例範圍為1:1.3~1:3.6,換言之,壓電層1072的尺寸小於致動部1063的尺寸。 The piezoelectric component 107 further includes a lower electrode layer 1071, a piezoelectric layer 1072, an insulating layer 1073, and an upper electrode layer 1074. The piezoelectric layer 1072 is stacked on the lower electrode layer 1071; the insulating layer 1073 is laid on a portion of the surface of the piezoelectric layer 1072 and a portion of the surface of the lower electrode layer 1071, wherein the insulating layer 1073 is electrically insulating; and the upper electrode layer 1074 is stacked on the insulating layer 1073 and on the remaining surface of the piezoelectric layer 1072 where the insulating layer 1073 is not provided. It is worth noting that the piezoelectric layer 1072 is circularly disposed above the actuating portion 1063 of the third substrate 106, so that the actuating portion 1063 is also circular. In addition, it is worth noting that the diameter of the piezoelectric layer 1072 is 140~500μm, but it is not limited to this. The diameter of the piezoelectric layer 1072 can be adjusted according to the overall size of the microfluidic pump 10. In addition, it is worth noting that the diameter ratio of the piezoelectric layer 1072 to the actuating portion 1063 ranges from 1:1.3 to 1:3.6. In other words, the size of the piezoelectric layer 1072 is smaller than the size of the actuating portion 1063.

透過壓電組件107的作動,致動部1063亦跟著上下振動,第二基板103的振動部1032隨之呈不同相位振動,使共振腔室1061形成負壓,流體便由流體通槽1011通過第一流體通道1012,再經過第二流體通道104,並由第二基板103的穿孔1031繼續流經共振腔室1061,最後通過第三基板106的第三流體通道1062完成流體的輸送。值得注意的是致動部1063的作動頻率為0.1~1.5MHz高頻範圍,藉此微流體可以積少成多產生更多的流量,但不以此為限,致動部1063的作動頻率可由整體微型流體泵浦10之設計加以調整。此外,值得注意的是,致動部1063呈圓形且直徑為400~550μm,但不以此為限,致動部1063的形狀尺寸亦可由整體微型流體泵浦10之設計加以調整。 Through the actuation of the piezoelectric component 107, the actuator 1063 also vibrates up and down, and the vibrating portion 1032 of the second substrate 103 vibrates in different phases, so that the resonance chamber 1061 forms a negative pressure, and the fluid passes through the first fluid channel 1012 from the fluid groove 1011, and then passes through the second fluid channel 104, and continues to flow through the resonance chamber 1061 through the through hole 1031 of the second substrate 103, and finally passes through the third fluid channel 1062 of the third substrate 106 to complete the fluid delivery. It is worth noting that the actuation frequency of the actuator 1063 is in the high frequency range of 0.1~1.5MHz, so that the microfluid can accumulate a small amount to generate more flow, but it is not limited to this. The actuation frequency of the actuator 1063 can be adjusted by the design of the overall microfluid pump 10. In addition, it is worth noting that the actuator 1063 is circular and has a diameter of 400-550 μm, but is not limited thereto. The shape and size of the actuator 1063 can also be adjusted by the design of the overall microfluidic pump 10.

微型流體泵浦10的工作電壓為2~12V,值得一提的是,微型流體泵浦10的工作電壓、第三基板106的致動部1063之作動頻率、第三基板106的厚度以及第二基板103的振動部1032之共振皆會影響流體的輸送量與效率。 The operating voltage of the microfluid pump 10 is 2~12V. It is worth mentioning that the operating voltage of the microfluid pump 10, the operating frequency of the actuator 1063 of the third substrate 106, the thickness of the third substrate 106 and the resonance of the vibration part 1032 of the second substrate 103 will all affect the delivery volume and efficiency of the fluid.

請參閱第3T圖,係為本案之微型流體泵浦之第二實施例,與第一實施例主要的差異處在於第三基板206具有蝕刻一深度。於本實施例中,微型流體泵浦20包含第一基板201、第一接著層202、第二基板203、第二接著層205、第三基板206及壓電組件207第一基板201設有流體通槽2011以及至少一第一流體通道2012,其中流體通槽2011為深槽狀;第一基板201、第一接著層202、第二基板203依序由下而上疊設,並定義出第二流體通道204,第二流體通道204頂端設有穿孔2031,穿孔2031係位於第二基板203的中心,穿孔2031的外圍由振動部2032環繞,振動部 2032由固定部2033環繞;第二基板203、第二接著層205、第三基板206依序由下而上疊設,並定義出共振腔室2061;第三基板206更包含至少一第三流體通道2062、致動部2063、連接部2064與外周部2065,其中外周部2065環設於致動部2063的外圍,外周部2065並透過連接部2064耦接致動部2063,第三流體通道2062則貫通第三基板206,使第三流體通道2062、共振腔室2061得透過穿孔2031依序連通第二流體通道204、第一流體通道2012、流體通槽2011;壓電組件207疊設於致動部2063之上,包含下電極層2071、壓電層2072、絕緣層2073及上電極層2074。 Please refer to FIG. 3T, which is a second embodiment of the microfluid pump of the present invention. The main difference from the first embodiment is that the third substrate 206 is etched to a depth. In this embodiment, the microfluid pump 20 comprises a first substrate 201, a first connecting layer 202, a second substrate 203, a second connecting layer 205, a third substrate 206 and a piezoelectric component 207. The first substrate 201 is provided with a fluid through groove 2011 and at least one first fluid channel 2012, wherein the fluid through groove 2011 is a deep groove; the first substrate 201, the first connecting layer 202 and the second substrate 203 are stacked from bottom to top in sequence and define a second fluid channel 204. The second fluid channel 204 is provided with a through hole 2031 at the top. The through hole 2031 is located at the center of the second substrate 203. The outer periphery of the through hole 2031 is surrounded by a vibrating portion 2032, and the vibrating portion 2032 is surrounded by a fixing portion 2033; the second substrate 203, the second connecting layer 205 and the third substrate 2 06 are stacked from bottom to top, and define a resonance chamber 2061; the third substrate 206 further includes at least one third fluid channel 2062, an actuating portion 2063, a connecting portion 2064 and a peripheral portion 2065, wherein the peripheral portion 2065 is arranged around the periphery of the actuating portion 2063, and the peripheral portion 2065 is coupled to the actuating portion 2063 through the connecting portion 2064, and the third fluid channel 206 2 penetrates the third substrate 206, so that the third fluid channel 2062 and the resonance chamber 2061 can be connected to the second fluid channel 204, the first fluid channel 2012, and the fluid channel 2011 in sequence through the through hole 2031; the piezoelectric component 207 is stacked on the actuator 2063, including a lower electrode layer 2071, a piezoelectric layer 2072, an insulating layer 2073 and an upper electrode layer 2074.

請參閱第1A圖至第1C圖及第3A圖至第3T圖,如第3A圖所示,步驟1.準備一第一基板201。值得注意的是,第一基板201係為矽基材(Si),厚度為270~430μm,但不以此為限。 Please refer to Figures 1A to 1C and Figures 3A to 3T. As shown in Figure 3A, step 1. prepare a first substrate 201. It is worth noting that the first substrate 201 is a silicon substrate (Si) with a thickness of 270~430μm, but not limited to this.

如第3B圖所示,步驟2.蝕刻第一基板201的一上表面,形成至少一第一凹槽201A。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。 As shown in FIG. 3B, step 2. Etching an upper surface of the first substrate 201 to form at least one first groove 201A. It is worth noting that this etching method can be physical or chemical etching.

如第3C圖所示,步驟3.蝕刻第一基板201的上表面,形成第二凹槽201B,其中第一凹槽201A位於第二凹槽201B的底部。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。 As shown in FIG. 3C, step 3. Etching the upper surface of the first substrate 201 to form a second groove 201B, wherein the first groove 201A is located at the bottom of the second groove 201B. It is worth noting that this etching method can be physical or chemical etching.

如第3D圖所示,步驟4.沉積第一接著層202於第一基板201之至少一第一凹槽201A及第二凹槽201B的表面上。值得注意的是,第一接著層202係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於第一基板201的表面,第一接著層202係為氧化矽,厚度範圍為1~5μm。 As shown in FIG. 3D, step 4. depositing a first bonding layer 202 on the surface of at least one first groove 201A and a second groove 201B of the first substrate 201. It is worth noting that the first bonding layer 202 is formed on the surface of the first substrate 201 by physical vapor deposition or chemical vapor deposition or thermal oxidation. The first bonding layer 202 is silicon oxide with a thickness ranging from 1 to 5 μm.

如第3E圖所示,步驟5.準備第三基板206。值得注意的是,第三基板206可以是一絕緣層上覆矽(SOI)晶圓,但不以此為限。 As shown in FIG. 3E, step 5. prepare the third substrate 206. It is worth noting that the third substrate 206 can be a silicon-on-insulation layer (SOI) wafer, but is not limited thereto.

如第3F圖所示,步驟6.沉積第二接著層205於第三基板206的表面上。值得注意的是,第二接著層205係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於第三基板206的表面,第二接著層205的厚度範圍為1-5μm。 As shown in FIG. 3F, step 6. depositing the second bonding layer 205 on the surface of the third substrate 206. It is worth noting that the second bonding layer 205 is formed on the surface of the third substrate 206 by physical vapor deposition or chemical vapor deposition or thermal oxidation, and the thickness of the second bonding layer 205 ranges from 1 to 5 μm.

如第3G圖所示,步驟7.圖案化蝕刻第二接著層205。值得注意的是,經步驟7.圖案化蝕刻第二接著層205後,產生一共振腔室2061。 As shown in FIG. 3G, step 7. pattern etching the second connecting layer 205. It is worth noting that after step 7. pattern etching the second connecting layer 205, a resonant chamber 2061 is generated.

如第3H圖所示,經步驟7.圖案化蝕刻第二接著層205後,更包含蝕刻第三基板206至一深度。值得注意的是,第三基板206蝕刻至一深度,使得如第3T圖所示之共振腔室2061的空間提高了,適當降低擠壓膜阻尼(squeeze film damping),且當壓電組件207作動帶動第三基板206的致動部2063振動時,也較不易與第二基板203的振動部2032產生沾黏(stiction)效應。 As shown in FIG. 3H, after step 7. patterning and etching the second connecting layer 205, the third substrate 206 is further etched to a depth. It is worth noting that etching the third substrate 206 to a depth increases the space of the resonance chamber 2061 shown in FIG. 3T, appropriately reduces the squeeze film damping, and when the piezoelectric component 207 is actuated to drive the actuating portion 2063 of the third substrate 206 to vibrate, it is less likely to produce a stiction effect with the vibrating portion 2032 of the second substrate 203.

如第3I圖所示,步驟8.準備第二基板203,將第二基板203與第三基板206之圖案化蝕刻的第二接著層205相互結合。值得注意的是,第二基板203可以是一絕緣層上覆矽(SOI)晶圓,但不以此為限。 As shown in FIG. 3I, step 8. prepare the second substrate 203, and bond the second substrate 203 and the patterned second bonding layer 205 of the third substrate 206 to each other. It is worth noting that the second substrate 203 can be a silicon-on-insulation layer (SOI) wafer, but is not limited thereto.

如第3J圖所示,步驟9.移除部分的第二基板203。值得注意的是,經步驟9.移除部分的第二基板203剩餘的厚度範圍為1-5μm。 As shown in Figure 3J, step 9. removes part of the second substrate 203. It is worth noting that the remaining thickness of the second substrate 203 after step 9. removes part of the second substrate 203 is in the range of 1-5μm.

如第3K圖所示,步驟10.圖案化蝕刻第二基板203。值得注意的是,經步驟10.圖案化蝕刻第二基板203後,第二基板203區分為一穿孔2031、一振動部2032及一固定部2033。 As shown in FIG. 3K, step 10. patterning the second substrate 203. It is worth noting that after step 10. patterning the second substrate 203, the second substrate 203 is divided into a through hole 2031, a vibration portion 2032 and a fixed portion 2033.

如第3L圖所示,步驟11.將第一基板201具有至少一第一凹槽201A及第二凹槽201B的表面與第二基板203相互結合。值得注意的是,將第二基板203接合第三基板206的順序優先於將第二基板203接合第一基板201。其中,基板接合的順序係考量避免在接合時產生接合不良(Poor Bonding)所造成微型流體泵浦20的良率問題,因此先將第二基板203與第三基板206接合後再與第一基板201接合可以提升接合良率。 As shown in FIG. 3L, step 11. The surface of the first substrate 201 having at least one first groove 201A and a second groove 201B is bonded to the second substrate 203. It is worth noting that the order of bonding the second substrate 203 to the third substrate 206 is prior to bonding the second substrate 203 to the first substrate 201. The order of bonding the substrates is considered to avoid the yield problem of the microfluid pump 20 caused by poor bonding during bonding. Therefore, bonding the second substrate 203 to the third substrate 206 first and then to the first substrate 201 can improve the bonding yield.

如第3M圖所示,步驟12.移除部分的第三基板206。值得注意的是,經步驟12.移除部分的第三基板206剩餘的厚度範圍為5-20μm。 As shown in FIG. 3M, step 12. removes part of the third substrate 206. It is worth noting that the remaining thickness of the third substrate 206 after the part of the third substrate 206 is removed in step 12. ranges from 5 to 20 μm.

如第3N圖所示,步驟13.依序沉積下電極層2071及壓電層2072於第三基板206上。 As shown in Figure 3N, step 13. Sequentially deposit the lower electrode layer 2071 and the piezoelectric layer 2072 on the third substrate 206.

如第3O圖所示,步驟14.圖案化蝕刻下電極層2071及壓電層2072。 As shown in FIG. 30, step 14. Patterning and etching the lower electrode layer 2071 and the piezoelectric layer 2072.

如第3P圖所示,步驟15.沉積絕緣層2073,並圖案化蝕刻絕緣層2073。 As shown in Figure 3P, step 15. Deposit the insulating layer 2073 and pattern-etch the insulating layer 2073.

如第3Q圖所示,步驟16.沉積上電極層2074,並圖案化蝕刻上電極層2074。 As shown in FIG. 3Q, step 16. depositing the upper electrode layer 2074 and patterning and etching the upper electrode layer 2074.

如第3R圖所示,步驟17.圖案化蝕刻絕緣層2073及第三基板206。值得注意的是,經步驟17.圖案化蝕刻絕緣層2073及第三基板206後,產生至少一第三流體通道2062,第三基板206區分為致動部2063、至少一外周部2065,其中,至少一連接部2064連接致動部2063與外周部2065,至少一第三流體通道2062亦介於致動部2063與外周部2065之間。此外,值得注意的是,位於第三基板206之致動部2063上的下電極層2071、壓電層2072、絕緣層2073及上電極層2074係為壓電組件207。另外,值得注意的是,壓電層2072為圓形設置於第三基板206之致動部2063上方,使致動部2063亦呈圓形。 As shown in FIG. 3R, step 17. patterning the insulating layer 2073 and the third substrate 206. It is worth noting that after step 17. patterning the insulating layer 2073 and the third substrate 206, at least one third fluid channel 2062 is generated, and the third substrate 206 is divided into an actuating portion 2063 and at least one peripheral portion 2065, wherein at least one connecting portion 2064 connects the actuating portion 2063 and the peripheral portion 2065, and at least one third fluid channel 2062 is also between the actuating portion 2063 and the peripheral portion 2065. In addition, it is worth noting that the lower electrode layer 2071, the piezoelectric layer 2072, the insulating layer 2073 and the upper electrode layer 2074 located on the actuating portion 2063 of the third substrate 206 are the piezoelectric component 207. In addition, it is worth noting that the piezoelectric layer 2072 is circularly disposed above the actuating portion 2063 of the third substrate 206, so that the actuating portion 2063 is also circular.

如第3S圖所示,步驟18.圖案化蝕刻第一基板201的一下表面。 As shown in FIG. 3S, step 18. patterning and etching the lower surface of the first substrate 201.

如第3T圖所示,步驟19.蝕刻第一接著層202。即完成微型流體泵浦20的製作。 As shown in Figure 3T, step 19. Etch the first bonding layer 202. The production of the microfluidic pump 20 is completed.

值得注意的是,如第3T圖所示之流體通槽2011為分段蝕刻,解決了先前技術的蝕刻角度過大或高深寬比蝕刻問題,並且降低了流體流通第 一流體通道2012的流阻。此外,第一接著層202係為氧化矽,但厚度調整為1~5μm,可以避免與第二基板203接合所造成的應力剝離問題。另外,第二流體通道204則以蝕刻第一基板201來定義出。 It is worth noting that the fluid channel 2011 shown in Figure 3T is segmented etching, which solves the problem of excessive etching angle or high aspect ratio etching in the previous technology, and reduces the flow resistance of the fluid flowing through the first fluid channel 2012. In addition, the first connecting layer 202 is silicon oxide, but the thickness is adjusted to 1~5μm, which can avoid the stress peeling problem caused by bonding with the second substrate 203. In addition, the second fluid channel 204 is defined by etching the first substrate 201.

再者,值得注意的是,如第3T圖所示之第二基板203係為矽結構層,可以由SOI晶片轉移而來,厚度為1~5μm,但不以此為限,第二基板203的厚度可視設計需求加以調整。第二基板203區分為穿孔2031、振動部2032及固定部2033三個區域,穿孔2031位於中心位置,振動部2032位於穿孔2031的周邊區域,固定部2033位於第二基板203的周緣區域。 Furthermore, it is worth noting that the second substrate 203 shown in FIG. 3T is a silicon structure layer, which can be transferred from an SOI chip, and has a thickness of 1 to 5 μm, but is not limited thereto. The thickness of the second substrate 203 can be adjusted according to design requirements. The second substrate 203 is divided into three areas: a through hole 2031, a vibration part 2032, and a fixed part 2033. The through hole 2031 is located at the center, the vibration part 2032 is located at the peripheral area of the through hole 2031, and the fixed part 2033 is located at the peripheral area of the second substrate 203.

另外,值得注意的是,如第3T圖所示之第二接著層205係為氧化矽,厚度為1~5μm。第一接著層202的厚度可以等於第二接著層205的厚度,其厚度可以是1.1μm,但不以此為限,第一接著層202的厚度與第二接著層205的厚度亦可以不相等,可視設計需求加以調整。第二接著層205堆疊於第二基板203上方。 In addition, it is worth noting that the second bonding layer 205 shown in FIG. 3T is silicon oxide with a thickness of 1 to 5 μm. The thickness of the first bonding layer 202 can be equal to the thickness of the second bonding layer 205, and its thickness can be 1.1 μm, but it is not limited to this. The thickness of the first bonding layer 202 and the thickness of the second bonding layer 205 can also be unequal, and can be adjusted according to design requirements. The second bonding layer 205 is stacked on the second substrate 203.

除此,值得注意的是,如第3T圖所示之第三基板206係為矽結構層,可以由SOI晶片轉移而來,厚度為10~20μm,但不以此為限,第三基板206的厚度可視設計需求加以調整;第三基板206堆疊於第二接著層205上方,形成共振腔室2061;第三基板206具有致動部2063及外周部2065,致動部2063的外環具有第三流體通道2062及連接部2064,連接部2064係用以連接致動部2063與外周部2065。 In addition, it is worth noting that the third substrate 206 shown in FIG. 3T is a silicon structure layer, which can be transferred from an SOI chip, and has a thickness of 10~20μm, but is not limited thereto. The thickness of the third substrate 206 can be adjusted according to design requirements; the third substrate 206 is stacked on the second bonding layer 205 to form a resonance chamber 2061; the third substrate 206 has an actuating portion 2063 and a peripheral portion 2065, and the outer ring of the actuating portion 2063 has a third fluid channel 2062 and a connecting portion 2064, and the connecting portion 2064 is used to connect the actuating portion 2063 and the peripheral portion 2065.

值得注意的是,第二基板203、第三基板206可以是單晶矽、多晶矽或非晶矽。第二基板203、第三基板206也可以使用沉積或薄化製程而來。 It is worth noting that the second substrate 203 and the third substrate 206 can be single crystal silicon, polycrystalline silicon or amorphous silicon. The second substrate 203 and the third substrate 206 can also be made using a deposition or thinning process.

壓電組件207更包含下電極層2071、壓電層2072、絕緣層2073及上電極層2074。壓電層2072疊設於下電極層2071上;絕緣層2073鋪設於壓電層2072之部分表面上及下電極層2071之部分表面上,其中絕緣層2073為 電性絕緣;上電極層2074疊設於絕緣層2073上以及壓電層2072未設有絕緣層2073之其餘表面上。值得注意的是,壓電層2072為圓形設置於第三基板206之致動部2063上方,使致動部2063亦呈圓形。此外,值得注意的是,壓電層2072的直徑為140~500μm,但不以此為限,壓電層2072的直徑,可視微型流體泵浦20整體大小加以調整。另外,值得注意的是,壓電層2072與致動部2063的直徑比例範圍為1:1.3~1:3.6,換言之,壓電層2072的尺寸小於致動部2063的尺寸。 The piezoelectric component 207 further includes a lower electrode layer 2071, a piezoelectric layer 2072, an insulating layer 2073 and an upper electrode layer 2074. The piezoelectric layer 2072 is stacked on the lower electrode layer 2071; the insulating layer 2073 is laid on a portion of the surface of the piezoelectric layer 2072 and a portion of the surface of the lower electrode layer 2071, wherein the insulating layer 2073 is electrically insulating; the upper electrode layer 2074 is stacked on the insulating layer 2073 and on the remaining surface of the piezoelectric layer 2072 where the insulating layer 2073 is not provided. It is worth noting that the piezoelectric layer 2072 is circularly disposed above the actuating portion 2063 of the third substrate 206, so that the actuating portion 2063 is also circular. In addition, it is worth noting that the diameter of the piezoelectric layer 2072 is 140~500μm, but it is not limited to this. The diameter of the piezoelectric layer 2072 can be adjusted according to the overall size of the microfluidic pump 20. In addition, it is worth noting that the diameter ratio of the piezoelectric layer 2072 to the actuating portion 2063 is in the range of 1:1.3~1:3.6. In other words, the size of the piezoelectric layer 2072 is smaller than the size of the actuating portion 2063.

透過壓電組件207的作動,致動部2063亦跟著上下振動,第二基板203的振動部2032隨之呈不同相位振動,使共振腔室2061形成負壓,流體便由流體通槽2011通過第一流體通道2012,再經過第二流體通道204,並由第二基板203的穿孔2031繼續流經共振腔室2061,最後通過第三基板206的第三流體通道2062完成流體的輸送。值得注意的是致動部2063的作動頻率為0.1~1.5MHz高頻範圍,藉此微流體可以積少成多產生更多的流量,但不以此為限,致動部2063的作動頻率可由整體微型流體泵浦20之設計加以調整。此外,值得注意的是,致動部2063呈圓形且直徑為400~550μm,但不以此為限,致動部2063的形狀尺寸亦可由整體微型流體泵浦20之設計加以調整。 Through the actuation of the piezoelectric component 207, the actuator 2063 also vibrates up and down, and the vibrating part 2032 of the second substrate 203 vibrates in different phases, so that the resonance chamber 2061 forms a negative pressure, and the fluid passes through the first fluid channel 2012 from the fluid groove 2011, and then passes through the second fluid channel 204, and continues to flow through the resonance chamber 2061 through the through hole 2031 of the second substrate 203, and finally passes through the third fluid channel 2062 of the third substrate 206 to complete the fluid delivery. It is worth noting that the actuation frequency of the actuator 2063 is in the high frequency range of 0.1~1.5MHz, so that the microfluid can accumulate a small amount to generate more flow, but it is not limited to this. The actuation frequency of the actuator 2063 can be adjusted by the design of the overall microfluid pump 20. In addition, it is worth noting that the actuator 2063 is circular and has a diameter of 400-550 μm, but is not limited thereto. The shape and size of the actuator 2063 can also be adjusted by the design of the overall microfluidic pump 20.

微型流體泵浦20的工作電壓為2~12V,值得一提的是,微型流體泵浦20的工作電壓、第三基板206的致動部2063之作動頻率、第三基板206的厚度以及第二基板203的振動部2032之共振皆會影響流體的輸送量與效率。 The working voltage of the microfluid pump 20 is 2~12V. It is worth mentioning that the working voltage of the microfluid pump 20, the operating frequency of the actuator 2063 of the third substrate 206, the thickness of the third substrate 206 and the resonance of the vibration part 2032 of the second substrate 203 will all affect the delivery volume and efficiency of the fluid.

另外,值得注意的是,第二實施例與第一實施例最主要的差異在於第三基板206具有蝕刻一深度,其改良的特色在於,因為共振腔室2061的空間提高了,可以適當降低擠壓膜阻尼(squeeze film damping),且當壓電 組件207作動帶動第三基板206的致動部2063振動時,也較不易與第二基板203的振動部2032產生沾黏(stiction)效應。 In addition, it is worth noting that the main difference between the second embodiment and the first embodiment is that the third substrate 206 has an etched depth. The improved feature is that because the space of the resonance chamber 2061 is increased, the squeeze film damping can be appropriately reduced, and when the piezoelectric component 207 is actuated to drive the actuating portion 2063 of the third substrate 206 to vibrate, it is less likely to produce a stiction effect with the vibrating portion 2032 of the second substrate 203.

請參閱第4S圖,係為本案之微型流體泵浦之第三實施例,與第一實施例主要的差異處在於第二接著層305係為氧化矽-多晶矽-氧化矽的複合結構。於本實施例中,微型流體泵浦30包含第一基板301、第一接著層302、第二基板303、第二接著層305、第三基板306及壓電組件307第一基板301設有流體通槽3011以及至少一第一流體通道3012,其中流體通槽3011為深槽狀;第一基板301、第一接著層302、第二基板303依序由下而上疊設,並定義出第二流體通道304,第二流體通道304頂端設有穿孔3031,穿孔3031係位於第二基板303的中心,穿孔3031的外圍由振動部3032環繞,振動部3032由固定部3033環繞;第二基板303、第二接著層305、第三基板306依序由下而上疊設,並定義出共振腔室3061;第三基板306更包含至少一第三流體通道3062、致動部3063、連接部3064與外周部3065,其中外周部3065環設於致動部3063的外圍,外周部3065並透過連接部3064耦接致動部3063,第三流體通道3062則貫通第三基板306,使第三流體通道3062、共振腔室3061得透過穿孔3031依序連通第二流體通道304、第一流體通道3012、流體通槽3011;壓電組件307疊設於致動部3063之上,包含下電極層3071、壓電層3072、絕緣層3073及上電極層3074。 Please refer to FIG. 4S, which is a third embodiment of the microfluid pump of the present invention. The main difference from the first embodiment is that the second bonding layer 305 is a composite structure of silicon oxide-polysilicon-silicon oxide. In this embodiment, the microfluid pump 30 comprises a first substrate 301, a first connecting layer 302, a second substrate 303, a second connecting layer 305, a third substrate 306 and a piezoelectric component 307. The first substrate 301 is provided with a fluid through groove 3011 and at least one first fluid channel 3012, wherein the fluid through groove 3011 is a deep groove; the first substrate 301, the first connecting layer 302 and the second substrate 303 are stacked from bottom to top in sequence and define a second fluid channel 304, wherein a through hole 3031 is provided at the top of the second fluid channel 304, and the through hole 3031 is located at the center of the second substrate 303, and the outer periphery of the through hole 3031 is surrounded by a vibrating portion 3032, and the vibrating portion 3032 is surrounded by a fixing portion 3033; the second substrate 303, the second connecting layer 305 and the third substrate 306 are provided with a vibrating portion 3032, and the vibrating portion 3032 is surrounded by a fixing portion 3033; 6 are stacked from bottom to top, and define a resonance chamber 3061; the third substrate 306 further includes at least one third fluid channel 3062, an actuating portion 3063, a connecting portion 3064 and a peripheral portion 3065, wherein the peripheral portion 3065 is arranged around the periphery of the actuating portion 3063, and the peripheral portion 3065 is coupled to the actuating portion 3063 through the connecting portion 3064, and the third fluid channel 3062 The third substrate 306 is penetrated, so that the third fluid channel 3062 and the resonance chamber 3061 can be connected to the second fluid channel 304, the first fluid channel 3012, and the fluid channel 3011 in sequence through the through hole 3031; the piezoelectric component 307 is stacked on the actuator 3063, including a lower electrode layer 3071, a piezoelectric layer 3072, an insulating layer 3073, and an upper electrode layer 3074.

請參閱第1A圖至第1C圖及第4A圖至第4S圖,如第4A圖所示,步驟1.準備一第一基板301。值得注意的是,第一基板301係為矽基材(Si),厚度為270~430μm,但不以此為限。 Please refer to Figures 1A to 1C and Figures 4A to 4S. As shown in Figure 4A, step 1. prepare a first substrate 301. It is worth noting that the first substrate 301 is a silicon substrate (Si) with a thickness of 270~430μm, but not limited to this.

如第4B圖所示,步驟2.蝕刻第一基板301的一上表面,形成至少一第一凹槽301A。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。 As shown in FIG. 4B, step 2. Etching an upper surface of the first substrate 301 to form at least one first groove 301A. It is worth noting that this etching method can be physical or chemical etching.

如第4C圖所示,步驟3.蝕刻第一基板301的上表面,形成第二凹槽301B,其中第一凹槽301A位於第二凹槽301B的底部。值得注意的是,此蝕刻方式係可以物理或化學方式蝕刻。 As shown in FIG. 4C, step 3. Etching the upper surface of the first substrate 301 to form a second groove 301B, wherein the first groove 301A is located at the bottom of the second groove 301B. It is worth noting that this etching method can be physical or chemical etching.

如第4D圖所示,步驟4.沉積第一接著層302於第一基板301之至少一第一凹槽301A及第二凹槽301B的表面上。值得注意的是,第一接著層302係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於第一基板301的表面,第一接著層302係為氧化矽,厚度範圍為1~5μm。 As shown in FIG. 4D, step 4. depositing a first bonding layer 302 on the surface of at least one first groove 301A and a second groove 301B of the first substrate 301. It is worth noting that the first bonding layer 302 is formed on the surface of the first substrate 301 by physical vapor deposition or chemical vapor deposition or thermal oxidation. The first bonding layer 302 is silicon oxide with a thickness ranging from 1 to 5 μm.

如第4E圖所示,步驟5.準備第三基板306。值得注意的是,第三基板306可以是一絕緣層上覆矽(SOI)晶圓,但不以此為限。 As shown in FIG. 4E, step 5. prepare the third substrate 306. It is worth noting that the third substrate 306 can be a silicon-on-insulation layer (SOI) wafer, but is not limited thereto.

如第4F圖所示,步驟6.沉積第二接著層305於第三基板306的表面上。值得注意的是,第二接著層305更包含至少一多晶矽層3052,多晶矽層3052之下層3051與上層3053各為矽氧化層所包覆,但不以此為限,第二接著層305除了矽氧化層-多晶矽層-矽氧化層外,第二接著層305更可具有多個多晶矽層3052,如矽氧化層-多晶矽層-矽氧化層-多晶矽層-矽氧化層。 As shown in FIG. 4F, step 6. depositing the second bonding layer 305 on the surface of the third substrate 306. It is worth noting that the second bonding layer 305 further includes at least one polysilicon layer 3052, and the lower layer 3051 and the upper layer 3053 of the polysilicon layer 3052 are each covered by a silicon oxide layer, but not limited to this. In addition to silicon oxide layer-polysilicon layer-silicon oxide layer, the second bonding layer 305 may also have multiple polysilicon layers 3052, such as silicon oxide layer-polysilicon layer-silicon oxide layer-polysilicon layer-silicon oxide layer.

如第4G圖所示,步驟7.圖案化蝕刻第二接著層305。值得注意的是,經步驟7.圖案化蝕刻第二接著層305後,產生一共振腔室3061。值得注意的是,第二接著層305具有蝕刻一深度,使得如第4S圖所示之共振腔室3061的空間提高了,適當降低擠壓膜阻尼(squeeze film damping),且當壓電組件307作動帶動第三基板306的致動部3063振動時,也較不易與第二基板303的振動部3032產生沾黏(stiction)效應。 As shown in FIG. 4G, step 7. patterning the second connecting layer 305. It is worth noting that after step 7. patterning the second connecting layer 305, a resonance chamber 3061 is generated. It is worth noting that the second connecting layer 305 has an etching depth, so that the space of the resonance chamber 3061 shown in FIG. 4S is increased, the squeeze film damping is appropriately reduced, and when the piezoelectric component 307 is actuated to drive the actuating portion 3063 of the third substrate 306 to vibrate, it is less likely to produce a stiction effect with the vibrating portion 3032 of the second substrate 303.

如第4H圖所示,步驟8.準備第二基板303,將第二基板303與第三基板306之圖案化蝕刻的第二接著層305相互結合。值得注意的是,第二基板303可以是一絕緣層上覆矽(SOI)晶圓,但不以此為限。 As shown in FIG. 4H, step 8. prepare the second substrate 303, and bond the second substrate 303 and the patterned second bonding layer 305 of the third substrate 306 to each other. It is worth noting that the second substrate 303 can be a silicon-on-insulation layer (SOI) wafer, but is not limited thereto.

如第4I圖所示,步驟9.移除部分的第二基板303。值得注意的是,經步驟9.移除部分的第二基板303剩餘的厚度範圍為1-5μm。 As shown in Figure 4I, step 9. removes part of the second substrate 303. It is worth noting that the remaining thickness of the second substrate 303 after step 9. removes part of the second substrate 303 is in the range of 1-5μm.

如第4J圖所示,步驟10.圖案化蝕刻第二基板303。值得注意的是,經步驟10.圖案化蝕刻第二基板303後,第二基板303區分為一穿孔3031、一振動部3032及一固定部3033。 As shown in FIG. 4J, step 10. patterning the second substrate 303. It is worth noting that after step 10. patterning the second substrate 303, the second substrate 303 is divided into a through hole 3031, a vibration portion 3032 and a fixed portion 3033.

如第4K圖所示,步驟11.將第一基板301具有至少一第一凹槽301A及第二凹槽301B的表面與第二基板303相互結合。值得注意的是,將第二基板303接合第三基板306的順序優先於將第二基板303接合第一基板301。其中,基板接合的順序係考量避免在接合時產生接合不良(Poor Bonding)所造成微型流體泵浦30的良率問題,因此先將第二基板303與第三基板306接合後再與第一基板301接合可以提升接合良率。 As shown in FIG. 4K, step 11. The surface of the first substrate 301 having at least one first groove 301A and a second groove 301B is bonded to the second substrate 303. It is worth noting that the order of bonding the second substrate 303 to the third substrate 306 is prior to bonding the second substrate 303 to the first substrate 301. The order of bonding the substrates is considered to avoid the yield problem of the microfluid pump 30 caused by poor bonding during bonding. Therefore, bonding the second substrate 303 to the third substrate 306 first and then to the first substrate 301 can improve the bonding yield.

如第4L圖所示,步驟12.移除部分的第三基板306。值得注意的是,經步驟12.移除部分的第三基板306剩餘的厚度範圍為5-20μm。 As shown in FIG. 4L, step 12. removes part of the third substrate 306. It is worth noting that the remaining thickness of the third substrate 306 after the part of the third substrate 306 is removed in step 12. ranges from 5 to 20 μm.

如第4M圖所示,步驟13.依序沉積下電極層3071及壓電層3072於第三基板306上。 As shown in Figure 4M, step 13. Sequentially deposit the lower electrode layer 3071 and the piezoelectric layer 3072 on the third substrate 306.

如第4N圖所示,步驟14.圖案化蝕刻下電極層3071及壓電層3072。 As shown in Figure 4N, step 14. Patterning and etching the lower electrode layer 3071 and the piezoelectric layer 3072.

如第4O圖所示,步驟15.沉積絕緣層3073,並圖案化蝕刻絕緣層3073。 As shown in FIG. 40, step 15. depositing an insulating layer 3073 and patterning and etching the insulating layer 3073.

如第4P圖所示,步驟16.沉積上電極層3074,並圖案化蝕刻上電極層3074。 As shown in Figure 4P, step 16. depositing the upper electrode layer 3074 and patterning and etching the upper electrode layer 3074.

如第4Q圖所示,步驟17.圖案化蝕刻絕緣層3073及第三基板306。值得注意的是,經步驟17.圖案化蝕刻絕緣層3073及第三基板306後,產生至少一第三流體通道3062,第三基板306區分為致動部3063、至少一外周部3065,其中,至少一連接部3064連接致動部3063與外周部3065,至少一第三流體通道3062亦介於致動部3063與外周部3065之間。此外,值得注 意的是,位於第三基板306之致動部3063上的下電極層3071、壓電層3072、絕緣層3073及上電極層3074係為壓電組件307。另外,值得注意的是,壓電層3072為圓形設置於第三基板306之致動部3063上方,使致動部3063亦呈圓形。 As shown in FIG. 4Q, step 17. patterning the insulating layer 3073 and the third substrate 306. It is worth noting that after step 17. patterning the insulating layer 3073 and the third substrate 306, at least one third fluid channel 3062 is generated, and the third substrate 306 is divided into an actuating portion 3063 and at least one peripheral portion 3065, wherein at least one connecting portion 3064 connects the actuating portion 3063 and the peripheral portion 3065, and at least one third fluid channel 3062 is also between the actuating portion 3063 and the peripheral portion 3065. In addition, it is worth noting that the lower electrode layer 3071, the piezoelectric layer 3072, the insulating layer 3073 and the upper electrode layer 3074 located on the actuating portion 3063 of the third substrate 306 are the piezoelectric component 307. In addition, it is worth noting that the piezoelectric layer 3072 is circularly arranged above the actuating portion 3063 of the third substrate 306, so that the actuating portion 3063 is also circular.

如第4R圖所示,步驟18.圖案化蝕刻第一基板301的一下表面。 As shown in FIG. 4R, step 18. patterning and etching the lower surface of the first substrate 301.

如第4S圖所示,步驟19.蝕刻第一接著層302。即完成微型流體泵浦30的製作。 As shown in FIG. 4S, step 19. Etch the first bonding layer 302. The production of the microfluidic pump 30 is completed.

值得注意的是,如第4S圖所示之流體通槽3011為分段蝕刻,解決了先前技術的蝕刻角度過大或高深寬比蝕刻問題,並且降低了流體流通第一流體通道3012的流阻。此外,第一接著層302係為氧化矽,但厚度調整為1~5μm,可以避免與第二基板303接合所造成的應力剝離問題。另外,第二流體通道304則以蝕刻第一基板301來定義出。 It is worth noting that the fluid channel 3011 shown in FIG. 4S is segmented etching, which solves the problem of excessive etching angle or high aspect ratio etching in the previous technology, and reduces the flow resistance of the fluid flowing through the first fluid channel 3012. In addition, the first connecting layer 302 is silicon oxide, but the thickness is adjusted to 1~5μm, which can avoid the stress peeling problem caused by bonding with the second substrate 303. In addition, the second fluid channel 304 is defined by etching the first substrate 301.

再者,值得注意的是,如第4S圖所示之第二基板303係為矽結構層,可以由SOI晶片轉移而來,厚度為1~5μm,但不以此為限,第二基板303的厚度可視設計需求加以調整。第二基板303區分為穿孔3031、振動部3032及固定部3033三個區域,穿孔3031位於中心位置,振動部3032位於穿孔3031的周邊區域,固定部3033位於第二基板303的周緣區域。 Furthermore, it is worth noting that the second substrate 303 shown in FIG. 4S is a silicon structure layer, which can be transferred from an SOI chip, and has a thickness of 1 to 5 μm, but is not limited thereto. The thickness of the second substrate 303 can be adjusted according to design requirements. The second substrate 303 is divided into three areas: a through hole 3031, a vibration part 3032, and a fixed part 3033. The through hole 3031 is located at the center, the vibration part 3032 is located at the peripheral area of the through hole 3031, and the fixed part 3033 is located at the peripheral area of the second substrate 303.

另外,值得注意的是,如第4S圖所示之第二接著層305係為氧化矽層-多晶矽層-氧化矽層,厚度為1~10μm。第一接著層302的厚度可以等於第二接著層305的厚度,其厚度可以是1.1μm,但不以此為限,第一接著層302的厚度與第二接著層305的厚度亦可以不相等,可視設計需求加以調整。第二接著層305堆疊於第二基板303上方。 In addition, it is worth noting that the second bonding layer 305 shown in FIG. 4S is a silicon oxide layer-polysilicon layer-silicon oxide layer with a thickness of 1-10 μm. The thickness of the first bonding layer 302 can be equal to the thickness of the second bonding layer 305, and its thickness can be 1.1 μm, but it is not limited to this. The thickness of the first bonding layer 302 and the thickness of the second bonding layer 305 can also be unequal, and can be adjusted according to design requirements. The second bonding layer 305 is stacked on the second substrate 303.

除此,值得注意的是,如第4S圖所示之第三基板306係為矽結構層,可以由SOI晶片轉移而來,厚度為10~20μm,但不以此為限,第三基板306 的厚度可視設計需求加以調整;第三基板306堆疊於第二接著層305上方,形成共振腔室3061;第三基板306具有致動部3063及外周部3065,致動部3063的外環具有第三流體通道3062及連接部3064,連接部3064係用以連接致動部3063與外周部3065。 In addition, it is worth noting that the third substrate 306 shown in FIG. 4S is a silicon structure layer, which can be transferred from an SOI chip, and has a thickness of 10~20μm, but is not limited thereto. The thickness of the third substrate 306 can be adjusted according to design requirements; the third substrate 306 is stacked on the second bonding layer 305 to form a resonance chamber 3061; the third substrate 306 has an actuating portion 3063 and a peripheral portion 3065, and the outer ring of the actuating portion 3063 has a third fluid channel 3062 and a connecting portion 3064, and the connecting portion 3064 is used to connect the actuating portion 3063 and the peripheral portion 3065.

值得注意的是,第二基板303、第三基板306可以是單晶矽、多晶矽或非晶矽。第二基板303、第三基板306也可以使用沉積或薄化製程而來。 It is worth noting that the second substrate 303 and the third substrate 306 can be single crystal silicon, polycrystalline silicon or amorphous silicon. The second substrate 303 and the third substrate 306 can also be made using a deposition or thinning process.

壓電組件307更包含下電極層3071、壓電層3072、絕緣層3073及上電極層3074。壓電層3072疊設於下電極層3071上;絕緣層3073鋪設於壓電層3072之部分表面上及下電極層3071之部分表面上,其中絕緣層3073為電性絕緣;上電極層3074疊設於絕緣層3073上以及壓電層3072未設有絕緣層3073之其餘表面上。值得注意的是,壓電層3072為圓形設置於第三基板306之致動部3063上方,使致動部3063亦呈圓形。此外,值得注意的是,壓電層3072的直徑為140~500μm,但不以此為限,壓電層3072的直徑,可視微型流體泵浦30整體大小加以調整。另外,值得注意的是,壓電層3072與致動部3063的直徑比例範圍為1:1.3~1:3.6,換言之,壓電層3072的尺寸小於致動部3063的尺寸。 The piezoelectric component 307 further includes a lower electrode layer 3071, a piezoelectric layer 3072, an insulating layer 3073, and an upper electrode layer 3074. The piezoelectric layer 3072 is stacked on the lower electrode layer 3071; the insulating layer 3073 is laid on a portion of the surface of the piezoelectric layer 3072 and a portion of the surface of the lower electrode layer 3071, wherein the insulating layer 3073 is electrically insulating; and the upper electrode layer 3074 is stacked on the insulating layer 3073 and on the remaining surface of the piezoelectric layer 3072 where the insulating layer 3073 is not provided. It is worth noting that the piezoelectric layer 3072 is circularly disposed above the actuating portion 3063 of the third substrate 306, so that the actuating portion 3063 is also circular. In addition, it is worth noting that the diameter of the piezoelectric layer 3072 is 140~500μm, but it is not limited to this. The diameter of the piezoelectric layer 3072 can be adjusted according to the overall size of the microfluidic pump 30. In addition, it is worth noting that the diameter ratio of the piezoelectric layer 3072 to the actuating portion 3063 ranges from 1:1.3 to 1:3.6. In other words, the size of the piezoelectric layer 3072 is smaller than the size of the actuating portion 3063.

透過壓電組件307的作動,致動部3063亦跟著上下振動,第二基板303的振動部3032隨之呈不同相位振動,使共振腔室3061形成負壓,流體便由流體通槽3011通過第一流體通道3012,再經過第二流體通道304,並由第二基板303的穿孔3031繼續流經共振腔室3061,最後通過第三基板306的第三流體通道3062完成流體的輸送。值得注意的是致動部3063的作動頻率為0.1~1.5MHz高頻範圍,藉此微流體可以積少成多產生更多的流量,但不以此為限,致動部3063的作動頻率可由整體微型流體泵浦30之設計加以調整。此外,值得注意的是,致動部3063呈圓形且直徑為 400~550μm,但不以此為限,致動部3063的形狀尺寸亦可由整體微型流體泵浦30之設計加以調整。 Through the actuation of the piezoelectric component 307, the actuator 3063 also vibrates up and down, and the vibrating part 3032 of the second substrate 303 vibrates in different phases, so that the resonance chamber 3061 forms a negative pressure, and the fluid passes through the first fluid channel 3012 from the fluid groove 3011, and then passes through the second fluid channel 304, and continues to flow through the resonance chamber 3061 through the through hole 3031 of the second substrate 303, and finally completes the fluid delivery through the third fluid channel 3062 of the third substrate 306. It is worth noting that the actuation frequency of the actuator 3063 is in the high frequency range of 0.1~1.5MHz, so that the microfluid can accumulate a small amount to generate more flow, but it is not limited to this. The actuation frequency of the actuator 3063 can be adjusted by the design of the overall microfluid pump 30. In addition, it is worth noting that the actuator 3063 is circular and has a diameter of 400~550μm, but is not limited to this. The shape and size of the actuator 3063 can also be adjusted by the design of the overall microfluidic pump 30.

微型流體泵浦30的工作電壓為2~12V,值得一提的是,微型流體泵浦30的工作電壓、第三基板306的致動部3063之作動頻率、第三基板306的厚度以及第二基板303的振動部3032之共振皆會影響流體的輸送量與效率。 The working voltage of the microfluid pump 30 is 2~12V. It is worth mentioning that the working voltage of the microfluid pump 30, the operating frequency of the actuator 3063 of the third substrate 306, the thickness of the third substrate 306 and the resonance of the vibration part 3032 of the second substrate 303 will all affect the delivery volume and efficiency of the fluid.

另外,值得注意的是,第三實施例與第一實施例最主要的差異在於第二接著層305係為氧化矽-多晶矽-氧化矽的複合結構,其改良的特色在於,因為共振腔室3061的空間提高了,可以適當降低擠壓膜阻尼(squeeze film damping),且當壓電組件307作動帶動第三基板306的致動部3063振動時,也較不易與第二基板303的振動部3032產生沾黏(stiction)效應。 In addition, it is worth noting that the main difference between the third embodiment and the first embodiment is that the second bonding layer 305 is a composite structure of silicon oxide-polycrystalline silicon-silicon oxide. The improved feature is that because the space of the resonance chamber 3061 is increased, the squeeze film damping can be appropriately reduced, and when the piezoelectric component 307 is actuated to drive the actuating portion 3063 of the third substrate 306 to vibrate, it is less likely to produce a stiction effect with the vibrating portion 3032 of the second substrate 303.

綜上所述,本案提供一種微型流體泵浦的製造方法,係利用半導體製程來完成微型流體泵浦的結構,以利縮小泵浦的體積,此外改善了先前技術在錐狀的第一流體通道蝕刻的問題,降低流阻,更改善了流體進入微型流體泵浦的效率,另外,於第二實施例及第三實施例更增加了第三基板的致動部與第二基板的振動部之間的距離,降低共振腔室的阻尼,也較不易使第三基板的致動部與第二基板的振動部產生沾黏效應,提高了微型流體泵浦的使用壽命,極具產業之利用價值,爰依法提出申請。 In summary, this case provides a method for manufacturing a microfluid pump, which uses a semiconductor process to complete the structure of the microfluid pump, so as to reduce the volume of the pump. In addition, the problem of etching the tapered first fluid channel in the prior art is improved, the flow resistance is reduced, and the efficiency of the fluid entering the microfluid pump is improved. In addition, in the second and third embodiments, the distance between the actuating portion of the third substrate and the vibrating portion of the second substrate is increased, the damping of the resonance chamber is reduced, and it is less likely to cause the actuating portion of the third substrate and the vibrating portion of the second substrate to produce a sticking effect, thereby increasing the service life of the microfluid pump. It has great industrial utilization value, and therefore an application is filed in accordance with the law.

本案得由熟習此技術之人士任施匠思而為諸般修飾,然皆不脫如附申請專利範圍所欲保護者。 This case can be modified in various ways by people familiar with this technology, but it will not deviate from the scope of protection of the attached patent application.

S1~S7:步驟 S1~S7: Steps

Claims (15)

一種微型流體泵浦的製造方法,包含:準備一第一基板;蝕刻該第一基板的一上表面,形成至少一第一凹槽;蝕刻該第一基板的該上表面,形成一第二凹槽,其中該至少一第一凹槽位於該第二凹槽的底部;沉積一第一接著層於該第一基板之該至少一第一凹槽及該第二凹槽的表面上;準備一第三基板;沉積一第二接著層於該第三基板的表面上;圖案化蝕刻該第二接著層;準備一第二基板,將該第二基板與該第三基板之圖案化蝕刻的該第二接著層相互結合;移除部分的該第二基板;圖案化蝕刻該第二基板;將該第一基板具有該至少一第一凹槽及該第二凹槽的表面與該第二基板相互結合;移除部分的該第三基板;依序沉積一下電極層及一壓電層於該第三基板上;圖案化蝕刻該下電極層及該壓電層;沉積一絕緣層,並圖案化蝕刻該絕緣層;沉積一上電極層,並圖案化蝕刻該上電極層;圖案化蝕刻該絕緣層及該第三基板;圖案化蝕刻該第一基板的一下表面; 蝕刻該第一接著層。 A method for manufacturing a microfluidic pump comprises: preparing a first substrate; etching an upper surface of the first substrate to form at least one first groove; etching the upper surface of the first substrate to form a second groove, wherein the at least one first groove is located at the bottom of the second groove; depositing a first bonding layer on the surface of the at least one first groove and the second groove of the first substrate; preparing a third substrate; depositing a second bonding layer on the surface of the third substrate; pattern-etching the second bonding layer; preparing a second substrate, and bonding the second substrate and the pattern-etched second bonding layer of the third substrate. The first substrate is bonded to the second substrate; a portion of the second substrate is removed; the second substrate is patterned and etched; the surface of the first substrate having the at least one first groove and the second groove is bonded to the second substrate; a portion of the third substrate is removed; a lower electrode layer and a piezoelectric layer are sequentially deposited on the third substrate; the lower electrode layer and the piezoelectric layer are patterned and etched; an insulating layer is deposited and patterned and etched; an upper electrode layer is deposited and patterned and etched; the insulating layer and the third substrate are patterned and etched; a lower surface of the first substrate is patterned and etched; the first connecting layer is etched. 如請求項1所述微型流體泵浦的製造方法,其中圖案化蝕刻該第二接著層後,產生一共振腔室。 A method for manufacturing a microfluidic pump as described in claim 1, wherein a resonant chamber is generated after patterning and etching the second follower layer. 如請求項1所述微型流體泵浦的製造方法,其中圖案化蝕刻該第二基板後,該第二基板區分為一穿孔、一振動部及一固定部。 The manufacturing method of the microfluid pump as described in claim 1, wherein after patterning and etching the second substrate, the second substrate is divided into a through hole, a vibration portion and a fixed portion. 如請求項1所述微型流體泵浦的製造方法,其中圖案化蝕刻該絕緣層及該第三基板後,產生至少一第三流體通道,該第三基板區分為一致動部、至少一外周部,其中,至少一連接部連接該致動部與該外周部,該至少一第三流體通道亦介於該致動部與該外周部之間。 The manufacturing method of the microfluid pump as described in claim 1, wherein after patterning the insulating layer and the third substrate, at least one third fluid channel is generated, and the third substrate is divided into an actuating portion and at least one peripheral portion, wherein at least one connecting portion connects the actuating portion and the peripheral portion, and the at least one third fluid channel is also between the actuating portion and the peripheral portion. 如請求項4所述微型流體泵浦的製造方法,其中位於該第三基板之該致動部上的該下電極層、該壓電層、該絕緣層及該上電極層係為一壓電組件。 The manufacturing method of the microfluid pump as described in claim 4, wherein the lower electrode layer, the piezoelectric layer, the insulating layer and the upper electrode layer located on the actuator portion of the third substrate are a piezoelectric component. 如請求項1所述微型流體泵浦的製造方法,其中將該第二基板接合該第三基板的順序優先於將該第二基板接合該第一基板。 A method for manufacturing a microfluidic pump as described in claim 1, wherein the order of bonding the second substrate to the third substrate takes precedence over bonding the second substrate to the first substrate. 如請求項1所述微型流體泵浦的製造方法,其中該第一接著層係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於該第一基板的表面。 The manufacturing method of the microfluidic pump as described in claim 1, wherein the first connecting layer is formed on the surface of the first substrate by physical vapor deposition or chemical vapor deposition or thermal oxidation. 如請求項1所述微型流體泵浦的製造方法,其中該第二接著層係藉由物理氣相沉積或化學氣相沉積或熱氧化形成於該第三基板的表面。 The manufacturing method of the microfluidic pump as described in claim 1, wherein the second connecting layer is formed on the surface of the third substrate by physical vapor deposition or chemical vapor deposition or thermal oxidation. 如請求項1所述微型流體泵浦的製造方法,其中該第一接著層的厚度範圍為1-5μm。 The manufacturing method of the microfluidic pump as described in claim 1, wherein the thickness of the first bonding layer ranges from 1 to 5 μm. 如請求項1所述微型流體泵浦的製造方法,其中該第二接著層的厚度範圍為1-10μm。 The manufacturing method of the microfluidic pump as described in claim 1, wherein the thickness of the second bonding layer ranges from 1 to 10 μm. 如請求項1所述微型流體泵浦的製造方法,其中移除部分的該第二基板後剩餘的厚度範圍為1-5μm。 The manufacturing method of the microfluidic pump as described in claim 1, wherein the remaining thickness after removing part of the second substrate is in the range of 1-5μm. 如請求項1所述微型流體泵浦的製造方法,其中移除部分的該第三基板後剩餘的厚度範圍為5-20μm。 The manufacturing method of the microfluidic pump as described in claim 1, wherein the remaining thickness after removing part of the third substrate is in the range of 5-20μm. 如請求項4所述微型流體泵浦的製造方法,其中該壓電層為圓形設置於該第三基板之該致動部上方,該致動部亦呈圓形。 The manufacturing method of the microfluidic pump as described in claim 4, wherein the piezoelectric layer is circularly arranged above the actuating portion of the third substrate, and the actuating portion is also circular. 如請求項1所述微型流體泵浦的製造方法,其中圖案化蝕刻該第二接著層後,更包含蝕刻該第三基板至一深度。 The manufacturing method of the microfluid pump as described in claim 1, wherein after patterning and etching the second connecting layer, the method further includes etching the third substrate to a depth. 如請求項1所述微型流體泵浦的製造方法,其中沉積一第二接著層於該第三基板的表面上時,該第二接著層更包含至少一多晶矽層,該多晶矽層之下層與上層各為一矽氧化層所包覆。 In the manufacturing method of the microfluid pump as described in claim 1, when a second bonding layer is deposited on the surface of the third substrate, the second bonding layer further comprises at least one polycrystalline silicon layer, and the lower layer and the upper layer of the polycrystalline silicon layer are each covered by a silicon oxide layer.
TW111140483A 2022-10-25 2022-10-25 Method for manufacturing micro fluid pump TWI839913B (en)

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Citations (3)

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US20190062151A1 (en) * 2017-08-28 2019-02-28 Taiwan Semiconductor Manufacturing Company Ltd. Mems device with viewer window and manufacturing method thereof
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US20200371376A1 (en) * 2019-05-24 2020-11-26 Stmicroelectronics S.R.L. Piezoelectric mems actuator for compensating unwanted movements and manufacturing process thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190062151A1 (en) * 2017-08-28 2019-02-28 Taiwan Semiconductor Manufacturing Company Ltd. Mems device with viewer window and manufacturing method thereof
US20200088185A1 (en) * 2018-09-17 2020-03-19 Microjet Technology Co., Ltd. Micro-electromechanical system pump
US20200371376A1 (en) * 2019-05-24 2020-11-26 Stmicroelectronics S.R.L. Piezoelectric mems actuator for compensating unwanted movements and manufacturing process thereof

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