TWI839009B - Semiconductor device - Google Patents

Abstract

A semiconductor device including a substrate, a first conductive layer, a first insulating layer, a gate structure, a semiconductor layer and a second insulating layer is provided. The first conductive layer is disposed on the substrate. The insulating layer is disposed on the first conductive layer. The gate structure is disposed above the first insulating layer. The semiconductor layer is disposed between the first insulating layer and the gate structure. The semiconductor layer includes a channel region, a first heavily doped region, a second heavily doped region and at least one lightly doped region. The channel region is overlapped with the gate structure. The first heavily doped region and the second heavily doped region are located at two sides of the channel region, respectively. The at least on lightly doped region is between the first heavily doped region and the channel region or between the second heavily doped region and the channel region, to form an asymmetric doped structure at the two sides of the channel region. The second insulating layer is disposed between the semiconductor layer and the gate structure.

Description

Semiconductor Devices

The present invention relates to a device, and in particular to a semiconductor device.

Semiconductor devices, such as thin film transistors, are widely used in electronic products to control current switches. As electronic products are becoming thinner and smaller, how to make semiconductor devices meet high current or high voltage applications in a small volume or size is a problem that needs to be improved.

The present invention provides a semiconductor device which is small in size and has improved carrier mobility and tolerance.

The semiconductor device of the present invention comprises a substrate, a gate structure, a semiconductor layer and a second insulating layer. The gate structure is arranged on the substrate. The semiconductor layer is arranged between the substrate and the gate structure. The semiconductor layer comprises a channel region, a first heavily doped region, a second heavily doped region and at least one lightly doped region. The channel region overlaps the gate structure in the normal direction of the substrate. The first heavily doped region and the second heavily doped region are respectively located on both sides of the channel region. At least one lightly doped region is located between the first heavily doped region and the channel region or between the second heavily doped region and the channel region to form an asymmetric doped structure on both sides of the channel region. The second insulating layer is disposed on the semiconductor layer and is located between the semiconductor layer and the gate structure.

The semiconductor device of the present invention includes a substrate, a semiconductor layer, a gate structure and an insulating layer. The semiconductor layer is arranged on the substrate, and includes a channel region. The channel region includes a first undoped region, a second undoped region and a channel doped region. The channel doped region is located between the first undoped region and the second undoped region. The gate structure is arranged on the semiconductor layer. The gate structure includes a first conductive part, a second conductive part and a third conductive part. The first conductive part overlaps the first undoped region in the normal direction of the substrate. The second conductive part overlaps the second undoped region in the normal direction of the substrate. The third conductive portion is disposed on the first conductive portion and the second conductive portion and partially overlaps the channel doping region in the normal direction of the substrate. The first conductive portion and the second conductive portion are separated from each other, and the third conductive portion electrically connects the first conductive portion and the second conductive portion. The insulating layer is disposed on the semiconductor layer and is located between the semiconductor layer and the gate structure.

Based on the above, the semiconductor device of the present invention has an asymmetric doping structure on both sides of the channel region. Compared with semiconductor devices with the same volume, the width of the second lightly doped region close to the drain can be increased, so that the drain end has more buffering to reduce the possible damage of the semiconductor device caused by the high electric field, thereby making the semiconductor device have improved carrier mobility and tolerance.

10,10a,10b,20,30,40,50,60:Semiconductor devices

100: Substrate

110: First conductive layer

112: Fourth conductive part

114: Fifth conductive part

120: First insulation layer

130:Semiconductor layer

140: Second insulation layer

152: First conductive part

152’: Initial first conductive part

152a,154a: Inner wall

152b,154b: Outer wall

152c,154c: Top

154: Second conductive part

154’: Initial second conductive part

156: Conductive extension part

160: Interlayer dielectric layer

162: The third conductive part

162a,162b: Side wall

A-A’,B-B’,C-C’,D-D’,E-E’,F-F’: section line

CH: Channel area

ch1: first undoped area

ch2: The second undoped area

ch3: channel doping area

D: Drain

G: Gate structure

H1: The first heavily doped zone

H2: Second heavy doping zone

L1: First lightly doped zone

L2: Second lightly doped zone

N: Normal direction

PR: Patterned photoresist

P1, P2: doping process

S: Source

W1: First width

W2: Second width

θ ₁ , θ ₃ : internal angle

θ ₂ , θ ₄ : External angle

FIG1 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention along the section line A-A' of FIG1.

FIG3 is a schematic cross-sectional view of a semiconductor device according to another embodiment along the section line A-A' of FIG1.

FIG4 is a schematic cross-sectional view of a semiconductor device according to another embodiment along the section line A-A' of FIG1.

FIG5 is a schematic top view of a semiconductor device according to another embodiment of the present invention.

FIG6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention along the section line B-B' of FIG5.

FIG7 is a schematic top view of a semiconductor device according to another embodiment of the present invention.

FIG8 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention along the section line C-C' of FIG7.

FIG9 is a schematic top view of a semiconductor device according to another embodiment of the present invention.

FIG10 is a schematic top view of a semiconductor device according to another embodiment of the present invention.

FIG11 is a schematic cross-sectional view of a semiconductor device according to an embodiment along the section line D-D' of FIG9 or FIG10.

FIG12 is a schematic top view of a semiconductor device according to another embodiment of the present invention.

FIG13 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention along the section line E-E' of FIG12.

FIG14 is a schematic top view of a semiconductor device according to another embodiment of the present invention.

FIG15 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention along the section line F-F' of FIG14.

Figures 16A to 16D are cross-sectional schematic diagrams of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

Figures 17A to 17C are cross-sectional schematic diagrams of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment along the section line A-A' of FIG. 1. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment along the section line A-A' of FIG. 1. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment along the section line A-A' of FIG. 1.

1 and 2, the semiconductor device 10 includes a substrate 100, a first conductive layer 110, a first insulating layer 120, a semiconductor layer 130, a gate structure G, and a second insulating layer 140. In this embodiment, the semiconductor device 10 further includes an interlayer dielectric layer 160, a source S, and a drain D.

The material of the substrate 100 may be glass, quartz, organic polymer, or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyimide (PI) or metal foil or other flexible materials.

The first conductive layer 110 is disposed on the substrate 100, and the first insulating layer 120 is disposed on the first conductive layer 110. The material of the first conductive layer 110 may be a metal or an alloy, such as copper, aluminum, silver, gold, molybdenum, alloys of the above metals, or other suitable metals or alloys.

In some embodiments, the semiconductor device 10 may further include a buffer layer (not shown), which is disposed between the substrate 100 and the first conductive layer 110. The material of the buffer layer may include silicon nitride, silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials, but the present invention is not limited thereto.

The semiconductor layer 130 is disposed on the first insulating layer 120, the second insulating layer 140 is disposed on the semiconductor layer 130, and the gate structure G is disposed on the second insulating layer 140. That is, the semiconductor layer 130 is disposed between the first insulating layer 120 and the gate structure G, and the second insulating layer 140 is disposed between the semiconductor layer 130 and the gate structure G. The materials of the first insulating layer 120 and the second insulating layer 140 may include silicon nitride, silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials, and the present invention is not limited thereto.

The semiconductor layer 130 includes a channel region CH, a first heavily doped region H1, a second heavily doped region H2, and at least one lightly doped region (e.g., a first lightly doped region L1, a second lightly doped region L2). The channel region CH overlaps the gate structure G in the normal direction N of the substrate 100. The first heavily doped region H1 and the second heavily doped region H2 are respectively located on both sides of the channel region CH. At least one lightly doped region is located between the first heavily doped region H1 and the channel region CH or between the second heavily doped region H2 and the channel region CH to form an asymmetric doping structure on both sides of the channel region CH. Herein, the asymmetric doping structure means that the semiconductor layer 130 has different ranges or degrees of doping on both sides of the channel region CH. For example, in the present embodiment, as shown in FIG. 2 , the semiconductor layer 130 includes a first lightly doped region L1 having a first width W1 on one side of the channel region CH, and the semiconductor layer 130 includes a second lightly doped region L2 having a second width W2 on the other side of the channel region CH, wherein the first width W1 is smaller than the second width W2, that is, the first lightly doped region L1 is asymmetric with the second lightly doped region L2. In other embodiments, the semiconductor layer 130 may include only a heavily doped region (e.g., the first heavily doped region H1) without a lightly doped region on one side of the channel region CH, and the semiconductor layer 130 may include a lightly doped region (e.g., the second lightly doped region L2) and a heavily doped region (e.g., the second heavily doped region H2) on the other side of the channel region CH, so that the two sides of the channel region CH have an asymmetric doping structure.

In this embodiment, the material of the semiconductor layer 130 may include polycrystalline silicon. In other embodiments, the material of the semiconductor layer 130 may also include amorphous silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material (for example: indium zinc oxide, indium gallium zinc oxide or other suitable materials) or a combination thereof, but the present invention is not limited thereto.

In some embodiments, the channel region CH includes a first undoped region ch1, a second undoped region ch2, and a channel doped region ch3, and the channel doped region ch3 is located between the first undoped region ch1 and the second undoped region ch2.

The first heavily doped region H1, the second heavily doped region H2, the first lightly doped region L1, the second lightly doped region L2 and the channel doped region ch3 of the semiconductor layer 130 may be semiconductors doped with dopant. For example, the dopant may be a group V element, such as phosphorus, arsenic, etc., to form an N-type doped region, or the dopant may be a group III element, such as boron, aluminum, etc., to form a P-type doped region. The present invention does not limit the type of doping, which may be adjusted according to actual needs.

In some embodiments, the first conductive layer 110 may overlap the channel region CH, the first lightly doped region L1, and the second lightly doped region L2 in the normal direction N of the substrate 100. In this way, the first conductive layer 110 can be used as a shielding layer to reduce the light leakage phenomenon of the semiconductor device. In addition, since the first conductive layer 110 overlaps with the first lightly doped region L1 and the second lightly doped region L2 in the normal direction N of the substrate 100, the kink effect at the drain end can be reduced, thereby improving the reliability of the semiconductor device 10.

Although FIG. 2 shows that the first conductive layer 110 overlaps the first lightly doped region L1 and the second lightly doped region L2 in the normal direction N of the substrate 100, it is not intended to limit the present invention. The first conductive layer 110 may be selectively overlapped with the first lightly doped region L1 or the second lightly doped region L2 in the normal direction N of the substrate 100 based on actual needs.

In some embodiments, the orthographic projection area of the first conductive layer 110 on the substrate 100 is larger than the orthographic projection area of the gate structure G on the substrate 100.

The gate structure G includes a first conductive portion 152, a second conductive portion 154, and a third conductive portion 162. The first conductive portion 152 and the second conductive portion 154 are disposed on the second insulating layer 140 and are separated from each other. In some embodiments, the first conductive portion 152 is parallel to the second conductive portion 154, that is, the first conductive portion 152 and the second conductive portion 154 have the same extension direction. In this embodiment, the width of the first conductive portion 152 is different from the width of the second conductive portion 154, but the present invention is not limited thereto. In other embodiments, the width of the first conductive portion 152 and the width of the second conductive portion 154 may be the same. The third conductive portion 162 is disposed on the first conductive portion 152 and the second conductive portion 154 to electrically connect the first conductive portion 152 and the second conductive portion 154.

The material of the gate structure G may be a metal or alloy, such as copper, aluminum, silver, gold, molybdenum, alloys of the above metals, or other metals or alloys that are easy to etch. In some embodiments, the material of the third conductive portion 162 may be the same as or different from the material of the first conductive portion 152 and the second conductive portion 154.

In some embodiments, the first conductive portion 152 overlaps the first undoped region ch1 in the normal direction N of the substrate 100, and the second conductive portion 154 overlaps the second undoped region ch2 in the normal direction N of the substrate 100. The third conductive portion 162 overlaps the channel region CH in the normal direction N of the substrate 100, that is, the third conductive portion 162 overlaps the first undoped region ch1, the second undoped region ch2 and the channel doped region ch3 in the normal direction N of the substrate 100. It can be seen that the gate structure G does not overlap with the first heavily doped region H1, the second heavily doped region H2, the first lightly doped region L1 and the second lightly doped region L2 in the normal direction N of the substrate 100.

In some embodiments, the shortest distance between the first conductive portion 152 and the second conductive portion 154 may be less than 2 μm. On the other hand, the width of the channel doping region ch3 may be less than 2 μm.

In some embodiments, the first conductive portion 152 has an inner sidewall 152a, an outer sidewall 152b, and a top surface 152c connecting the inner sidewall 152a and the outer sidewall 152b. The second conductive portion 154 has an inner sidewall 154a, an outer sidewall 154b, and a top surface 154c connecting the inner sidewall 154a and the outer sidewall 154b. The third conductive portion 162 covers the top surface 152c and the inner sidewall 152a of the first conductive portion 152 and the top surface 154c and the inner sidewall 154a of the second conductive portion 154.

In some embodiments, the sidewall 162a of the third conductive portion 162 is aligned with the outer sidewall 152b of the first conductive portion 152, and the sidewall 162b of the third conductive portion 162 is aligned with the outer sidewall 154b of the second conductive portion 154, but the present invention is not limited thereto. In other embodiments, the sidewall 162a or the sidewall 162b of the third conductive portion 162 may be retracted to the outer sidewall 152b of the first conductive portion 152 or the outer sidewall 154b of the second conductive portion 154. In yet other embodiments, one of the sidewalls 162a or the sidewall 162b of the third conductive portion 162 may cover the outer sidewall 152b of the first conductive portion 152 or the outer sidewall 154b of the second conductive portion 154.

In some embodiments, the first conductive portion 152 and the second conductive portion 154 are asymmetric structures. For example, the inner angle _θ1 between the inner sidewall 152a of the first conductive portion 152 and the second insulating layer 140 is different from the outer angle _θ2 between the outer sidewall 152b of the first conductive portion 152 and the second insulating layer 140. The inner angle _θ3 between the inner sidewall 154a of the second conductive portion 154 and the second insulating layer 140 is different from the outer angle _θ4 between the outer sidewall 154b of the second conductive portion 154 and the second insulating layer 140. In some embodiments, the inner angle _θ1 of the first conductive portion 152 is greater than the outer angle _θ2 of the first conductive portion 152, for example, the inner angle _θ1 of the first conductive portion 152 is greater than the outer angle θ2 of the first conductive portion ₁₅₂ by 10 degrees or more, but the present invention is not limited thereto. In some embodiments, the inner angle _θ3 of the second conductive portion 154 is greater than the outer angle _θ4 of the second conductive portion 154, for example, the inner angle _θ3 of the second conductive portion 154 is greater than the outer angle _θ4 of the second conductive portion 154 by 10 degrees or more, but the present invention is not limited thereto. However, in other embodiments, the first conductive portion 152 and the second conductive portion 154 may be symmetrical structures, that is, the inner angle _θ1 of the first conductive portion 152 is the same as the outer angle _θ2 , and the inner angle _θ3 of the second conductive portion 154 is the same as the outer angle _θ4 , but the present invention is not limited thereto.

In some embodiments, the angle of the outer angle _θ2 of the first conductive portion 152 may be substantially the same as the angle of the outer angle _θ4 of the second conductive portion 154, that is, the angles of the opposite side walls of the gate structure G and the second insulating layer 140 are substantially the same, but the present invention is not limited thereto. In other embodiments, the angle of the outer angle _θ2 of the first conductive portion 152 may be different from the angle of the outer angle _θ4 of the second conductive portion 154. In some embodiments, the angle of the inner angle _θ1 of the first conductive portion 152 may be substantially the same as the angle of the inner angle _θ3 of the second conductive portion 154, but the present invention is not limited thereto. In other embodiments, the angle of the inner angle _θ1 of the first conductive portion 152 may be different from the angle of the inner angle _θ3 of the second conductive portion 154.

In some embodiments, the first conductive layer 110 can be electrically connected to the gate structure G or the semiconductor layer 130 through a via (not shown), that is, the first conductive layer 110 can serve as another gate to jointly control the semiconductor device 10, but the present invention is not limited thereto. In other embodiments, the first conductive layer 110 can be floating.

The interlayer dielectric layer 160 is disposed on the second insulating layer 140 and covers the gate structure G. The source S and the drain D are disposed on the interlayer dielectric layer 160 and penetrate the interlayer dielectric layer 160 and the second insulating layer 140 to be electrically connected to the first heavily doped region H1 and the second heavily doped region H2, respectively. The material of the interlayer dielectric layer 160 may include acrylic, silicone, polyimide, epoxy or other suitable materials, but the present invention is not limited thereto. The interlayer dielectric layer 160 may have a single-layer structure or a multi-layer structure, but the present invention is not limited thereto. The source S and drain D may be made of metal or alloy, such as copper, aluminum, silver, gold, molybdenum, alloys of the above metals or other suitable metals or alloys, but the present invention is not limited thereto.

In some embodiments, the second width W2 of the second lightly doped region L2 near the drain D is greater than the first width W1 of the first lightly doped region L1 near the source S. Since the semiconductor device 10 has an asymmetric doping structure, compared with a semiconductor device with the same volume, the width of the second lightly doped region L2 near the drain D can be increased, so that the drain D end has more buffering to reduce possible damage to the semiconductor device 10 caused by a high electric field.

FIG3 is a schematic cross-sectional view of a semiconductor device of another embodiment along the section line A-A' of FIG1. It must be noted that the embodiment of FIG3 uses the component numbers and partial contents of the embodiments of FIG1 and FIG2, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can be referred to the aforementioned embodiment, which will not be elaborated here.

3 , the main difference between the semiconductor device 10a and the semiconductor device 10 is that the third conductive portion 162 of the gate structure G of the semiconductor device 10a covers the outer wall 152b of the first conductive portion 152, and there is no lightly doped region between the first heavily doped region H1 and the first undoped region ch1 of the semiconductor layer 130. In other words, the first heavily doped region H1 is adjacent to the first undoped region ch1. The third conductive portion 162 of the gate structure G partially overlaps the first heavily doped region H1 in the normal direction N of the substrate 100. Since the semiconductor layer 130 includes only the first heavily doped region H1 on one side of the channel region CH but not the lightly doped region, and the semiconductor layer 130 includes the second lightly doped region L2 and the second heavily doped region H2 on the other side of the channel region CH, the two sides of the channel region CH have an asymmetric doping structure. Compared with semiconductor devices with the same volume, the width of the second lightly doped region L2 close to the drain D can be increased, so that the drain D end has more buffering to reduce possible damage to the semiconductor device 10a caused by high electric fields.

FIG. 3 schematically shows that the side wall 162b of the third conductive portion 162 is aligned with the outer side wall 154b of the second conductive portion 154, but it is not intended to limit the present invention. In other embodiments, the side wall 162b of the third conductive portion 162 may be retracted into the outer side wall 154b of the second conductive portion 154.

FIG4 is a schematic cross-sectional view of a semiconductor device of another embodiment along the section line A-A' of FIG1. It must be noted that the embodiment of FIG4 uses the component numbers and partial contents of the embodiments of FIG1 and FIG2, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

4 , the main difference between the semiconductor device 10b and the semiconductor device 10 is that the side walls 162a and 162b of the third conductive portion 162 of the gate structure G of the semiconductor device 10b are respectively retracted from the outer side walls 152b of the first conductive portion 152 and the outer side walls 154b of the second conductive portion 154. In other words, a portion of the top surface 152c of the first conductive portion 152 is not covered by the third conductive portion 162, and a portion of the top surface 154c of the second conductive portion 154 is not covered by the third conductive portion 162. FIG. 4 schematically shows that the side walls 162a and 162b of the third conductive portion 162 are respectively retracted into the outer side wall 152b of the first conductive portion 152 and the outer side wall 154b of the second conductive portion 154, but this is not intended to limit the present invention. The third conductive portion 162 may have only one side of the side wall retracted, while the other side of the side wall is aligned with or covers the outer side wall of the corresponding first conductive portion 152 or second conductive portion 154.

FIG5 is a schematic top view of a semiconductor device according to another embodiment of the present invention. FIG6 is a schematic cross-sectional view of a semiconductor device according to an embodiment along the section line B-B' of FIG5. It must be noted that the embodiments of FIG5 and FIG6 use the component numbers and partial contents of the embodiments of FIG1 and FIG2, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

5 and 6 , the main difference between the semiconductor device 20 and the semiconductor device 10 is that the first conductive layer 110 of the semiconductor device 20 includes a fourth conductive portion 112 and a fifth conductive portion 114 separated from each other. The fourth conductive portion 112 corresponds to the first conductive portion 152, and the fifth conductive portion 114 corresponds to the second conductive portion 154. In this embodiment, the fourth conductive portion 112 overlaps with the first undoped region ch1 and the first lightly doped region L1 in the normal direction N of the substrate 100, and the fifth conductive portion 114 overlaps with the second undoped region ch2 and the second lightly doped region L2 in the normal direction N of the substrate 100, but the present invention is not limited thereto, as long as the first conductive layer 110 overlaps with the first undoped region ch1 and the second undoped region ch2 in the normal direction N of the substrate 100 and overlaps with at least one of the first lightly doped region L1 and the second lightly doped region L2.

FIG7 is a schematic diagram of a semiconductor device according to another embodiment of the present invention from above. FIG8 is a schematic diagram of a semiconductor device according to an embodiment along the section line C-C' of FIG7 from below. FIG9 is a schematic diagram of a semiconductor device according to another embodiment of the present invention from above, wherein the schematic diagram of the section along the section line C-C' of FIG9 is similar to FIG8 and can be understood with reference to FIG8. It must be noted that the embodiments of FIG7 to FIG9 use the component numbers and partial contents of the embodiments of FIG1 and FIG2, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the aforementioned embodiments and will not be repeated here.

7 and 8 , the main difference between the semiconductor device 30 and the semiconductor device 10 is that the gate structure G of the semiconductor device 30 includes a first conductive portion 152, a second conductive portion 154, and a conductive extension portion 156. The first conductive portion 152 and the second conductive portion 154 are disposed on the second insulating layer 140 and are separated from each other. The width of the first conductive portion 152 and the width of the second conductive portion 154 can be the same or different, and the present invention is not limited thereto. The conductive extension portion 156 is disposed on the second insulating layer 140 and connects the first conductive portion 152 and the second conductive portion 154. The first conductive portion 152, the second conductive portion 154 and the conductive extension portion 156 are the same film layer, and the material of the conductive extension portion 156 can be the same as that of the first conductive portion 152 and the second conductive portion 154. In FIG7, the gate structure G is in a U shape. The conductive extension portion 156 does not overlap with the semiconductor layer 130 in the normal direction N of the substrate 100, and the gate structure G does not overlap with the channel doping region ch3 in the normal direction N of the substrate 100.

Although FIG8 shows that the two sides of the channel region CH have asymmetric first lightly doped region L1 and second lightly doped region L2, it is not intended to limit the present invention. The two sides of the channel region CH in FIG8 can also be similar to the embodiment of FIG3, where only one side has a lightly doped region adjacent to the channel region, and the other side has a heavily doped region adjacent to the channel region.

Referring to FIG. 9 , the main difference between the semiconductor device 30a and the semiconductor device 30 is that the gate structure G of the semiconductor device 30a includes a first conductive portion 152 and a second conductive portion 154, but does not include a conductive extension portion. In other words, the gate structure G of the semiconductor device 30a has two first conductive portions 152 and second conductive portions 154 that are separated from each other and parallel.

FIG10 is a schematic top view of a semiconductor device according to another embodiment of the present invention. FIG11 is a schematic cross-sectional view of a semiconductor device according to an embodiment along the section line D-D' of FIG10. It must be noted that the embodiments of FIG10 and FIG11 use the component numbers and partial contents of the embodiments of FIG5 and FIG7, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

10 and 11 , the main difference between the semiconductor device 40 and the semiconductor device 30 is that the first conductive layer 110 of the semiconductor device 40 includes a fourth conductive portion 112 and a fifth conductive portion 114 separated from each other. The fourth conductive portion 112 corresponds to the first conductive portion 152 , and the fifth conductive portion 114 corresponds to the second conductive portion 154 . In this embodiment, the fourth conductive portion 112 overlaps with the first undoped region ch1 and the first lightly doped region L1 in the normal direction N of the substrate 100, and the fifth conductive portion 114 overlaps with the second undoped region ch2 and the second lightly doped region L2 in the normal direction N of the substrate 100, but the present invention is not limited thereto, as long as the first conductive layer 110 overlaps with the first undoped region ch1 and the second undoped region ch2 in the normal direction N of the substrate 100 and overlaps with at least one of the first lightly doped region L1 and the second lightly doped region L2.

Although FIG. 10 shows that the gate structure G includes the first conductive portion 152, the second conductive portion 154 and the conductive extension portion 156, it is not intended to limit the present invention. The gate structure G may also include only the first conductive portion 152 and the second conductive portion 154 similar to the embodiment of FIG. 9.

FIG12 is a schematic top view of a semiconductor device according to another embodiment of the present invention. FIG13 is a schematic cross-sectional view of a semiconductor device according to an embodiment along the section line E-E' of FIG12. It must be noted that the embodiments of FIG12 and FIG13 use the component numbers and partial contents of the embodiments of FIG1 and FIG2, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

Please refer to FIG. 12 and FIG. 13 . The main difference between the semiconductor device 50 and the semiconductor device 10 is that the semiconductor device 50 includes a substrate 100, a semiconductor layer 130, a gate structure G, a second insulating layer 140, an interlayer dielectric layer 160, a source S, and a drain D, but does not include the first conductive layer 110 and the first insulating layer 120 of FIG. 2 . FIG. 13 only schematically illustrates the semiconductor device 50 , and its gate structure G and semiconductor layer 130 can be adjusted according to actual needs with reference to the aforementioned embodiments. In some embodiments, the semiconductor device 50 may further include a buffer layer (not shown) disposed between the substrate 100 and the semiconductor layer 130 . The material of the buffer layer may include silicon nitride, silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials, but the present invention is not limited thereto.

FIG. 14 is a schematic top view of a semiconductor device according to another embodiment of the present invention. FIG. 15 is a schematic cross-sectional view of a semiconductor device according to an embodiment along the section line F-F' of FIG. 14. It must be noted that the embodiments of FIG. 14 and FIG. 15 use the component numbers and partial contents of the embodiments of FIG. 7 and FIG. 8, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

14 and 15 , the main difference between the semiconductor device 60 and the semiconductor device 30 is that the semiconductor device 60 includes a substrate 100, a semiconductor layer 130, a gate structure G, a second insulating layer 140, an interlayer dielectric layer 160, a source S, and a drain D, but does not include the first conductive layer 110 and the first insulating layer 120 of FIG. 8 . FIG. 15 only schematically illustrates the semiconductor device 60, and its gate structure G and the semiconductor layer 130 can be adjusted according to the above-mentioned embodiments according to actual needs. In some embodiments, the semiconductor device 60 may further include a buffer layer (not shown) disposed between the substrate 100 and the semiconductor layer 130. The material of the buffer layer may include silicon nitride, silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials, but the present invention is not limited thereto.

Figures 16A to 16D are cross-sectional schematic diagrams of a manufacturing process of a semiconductor device according to an embodiment of the present invention. It must be noted that the embodiments of Figures 16A and 16D use the component numbers and partial contents of the embodiment of Figure 2, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the aforementioned embodiments, which will not be elaborated here.

Referring to FIG. 16A , a substrate 100 is provided, a first conductive layer 110 is formed on the substrate 100, and then a first insulating layer 120 is formed on the substrate 100 and covers the first conductive layer 110. Thereafter, a semiconductor layer 130 and a second insulating layer 140 are sequentially formed on the first insulating layer 120. In some embodiments, before forming the first conductive layer 110, a buffer layer (not shown) may be formed on the substrate 100.

16B, an initial first conductive portion 152' and an initial second conductive portion 154' are formed on the second insulating layer 140. For example, the initial first conductive portion 152' and the initial second conductive portion 154' can be formed in the same process by photolithography. In this embodiment, the initial first conductive portion 152' and the initial second conductive portion 154' are not connected, and the shortest distance between the two can be less than 2μm. Then, the semiconductor layer 130 is doped with the initial first conductive portion 152' and the initial second conductive portion 154' as masks, so that the first heavily doped region H1, the channel doped region ch3 and the second heavily doped region H2 are formed in the portion that does not overlap with the initial first conductive portion 152' and the initial second conductive portion 154' in the normal direction N of the substrate 100.

Referring to FIG. 16C , a gate structure G including a first conductive portion 152, a second conductive portion 154, and a third conductive portion 162 is formed. For example, a conductive material layer (not shown) may be first formed on the second insulating layer 140, the initial first conductive portion 152', and the initial second conductive portion 154'. Thereafter, a patterned photoresist PR is formed on the conductive material layer, and then the patterned photoresist PR is used as a mask to form the third conductive portion 162 through a photolithography process. The patterned photoresist PR may define the position of the third conductive portion 162, and further define the range of the lightly doped region to be formed subsequently. In the present embodiment, the patterned photoresist PR overlaps more of the first conductive portion 152 than the second conductive portion 154 in the normal direction N of the substrate 100, so as to subsequently form the first lightly doped region L1 and the second lightly doped region L2 with different widths (shown in FIG. 16D ), but the present invention is not limited thereto, and the position of the patterned photoresist PR can be adjusted according to actual needs. In other embodiments, the patterned photoresist PR can completely overlap the initial first conductive portion 152' and partially overlap the initial second conductive portion 154' in the normal direction N of the substrate 100, so as to subsequently form a semiconductor layer 130 similar to FIG. 3 including only a lightly doped region. In some embodiments, during the process of etching the conductive material layer to form the third conductive portion 162, the initial first conductive portion 152' and the initial second conductive portion 154' may be etched simultaneously to form the first conductive portion 152 and the second conductive portion 154, but the present invention is not limited thereto. Since the first conductive portion 152 and the second conductive portion 154 are formed by two etchings, the width of the gate structure G can be fine-tuned, and the inner angle _θ1 of the first conductive portion 152 can be different from the outer angle _θ2 of the first conductive portion 152, and the inner angle _θ3 of the second conductive portion 154 can be different from the outer angle _θ4 of the second conductive portion 154.

In other embodiments, the patterned photoresist PR and the third conductive portion 162 may be used as a mask to etch the initial first conductive portion 152' and the initial second conductive portion 154' to form the first conductive portion 152 and the second conductive portion 154.

In some embodiments, after the first conductive portion 152 and the second conductive portion 154 are substantially formed, the patterned photoresist PR can be etched simultaneously with the first conductive portion 152, the second conductive portion 154 and the third conductive portion 162 by using a suitable etching gas to adjust the morphology of the gate structure G.

Please refer to FIG. 16D , the patterned photoresist PR is removed, and then the gate structure G is used as a mask to perform a doping process P2 on the semiconductor layer 130, so that the undoped portion that does not overlap with the gate structure G in the normal direction N of the substrate 100 forms a first lightly doped region L1 and a second lightly doped region L2. Since the portion where the semiconductor layer 130 overlaps with the first conductive portion 152 and the second conductive portion 154 in the normal direction N of the substrate 100 is not doped by the doping processes P1 and P2, the first undoped region ch1 and the second undoped region ch2 are formed.

Afterwards, referring to FIG. 2 , an interlayer dielectric layer 160 is formed on the second insulating layer 140 and covers the gate structure G. Subsequently, a through hole (not shown) is formed through the interlayer dielectric layer 160 and the second insulating layer 140 to expose a portion of the surface of the first heavily doped region H1 and the surface of the second heavily doped region H2, respectively. Afterwards, a conductive material layer (not shown) is formed on the interlayer dielectric layer 160 and in the through hole, and then the conductive material layer is patterned to form a source S and a drain D.

After the above process, the production of the semiconductor device 10 can be roughly completed.

Figures 17A to 17C are cross-sectional schematic diagrams of a manufacturing process of a semiconductor device according to an embodiment of the present invention. It must be noted that the embodiments of Figures 17A and 17C use the component numbers and partial contents of the embodiments of Figures 8 and 16A to 16D, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the aforementioned embodiments, which will not be elaborated here.

FIG. 17A may be a process that continues the process of FIG. 16B. In some embodiments, during the process of forming the initial first conductive portion 152' and the initial second conductive portion 154' on the second insulating layer 140, the conductive extension structure 156 (marked in FIG. 7) may be formed simultaneously.

Referring to FIG. 17A , a patterned photoresist PR is formed on the second insulating layer 140, the initial first conductive portion 152′, and the initial second conductive portion 154′. The patterned photoresist PR can define the positions of the first conductive portion and the second conductive portion to be formed subsequently, and further determine the doping range of the first lightly doped region or the second lightly doped region to be formed subsequently. In the present embodiment, the patterned photoresist PR overlaps more initial first conductive portion 152′ than the initial second conductive portion 154′ in the normal direction N of the substrate 100, so as to subsequently form the first lightly doped region L1 and the second lightly doped region L2 with different widths (shown in FIG. 17C ), but the present invention is not limited thereto, and the position of the patterned photoresist PR can be adjusted according to actual needs. In other embodiments, the patterned photoresist PR can completely overlap the initial first conductive portion 152' and partially overlap the initial second conductive portion 154' in the normal direction N of the substrate 100, so as to subsequently form a semiconductor layer 130 similar to FIG. 3 including only a lightly doped region.

Referring to FIG. 17B , the initial first conductive portion 152' and the initial second conductive portion 154' are etched using the patterned photoresist PR as a mask to form a gate structure G including the first conductive portion 152 and the second conductive portion 154. In some embodiments, after the first conductive portion 152 and the second conductive portion 154 are substantially formed, the patterned photoresist PR can be etched simultaneously with the first conductive portion 152 and the second conductive portion 154 by using a suitable etching gas to adjust the morphology of the gate structure G.

Please refer to FIG. 17C , the patterned photoresist PR is removed, and then the semiconductor layer 130 is doped with the first conductive portion 152 and the second conductive portion 154 as masks, so that the undoped portion that does not overlap with the first conductive portion 152 and the second conductive portion 154 in the normal direction N of the substrate 100 forms the first lightly doped region L1 and the second lightly doped region L2. Since the portion of the semiconductor layer 130 that overlaps with the first conductive portion 152 and the second conductive portion 154 in the normal direction N of the substrate 100 is not doped by the doping processes P1 and P2, the first undoped region ch1 and the second undoped region ch2 are formed.

Afterwards, referring to FIG. 8 , an interlayer dielectric layer 160 is formed on the second insulating layer 140 and covers the first conductive portion 152 and the second conductive portion 154. Subsequently, a through hole (not shown) is formed through the interlayer dielectric layer 160 and the second insulating layer 140 to expose a portion of the surface of the first heavily doped region H1 and the surface of the second heavily doped region H2, respectively. Afterwards, a conductive material layer (not shown) is formed on the interlayer dielectric layer 160 and in the through hole, and the conductive material layer is patterned to form a source S and a drain D.

After the above process, the production of the semiconductor device 30 can be roughly completed.

In summary, the semiconductor device of the present invention has an asymmetric doping structure on both sides of the channel region. Compared with semiconductor devices of the same volume, the width of the second lightly doped region close to the drain can be increased, so that the drain end has more buffering to reduce possible damage to the semiconductor device caused by high electric fields.

10: Semiconductor devices

100: Substrate

110: First conductive layer

120: First insulation layer

130:Semiconductor layer

140: Second insulation layer

152: First conductive part

152a,154a: Inner wall

152b,154b: Outer wall

152c,154c: Top

154: Second conductive part

160: Interlayer dielectric layer

162: The third conductive part

162a,162b: Side wall

A-A’: section line

CH: Channel area

ch1: first undoped area

ch2: The second undoped area

ch3: channel doping area

D: Drain

G: Gate structure

H1: The first heavily doped zone

H2: Second heavy doping zone

L1: First lightly doped zone

L2: Second lightly doped zone

N: Normal direction

S: Source

W1: First width

W2: Second width

θ ₁ , θ ₃ : internal angle

θ ₂ , θ ₄ : External angle

Claims (12)

A semiconductor device comprises: a substrate; a gate structure disposed on the substrate, wherein the gate structure comprises a first conductive part and a second conductive part separated from each other, a width of the first conductive part being different from a width of the second conductive part; a semiconductor layer disposed between the substrate and the gate structure, wherein the semiconductor layer comprises: a channel region overlapping the gate structure in a normal direction of the substrate, wherein the channel region comprises a first undoped region overlapping with the first conductive part in the normal direction of the substrate, and a second undoped region overlapping with the first conductive part in the normal direction of the substrate. A second undoped region with two conductive parts overlapping in the normal direction of the substrate, and a channel doped region located between the first undoped region and the second undoped region; a first heavily doped region and a second heavily doped region, respectively located on both sides of the channel region; and at least one lightly doped region, located between the first heavily doped region and the channel region or between the second heavily doped region and the channel region, to form an asymmetric doped structure on both sides of the channel region; and a second insulating layer, disposed on the semiconductor layer and located between the semiconductor layer and the gate structure. A semiconductor device as described in claim 1, wherein the gate structure further includes: a third conductive portion, disposed on the first conductive portion and the second conductive portion, to electrically connect the first conductive portion and the second conductive portion. A semiconductor device as described in claim 2, wherein the channel doping region and the third conductive portion partially overlap in the normal direction of the substrate. A semiconductor device as described in claim 1, wherein the gate structure further comprises: a conductive extension portion disposed on the second insulating layer and connecting the first conductive portion and the second conductive portion, wherein the conductive extension portion does not overlap with the semiconductor layer in the normal direction of the substrate. The semiconductor device as described in claim 1 further comprises: a first conductive layer disposed on the substrate; and a first insulating layer disposed on the first conductive layer, wherein the orthographic projection area of the first conductive layer on the substrate is larger than the orthographic projection area of the gate structure on the substrate. A semiconductor device as described in claim 5, wherein the first conductive layer partially overlaps the at least one lightly doped region in the normal direction of the substrate. A semiconductor device as described in claim 5, wherein the at least one lightly doped region comprises: a first lightly doped region located between the first heavily doped region and the channel region; and a second lightly doped region located between the second heavily doped region and the channel region, wherein the width of the first lightly doped region is different from the width of the second lightly doped region. The semiconductor device as described in claim 7 further comprises: a source electrically connected to the first heavily doped region; and a drain electrically connected to the second heavily doped region, wherein the width of the second lightly doped region is greater than the width of the first lightly doped region. A semiconductor device as described in claim 7, wherein: the first conductive layer includes a fourth conductive portion and a fifth conductive portion separated from each other, the fourth conductive portion corresponds to the first conductive portion and overlaps with the first conductive portion and the first lightly doped region in the normal direction of the substrate, and the fifth conductive portion corresponds to the second conductive portion and overlaps with the second conductive portion and the second lightly doped region in the normal direction of the substrate. A semiconductor device as described in claim 1, wherein an outer angle of the first conductive portion is different from an inner angle of the first conductive portion. A semiconductor device as described in claim 10, wherein the angle of the inner angle of the first conductive portion is greater than the angle of the outer angle of the first conductive portion. A semiconductor device comprises: a substrate; a semiconductor layer disposed on the substrate, wherein the semiconductor layer comprises a channel region, the channel region comprises: a first undoped region; a second undoped region; and a channel doped region located between the first undoped region and the second undoped region; a gate structure disposed on the semiconductor layer, wherein the gate structure comprises: a first conductive portion overlapping the first undoped region in a normal direction of the substrate; a second conductive portion , overlapping the second undoped region in the normal direction of the substrate; and a third conductive portion, disposed on the first conductive portion and the second conductive portion and partially overlapping the channel doped region in the normal direction of the substrate, wherein the first conductive portion and the second conductive portion are separated from each other, and the third conductive portion electrically connects the first conductive portion and the second conductive portion; and an insulating layer, disposed on the semiconductor layer and located between the semiconductor layer and the gate structure.

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