TWI830291B - Circuit board with embedded capacitance and manufacturing method thereof - Google Patents
Circuit board with embedded capacitance and manufacturing method thereof Download PDFInfo
- Publication number
- TWI830291B TWI830291B TW111126763A TW111126763A TWI830291B TW I830291 B TWI830291 B TW I830291B TW 111126763 A TW111126763 A TW 111126763A TW 111126763 A TW111126763 A TW 111126763A TW I830291 B TWI830291 B TW I830291B
- Authority
- TW
- Taiwan
- Prior art keywords
- conductive electrodes
- substrate
- dielectric space
- capacitor
- opening
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 128
- 239000010410 layer Substances 0.000 claims description 178
- 239000003990 capacitor Substances 0.000 claims description 134
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 57
- 239000011889 copper foil Substances 0.000 claims description 54
- 239000000463 material Substances 0.000 claims description 54
- 239000010408 film Substances 0.000 claims description 41
- 239000000853 adhesive Substances 0.000 claims description 40
- 230000001070 adhesive effect Effects 0.000 claims description 40
- 239000012790 adhesive layer Substances 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 13
- 238000005452 bending Methods 0.000 claims description 4
- 239000013039 cover film Substances 0.000 claims description 2
- 239000000945 filler Substances 0.000 claims 2
- 238000000034 method Methods 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
本申請涉及電路板領域,尤其涉及一種內嵌電容之電路板及其製造方法。 The present application relates to the field of circuit boards, and in particular to a circuit board with built-in capacitors and a manufacturing method thereof.
將無源器件(如電阻、電容等)埋嵌於印製電路板之內部既可以減小印製電路板之面積、降低印製電路板之重量,亦可以提升電子產品之可靠性。 Embedding passive components (such as resistors, capacitors, etc.) inside the printed circuit board can not only reduce the area and weight of the printed circuit board, but also improve the reliability of electronic products.
一般情況下,於印製電路板中埋嵌電容之方式是將習知之離散式電容埋入到印製電路板之基板中以實現無源器件之小型化,其結構類似與平行板電容器,兩側是金屬層,中間是高介電常數(DK),低介質損耗之介電層。 Generally, the way to embed capacitors in printed circuit boards is to embed conventional discrete capacitors into the substrate of the printed circuit board to achieve miniaturization of passive devices. Its structure is similar to that of parallel plate capacitors. The side is a metal layer, and the middle is a dielectric layer with high dielectric constant (DK) and low dielectric loss.
然而,於整面電路板中,並非所有區域均需要高介電常數(DK),低介質損耗之介電層,整板面使用該介電層材料不僅會造成資源浪費,同時還不利於印製電路板之厚度降低。 However, in the entire circuit board, not all areas require a high dielectric constant (DK) and low dielectric loss dielectric layer. Using this dielectric layer material on the entire board will not only cause a waste of resources, but is also not conducive to printing. The thickness of the circuit board is reduced.
為解決背景技術中之問題,本申請還提供一種內嵌電容之電路板之製造方法。 In order to solve the problems in the background technology, the present application also provides a method for manufacturing a circuit board with embedded capacitors.
另外,本申請還提供一種內嵌電容之電路板。 In addition, this application also provides a circuit board with built-in capacitors.
一種內嵌電容之電路板之製造方法,包括步驟:提供一基板,所述基板包括基板本體及待移除體,所述待移除體設於所述基板本體之一側,所述待移除體包括相對設置之內表面與外表面;於所述基板本體上設置線路結構,所述線路結構包括結構本體及多個導電極,多個所述導電極相對間隔設於所述結構本體之一側,所述結構本體貫穿設有多個開口,所述待移除體穿過所述開口,所述導電極設於所述內表面與所述外表面;以及移除所述待移除體以形成介電空間,獲得內嵌電容之所述電路板,其中,所述電容包括相對間隔設置之兩個導電極以及相對間隔設置之兩個導電極之間之介電空間。 A method of manufacturing a circuit board with embedded capacitors, including the steps of: providing a substrate, the substrate includes a substrate body and a body to be removed, the body to be removed is provided on one side of the substrate body, the body to be removed The removal body includes an inner surface and an outer surface arranged oppositely; a circuit structure is provided on the substrate body, the circuit structure includes a structural body and a plurality of conductive electrodes, and a plurality of the conductive electrodes are relatively spaced apart from the structural body. On one side, the structural body is provided with a plurality of openings, the object to be removed passes through the openings, and the conductive electrode is provided on the inner surface and the outer surface; and remove the to-be-removed object The body is formed to form a dielectric space to obtain the circuit board with embedded capacitor, wherein the capacitor includes two conductive electrodes arranged at opposite intervals and a dielectric space between the two conductive electrodes arranged at opposite intervals.
一種內嵌電容之電路板之製造方法,包括步驟:提供一第一基板,所述第一基板包括第一基板本體與多個外側待移除體,所述外側待移除體設於所述第一基板本體之一側,每一所述外側待移除體包括一內表面及與所述內表面相對之一外表面;於所述第一基板上設置第一線路結構,所述第一線路結構包括第一結構本體及多個外側導電極,兩個所述外側導電極相對間隔設於所述第一結構本體,所述第一結構本體貫穿設有多個開口,所述開口設於兩個所述外側導電極之間,所述外側待移除體穿過所述開口,一個所述外側導電極設於一個所述內表面,另一個所述外側導電極設於另一個所述外表面;於所述第一線路結構設置第一覆蓋體,所述第一覆蓋體覆蓋所述外側待移除體與所述外側導電極。 A method of manufacturing a circuit board with embedded capacitors, including the steps of: providing a first substrate, the first substrate including a first substrate body and a plurality of outer bodies to be removed, the outer bodies to be removed are provided on the On one side of the first substrate body, each outer body to be removed includes an inner surface and an outer surface opposite to the inner surface; a first circuit structure is provided on the first substrate, and the first The circuit structure includes a first structural body and a plurality of outer conductive electrodes. The two outer conductive electrodes are relatively spaced apart from the first structural body. The first structural body is provided with a plurality of openings, and the openings are provided in Between the two outer conductive electrodes, the outer body to be removed passes through the opening, one of the outer conductive electrodes is provided on one of the inner surfaces, and the other outer conductive electrode is provided on the other of the inner surfaces. Outer surface: A first covering body is provided on the first circuit structure, and the first covering body covers the outer body to be removed and the outer conductive electrode.
移除所述外側待移除體以形成外側介電空間,獲得內嵌電容之所述電容板,其中,所述電容包括所述外側導電極及所述外側介電空間。 The outer body to be removed is removed to form an outer dielectric space, and the capacitor plate with embedded capacitor is obtained, wherein the capacitor includes the outer conductive electrode and the outer dielectric space.
進一步地,所述外側待移除體包括第一外側待移除體與第二外側待移除體,所述第一外側待移除體與所述第二外側待移除體相對間隔設於所述第一基板本體之一側,所述第一外側待移除體包括第一內表面及與所述第一內表面相對之第一外表面,所述第二外側待移除體包括第二內表面及與所述第二內表面相對之第二外表面;所述第一結構本體貫穿設有第一開口與第二開口,所述外側導電極包括兩個第一外側導電極與兩個第二外側導電極,所述第一開口設於兩個所述第一外側導電極之間,所述第二開口設於兩個所述第二外側導電極之間;步驟“於所述第一基板上設置第一線路結構”還包括:將兩個所述第一外側導電極以及兩個所述第一外側導電極之間之第一外側待移除體穿過所述第一開口;將兩個所述第二外側導電極以及兩個所述第二外側導電極之間之第二外側待移除體穿過所述第二開口;將一個所述第一外側導電極設於所述第一內表面,另一個所述第一外側導電極設於所述第一外表面;以及將一個所述第二外側導電極設於所述第二內表面,另一個所述第二外側導電極設於所述第二外表面。 Further, the outer body to be removed includes a first outer body to be removed and a second outer body to be removed. The first outer body to be removed and the second outer body to be removed are relatively spaced apart from each other. On one side of the first substrate body, the first outer body to be removed includes a first inner surface and a first outer surface opposite to the first inner surface, and the second outer body to be removed includes a first inner surface. two inner surfaces and a second outer surface opposite to the second inner surface; the first structural body is provided with a first opening and a second opening, and the outer conductive electrode includes two first outer conductive electrodes and two a second outer conductive electrode, the first opening is disposed between the two first outer conductive electrodes, the second opening is disposed between the two second outer conductive electrodes; step "in "Providing the first circuit structure on the first substrate" also includes: passing the two first outer conductive electrodes and the first outer body to be removed between the two first outer conductive electrodes through the first opening. ; Pass the two second outer conductive electrodes and the second outer body to be removed between the two second outer conductive electrodes through the second opening; place one of the first outer conductive electrodes in The first inner surface, another first outer conductive electrode is provided on the first outer surface; and one second outer conductive electrode is provided on the second inner surface, and the other second outer conductive electrode is provided on the first inner surface. The outer conductive electrode is provided on the second outer surface.
進一步地,所述電容包括第一電容與第二電容,所述外側介電空間包括第一外側介電空間與第二外側介電空間,步驟“移除所述外側待移除體”包括:移除所述第一外側待移除體以形成所述第一外側介電空間,其中,所述第一電容包括兩個所述第一外側導電極與所述第一外側介電空間;以及移除所述第二外側待移除體以形成第二外側介電空間,其中,所述第二電容包括兩個所述第二外側導電極與所述第二外側介電空間。 Further, the capacitor includes a first capacitor and a second capacitor, the outer dielectric space includes a first outer dielectric space and a second outer dielectric space, and the step "removing the outer object to be removed" includes: Remove the first outer body to be removed to form the first outer dielectric space, wherein the first capacitor includes two first outer conductive electrodes and the first outer dielectric space; and The second outer body to be removed is removed to form a second outer dielectric space, wherein the second capacitor includes two second outer conductive electrodes and the second outer dielectric space.
進一步地,所述第一覆蓋體包括第一彈性連接體與第一覆蓋膜,所述第一彈性連接體連接兩個所述第一外側導電極,所述第一覆蓋膜連接兩個所述第二外側導電極,所述第一電容包括兩個所述第一外側導電極、所述第一外側介電空間、以及連接於兩個所述第一外側導電極之間之第一彈性連接體。 Further, the first covering body includes a first elastic connecting body and a first covering film. The first elastic connecting body connects the two first outer conductive electrodes, and the first covering film connects the two first outer conductive electrodes. A second outer conductive electrode, the first capacitor includes two first outer conductive electrodes, the first outer dielectric space, and a first elastic connection connected between the two first outer conductive electrodes. body.
進一步地,還包括步驟,於所述第二外側介電空間設置第一填充體,所述第二電容還包括所述第一填充體,所述第二電容包括兩個所述第二外側導電極、所述第二外側介電空間、以及填充於所述第二外側介電空間之所述第一填充體。 Further, the method further includes the step of arranging a first filling body in the second outer dielectric space, the second capacitor further includes the first filling body, and the second capacitor includes two second outer conductors. An electrode, the second outer dielectric space, and the first filling body filled in the second outer dielectric space.
進一步地,所述第一線路結構之製造方法包括:提供一第一覆銅基板,所述第一覆銅基板包括第一基材層與第一銅箔層,所述第一銅箔層設於所述第一基材層之一側;蝕刻所述第一銅箔層以形成第一線路層,獲得一線路中間體;於所述線路中間體貫穿設置兩個第一狹縫、兩個第二狹縫、以及兩個第三狹縫,兩個所述第一狹縫相對平行設置,一個所述第三狹縫連通於兩個所述第一狹縫之間,兩個所述第二狹縫相對平行設置,另一個所述第三狹縫連通於兩個所述第二狹縫之間;朝一側彎折兩個所述第一狹縫之間之部分所述第一線路中間體以形成兩個第一導電極;以及朝一側彎折兩個所述第二狹縫之間之部分所述第一線路中間體以形成兩個第二導電極,獲得第一線路結構。 Further, the manufacturing method of the first circuit structure includes: providing a first copper-clad substrate, the first copper-clad substrate includes a first base material layer and a first copper foil layer, the first copper foil layer is provided On one side of the first base material layer, the first copper foil layer is etched to form a first circuit layer to obtain a circuit intermediate body; two first slits and two first slits are provided through the circuit intermediate body. a second slit, and two third slits. The two first slits are relatively parallel to each other. One third slit is connected between the two first slits. The two first slits are connected to each other. Two slits are arranged relatively parallel, and the other third slit is connected between the two second slits; the middle part of the first line between the two first slits is bent to one side. body to form two first conductive electrodes; and bend the portion of the first circuit intermediate body between the two second slits toward one side to form two second conductive electrodes to obtain a first circuit structure.
進一步地,所述第一基板之製造方法包括:提供第一基板本體,所述第一基板本體包括離型膜、剝離載板、以及金屬層,所述剝離載板與所述金屬層分別設於所述離型膜之相對之兩個側表面; 於所述金屬層背離所述離型膜之一側設置第一外側待移除體與第二外側待移除體,獲得所述第一基板;其中,所述第一外側待移除體包括第一內表面及與所述第一內表面相對之第一外表面,所述第二外側待移除體包括第二內表面及與所述第二內表面相對之第二外表面,所述第一內表面與所述第二內表面相對設置。 Further, the manufacturing method of the first substrate includes: providing a first substrate body, the first substrate body includes a release film, a peeling carrier plate, and a metal layer, the peeling carrier plate and the metal layer are respectively provided On the two opposite side surfaces of the release film; A first outer body to be removed and a second outer body to be removed are provided on a side of the metal layer facing away from the release film to obtain the first substrate; wherein the first outer body to be removed includes a first inner surface and a first outer surface opposite to the first inner surface; the second outer body to be removed includes a second inner surface and a second outer surface opposite to the second inner surface; The first inner surface is opposite to the second inner surface.
進一步地,步驟“於所述第一基板上設置第一線路結構”之前還包括:於所述金屬層設置第一黏接層,所述第一黏接層具有第一開孔與第二開孔,所述第一外側待移除體穿過所述第一開孔,所述第二外側待移除體穿過所述第二開孔;於所述第一內表面與所述第一外表面各設置一個第一黏接片;以及於所述第二內表面與所述第二外表面各設置一個第二黏接片;步驟“於所述基板本體上設置線路結構”包括:於所述第一黏接層上設置所述第一結構本體;於所述第一黏接片設置所述第一外側導電極;以及於所述第二黏接片設置所述第二外側導電極。 Further, before the step of "setting a first circuit structure on the first substrate", the step further includes: setting a first adhesive layer on the metal layer, the first adhesive layer having a first opening and a second opening. hole, the first outer body to be removed passes through the first opening, and the second outer body to be removed passes through the second opening; between the first inner surface and the first A first adhesive sheet is provided on each outer surface; and a second adhesive sheet is provided on each of the second inner surface and the second outer surface; the step "providing a circuit structure on the substrate body" includes: The first structural body is provided on the first adhesive layer; the first outer conductive electrode is provided on the first adhesive sheet; and the second outer conductive electrode is provided on the second adhesive sheet. .
進一步地,步驟“移除所述外側待移除體以形成外側介電空間”還包括:移除所述離型膜,以使所述剝離載板與所述金屬層分離;以及蝕刻去除所述金屬層。 Further, the step "removing the outer body to be removed to form an outer dielectric space" also includes: removing the release film to separate the peeling carrier plate from the metal layer; and etching to remove the release film. The metal layer.
進一步地,還包括步驟:於所述第一黏接層背離所述第一線路層之一側設置第一防焊層,所述第一防焊層貫穿設有第一開窗與第二開窗,所述第一開窗對應所述第一電容設置,所述第二開窗對應所述第二電容設置。 Further, the method further includes the step of: arranging a first solder resist layer on a side of the first adhesive layer away from the first circuit layer, and the first solder resist layer is provided with a first opening and a second opening. The first window is arranged corresponding to the first capacitor, and the second window is arranged corresponding to the second capacitor.
一種內嵌電容之電路板之製造方法,包括步驟:提供一第二基板,所述第二基板包括第二基板本體與多個內側待移除體,所述內側待移除體設於所述第二基板本體之一側,每一所述內側待移除體包括一內表面及與所述內表面相對之一外表面;於所述第二基板上設置第二線路結構,所述第二線路結構包括第二結構本體及多個內側導電極,兩個所述內側導電極相對間隔設於所述第二結構本體,所述第二結構本體貫穿設有多個開口,所述開口設於每兩個所述內側導電極之間,所述內側待移除體穿過所述開口,一個所述內側導電極設於一個所述內表面,另一個所述內側導電極設於另一個所述外表面;於所述第二基板背離所述第二結構本體之一側設置第一覆蓋膜,以及於所述第二結構本體背離所述第二基板之一側設置第二覆蓋膜;以及移除所述內側待移除體以形成內側介電空間,獲得內嵌電容之所述電容板,其中,所述電容包括所述內側導電極及所述內側介電空間。 A method of manufacturing a circuit board with embedded capacitors, including the steps of: providing a second substrate, the second substrate includes a second substrate body and a plurality of inner to-be-removed bodies, and the inner to-be-removed bodies are provided on the On one side of the second substrate body, each inner body to be removed includes an inner surface and an outer surface opposite to the inner surface; a second circuit structure is provided on the second substrate, and the second The circuit structure includes a second structural body and a plurality of inner conductive electrodes. The two inner conductive electrodes are relatively spaced apart from each other on the second structural body. The second structural body is provided with a plurality of openings, and the openings are provided on Between each two inner conductive electrodes, the inner body to be removed passes through the opening, one inner conductive electrode is provided on one of the inner surfaces, and the other inner conductive electrode is provided on the other inner surface. The outer surface; a first covering film is provided on a side of the second substrate facing away from the second structural body, and a second covering film is provided on a side of the second structural body facing away from the second substrate; and The inner body to be removed is removed to form an inner dielectric space, and the capacitor plate with embedded capacitor is obtained, wherein the capacitor includes the inner conductive electrode and the inner dielectric space.
進一步地,所述內側待移除體包括兩個第一內側待移除體與兩個第二內側待移除體,所述第一內側待移除體與所述第二內側待移除體相對間隔設於所述第二基板本體之一側,所述第一內側待移除體包括第三內表面及與所述第三內表面相對之第三外表面,所述第二內側待移除體包括第四內表面及與所述第四內表面相對之第四外表面。所述開口包括第三開口與第四開口,所述內側導電極包括兩個第一內側導電極與兩個第二內側導電極,所述第三開口設於兩個所述第一內側導電極之間,所述第四開口設於兩個所述第二內側導電極之間。步驟“於所述第二基板上設置第二線路結構”還包括:將一個所述第一內側導電極設於所述第三內表面,另一個所述第一內側導電極設於所述第三外表面以及將一個所述第二內側導電極設於所述第四內表面,另一個所述第二內側導電極設於所述第四外表面。 Further, the inner body to be removed includes two first inner bodies to be removed and two second inner bodies to be removed, the first inner body to be removed and the second inner body to be removed Relatively spaced on one side of the second substrate body, the first inner body to be removed includes a third inner surface and a third outer surface opposite to the third inner surface, and the second inner body to be removed is The body includes a fourth inner surface and a fourth outer surface opposite to the fourth inner surface. The opening includes a third opening and a fourth opening, the inner conductive electrode includes two first inner conductive electrodes and two second inner conductive electrodes, and the third opening is provided on the two first inner conductive electrodes. The fourth opening is provided between the two second inner conductive electrodes. The step of "providing a second circuit structure on the second substrate" also includes: disposing one of the first inner conductive electrodes on the third inner surface, and disposing the other first inner conductive electrode on the third inner surface. Three outer surfaces, one of the second inner conductive electrodes is provided on the fourth inner surface, and the other second inner conductive electrode is provided on the fourth outer surface.
進一步地,所述電容包括第三電容與第四電容,所述內側介電空間包括第一內側介電空間與第二內側介電空間,步驟“移除所述內側待移除體”包括:移除所述第一內側待移除體以形成所述第一內側介電空間,其中,所述第三電容包括兩個所述第一內側導電極與所述第一內側介電空間以及移除所述第二內側待移除體以形成所述第二內側介電空間,其中,所述第四電容包括兩個所述第二內側導電極與所述第二內側介電空間。 Further, the capacitor includes a third capacitor and a fourth capacitor, the inner dielectric space includes a first inner dielectric space and a second inner dielectric space, and the step "removing the inner object to be removed" includes: The first inner body to be removed is removed to form the first inner dielectric space, wherein the third capacitor includes two first inner conductive electrodes and the first inner dielectric space and a moving The second inner body to be removed is removed to form the second inner dielectric space, wherein the fourth capacitor includes two second inner conductive electrodes and the second inner dielectric space.
進一步地,所述第二基板之製造方法包括步驟:提供一第二覆銅基板,所述第二覆銅基板包括第二基材層、第二銅箔層、以及第三銅箔層,所述第二銅箔層與所述第三銅箔層分別設於所述第二基材層之相對兩個表面。蝕刻所述第二銅箔層以形成第一內側線路層以形成所述第二基板本體。於所述第二基板本體上設置第一內側待移除體及第二內側待移除體,獲得所述第二基板。 Further, the manufacturing method of the second substrate includes the step of: providing a second copper-clad substrate, the second copper-clad substrate includes a second base material layer, a second copper foil layer, and a third copper foil layer, so The second copper foil layer and the third copper foil layer are respectively provided on two opposite surfaces of the second base material layer. The second copper foil layer is etched to form a first inner circuit layer to form the second substrate body. A first inner body to be removed and a second inner body to be removed are arranged on the second substrate body to obtain the second substrate.
進一步地,步驟“於所述第二基板上設置第二線路結構”之前還包括:於所述第一內側線路層設置第二黏接層,所述第二黏接層貫穿設有第三開孔與第四開孔,所述第一內側待移除體穿過所述第三開孔,所述第二內側待移除體穿過所述第四開孔。於所述第三內表面與所述第三外表面分別設置一個第三黏接片以及於所述第四內表面與所述第四外表面分別設置一個第四黏接片。 Further, before the step of "setting a second circuit structure on the second substrate", the step further includes: setting a second adhesive layer on the first inner circuit layer, and the second adhesive layer is provided with a third opening therethrough. hole and a fourth opening, the first inner body to be removed passes through the third opening, and the second inner body to be removed passes through the fourth opening. A third adhesive sheet is respectively provided on the third inner surface and the third outer surface, and a fourth adhesive sheet is respectively provided on the fourth inner surface and the fourth outer surface.
進一步地,步驟“於所述第二基板上設置第二線路結構”還包括:於所述第三黏接片設置所述第一內側導電極,以及於所述第四黏接片設置第二內側導電極。 Further, the step of "setting a second circuit structure on the second substrate" also includes: setting the first inner conductive electrode on the third adhesive sheet, and setting a second inner conductive electrode on the fourth adhesive sheet. Inner conductive electrode.
進一步地,步驟“於所述第二基板上設置第二線路結構”之後,以及步驟“於所述第二結構本體背離所述第二基板之一側設置第二覆蓋膜”之前還包括:蝕刻部分所述第二本結構本體以形成第二內側線路層;於所述第二內側線路層設置第三黏接層於所述第三黏接層上設置第三覆銅基板,所述第三覆銅基板包括第三基材層及設於所述第三基材層之第四銅箔層,所述第三基材層設於所述第四銅箔層與所述第三黏接層之間。蝕刻所述第二銅箔層以形成第一外側 線路層以及蝕刻所述第四銅箔層以形成第二外側線路層。 Further, after the step of "arranging a second circuit structure on the second substrate" and before the step of "arranging a second covering film on a side of the second structural body facing away from the second substrate", it also includes: etching Part of the second structural body is used to form a second inner circuit layer; a third adhesive layer is provided on the second inner circuit layer, and a third copper-clad substrate is provided on the third adhesive layer. The copper-clad substrate includes a third base material layer and a fourth copper foil layer provided on the third base material layer. The third base material layer is provided on the fourth copper foil layer and the third adhesive layer. between. Etch the second copper foil layer to form a first outer circuit layer and etching the fourth copper foil layer to form a second outer circuit layer.
進一步地,還包括步驟:於所述第一覆蓋膜設置下開窗,所述下開窗對應所述第一內側介電空間設置以及於所述下開窗設置第二彈性連接體,其中,所述第三電容包括兩個所述第一內側導電極、所述第一內側介電空間及所述第二彈性連接體。 Further, the method further includes the steps of: arranging a lower window on the first covering film, the lower window being arranged corresponding to the first inner dielectric space, and arranging a second elastic connector on the lower window, wherein, The third capacitor includes two first inner conductive electrodes, the first inner dielectric space and the second elastic connector.
進一步地,還包括步驟:於所述第二覆蓋膜設置上開窗,所述上開窗對應所述第二內側介電空間設置,以及於所述第二內側介電空間內設置第二填充體,其中,所述第四電容包括兩個所述第二內側導電極、所述第二內側介電空間及所述第二填充體。 Further, the method further includes the steps of: arranging an upper window on the second covering film, the upper window being arranged corresponding to the second inner dielectric space, and arranging a second filling in the second inner dielectric space. body, wherein the fourth capacitor includes two second inner conductive electrodes, the second inner dielectric space and the second filling body.
進一步地,還包括步驟:移除所述第二彈性連接體對應之部分所述第二基材層。 Further, the method further includes the step of removing the portion of the second base material layer corresponding to the second elastic connector.
一種內嵌電容之電路板,包括線路結構,所述線路結構包括結構本體、兩個第一導電極、以及兩個第二導電極,兩個所述第一導電極相對間隔設於所述結構本體之一側,兩個所述第二導電極相對間隔設於所述線路結構之一側,所述線路結構貫穿設有第一開口,所述第一開口設於兩個所述第一導電極之間以形成第一外側介電空間,兩個所述第一導電極及所述第一外側介電空間形成第一電容,所述線路結構貫穿設有第二開口,所述第二開口設於兩個所述第二導電極之間以形成第二外側介電空間,兩個所述第二導電極及所述第二外側介電空間形成第二電容。 A circuit board with embedded capacitors, including a circuit structure. The circuit structure includes a structural body, two first conductive electrodes, and two second conductive electrodes. The two first conductive electrodes are relatively spaced apart from the structure. On one side of the body, two second conductive electrodes are arranged relatively spaced apart on one side of the circuit structure. The circuit structure is provided with a first opening, and the first opening is provided on the two first conductive electrodes. A first outer dielectric space is formed between the electrodes. The two first conductive electrodes and the first outer dielectric space form a first capacitor. A second opening is provided through the circuit structure. The second opening It is disposed between the two second conductive electrodes to form a second outer dielectric space, and the two second conductive electrodes and the second outer dielectric space form a second capacitor.
進一步地,還包括彈性連接體與填充體,所述彈性連接體設於兩個所述第一導電極之間,所述填充體設於兩個所述第二導電極之間。 Furthermore, it also includes an elastic connector and a filling body, the elastic connector is provided between the two first conductive electrodes, and the filling body is provided between the two second conductive electrodes.
相比於習知技術,本申請提供之內嵌電容之電路板之製造方法具有如下優點:(一)藉由先形成第一外側待移除體與第二外側待移除體,然後於第一外側待移除體之兩側形成第一導電極、於第二外側待移除體之兩側形成第二導電極,最後去除第一導電極與第二導電極,從而於電路板內形成內嵌之第一電容與第二電容,該方法製造之電容無需於電路板之整版設置介電材料,有利於電路板之厚度並節省製作電容所需之材料,同時,該方法具製作之電容之位置靈活多變,適用於多數需要內嵌電容之電路板。(二)藉由於兩個第一導電極之間設置第一彈性連接體,使得兩個第一導電極之間之距離可以發生變化,實現所述第一電容之電容值可變;藉由於兩個第二導電極之間設置第一填充體,使得第二導電極之間之距離不可改變,即,所述第二電容之電容值為固定值。 Compared with the prior art, the manufacturing method of a circuit board with embedded capacitor provided by the present application has the following advantages: (1) By first forming the first outer body to be removed and the second outer body to be removed, and then forming the first outer body to be removed, and then forming the second outer body to be removed. First conductive electrodes are formed on both sides of an outer body to be removed, second conductive electrodes are formed on both sides of the second outer body to be removed, and finally the first conductive electrode and the second conductive electrode are removed to form a circuit board The first capacitor and the second capacitor are embedded. The capacitor manufactured by this method does not need to be provided with dielectric materials on the entire circuit board, which is beneficial to the thickness of the circuit board and saves the materials required for manufacturing the capacitor. At the same time, this method has The position of the capacitor is flexible and adaptable to most circuit boards that require embedded capacitors. (2) By disposing a first elastic connector between the two first conductive electrodes, the distance between the two first conductive electrodes can be changed, so that the capacitance value of the first capacitor can be variable; A first filling body is disposed between the second conductive electrodes so that the distance between the second conductive electrodes cannot be changed, that is, the capacitance value of the second capacitor is a fixed value.
100:電容 100: Capacitor
101:第一電容 101: First capacitor
102:第二電容 102: Second capacitor
10:待移除體 10: Object to be removed
11:表面 11:Surface
20:導電極 20: Conductive electrode
21:空氣 21:Air
22:彈性連接體 22: Elastic connector
23:填充體 23: Filling body
30:第一基板本體 30: First substrate body
31:離型膜 31: Release film
32:剝離載板 32: Peel off the carrier board
33:金屬層 33:Metal layer
34:第一外側待移除體 34: The first outer body to be removed
341:第一內表面 341: First inner surface
342:第一外表面 342: First outer surface
35:第二外側待移除體 35: The second outer body to be removed
351:第二內表面 351: Second inner surface
352:第二外表面 352:Second outer surface
36:第一黏接層 36: First bonding layer
36a:第一開孔 36a: First opening
36b:第二開孔 36b: Second opening
362:第一黏接片 362: First bonding piece
363:第二黏接片 363:Second bonding piece
366:第一中間體 366:First intermediate
39:第一基板 39:First substrate
40:第一線路結構 40: First line structure
41:第一結構本體 41:First structural ontology
411:第一開口 411:First opening
412:第二開口 412:Second opening
42:第一導電極 42: First conductive electrode
43:第二導電極 43: Second conductive electrode
44:第一覆銅基板 44: The first copper-clad substrate
441:第一基材層 441: First base material layer
442:第一銅箔層 442: First copper foil layer
443:第一線路層 443: First line layer
444:第一線路中間體 444:First line intermediate
444a:第一狹縫 444a: first slit
444b:第二狹縫 444b: Second slit
444c:第三狹縫 444c: Third slit
45:第一彈性連接體 45: First elastic connector
451:第一彈性部分 451: First elastic part
452:第一連接部分 452: First connection part
453:第二連接部分 453: Second connection part
46:第一覆蓋膜 46:First covering film
47:第一防焊層 47: First solder mask
471:第一開窗 471:First window opening
472:第二開窗 472: Second window opening
48:第一填充體 48: First filling body
200、300:電路板 200, 300: circuit board
211:第一外側介電空間 211: First outer dielectric space
212:第二外側介電空間 212: Second outer dielectric space
50:第二覆銅基板 50: Second copper-clad substrate
501:第二基板本體 501: Second substrate body
502:第二基板 502: Second substrate
521:第一內側線路層 521: First inside line layer
51:第二基材層 51: Second base material layer
52:第二銅箔層 52: Second copper foil layer
53:第三銅箔層 53: The third copper foil layer
531:第一外側線路層 531: First outside line layer
54:第一內側待移除體 54: The first inner body to be removed
541:第三內表面 541:Third inner surface
542:第三外表面 542:Third outer surface
543:第一內側介電空間 543: First inner dielectric space
55:第二內側待移除體 55: The second inner body to be removed
551:第四內表面 551:Fourth inner surface
552:第四外表面 552:Fourth outer surface
553:第二內側介電空間 553: Second inner dielectric space
56:第二黏接層 56:Second bonding layer
56a:第三開孔 56a:Third opening
56b:第四開孔 56b: The fourth opening
561:第三黏接片 561:Third bonding piece
562:第四黏接片 562: The fourth adhesive piece
563:第二中間體 563:Second intermediate
60:第二線路結構 60: Second line structure
61:第二結構本體 61:Second structural ontology
61a:第三開口 61a:The third opening
61b:第四開口 61b:The fourth opening
611:第三基材層 611: The third base material layer
612:第五銅箔層 612: The fifth copper foil layer
62:第三導電極 62: The third conductive electrode
63:第四導電極 63: The fourth conductive electrode
64:第三黏接層 64:Third bonding layer
65:第三覆銅基板 65: The third copper-clad substrate
651:第三基材層 651: The third base material layer
652:第四銅箔層 652: The fourth copper foil layer
653:第一通孔 653: First through hole
654:第二通孔 654: Second through hole
655:第二外側線路層 655: Second outside line layer
66:第一覆蓋膜 66: First covering film
661:下開窗 661: Bottom opening window
67:第二覆蓋膜 67: Second covering film
671:上開窗 671: Top opening window
70:第二彈性連接體 70: Second elastic connector
71:第二彈性部分 71: Second elastic part
72:第三連接部分 72: The third connection part
73:第四連接部分 73: The fourth connection part
75:第三電容 75: The third capacitor
76:第四電容 76: The fourth capacitor
761:第二填充體 761:Second filling body
A:第一方向 A:First direction
B:第二方向 B:Second direction
C:第三方向 C:Third direction
D:第四方向 D:Fourth direction
圖1為本申請一實施例提供之待移除體之截面示意圖。 Figure 1 is a schematic cross-sectional view of an object to be removed according to an embodiment of the present application.
圖2為圖1所示之待移除體設置導電極後之截面示意圖。 FIG. 2 is a schematic cross-sectional view of the body to be removed shown in FIG. 1 after being provided with conductive electrodes.
圖3為本申請一實施例提供之電容之截面示意圖。 FIG. 3 is a schematic cross-sectional view of a capacitor provided by an embodiment of the present application.
圖4為圖3所示之電容設置彈性連接體後之截面示意圖。 FIG. 4 is a schematic cross-sectional view of the capacitor shown in FIG. 3 after being provided with an elastic connector.
圖5為圖3所示之電容設置填充體後之截面示意圖。 FIG. 5 is a schematic cross-sectional view of the capacitor shown in FIG. 3 after being provided with a filling body.
圖6為本申請一實施例提供之第一基板本體之截面示意圖。 FIG. 6 is a schematic cross-sectional view of the first substrate body provided by an embodiment of the present application.
圖7為圖6所示之第一基板本體設置第一外側待移除體後之截面示意圖。 FIG. 7 is a schematic cross-sectional view of the first substrate body shown in FIG. 6 after being provided with a first outer body to be removed.
圖8為圖7所示之第一外側待移除體設置第一黏接片後之截面示意圖。 FIG. 8 is a schematic cross-sectional view of the first outer body to be removed shown in FIG. 7 after being provided with a first adhesive sheet.
圖9為圖8所示之第一黏接片設置第一導電極後之截面示意圖。 FIG. 9 is a schematic cross-sectional view of the first adhesive sheet shown in FIG. 8 after being provided with a first conductive electrode.
圖10為本申請一實施例體提供之第一覆銅基板之截面示意圖。 FIG. 10 is a schematic cross-sectional view of a first copper-clad substrate provided by an embodiment of the present application.
圖11為蝕刻圖10所述覆銅基板之第一銅箔層以形成第一線路中間體後之截面示意圖。 FIG. 11 is a schematic cross-sectional view after etching the first copper foil layer of the copper-clad substrate shown in FIG. 10 to form a first circuit intermediate body.
圖12為圖11所示之第一線路中間體設置兩個第一狹縫後之俯視圖。 FIG. 12 is a top view of the first circuit intermediate body shown in FIG. 11 after two first slits are provided.
圖13為彎折圖12所示之兩個第一狹縫之間之部分第一線路中間體後形成之第一線路結構之截面示意圖。 FIG. 13 is a schematic cross-sectional view of the first circuit structure formed after bending part of the first circuit intermediate body between the two first slits shown in FIG. 12 .
圖14為圖9所示之第一黏接片設置圖13所示之第一導電極後之截面示意圖。 FIG. 14 is a schematic cross-sectional view of the first adhesive sheet shown in FIG. 9 after being provided with the first conductive electrode shown in FIG. 13 .
圖15為圖14所示之第一基板本體部分移除後之截面示意圖。 FIG. 15 is a schematic cross-sectional view of the first substrate body shown in FIG. 14 with part thereof removed.
圖16為移除圖14所示之第一外側待移除體後之截面示意圖。 FIG. 16 is a schematic cross-sectional view after removing the first outer body to be removed shown in FIG. 14 .
圖17為本申請一實施例提供之內嵌電容之電路板之截面示意圖。 FIG. 17 is a schematic cross-sectional view of a circuit board with built-in capacitors provided by an embodiment of the present application.
圖18為本申請另一實施例提供之第二覆銅基板之截面示意圖。 FIG. 18 is a schematic cross-sectional view of a second copper-clad substrate provided by another embodiment of the present application.
圖19為蝕刻圖18所示之第二覆銅基板以形成第二基板本體後之截面示意圖。 FIG. 19 is a schematic cross-sectional view after etching the second copper-clad substrate shown in FIG. 18 to form a second substrate body.
圖20為圖19所示之第二基板本體設置第一內側待移除體後形成第二基板之截面示意圖。 FIG. 20 is a schematic cross-sectional view of the second substrate body shown in FIG. 19 after being provided with a first inner body to be removed to form a second substrate.
圖21為圖20所示之第二基板設置第二黏接層後形成之第二中間體之截面示意圖。 FIG. 21 is a schematic cross-sectional view of the second intermediate body formed after the second substrate shown in FIG. 20 is provided with a second adhesive layer.
圖22為圖21所示之第二中間體設置第二線路結構之截面示意圖。 FIG. 22 is a schematic cross-sectional view of the second intermediate body shown in FIG. 21 provided with a second circuit structure.
圖23為蝕刻圖22所示之第五銅箔層以形成第二內側線路層之截面示意圖。 FIG. 23 is a schematic cross-sectional view of etching the fifth copper foil layer shown in FIG. 22 to form a second inner circuit layer.
圖24為圖23所示之第二內側線路層上設置第三覆銅基板後之截面示意圖。 FIG. 24 is a schematic cross-sectional view after a third copper-clad substrate is disposed on the second inner circuit layer shown in FIG. 23 .
圖25為蝕刻圖24所示之第三覆銅基板後以形成第二外側之截面示意圖。 FIG. 25 is a schematic cross-sectional view of the third copper-clad substrate shown in FIG. 24 after etching to form a second outer side.
圖26為圖25所示之第二外側線路層設置第二覆蓋膜後之截面示意圖。 FIG. 26 is a schematic cross-sectional view of the second outer circuit layer shown in FIG. 25 after being provided with a second covering film.
圖27為圖26所示之第一覆蓋膜之下開窗設置第二彈性連接體後之截面示意圖。 FIG. 27 is a schematic cross-sectional view of the second elastic connector shown in FIG. 26 after opening a window under the first covering film.
圖28為移除圖27所示之第一內側待移除體與第二內側待移除體後之截面示意圖。 FIG. 28 is a schematic cross-sectional view after removing the first inner body to be removed and the second inner body to be removed shown in FIG. 27 .
圖29為圖28所示之第二內側介電空間內設置第二填充體後之截面示意圖。 FIG. 29 is a schematic cross-sectional view after the second filling body is disposed in the second inner dielectric space shown in FIG. 28 .
圖30為本申請另一實施例提供之內嵌電容之電路板之截面示意圖。 FIG. 30 is a schematic cross-sectional view of a circuit board with built-in capacitors according to another embodiment of the present application.
下面將結合本申請實施例中之附圖,對本申請實施例中之技術方案進行清楚、完整地描述,顯然,所描述之實施例僅僅是本申請一部分實施例,而不是全部之實施例。 The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments.
需要說明的是,當一個元件被認為是“連接”另一個元件,它可以是直接連接到另一個元件或者可能同時存於居中元件。當一個元件被認為是“設置於”另一個元件,它可以是直接設置於另一個元件上或者可能同時存於居中元件。 Note that when an element is said to be "connected" to another element, it can be directly connected to the other element or it may also be present on an intervening element. When an element is said to be "disposed on" another element, it can be directly located on the other element or it may also be present on a centered element.
請參見圖1至圖5,本申請一實施例提供一種電容100之製造方法,包括步驟:
Referring to Figures 1 to 5, one embodiment of the present application provides a method for manufacturing a
S1:請參見圖1,提供一個待移除體10。所述待移除體10包括相對間隔設置之兩個表面11。於本實施例中,所述待移除體10為銅塊。於本申請之其他實施例中,所述待移除體10之材質可以金屬、樹脂、或者金屬與樹脂之複合。
S1: Referring to Figure 1, a
S2:請參見圖2,於一個所述表面11設置一個導電極20,以及於另一所述表面11設置另一個導電極20。
S2: Referring to FIG. 2 , one
S2:請參見圖3,蝕刻移除所述待移除體10,獲得所述電容100。其中,所述電容100為平行板電容,所述電容100包括相對間隔設置之兩個導電極20、以及兩個所述導電極20之間之空氣21。
S2: Please refer to Figure 3. The
於一些實施例中,所述電容100之製造方法還包括步驟:
In some embodiments, the manufacturing method of the
S3:請參見圖4,於兩個所述導電極20之間連接彈性連接體22。所述彈性連接體22可以拉伸與壓縮,從而有利於實現兩個導電極20之間之距離調整(即,空氣之厚度調整),依據平行板電容之計算公式:C=S×Dk/T,其中,C:電容值;S:兩個導電極20有效之重叠面積,Dk:空氣之介電常數;T:空氣21之厚度。可知,改變兩個導電極20之相對距離可以實現所述電容100之電容值之改變,進而實現所述電容100之電容值可調。
S3: Refer to FIG. 4 , connect the
於另一些實施例中,所述電容100之製造方法還包括步驟:
In other embodiments, the manufacturing method of the
S4:請參見圖5,於兩個所述導電極20之間填入填充體23,所述填充體23之材質包括環氧樹脂、聚醯亞胺中之至少一種,從而使得所述電容100之電容值固定。
S4: Referring to FIG. 5 , a filling
相比於習知技術,本申請提供之電容100之製造方法具有以下優點:藉由於待移除體10之相對兩側分別設置導電極20,然後移除該待移除體10形成所述電容100,該方法不僅簡單可靠,且藉由於兩個導電極20之間設置彈性連接體22即可獲得可變電容,藉由於兩個導電極20之間設置填充體23即可獲得固定電容,不僅不會佔用過多之空間,且不會浪費材料。
Compared with the conventional technology, the manufacturing method of the
請參見圖6至圖17,本申請一實施例提供一種內嵌電容之電路板200之製造方法,包括步驟:
Referring to Figures 6 to 17, one embodiment of the present application provides a method of manufacturing a
S101:請參見圖6,提供第一基板本體30。所述第一基板本體30包括離型膜31、剝離載板32、以及金屬層33。所述剝離載板32與所述金屬層33分別設於所述離型膜31之相對之兩個側表面。定義所述第一基板本體30之厚度方向為第一方向A,以及定義所述第一基板本體30之延伸方向為第二方向B。
S101: Refer to Figure 6 to provide a
S102:請參見圖7,於所述金屬層33背離所述離型膜31之一側設置第一外側待移除體34與第二外側待移除體35,獲得第一基板39。其中,所
述第一外側待移除體34與所述第二外側待移除體35沿所述第二方向B間隔設置,所述第一外側待移除體34包括第一內表面341及與所述第一內表面341相對之第一外表面342。所述第二外側待移除體35包括第二內表面351及與所述第二內表面351相對之第二外表面352。所述第一內表面341與所述第二內表面351相對設置。具體地,所述第一外側待移除體34與所述第二外側待移除體35為藉由電鍍方式形成於所述金屬層33之銅塊。
S102: Referring to FIG. 7 , a first outer body to be removed 34 and a second outer body to be removed 35 are provided on a side of the
S103:請參見圖8,於所述第一基板39上設置第一黏接層36、第一黏接片362、以及第二黏接片363。具體地,於所述金屬層33未設置所述第一外側待移除體34與所述第二外側待移除體35之區域設置第一黏接層36。所述第一黏接層36具有第一開孔36a與第二開孔36b,所述第一外側待移除體34穿過所述第一開孔36a,所述第二外側待移除體35穿過所述第二開孔36b。同時,於所述第一內表面341與所述第一外表面342各設置一個第一黏接片362。同時,於所述第二內表面351與所述第二外表面352各設置一個第二黏接片363,獲得一第一中間體366。其中,所述第一黏接層36、兩個所述第一黏接片362、以及兩個所述第二黏接片363為一體結構。所述第一黏接層36、所述第一黏接片362以及所述第二黏接片363為純膠。
S103: Referring to FIG. 8 , a first
S104:請參見圖9,於所述第一中間體366上設置第一線路結構40。所述第一線路結構40包括第一結構本體41、兩個第一導電極42、以及兩個第二導電極43。兩個所述第一導電極42沿所述第一方向A間隔設於所述第一結構本體41之一側,兩個所述第二導電極43沿所述第一方向A間隔設於所述第一結構本體41之一側。所述第一結構本體41貫穿設有第一開口411與第二開口412。所述第一開口411設於間隔設置之兩個所述第一導電極42之間,所述第二開口412設於間隔設置之兩個所述第二導電極43之間。所述第一結構本體41設置於所述第一黏接層36上,所述第一外側待移除體34穿過所述第一開口411,兩個所述第一導電極42分別設於兩個所述第一黏接片362背離所述第一外側待移除體34之一側。所述第二外側待移除體35穿過所述第二開口412,兩個所述第二導電極43分別設於兩個所述第二黏接片363背離所述第二外側待移除體35之一側。
S104: Refer to FIG. 9 , set the
於一些實施例中,請參見圖10至圖12,步驟S104中,所述第一線路結構40之製造方法包括步驟:
In some embodiments, please refer to Figures 10 to 12. In step S104, the manufacturing method of the
S1041:請參見圖10,提供一個第一覆銅基板44。所述第一覆銅基板44包括第一基材層441與第一銅箔層442,所述第一銅箔層442設於所述第一基材層441之一側。
S1041: Referring to Figure 10, a first copper-clad
S1042:請參見圖11,蝕刻所述第一銅箔層442以形成第一線路層443,獲得一第一線路中間體444。
S1042: Referring to FIG. 11, the first copper foil layer 442 is etched to form a
S1043:請參見圖12,於所述第一線路中間體444貫穿設置兩個第一狹縫444a、兩個第二狹縫444b、以及兩個第三狹縫444c。兩個所述第一狹縫444a沿平行所述第二方向B相對設置,一個所述第三狹縫444c連通於兩個所述第一狹縫444a之間。兩個所述第二狹縫444b沿平行所述第二方向B相對設置,另一個所述第三狹縫444c連通於兩個所述第二狹縫444b之間。
S1043: Referring to FIG. 12, two
S1044:請參見圖13,朝一側彎折兩個所述第一狹縫444a之間之部分所述第一線路中間體444以形成兩個所述第一導電極42。以及朝一側彎折兩個所述第二狹縫444b之間之部分所述第一線路中間體444以形成兩個所述第二導電極43,獲得所述第一線路結構40。其中,每一所述第一導電極42包括部分所述第一基材層441與部分所述第一線路層443。每一所述第二導電極43包括部分所述第一基材層441與部分所述第一線路層443。
S1044: Refer to FIG. 13 , bend the portion of the first circuit
於另一些實施例中,所述第一線路層443設於所述第一基材層441與所述第一黏接層36之間。
In other embodiments, the
S105:請參見圖14,於所述第一線路結構40設置第一彈性連接體45,所述第一彈性連接體45包括第一彈性部分451、第一連接部分452、以及第二連接部分453。所述第一連接部分452與所述第二連接部分453分別設於所述第一彈性部分451之相對兩端。所述第一彈性部分451覆蓋所述第一外側待移除體34以及兩個所述第一導電極42。所述第二連接部分453連接一個所述第一導電極42之所述第一基材層441,所述第二連接部分453連接另一個所述第一導電極42之所述第一基材層441。使用時,外力牽拉所述第一彈性部分451即可使得兩個所述第一導電極42之間之距離發生改變,從而改變電容值。
S105: Please refer to FIG. 14. A first
於一些實施例中,步驟S105還包括: In some embodiments, step S105 also includes:
S1051:請參見圖14,於所述第一線路結構40設置第一覆蓋膜46,所述第一覆蓋膜46覆蓋所述第二外側待移除體35與兩個所述第二導電極43。
S1051: Please refer to FIG. 14. A
S106:請參見圖15,移除所述離型膜31,使得所述剝離載板32與所述金屬層33分離。
S106: Refer to FIG. 15 , remove the
S107:請參見圖16,蝕刻去除所述金屬層33以及設於所述金屬層33上之所述第一外側待移除體34與所述第二外側待移除體35。其中所述電路板200包括第一電容101與第二電容102。所述第一電容101為可變電容,所述第一電容101包括兩個所述第一導電極42、連接於兩個所述第一導電極42之第一彈性連接體45、以及形成於兩個所述第一導電極42之間之第一外側介電空間211。所述第二電容102包括兩個第二導電極43、以及形成於兩個所述第二導電極43之間之第二外側介電空間212。
S107: Refer to FIG. 16 , etching and removing the
於一些實施例中,步驟S107之後還包括: In some embodiments, step S107 also includes:
S108:請參見圖16,於所述第一黏接層36背離所述第一線路層443之一側設置第一防焊層47,所述第一防焊層47設有第一開窗471與第二開窗472,所述第一開窗471對應所述第一電容101設置,所述第二開窗472對應所述第二電容102設置。
S108: Please refer to Figure 16. A
S109:請參見圖17,於所述第二電容102之兩個所述第二導電極43之間填入第一填充體48,獲得所述電路板200。其中,所述第一填充體48為高介電常數、低介質損耗之聚醯亞胺。即,所述第二電容102為固定電容。
S109: Referring to FIG. 17 , fill the first filling body 48 between the two second
相比於習知技術,本申請提供之內嵌電容之電路板200之製造方法具有以下優點:
Compared with the conventional technology, the manufacturing method of the
(一)藉由先形成第一外側待移除體34與第二外側待移除體35,然後於第一外側待移除體34之兩側形成第一導電極42、於第二外側待移除體35之兩側形成第二導電極43,最後去除第一導電極42與第二導電極43,從而於電路板200內形成內嵌之第一電容101與第二電容102,該方法製造之電容無需於電路板200之整版設置介電材料,有利於電路板200之厚度並節省製作電容所需之材料,同時,該方法具製作之電容之位置靈活多變,適用於多數需要內嵌電容之電路板200。
(1) By first forming the first outer body to be removed 34 and the second outer body to be removed 35, and then forming the first
(二)藉由於兩個第一導電極42之間設置第一彈性連接體45,使得兩個第一導電極42之間之距離可以發生變化,實現所述第一電容101之電容值可變;藉由於兩個第二導電極43之間設置第一填充體48,使得第二導電極43之間之距離不可改變,即,所述第二電容102之電容值為固定值。
(2) By disposing the first
另外,請參見圖17,本申請還提供一種內嵌電容之電路板200,所述內嵌電容之電路板200包括第一線路結構40。所述第一線路結構40包括第一結構本體41、兩個第一導電極42、以及兩個第二導電極43。兩個所述第二導電極43相對間隔設於所述第一結構本體41之一側。兩個所述第二導電極43相對間隔設於所述第一結構本體41之一側。
In addition, please refer to FIG. 17 . The present application also provides a
請一併參見圖13,所述第一結構本體41貫穿設有第一開口411。所述第一開口411設於兩個所述第一導電極42之間以形成第一外側介電空間211。兩個所述第一導電極42及所述第一外側介電空間211形成第一電容101。
Please refer to FIG. 13 as well. The first
所述第一結構本體41貫穿設有第二開口412。所述第二開口412設於兩個所述第二導電極43之間以形成第二外側介電空間212。兩個所述第二導電極43及所述第二外側介電空間212形成第二電容102。
The first
請參見圖18至圖30,本申請另一實施例提供一種內嵌電容之電路板300之製造方法,包括步驟:
Referring to Figures 18 to 30, another embodiment of the present application provides a method of manufacturing a
S201:請參見圖18,提供一第二覆銅基板50,所述第二覆銅基板50包括第二基材層51、第二銅箔層52、以及第三銅箔層53。所述第二銅箔層52與所述第三銅箔層53分別設於所述第二基材層51之相對兩個表面。其中,定義所述第二覆銅基板50之厚度方向為第三方向C,以及定義所述第二覆銅基板50之延伸方向為第四方向D。
S201: Refer to FIG. 18 to provide a second copper-clad
S202:請參見圖19,蝕刻所述第二銅箔層52以形成第一內側線路層521,獲得第二基板本體501。其中,所述第二基板本體501包括第二基材層51、第一內側線路層521與第二銅箔層52,所述第一內側線路層521與所述第二銅箔層52分別設於所述第二基材層51之相對兩側。
S202: Referring to FIG. 19 , the second
S203:請參見圖20,於所述第二基板本體501上設置第一內側待移除體54及第二內側待移除體55,獲得第二基板502。具體地,於所述第一內側線路層521設置第一內側待移除體54與第二內側待移除體55。所述第一內側待移除體54與所述第二內側待移除體55沿所述第四方向D間隔設於所述第一內側線路層521。所述第一內側待移除體54與所述第二內側待移除體55沿所述第三方向C延伸。
S203: Refer to FIG. 20 , set the first inner body to be removed 54 and the second inner body to be removed 55 on the
所述第一內側待移除體54具有第三內表面541及與所述第三內表面541相對之第三外表面542,所述第三內表面541朝向所述第二內側待移除體
55。所述第二內側待移除體55具有第四內表面551及與所述第四內表面551相對之第四外表面552,所述第四內表面551朝向所述第三內表面541設置。具體地,所述第一內側待移除體54與所述第二內側待移除體55為藉由電鍍方式形成於所述第一內側線路層521之銅塊。可以理解地,於本申請之其他實施例中,所述第一內側待移除體54、所述第二內側待移除體55亦可以是其他材質,例如塑膠、陶瓷、鎳合金等。
The first inner body to be removed 54 has a third
S204:請參見圖21,於所述第二基板502設置第二黏接層56。具體地,於所述第一內側線路層521未設置所述第一內側待移除體54與所述第二內側待移除體55之區域設置第二黏接層56。所述第二黏接層56貫穿設有第三開孔56a與第四開孔56b,所述第一內側待移除體54穿過所述第三開孔56a,所述第二內側待移除體55穿過所述第四開孔56b。同時,於所述第三內表面541與所述第三外表面542分別設置一個所述第三黏接片561。同時,於所述第四內表面551與所述第四外表面552分別設置一個所述第四黏接片562,獲得第二中間體563。其中,所述第二黏接層56、所述第三黏接片561、以及所述第四黏接片562為一體結構。所述第二黏接層56、所述第三黏接片561、以及所述第四黏接片562為純膠。
S204: Referring to FIG. 21, a second
S205:請參見圖22,於所述第二中間體563上設置第二線路結構60。所述第二線路結構60包括第二結構本體61、兩個第三導電極62、以及兩個第四導電極63。
S205: Refer to Figure 22, set the
兩個所述第三導電極62沿所述第三方向C間隔設於所述第二結構本體61之一側。兩個所述第四導電極63沿所述第三方向C間隔設於所述第二結構本體61之一側。所述第二結構本體61貫穿設有第三開口61a與第四開口61b,所述第三開口61a設於間隔設置之兩個所述第三導電極62之間。所述第四開口61b設於間隔設置之兩個所述第四導電極63之間。
The two third
所述第一內側待移除體54及兩個所述第三黏接片561穿過所述第三開口61a。所述第二內側待移除體55及兩個所述第四黏接片562穿過所述第四開口61b。
The first inner body to be removed 54 and the two third
兩個所述第三導電極62分別設於兩個所述第三黏接片561背離所述第一內側待移除體54之一側。兩個所述第四導電極63分別設於兩個所述第四黏接片562背離所述第二內側待移除體55之一側。
The two third
其中,所述第二線路結構60與第一線路結構40之製造方法相同,再次不再贅述。所述第二結構本體61包括部分第三基材層611及部分第五銅箔層612。所述第三導電極62亦包括部分所述第三基材層611及部分所述第五銅箔層612。所述第四導電極63亦包括部分所述第三基材層611及部分所述第五銅箔層612。
The manufacturing methods of the
與其他實施例不同之處在於,所述第三基材層611設於所述第五銅箔層612與所述第二黏接層56之間,而其他實施例中,所述第一線路層443設於所述第一基材層441與所述第一黏接層36之間。
The difference from other embodiments is that the third
S206:請參見圖23,蝕刻所述第二結構本體61之部分所述第五銅箔層612以形成第二內側線路層613。
S206: Referring to FIG. 23, part of the fifth
S207:請參見圖24,於所述第二內側線路層613上設置第三黏接層64,以及於所述第三黏接層64上設置第三覆銅基板65。所述第三覆銅基板65包括第三基材層651及設於所述第三基材層651之第四銅箔層652。所述第三基材層651設於所述第四銅箔層652與所述第三黏接層64之間。所述第三覆銅基板65貫穿設有第一通孔653與第二通孔654。所述第一通孔653與所述第二通孔654沿所述第三方向C貫穿所述第四銅箔層652與所述第三基材層651。
S207: Referring to FIG. 24, a third
其中,所述第一內側待移除體54、兩個所述第三導電極62穿過所述第一通孔653。所述第一內側待移除體54背離所述第一內側線路層521之一側與所述第三銅箔層53背離所述第三基材層651之一側平齊,所述第三黏接層64還填入所述第一通孔653與所述第三導電極62之間的隙內。同樣地,所述第二內側待移除體55、兩個所述第四導電極63穿過所述第二通孔654。所述第二內側待移除體55背離所述第一內側線路層521之一側與所述第三銅箔層53背離所述第三基材層651之一側平齊,所述第三黏接層64還填入所述第二通孔654與所述第四導電極63之間的隙內。
The first inner body to be removed 54 and the two third
S208:請參見圖25,蝕刻所述第三銅箔層53以形成第一外側線路層531,以及蝕刻所述第四銅箔層652以形成第二外側線路層655。
S208: Referring to FIG. 25 , the third
S209:請參見圖26,於所述第一外側線路層531上設置第一覆蓋膜66,以及於所述第二外側線路層655上設置第二覆蓋膜67。所述第一覆蓋膜66貫穿設有一個下開窗661,部分所述第二基材層51於所述下開窗661之底部露
出(第一外側線路層531具有線槽,第二基材層51於該線槽與所述下開窗661之底部露出),所述第二覆蓋膜67貫穿設有兩個上開窗671。
S209: Referring to FIG. 26, a
沿所述第三方向C,所述第一內側待移除體54之正向投影位於所述下開窗661內。一個所述上開窗671對應所述第一內側待移除體54設置,另一個所述上開窗671對應所述第二內側待移除體55設置。
Along the third direction C, the front projection of the first inner body to be removed 54 is located in the
S210:請參見圖27,於所述下開窗661內設置第二彈性連接體70,所述第二彈性連接體70包括第二彈性部分71、第三連接部分72以及第四連接部分73。所述第二彈性部分71連接於所述第三連接部分72與所述第四連接部分73之間。所述第二彈性部分71連接於露出所述下開窗661之部分所述第二基材層51。所述第三連接部分72與所述第四連接部分73連接所述第一覆蓋膜66與所述第二基材層51。
S210: Refer to FIG. 27 , a second
S211:請參見圖28,移除所述第一內側待移除體54以形成第一內側介電空間543,以及移除所述第二內側待移除體55以形成第二內側介電空間553。兩個所述第三導電極62及所述第一內側介電空間543構成一第三電容75。兩個所述第四導電極63及所述第二內側介電空間553構成一第四電容76。具體使用時,藉由外力拉伸所述第二彈性部分71,即可改變所述第一內側介電空間543之大小,進而改變所述第三電容75之電容值。
S211: Referring to Figure 28, remove the first inner body to be removed 54 to form a first
S212:請參見圖29,於所述第二內側介電空間553內設置第二填充體761,所述第二填充體761之材質為高介電常數、低介質損耗之聚醯亞胺,該聚醯亞胺作為介電材料可以提高所述第四電容76之穩定性。
S212: Please refer to Figure 29. A
S213:請參見圖30,去除所述第一內側介電空間543對應之部分所述第二基材層51,獲得所述內嵌電容之電路板300。其中,去除部分所述第二基材層51可以部分第二彈性連接體70之拉伸或者壓縮。
S213: Referring to FIG. 30 , remove the portion of the second
另外,請參見一併參見圖23與圖30,本申請還提供一種內嵌電容之電路板300,所述內嵌電容之電路板300包括第二線路結構60,所述第二線路結構60包括第二結構本體61、兩個第三導電極62、以及兩個第四導電極63。兩個所述第三導電極62相對間隔設於所述第二結構本體61之一側。兩個所述第四導電極63相對間隔設於所述第二結構本體61之一側。
In addition, please refer to Figure 23 and Figure 30 together. The present application also provides a
所述第二結構本體61貫穿設有第三開口61a。所述第三開口61a設於兩個所述第三導電極62之間以形成第一內側介電空間543。兩個所述第三導電極62及所述第一內側介電空間543形成第三電容75。
The second
所述第二結構本體61貫穿設有第四開口61b。所述第四開口61b設於兩個所述第四導電極63之間以形成第二內側介電空間553。兩個所述第四導電極63及所述第二內側介電空間553形成第四電容76。
The second
另外,本技術領域之普通技術人員應當認識到,以上之實施方式僅是用以說明本發明,而並非用作為對本發明之限定,僅要於本發明之實質精神範圍之內,對以上實施例所作之適當改變與變化均落於本發明要求保護之範圍之內。 In addition, those of ordinary skill in the art should realize that the above embodiments are only used to illustrate the present invention and are not used to limit the present invention. Only within the scope of the essential spirit of the present invention, the above embodiments Appropriate changes and changes are made within the scope of protection claimed by the present invention.
200:電路板 200:Circuit board
45:第一彈性連接體 45: First elastic connector
451:第一彈性部分 451: First elastic part
452:第一連接部分 452: First connection part
453:第二連接部分 453: Second connection part
362:第一黏接片 362: First bonding piece
41:第一結構本體 41:First structural ontology
40:第一線路結構 40: First line structure
36:第一黏接層 36: First bonding layer
101:第一電容 101: First capacitor
42:第一導電極 42: First conductive electrode
102:第二電容 102: Second capacitor
43:第二導電極 43: Second conductive electrode
212:第二外側介電空間 212: Second outer dielectric space
47:第一防焊層 47: First solder mask
443:第一線路層 443: First line layer
411:第一開口 411:First opening
48:第一填充體 48: First filling body
363:第二黏接片 363:Second bonding piece
46:第一覆蓋膜 46:First covering film
211:第一外側介電空間 211: First outer dielectric space
A:第一方向 A:First direction
B:第二方向 B:Second direction
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202210726745.0A CN117336964A (en) | 2022-06-23 | 2022-06-23 | Circuit board with embedded capacitor and manufacturing method thereof |
CN202210726745.0 | 2022-06-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202402114A TW202402114A (en) | 2024-01-01 |
TWI830291B true TWI830291B (en) | 2024-01-21 |
Family
ID=89274273
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111126763A TWI830291B (en) | 2022-06-23 | 2022-07-15 | Circuit board with embedded capacitance and manufacturing method thereof |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN117336964A (en) |
TW (1) | TWI830291B (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200845843A (en) * | 2006-12-21 | 2008-11-16 | Nippon Mektron Kk | Method for manufacturing printed circuit board with built-in capacitor |
CN101364587A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Circuit board construction for embedding capacitor element and preparation thereof |
CN102595786A (en) * | 2012-02-20 | 2012-07-18 | 电子科技大学 | Printed circuit board with embedded capacitor and manufacturing method of printed circuit board |
TW201347628A (en) * | 2012-01-04 | 2013-11-16 | Samsung Electro Mech | Printed circuit board having embedded capacitor and method of manufacturing the same |
-
2022
- 2022-06-23 CN CN202210726745.0A patent/CN117336964A/en active Pending
- 2022-07-15 TW TW111126763A patent/TWI830291B/en active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200845843A (en) * | 2006-12-21 | 2008-11-16 | Nippon Mektron Kk | Method for manufacturing printed circuit board with built-in capacitor |
CN101364587A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Circuit board construction for embedding capacitor element and preparation thereof |
TW201347628A (en) * | 2012-01-04 | 2013-11-16 | Samsung Electro Mech | Printed circuit board having embedded capacitor and method of manufacturing the same |
CN102595786A (en) * | 2012-02-20 | 2012-07-18 | 电子科技大学 | Printed circuit board with embedded capacitor and manufacturing method of printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
CN117336964A (en) | 2024-01-02 |
TW202402114A (en) | 2024-01-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW547000B (en) | A method for forming a printed circuit board and a printed circuit board formed thereby | |
US20090084583A1 (en) | Multilayer printed wiring board and method for fabrication thereof | |
WO2021004459A1 (en) | Embedded circuit board and fabrication method therefor | |
CN109429443B (en) | Manufacturing method of rigid-flexible circuit board | |
TWI478642B (en) | Printed circuit board with embedded component and method for manufacturing same | |
TWI296492B (en) | Un-symmetric circuit board and method for fabricating the same | |
WO2009131182A1 (en) | Flex-rigid wiring board and method for manufacturing the same | |
KR101701380B1 (en) | Device embedded flexible printed circuit board and manufacturing method thereof | |
CN105210462A (en) | Method for manufacturing component-embedded substrate, and component-embedded substrate | |
TWI830291B (en) | Circuit board with embedded capacitance and manufacturing method thereof | |
US20140182899A1 (en) | Rigid-flexible printed circuit board and method for manufacturing same | |
CN109788664B (en) | Circuit substrate and manufacturing method thereof | |
WO2004017689A1 (en) | Multilayer printed wiring board and production method therefor | |
US11665831B2 (en) | Method for manufacturing a circuit board with embedded nickel resistor | |
KR20150083424A (en) | Method for manufacturing wiring board | |
TWI615075B (en) | Flexible circuit board and manufacturing method for same | |
KR100482822B1 (en) | Method of manufacturing capacitor-embedded printed circuit board | |
US7992290B2 (en) | Method of making a flexible printed circuit board | |
JP2017208371A (en) | Circuit board, manufacturing method of circuit board, and electronic device | |
KR20040107359A (en) | Manufacturing method of semiconductor device | |
CN112423472A (en) | Rigid-flexible circuit board and manufacturing method thereof | |
JP3871910B2 (en) | Flexible printed circuit board having cable and manufacturing method thereof | |
CN101038881A (en) | Method for manufacturing substrate | |
CN114793314B (en) | Microphone reinforced flexible circuit board and preparation method thereof | |
WO2019074312A1 (en) | Method for fabricating printed circuit board and printed circuit board fabricated thereby |