TWI821152B - Storage device, flash memory control and control method thereo - Google Patents

Abstract

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method comprises the steps of: receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; and determining quantity of blocks within each block according to a size of each zone and a size of each block within the flash memory module.

Description

Storage device, flash memory controller and control method thereof

The present invention relates to flash memory.

In the Non-Volatile Memory Express (NVMe) specification, a zoned namespace is standardized. However, since the above zoned namespace and each zone in it are purely based on the master device, From a perspective, therefore, the size of each area defined by the main device does not have a fixed relationship with the size of each block in the flash memory module of the storage device. Therefore, when the main device When preparing to write data corresponding to an area to the flash memory module, the flash memory controller will need to create a large number of mapping tables between logical addresses and physical addresses, for example, in data pages (pages). To record the mapping relationship between logical addresses and physical addresses, thus causing a burden on the flash memory controller in data processing, and also occupying Static Random Access Memory (Static Random Access Memory, SRAM) and/or The storage space of Dynamic Random Access Memory (DRAM).

Therefore, one of the objectives of the present invention is to provide a flash memory controller that can efficiently manage the data written by the host device to the regional namespace in the flash memory module, and the established logic The address to physical address mapping table has a smaller size to solve the problems described in the prior art.

In one embodiment of the present invention, a control method applied to a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory module The group includes multiple data planes, each data plane includes multiple blocks, and each block includes multiple data pages, and the control method includes: receiving a setting command from a master device, wherein the setting The instruction is to set at least a part of the flash memory module as a region namespace, wherein the region namespace logically includes multiple regions, and the master device must write and access data in the region namespace. It must be done in units of areas. The size of each area is the same. The logical addresses corresponding to each area must be continuous, and there will be no overlapping logical addresses between areas. For this area The namespace is configured to plan a plurality of first super blocks, where each first super block includes a plurality of blocks located in at least two data planes, and each first super block includes The number of blocks is determined based on the size of each area and the size of each block; receiving data corresponding to a specific area from the main device, where the data is all data in the specific area; according to the The sequence of the logical addresses of the data is used to sequentially write the data into a specific first super block among the plurality of first super blocks of the flash memory module; and when the data is completed writing After entering, write invalid data to the remaining data pages of the last block included in the specific first super block, or keep the remaining data pages blank and do not write according to the write command of the master device before erasing. Import data from this master device.

In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory module includes Multiple data planes, each data plane includes multiple blocks, and each block includes multiple data pages, and the flash memory controller includes: a read-only memory used to store a program code; a microprocessor for executing the code to control access to the flash memory module; and a buffer memory. The microprocessor receives a setting command from a host device, wherein the setting command sets at least a portion of the flash memory module as a region namespace, wherein the region namespace logically includes a plurality of regions. , the master device must write and access data in the area namespace in units of areas. The size of each area is the same, and the logical addresses corresponding to each area must be continuous. And there will be no overlapping logical addresses between areas; the microprocessor configures the area namespace to plan a plurality of first super blocks, where each first super block contains at least Multiple blocks within the two data planes, and the number of blocks included in each first super block is determined based on the size of each area and the size of each block; the microprocessor receives The main device corresponds to data in a specific area, where the data is all the data in the specific area, and the microprocessor writes the data to the flash in sequence according to the order of the logical addresses of the data. In a specific first super block among the plurality of first super blocks of the memory module; and after the data is completely written, the microprocessor writes the last one included in the specific first super block. Invalid data is written to the remaining data pages of the block, or the remaining data pages are kept blank and data from the master device is not written according to the write command of the master device before erasing.

In another embodiment of the present invention, a storage device is disclosed, which includes a flash memory module and a flash memory controller, wherein the flash memory module includes a plurality of data planes, each A data plane includes multiple blocks, and each block includes multiple data pages, and the flash memory controller is used to access the flash memory module. The flash memory controller receives a setting command from a host device, wherein the setting command sets at least a portion of the flash memory module as a region namespace, wherein the region namespace logically includes For multiple areas, the master device must write and access data in the area namespace in units of areas. The size of each area is the same, and the logical address corresponding to each area must be Continuous, and there will be no overlapping logical addresses between regions; wherein the flash memory controller configures the region namespace to plan a plurality of first super blocks, each of which is A block includes multiple blocks located in at least two data planes, and the number of blocks included in each first super block is determined based on the size of each area and the size of each block; The flash memory controller receives data corresponding to a specific area from the host device, where the data is all data in the specific area, and the flash memory controller is based on the order of logical addresses of the data, to sequentially write the data into a specific first super block among the plurality of first super blocks of the flash memory module; and after the writing of the data is completed, the flash memory The controller writes invalid data to the remaining data pages of the last block included in the specific first super block, or keeps the remaining data pages blank and does not write according to the write command of the host device before erasing. Data from this master device.

Figure 1 is a schematic diagram of an electronic device 100 according to an embodiment of the present invention. As shown in Figure 1, the electronic device includes a main device 110 and a plurality of storage devices 120_1~120_N. Each storage device, taking the storage device 120_1 as an example, includes a flash memory controller 122 and a flash memory controller 122. Flash memory module 124. In this embodiment, each of the plurality of storage devices 120_1 ~ 120_N can be a solid-state drive (SSD) or any storage device with a flash memory module, and the main device can be a The central processing unit or other electronic devices or components can be used to access the storage devices 120_1~120_N, and the electronic device 100 itself can be a server, a personal computer, a notebook computer or any portable electronic device. It should be noted that although Figure 1 depicts multiple storage devices 120_1~120_N, in an embodiment, the electronic device 100 may only have a single storage device 120_1.

Figure 2A is a schematic diagram of the flash memory controller 122 in the storage device 120_1 according to an embodiment of the present invention. As shown in Figure 2A, the flash memory controller 122 includes a microprocessor 212, a read only memory (Read Only Memory, ROM) 212M, a control logic 214, a buffer memory 216 and an interface logic 218. . The read-only memory 212M is used to store a program code 212C, and the microprocessor 212 is used to execute the program code 212C to control access to the flash memory module 124. The control logic 214 includes an encoder 232 and a decoder 234. The encoder 232 is used to encode the data written into the flash memory module 220 to generate a corresponding check code (or error correction code). (Error Correction Code, ECC), and the decoder 234 is used to decode the data read from the flash memory module 124 .

In a typical situation, the flash memory module 124 includes multiple flash memory chips, and each flash memory chip includes a plurality of blocks, and the flash memory controller 122 controls the flash memory. The memory module 124 performs the data erasing operation on a block basis. In addition, a block can record a specific number of data pages (pages), and the flash memory controller 122 writes data to the flash memory module 124 in units of data pages. In this embodiment, the flash memory module 124 is a 3D NAND-type flash module.

In practice, the flash memory controller 210 that executes the program code 212C through the microprocessor 212 can use its own internal components to perform many control operations, such as using the control logic 214 to control the flash memory module 124 Access operations (especially access operations to at least one block or at least one data page), use the buffer memory 216 to perform required buffering processing, and use the interface logic 218 to communicate with the host device 110 . The buffer memory 216 is implemented as random access memory (Random Access Memory, RAM). For example, the buffer memory 216 may be SRAM, but the present invention is not limited thereto. In addition, the flash memory controller 122 is coupled to a DRAM 240 . Please note that the DRAM 240 may also be included within the flash memory controller 122 , for example, in the same package as the flash memory controller 122 .

In this embodiment, the storage device 120_1 supports the NVMe standard, that is, the interface logic 218 can comply with a specific communication standard (such as the Peripheral Component Interconnect (PCI) standard or the PCIe standard), and can be based on the specific communication standard. Communicate with the host device 110 through a standard, such as a connector.

Figure 2B is a schematic diagram of a block 200 in the flash memory module 124 according to an embodiment of the present invention, where the flash memory module 124 is a three-dimensional NAND flash memory. As shown in Figure 2B, the block 200 includes a plurality of memory cells (such as the floating gate transistor 202 shown in the figure or other charge trap elements), which pass through a plurality of bit lines (only the floating gate transistor 202 shown in the figure). BL1~BL3) and multiple word lines (such as WL0~WL2, WL4~WL6 shown in the figure) are shown to form a three-dimensional NAND flash memory architecture. In Figure 2B, taking the top plane as an example, all the floating gate transistors on the word line WL0 constitute at least one data page, and all the floating gate transistors on the word line WL1 constitute another at least one page of data. page, and all the floating gate transistors of word line WL2 constitute another at least one data page... and so on. In addition, depending on the flash memory writing method, the definition between word line WL0 and data page (logical data page) will also be different. Specifically, when using single-level storage (Single-Level Cell , SLC) method, all floating gate transistors on word line WL0 only correspond to a single logical data page; when writing using double-level storage (Multi-Level Cell, MLC) method, the character All floating gate transistors on line WL0 correspond to two logical data pages; when writing using three-level storage (TLC), all floating gate transistors on word line WL0 correspond to three logical data pages ; And when writing using the four-level storage (QLC) method, all floating gate transistors on the word line WL0 correspond to four logical data pages. Since those with ordinary knowledge in the art should be able to understand the structure of the three-dimensional NAND flash memory and the relationship between word lines and data pages, the relevant details will not be described again here.

In this embodiment, the host device 110 can set at least a part of the flash memory module 124 as a zoned namespace by sending a setting command set, such as a Zoned Namespaces Command Set. (zoned namespace). Referring to FIG. 3 , the host device 110 can send a setting instruction set to the flash memory controller 122 so that the flash memory module 124 has at least one region namespace (in this embodiment, the region namespace 310_1 , 310_2 as an example) and at least one general storage space (in this embodiment, general storage spaces 320_1 and 320_2 are taken as an example). The area namespace 310_1 will be divided into multiple zones (zones) for access, and the main device 110 must write data in the area namespace 310_1 in units of logical block addresses (LBA). To proceed, a logical block address (or simply logical address) can represent a data amount of 512 bytes, and the master device 110 needs to continuously write to an area. Specifically, referring to Figure 4, the area namespace 310_1 is divided into multiple areas (for example, Z0, Z1, Z2, Z3... etc.), the size of which is set by the main device 110, but each The sizes of the areas are all the same. The logical addresses corresponding to each area must be continuous, and there will be no overlapping logical addresses between areas (that is, a logical address will only exist in one area. within). For example, assume that the size of each area is x logical addresses, and the starting logical address of area Z3 is LBA_k, then area Z3 is used to store the data corresponding to logical addresses LBA_k, LBA_(k+1) , LBA_(k+2), LBA_(k+3),..., LBA_(k+x-1) information. In one embodiment, the logical addresses of adjacent areas are also consecutive. For example, area Z0 is used to store data with logical addresses LBA_1~LBA_2000, and area Z1 is used to store data with logical addresses LBA_2001~LBA_4000. Area Z2 is used to store data with logical addresses LBA_4001~LBA_6000, area Z3 is used to store data with logical addresses LBA_6001~LBA_8000, and so on. In addition, the data size corresponding to a logical address can be determined by the host device 110. For example, the data size corresponding to a logical address can be 4 kilobytes (KB).

In addition, when writing data in each area, it must be done in the order of logical addresses. Specifically, the flash memory controller 122 sets a write point (write point) according to the written data to control the writing sequence of the data. Specifically, it is assumed that area Z1 is used to store data with logical addresses LBA_2001~LBA_4000, and when the host device 110 transmits data corresponding to logical addresses LBA_2001~LBA_2051 to the flash memory controller 122, the flash memory The bank controller 122 will set the write pointer to the next logical address LBA_2052. If the master device 110 subsequently transmits data belonging to the same area but does not have the logical address LBA_2052, for example, the master device 110 transmits data with the logical address LBA_3000, the flash memory controller 122 will reject the data writing this time. and returns a write failure message to the host device 110; in other words, only when the logical address of the received data is the same as the logical address pointed to by the write pointer, the flash memory controller 122 will allow Write data. In addition, if data in multiple areas are written alternately, each area can have its own writing indicator.

As mentioned above, the main device 110 will communicate with the storage device 120_1 in units of areas to access the area namespace 310_1. However, since the area namespace 310_1 and each area are viewed from the perspective of the main device 110 , therefore, the size of each area defined by the main device 110 does not have a fixed relationship with the size of each physical block in the flash memory module 124 in the storage device 120_1. Specifically, the flash memory modules produced by different flash memory module manufacturers are different. Different memory modules have physical blocks of different sizes, and the sizes of these physical blocks are not the same. It is not necessarily an integer multiple. For example, the physical block size of model A flash memory module may be 1.3 times larger than that of model B flash memory module, while the size of the physical block of model C flash memory module may be 1.3 times larger than that of model B flash memory module. The physical block size of the group may be 3.7 times larger than the physical block of the B-type flash memory module. As a result, it will be very difficult to align the area set by the main device 110 with the physical block. . At this time, the flash memory controller 122 will face great difficulties when mapping logical blocks to physical blocks. For example, it may cause a lot of redundant space in the storage device 120_1 that cannot be used by the user, or when the host When the device 110 is preparing to write data corresponding to a region to the flash memory module 124, the flash memory controller 122 is added to establish a logical address to physical address (L2P) mapping. complexity on the table. In the following embodiments, the present invention proposes a method that allows the flash memory controller 122 to efficiently access the area namespace 310_1 according to the access instructions of the host device 110 .

Figure 5 is a flow chart for writing data from the main device 110 to the region namespace 310_1 according to an embodiment of the present invention. This embodiment assumes that the amount of data corresponding to each region is larger than the flash memory model. The size of each physical block in the group 124, and the amount of data corresponding to each area is not an integer multiple of the size of each physical block in the flash memory module 124. In step 500, the process begins. The main device 110 and the storage device 120_1 are powered on and complete the initialization operation. The main device 110 sets the size of each area, the number of areas, and the logical block address size for at least part of the storage areas in the storage device 120_1. and other basic settings, such as using the Zoned Namespaces Command Set. In step 502, the host device 110 sends a write command and corresponding data to the flash memory controller 122, where the data is data corresponding to one or more areas, such as area Z3 in Figure 4 corresponding to the logic Data at addresses LBA_k~LBA_(k+x-1). In step 504, the flash memory controller 122 selects at least one block (blank block, or spare block) from the flash memory module 124, and sequentially receives the data from the main device 110. Data is written sequentially into the at least one block. Since the area size set by the main device 110 is very difficult to be consistent with the size of the physical block, when the main device issues write instructions to all logical addresses in area Z3, the data to be written by the main device 110 usually still remains. The storage space of the physical block cannot be filled, or in other words, the data storage amount corresponding to an area is usually not an integral multiple of the size of the area in a physical block used to store data written by the main device 110 . In step 506, when the data is written to the last block and the data writing is completed, the flash memory controller 122 writes invalid data to the remaining data pages of the last block, or directly Keep the remaining data pages blank. Please note that each block usually reserves several data pages to store system management information, such as writing schedules, logical entity correspondence tables, and error correction code check bits. , disk array parity data (RAID parity) and other data required for management. The remaining data page referred to here refers to the remaining data after writing the system management information and the data to be stored by the main device 110. Information page.

For example, referring to FIG. 6 , assuming that the amount of data corresponding to each area is between two blocks and three blocks in the flash memory module 124 , the flash memory controller 122 can In response to the write command sent by the master device 110 for the area Z1, the data of the area Z1 is sequentially written into the blocks B3, B7 and B8. Please note that in one embodiment, the write command sent by the master device 110 for the area Z1 includes the starting logical address of the area Z1, and the flash memory controller 122 sets the starting logical address of the area Z1. The address corresponds to the starting physical storage space of the physical block B3, such as the first physical data page, and the flash memory controller 122 will store the data corresponding to the starting logical address of the area Z1 into the physical block. In the starting entity storage space of B3, such as the first entity data page. Blocks B3, B7, and B8 all include data pages P1~PM, and the data in area Z1 is written sequentially from the first data page P1 of block B3 to the last data page PM according to the logical address. , and after the data writing in block B3 is completed, writing continues from the first data page P1 of block B7 to the last data page PM. Please note that even if the master device 110 continuously writes to the logical addresses in the area Z1, the flash memory controller 122 can still select discontinuous blocks B3 and B7 to store the logically continuous data. After block B7 completes data writing, writing continues from the first data page P1 of block B8 until the end of the data in area Z1; in addition, the remaining data pages of block B8 will remain blank or be written. Invalid data entered. Similarly, the flash memory controller 122 can sequentially write the data of area Z3 into blocks B12, B99 and B6, where blocks B12, B99 and B6 all include data pages P1~PM, and area Z3 The data is written sequentially from the first data page P1 of block B12 to the last data page PM according to the logical address. After the completion of data writing in block B12, it continues from the first data page P1 of block B99. A data page P1 starts to be written to the last data page PM, and after the data writing is completed in block B99, writing continues from the first data page P1 of block B6 until the end of the data in area Z3; In addition, the remaining data pages of block B6 will remain blank or have invalid data written to them. Please note that the flash memory controller 122 may not establish a link relationship between the logical page and the physical page for the physical data page where the invalid data is located. The physical blocks with physical data pages that remain blank or have invalid data written to them are usually mapped to the last part of each area by the flash memory controller 122, or in other words, the flash memory controller 122 will Store the data corresponding to the last logical address of the area in a physical block with blank pages or written invalid page data. For example, as shown in Figure 7B (which will be described in detail later), the logical address Z1_LBA+S+2*y will correspond to the physical block address PBA8. And if the data of the last logical address of the area is stored in the Xth storage unit of a physical block (such as a physical storage page or section), then the X+1th storage unit of the physical block will Reserved bits are blank pages or invalid page data is written, that is, blank pages or data pages written with invalid data are continued after the physical storage unit where the data at the last logical address of the corresponding area is stored. In another embodiment, the main device 110 defines a larger zone size (Zone Size) and a smaller zone capacity (Zone capacity). For example, the zone size is 512MB and the zone capacity is 500MB. In this example , the flash memory controller 122 may not directly connect blank pages or data pages with invalid data written after the physical storage unit where the data at the last logical address of the corresponding area is stored.

In another embodiment, the master device 110 sends write commands to the consecutive logical addresses of areas Z1 and Z2, and the flash memory controller 122 selects blocks B3, B7, B8, B12, B99, and B6. To store data belonging to areas Z1 and Z2. Since the area size set by the device 110 is not consistent with the size of the physical block, the data to be written by the main device 110 still cannot fill the storage space of the physical block. For example, the physical block B8 cannot be filled for storage. The storage space of the host data, so the flash memory controller 122 still needs to leave the storage space in the physical block B8 blank or fill it with invalid data, so although the main device 110 targets the continuous logical bits in the areas Z1 and Z2 The flash memory controller 122 still does not store the data corresponding to the starting logical address of area Z2 in physical block B8 when the physical block B8 still has space to store data. In other words, even if the master device 110 sends write commands with consecutive logical addresses (for example, a write command including the last logical address of area Z1 and the first logical address of area Z2), and a certain A specific physical block (such as physical block B8) has enough space to store the data of the continuous logical addresses, and the flash memory controller 122 still does not continuously store the data corresponding to the continuous logical addresses in the In this specific physical block, the data corresponding to the first logical address of area Z2 is jumped and written into another physical block, such as block B20. Correspondingly, if the master device 110 sends a read command for consecutive logical addresses in areas Z1 and Z2 (for example, a read command including the last logical address of area Z1 and the first logical address of area Z2), After reading the data stored in the last logical address of the corresponding area Z1 in the physical block P8, the flash memory controller 122 will also jump to read the first storage location of the block B20 to obtain Data of the first logical address of area Z2.

In step 508, the flash memory controller 122 creates or updates an L2P mapping table to record the mapping relationship between logical addresses and physical addresses for subsequent use in reading data from the region namespace 310_1. Figure 7A is a schematic diagram of an L2P mapping table 700 according to an embodiment of the present invention. The L2P mapping table 700 includes two fields, one of which records the starting logical address of the area, and the other field records the physical block address of the block. Referring to Figure 6 at the same time, since the data of area Z1 is written to blocks B3, B7 and B8 in sequence, and the data of area Z3 is written to blocks B12, B99 and B6 in sequence, the L2P mapping table 700 records The starting logical address Z1_LBA_S of area Z1 and the physical block addresses PBA3, PBA7 and PBA8 of blocks B3, B7 and B8, and the starting logical address Z3_LBA_S of area Z3 and the blocks B12, B99 and B6 are recorded Physical block addresses PBA12, PBA99 and PBA6. For example, assuming that area Z1 is used to store data with logical addresses LBA_2001~LBA_4000, and area Z3 is used to store data with logical addresses LBA_6001~LBA_8000, then the starting logical address Z1_LBA_S of area Z1 is LBA_2001 , and the starting logical address Z3_LBA_S of area Z3 is LBA_6001. Please note that as long as the steps in the flow chart of writing data from the master device 110 to the region namespace 310_1 can achieve the same purpose, they do not have to be performed in a fixed order. For example, step 508 can be executed after step 502. , those familiar with this art should understand it under the teaching of the present invention. Please note that in this embodiment, each physical block only corresponds to one area. For example, blocks B3, B7, and B8 only correspond to area Z1, and blocks B12, B99, and B6 only correspond to area Z3. In other words, a single block only stores data in a single area. For example, blocks B3, B7, and B8 only store data corresponding to area Z1, and blocks B12, B99, and B6 only store data corresponding to area Z3.

In addition, if the host device 110 wants to reset an area, such as the area Z1, the flash memory controller 122 usually modifies the L2P mapping table 700 to set the physical block address corresponding to the area Z1. Delete the fields, for example, delete the physical block addresses PBA3, PBA7 and PBA8 in the L2P mapping table 700, which means that the host no longer needs the data stored in these physical blocks. The flash memory controller 122 can erase these physical blocks later. Please note that the physical block B8 stores the data that the main device 110 wants to store and the invalid data. Although the main device 110 wants to The reset area Z1 does not contain the invalid data. For management convenience, after receiving the reset command for area Z1 from the master device 110, the flash memory controller 122 will still delete the physical block address PBA8 in the L2P mapping table 700 as a whole, even if the master device 110 The area Z1 to be reset does not contain the invalid data stored in the physical block B8. Moreover, before erasing the physical block B8, the flash memory controller 122 will not move the invalid data not included in the reset command issued by the master device 110 to other physical blocks, but will The entire entity block is deleted directly.

In the above embodiment, the data stored in any physical block in the area namespace 310_1 must belong to the same area, that is, the corresponding logical bits of all the data stored in any one physical block addresses will belong to the same region. Moreover, the main device 110 can only write continuously to the logical addresses in one area. Therefore, the L2P mapping table 700 in this embodiment may only include the physical block address of the area namespace 310_1, and will not include any data page addresses. That is, the L2P mapping table 700 will not record any data in the block. Data page serial number or related data page information. In addition, the L2P mapping table 700 only records the starting logical address of each area. Therefore, the L2P mapping table 700 itself only has a small amount of data. Therefore, the L2P mapping table 700 can be resident in the buffer memory 216 or DRAM. 240 without causing too much burden on the storage space of the buffer memory 216 or the DRAM 240. Please note that since the main device 110 sets the area size and the number of areas, the starting logical address of each area is fixed, so the L2P mapping table 700 can be further simplified to one field, that is, only Entity block address field. The starting logical address field of the region can be represented by an entry in the table, such as the L2P mapping table 710 shown in Figure 7B, without actually storing the starting logical addresses of multiple regions.

In the above embodiment, the L2P mapping table 700 may only contain the physical block address of the area namespace 310_1, but not any data page address. However, in another embodiment, the L2P mapping table 700 may include the starting logical address of each area and the corresponding physical block address and the physical data page address of the first data page. Since an area in the L2P mapping table only contains one physical block address and one physical data page address, it only has a small amount of data.

Figure 7C is a schematic diagram of an L2P mapping table 720 according to an embodiment of the present invention. The L2P mapping table 720 includes two fields, one of which records the logical address, and the other field records the physical block address of the block. Referring to Figure 6 at the same time, since the data of area Z1 is written to blocks B3, B7 and B8 in sequence, and the data of area Z3 is written to blocks B12, B99 and B6 in order, the L2P mapping table 720 records The starting logical address Z1_LBA_S of area Z1 and the physical block address PBA3 of block B3, the logical address (Z1_LBA_S+y) of area Z1, the physical block address PBA7 of block B7, and the logical bit of area Z1 address (Z1_LBA_S+2*y) and the physical block address PBA8 of block B8, where the logical address (Z1_LBA_S+y) can be the first logical address of the data written to block B7 (i.e., corresponds to the logical address of the data page P1 of block B7), and the logical address (Z1_LBA_S+2*y) can be the first logical address of the data written to block B8 (that is, corresponding to the area The logical address of data page P1 of block B8); similarly, the L2P mapping table 720 records the starting logical address Z3_LBA_S of area Z3, the physical block address PBA12 of block B12, and the logical address (Z3_LBA_S) of area Z3. +y) and the physical block address PBA99 of block B99, and the logical address (Z3_LBA_S+2*y) of area Z6 and the physical block address PBA6 of block B6, where the logical address (Z3_LBA_S+y) It can be the first logical address of the data written to block B99 (that is, the logical address corresponding to the data page P1 of block B99), and the logical address (Z3_LBA_S+2*y) can be written The first logical address of the data entered into block B6 (that is, the logical address corresponding to the data page P1 of block B6). It should be noted that the above "y" can represent how many logical addresses of data can be stored in a block, especially the data that the main device 110 sends to the storage device 120_1 and hopes that the storage device 120_1 stores the data. Please note that after the main device 110 sets the area size and number of areas, the starting logical address of each area is fixed, and the starting logical address of each sub-area is also fixed, such as Z1_LBA_S, Z1_LBA_S+y , Z1_LBA_S+2*y, Z2_LBA_S, Z2_LBA_S+y, Z2_LBA_S+2*y... etc. Therefore, similarly, the L2P mapping table 720 can be further simplified to one field, that is, only the physical block position address field. The logical address field can be represented by an entry in the table without actually storing the starting logical addresses of multiple sub-regions, such as shown in the L2P mapping table 740 in Figure 7D.

It should be noted that the L2P mapping table 720 in this embodiment only contains the physical block address of the regional namespace 310_1, and does not include any data page addresses. That is, the L2P mapping table 720 does not record any blocks. The data page serial number or related data page information. In addition, the L2P mapping table 720 will only record the first logical address corresponding to each block. Therefore, the L2P mapping table 720 itself only has a small amount of data, so the L2P mapping table 720 can be resident in the buffer memory. memory 216 or DRAM 240 without causing too much burden on the storage space of the buffer memory 216 or DRAM 240. In one embodiment, the physical block address recorded in the above-mentioned L2P mapping table 720 can be additionally matched with the physical data page address of the first data page, and adding an additional physical data page address will not be practical. Storage space creates too much of a burden.

Figure 8 is a flow chart of reading data from the area namespace 310_1 according to an embodiment of the present invention. This embodiment assumes that the area namespace 310_1 has already stored the data of the areas Z1 and Z3 shown in Figure 6. In step 800, the process starts. The main device 110 and the storage device 120_1 are powered on and complete the initialization operation (for example, the boot process). In step 802, the master device 110 sends a read command to request reading data with a specific logical address. In step 804, the microprocessor 212 in the flash memory controller 122 determines which area the specific logical address belongs to, and calculates the logical address according to the L2P mapping table 700 or the L2P mapping table 720. Obtain a physical data page address corresponding to the specific logical address. Take the L2P mapping table 700 in Figure 7A as an illustration. Since the L2P mapping table 700 records the starting logical address of each area, and the number of logical addresses in each area is known, the microprocessor The processor 212 can know which area the specific logical address belongs to based on the above information. Take the embodiments of Figures 6 and 7A for illustration. Assume that the specific logical address is LBA_2500, and one area contains 2000 logical addresses. , the L2P mapping table 700 records that the starting logical address Z1_LBA_S of the area Z1 is LBA_2001, then the microprocessor 212 can determine that the specific logical address belongs to the area Z1. Then, the microprocessor 212 determines the specific logical address based on the difference between the specific logical address and the starting logical address Z1_LBA_S of the area Z1, and based on how much data at the logical address can be stored in each data page of the block. The physical data page address corresponding to a specific logical address. For the convenience of explanation, assuming that each data page in the block can only store data at one logical address, the gap between this specific logical address and the starting logical address Z1_LBA_S of area Z1 is 500 logical addresses. Then the microprocessor 212 can calculate that the specific logical address corresponds to the physical data page address of the 500th data page P500 of block B3. If the number of data pages of block B3 is less than 500, then the physical data page address of block B3 is determined by the block B3. Count from the first data page P1 of block B3 to the 500th data page to obtain the address of the physical data page located in block B7.

On the other hand, taking the L2P mapping table 720 in Figure 7B as an illustration, the L2P mapping table 720 records multiple logical addresses of an area, and these logical addresses correspond to blocks B3, B7, and B8 respectively. The first data page P1, therefore, the microprocessor 212 can know which area and which block the specific logical address belongs to based on the above information. Then, based on the difference between the specific logical address and the logical address of area Z1 (for example, Z1_LBA_S, (Z1_LBA_S+y) or (Z1_LBA_S+2y)), the microprocessor 212 then generates How much data can be stored at a logical address is determined by determining the address of the physical data page corresponding to the specific logical address. For the convenience of explanation, assuming that each data page in the block can only store data at one logical address, the gap between this specific logical address and the starting logical address Z1_LBA_S of area Z1 is 500 logical addresses. Then the microprocessor 212 can calculate that the specific logical address corresponds to the physical data page address of the 500th data page P500 of block B3.

In step 806, the microprocessor 212 reads the corresponding data from the area namespace 310_1 according to the physical block address and the physical data page address determined in step 804, and returns the read data. to the main device 110.

As mentioned above, through the contents described in the above embodiments, the flash memory controller 122 can still effectively complete the area naming while only establishing a small size L2P mapping table 700/710/720/730. Data writing and reading in space 310_1. However, in this embodiment, many remaining data pages of the physical blocks are wasted, such as blank or invalid data pages in the physical blocks B8 and B6. These remaining data pages will greatly reduce the usage. Although this method can reduce the management burden of the flash memory controller 122, it will also reduce the memory space available to the user, even in some extreme cases. , because the proportion of remaining data pages is too high, it may also cause the flash memory controller 122 to be unable to plan enough memory space for the user to use.

Figure 9 is a flow chart for writing data from the main device 110 to the region namespace 310_1 according to another embodiment of the present invention. This embodiment assumes that the amount of data corresponding to each region is larger than the flash memory. The size of each block in the module 124, and the amount of data corresponding to each area is not an integer multiple of the size of each block in the flash memory module 124. In step 900, the process begins. The main device 110 and the storage device 120_1 are powered on and complete the initialization operation. The main device 110 sets basic settings such as the size of each area, the number of areas, and the size of the logical block address for the storage device 120_1, such as Set using the Zoned Namespaces Command Set. In step 902, the host device 110 sends a write command and corresponding data to the flash memory controller 122, where the data is data corresponding to one or more areas. For example, area Z3 in Figure 4 corresponds to a logical bit. The data of address LBA_k~LBA_(k+x-1). In step 904, the flash memory controller 122 selects at least one block (blank block, or spare block) from the flash memory module 124, or selects at least one blank block or at least a common block. blocks, and sequentially writes the data of the master device 110 into these blocks. For example, referring to Figure 10, assuming that the amount of data corresponding to each area is between two blocks and three blocks in the flash memory module 124, the flash memory controller 122 can Write the data of area Z1 to blocks B3, B7 and B8 in sequence. Block B3 records the first part of the data Z1_0 of area Z1, and block B7 records the second part of the data Z1_1 of area Z1. , and block B8 records the third part of data Z1_2 in area Z1. In this embodiment, since the data stored in blocks B3 and B7 are completely the data of area Z1, and only part of the data pages of block B8 store the data of area Z1, in order to make full use of the remaining data of block B8, data page, so the microprocessor 212 will set block B8 as a shared block, that is, the remaining data pages of block B8 can be used to store data in other areas. Continuing to refer to Figure 10, the flash memory controller 122 is preparing to write the data of area Z3 to the area name space 310_1. Since there is still space left in the shared block B8, the microprocessor 212 selects two empty blocks B12. , B99 and shared block B8 to store the data of area Z3. Specifically, the flash memory controller 122 writes the data in area Z3 to blocks B12, B99, and B8 in sequence, where block B12 records the first part of data Z3_0 in area Z3, and the data in block B99. What is recorded is the second part of data Z3_1 of area Z3, and what is recorded in block B8 is the third part of data Z3_2 of area Z3. In this embodiment, the data stored in blocks B12 and B99 are completely the data of area Z3, while block B8 simultaneously records the third part of data Z1_2 of area Z1 and the third part of data Z3_2 of area Z3. Please note that for the convenience of management, the flash memory controller 122 will not store the first data of any area into the common block, because this will increase the number of steps the flash memory controller 122 needs to create the L2P mapping table. on the complexity. The flash memory controller 122 will store the first data of each area in dedicated blocks, such as blocks B3 and B12. These exclusive blocks will only store data belonging to the same area, so they are called exclusive blocks. The last piece of data in any area (the data corresponding to the last logical address of the area) will be stored in a shared block, such as block B8, and the last piece of data in another area will also be stored in this shared block. material. In this embodiment, the shared block stores data of more than one area, or the shared block stores the last data of more than one area, while the dedicated block only stores data of a single area.

In step 906, the flash memory controller 122 creates or updates an L2P mapping table to record the mapping relationship between the logical address and the physical address, and records a common block table for subsequent data processing from the regional namespace 310_1. Used when reading. Figure 11A is a schematic diagram of an L2P mapping table 1100A and a shared block table 1130A according to an embodiment of the present invention. The L2P mapping table 1100A includes two fields, one of which records the logical address, and the other field records the physical block address of the block. Referring to Figure 10 at the same time, since the data of area Z1 is written to blocks B3, B7, and B8 in sequence, and the data of area Z3 is written to blocks B12, B99, and B8 in order, the L2P mapping table 1100A records The starting logical address Z1_LBA_S of area Z1 and the physical block address PBA3 of block B3, the logical address (Z1_LBA_S+y) of area Z1, the physical block address PBA7 of block B7, and the logical bit of area Z1 address (Z1_LBA_S+2*y) and the physical block address PBA8 of block B8, where the logical address (Z1_LBA_S+y) can be the first logical address of the data written to block B7 (i.e., The first logical address of the second part of data Z1_1, and is also the logical address corresponding to the first data page P1 of block B7), and the logical address (Z1_LBA_S+2*y) can be written to the area The first logical address of the data of block B8 (that is, the first logical address of the third part of data Z1_2); similarly, the L2P mapping table 1100A records the starting logical address Z3_LBA_S and the block of area Z3 The physical block address PBA12 of B12, the logical address of area Z3 (Z3_LBA_S+y) and the physical block address PBA99 of block B99, and the logical address of area Z6 (Z3_LBA_S+2*y) and block B6 The physical block address PBA6, where the logical address (Z3_LBA_S+y) can be the first logical address of the data written to block B99 (that is, the first logical address of the second part of the data Z3_1 , and is also the logical address corresponding to the first data page P1 of block B99), and the logical address (Z3_LBA_S+2*y) can be the first logical address of the data written to block B8 ( That is, the first logical address of the third part of data Z3_2). It should be noted that the above "y" can be expressed as how many pieces of data from the host's logical address can be stored in a block. Please note that after the main device 110 sets the area size and number of areas, the starting logical address of each area is fixed, and the starting logical address of each sub-area is also fixed, such as Z1_LBA_S, Z1_LBA_S+y , Z1_LBA_S+2*y, Z2_LBA_S, Z2_LBA_S+y, Z2_LBA_S+2*y... etc. Therefore, similarly, the L2P mapping table 1100 can be further simplified to one field, that is, only the physical block position address field. The logical address field can be represented by an entry in the table without actually storing the starting logical addresses of multiple sub-regions. Please refer to the L2P mapping table 1100B in Figure 11B. Each logical address of the L2P mapping table 1100B has a fixed field, which is sorted from the lowest to the highest logical address (or highest to lowest). For example, Z0_LBA_S represents area 0. The starting logical address is the lowest logical address in the system. Z0_LBA_S+y represents the starting logical address of the second sub-area of area 0, where y represents the number of addresses used to store host data in each physical block. Z0_LBA_S+2*y represents the starting logical address of the third sub-area of area 0. Since the area size is fixed and the y value is also fixed, the value in the logical address field in Figure 11B is quite predictable. Therefore, this field can also be omitted and represented only by the entry of the L2P mapping table 1100B.

In addition, the shared block table 1130A includes two fields, one of which records the logical address, and the other field records the physical block address and physical data page address corresponding to the logical address. In Figure 11A, the shared block table 1130A records the first logical address (Z1_LBA_S+2*y) of the third part of the data Z1_2 in the area Z1 and the corresponding physical block address PBA8 and the physical data page address. P1, that is, the data corresponding to the first logical address in the third part of data Z1_2 is written in the first data page P1 of block B8; and the shared block table 1130A records the third part of data Z3_2 of area Z3 The first logical address (Z3_LBA_S+2*y) and the corresponding physical block address PBA8 and physical data page address P120, that is, the data corresponding to the first logical address in the third part of data Z3_2 is The 120th data page P120 written in block B8 (note that this assumes that each data page in the block can only store data at one logical address. The actual situation can be based on what one data page can store. How many logical address data to adjust accordingly). Similar to the L2P mapping table 1100B in Figure 11B, the shared block table 1130A in Figure 11A is also presented in the form of the shared block table 1130B in Figure 11B. The reasons are the same and will not be repeated here.

In addition, it should be noted that during the writing process of the data in area Z1 and area Z3, the writing process may not start writing the data in area Z3 to the area namespace after all the data in area Z1 is written. 310_1, in other words, it is possible that the flash memory controller 122 needs to start writing the data of area Z3 into the area namespace 310_1 before the data of area Z1 has been written. Therefore, in another embodiment of the present invention, the shared block table 1130 may additionally include a completion indicator field, which is used to indicate whether the data of the area has been completely written in the shared block. Referring to Figure 12, the shared block table 1230 shown in Figure 12 is a continuation of the embodiment of Figure 10. In Figure 12(a), after the third part of data Z1_2 in area Z1 is all written to the common block B8, the microprocessor 212 will modify the completion indicator from '0' to '1', and then the microprocessor 212 will When the processor 212 needs to write the third part of the data Z3_2 of the area Z3 to the area name space 310_1, since the completion indicator of the third part of the data Z1_2 of the area Z1 corresponding to the common block B8 is '1', the microprocessor 212 It can be determined that the common block B8 is currently available for data writing, so the third part of the data Z3_2 in the area Z3 is written into the common block B8, and the third part of the data Z3_2 and the corresponding physical block are recorded in the common block table 1230 address and physical data page address. On the other hand, in Figure 12(b), when the third part of data Z1_2 of area Z1 is being written to the common block B8, its corresponding completion indicator is '0' (representing the third part of area Z1 The three parts of data Z1_2 have not yet been fully written to the common block B8), and if at this time the microprocessor 212 needs to write the third part of the data Z3_2 of the area Z3 to the area name space 310_1, since it corresponds to the common block B8 If the completion indicator of the third part data Z1_2 in area Z1 is '0', the microprocessor 212 can determine that the common block B8 is currently unavailable for the third part data Z3_2 to write, so the microprocessor 212 selects another blank block. (for example, block B15), and write the third part of data Z3_2 of area Z3 into block B15, and record the three parts of data Z3_2 and the corresponding physical block address PBA15 and physical data in the common block table 1230 Page address P1. Please note that the shared block table 1230 in Figure 12 is also presented in a form similar to the shared block table 1130B in Figure 11B with the completion indicator field added, replacing the logical address with a fixed logical address location. The reason for the field is the same as that of the L2P mapping table 1100B and the shared block table 1130B, and will not be described again here.

In one embodiment, if the master device 110 wants to reset an area, such as the area Z1, the flash memory controller 122 usually modifies the L2P mapping table 1100A/1100B to change the physical area corresponding to the area Z1. The field of the block address is deleted, for example, deleting the physical block addresses PBA3, PBA7, and PBA8 in the L2P mapping table 1100A/1100B, which means that the host no longer needs the data stored in these physical blocks. The flash memory controller 122 can erase these physical blocks later. Please note that the physical block B8 stores the data to be stored by the main device 110 and the data of the area Z3. Although the main device 110 The area Z1 to be reset does not contain the data of area Z3. For management convenience, after receiving the reset command for area Z1 from the master device 110, the flash memory controller 122 still needs to modify the physical block address and physical data in the common block table 1130A/1130B/1230. For the page address, delete PBA8 and P1, for example, rewrite it as FFFF. Please note that the completion indicator in the common block table 1230 still remains at 1 because the third part of the area Z1 still occupies part of the space Z1_3 in the physical block B8. Before the physical block B8 is erased, the These spaces can no longer be written to. Furthermore, before erasing the physical block B8, the flash memory controller 122 does not need to move the valid data (such as the data in the area Z3) that is not included in the reset command issued by the host device 110 to other entities. Block to go.

In the above embodiments, since a common block is used to store data corresponding to different areas, it can be regarded that data with logical addresses belonging to different areas can be stored in the same physical block, so physical blocks can be effectively used. The space of the block is to avoid the inconsistency between the area size and the physical block size. When the logical address corresponding to an area has been completely written, it still cannot fill the space of an integer physical block, resulting in physical The remaining data pages in the block do not store data, causing waste.

It should be noted that the L2P mapping table 1100A/1100B in this embodiment only contains the physical block address of the area namespace 310_1, and does not contain any data page address. That is, the L2P mapping table 1100A/1100B does not Record the data page serial number or related data page information in any block. In addition, the common block table 1130A/1130B/1230 will only record a small number of logical addresses. Even because the logical addresses of the common block table 1130A/1130B/1230 are extremely regular, the logical address field can be omitted. Represented only by table entries. Therefore, the L2P mapping table 1100A/1100B and the common block table 1130A/1130B/1230 themselves only have a small amount of data, so the L2P mapping table 1100A/1100B and the common block table 1130A/1130B/1230 can reside in the buffer memory 216 or DRAM 240 without causing too much burden on the storage space of the buffer memory 216 or DRAM 240.

In addition, because the physical block addresses corresponding to the last part of the fields in the area such as (Z1_LBA_S+2*y), (Z3_LBA_S+2*y)... of the L2P mapping table 1100A/1100B are not accurate physical locations, address, the microprocessor 212 needs to find the correct physical page address by searching the common block table 1130A/1130B/1230. Therefore, (Z1_LBA_S+2*y) and (Z3_LBA_S of the L2P mapping table 1100A/1100B can also be +2*y)... Wait until the entity address corresponding to the last part of the field in the area, such as PBA8, is directly changed to the entry address corresponding to the common block table 1130A/1130B/1230, allowing the microprocessor 212 to directly store Get the entry address corresponding to the common block table 1130A/1130B/1230. For example, directly change the PBA8 corresponding to the (Z1_LBA_S+2*y) field in the L2P mapping table 1100A/1100B to the memory address corresponding to the (Z1_LBA_S+2*y) field in the common block table 1130A/1130B, and change the L2P The PBA8 corresponding to the (Z3_LBA_S+2*y) field in the mapping table 1100A/1100B is directly changed to the memory address corresponding to the (Z3_LBA_S+2*y) field in the common block table 1130A/1130B (for example, in DRAM or address in SRAM) to speed up the search speed.

Figure 13 is a flow chart of reading data from the area namespace 310_1 according to an embodiment of the present invention. This embodiment assumes that the area namespace 310_1 has already stored the data of the areas Z1 and Z3 shown in Figure 10. In step 1300, the process starts. The main device 110 and the storage device 120_1 are powered on and complete the initialization operation (for example, the boot process). In step 1302, the master device 110 sends a read command to request to read data with a specific logical address. In step 1304, the microprocessor 212 in the flash memory controller 122 determines which area the specific logical address belongs to, and determines the area according to the L2P mapping table 1100A/1100B and/or the common block table 1130A/1130B/1230 The recorded logical address is used to calculate a physical data page address corresponding to the specific logical address. Take the L2P mapping table 1100A in Figure 11A as an illustration. The L2P mapping table 1100A records multiple logical addresses in multiple areas, and these logical addresses correspond to the numbers of blocks B3, B7, and B8 respectively. The data page and the number of logical addresses that can be stored in each block are known. Therefore, the microprocessor 212 can know which area and which block the specific logical address belongs to based on the above information. Next, assuming that the specific logical address belongs to the area Z1, the microprocessor 212 determines the relationship between the specific logical address and the logical address of the area Z1 (for example, Z1_LBA_S, (Z1_LBA_S+y) or (Z1_LBA_S+2y)). The difference is determined based on how much data of the logical address can be stored in each data page of the block to determine the physical data page address corresponding to the specific logical address. For the convenience of explanation, assuming that each data page in the block can only store data at one logical address, the gap between this specific logical address and the starting logical address Z1_LBA_S of area Z1 is 500 logical addresses. And the specific logical address is between Z1_LBA_S and (Z1_LBA_S+y) (where y represents the number of addresses used to store host data in each physical block, and in this example y>500), then the microprocessor 212 can calculate that the specific logical address corresponds to the physical data page address of the 500th data page P500 of block B3. In this example, the microprocessor 212 divides the difference 500 by y to obtain a quotient of 0, The remainder is 500, then the microprocessor 212 can know that the physical block address corresponding to the specific logical address should be in the first entry of the L2P mapping table 1100A. After searching, the microprocessor 212 finds that the physical block address corresponding to the specific logical address should be in the first entry of the L2P mapping table 1100A. The physical block address is PBA3. Since the remainder is 500, the microprocessor 212 can know that the physical page address corresponding to the specific logical address is P500. Please note that in addition to using the physical page as the unit, it can also be addressed in smaller read units, such as Sector or 4Kbyte and other addressing units that comply with the NVMe specification; on the other hand, assuming that the specific logical address belongs to area Z3, the microprocessor 212 determines the specific logical address and the logical address of area Z3 according to the specific logical address. (For example, the difference between Z3_LBA_S, (Z3_LBA_S+y) or (Z3_LBA_S+2y)), and then based on how much data at the logical address can be stored in each data page of the block, the location of the specific logical address is determined. The corresponding address of the entity data page. For the convenience of explanation, it is assumed that each data page in the block can only store data at one logical address. The specific logical address is greater than (Z3_LBA_S+2y) and less than or equal to the maximum logical address of area Z3, and the specific logical address The gap between the address and the logical address of area Z3 (Z3_LBA_S+2y) is eighty logical addresses, then the microprocessor 212 can refer to the third part of the data Z3_2 of area Z3 recorded in the common block table 1130 corresponding to The physical data page address P120 is calculated, and the physical data page address corresponding to the two-hundredth data page P200 of the shared block B8 is calculated accordingly.

In step 1306, the microprocessor 212 reads the corresponding data from the area namespace 310_1 according to the physical block address and the physical data page address determined in step 1304, and returns the read data. to the main device 110.

As mentioned above, through the content described in the above embodiments, the flash memory controller 122 can only create a very small size of the L2P mapping table 1100A/1100B and the common data table 1130A/1130B/1230, and still can effectively complete the task. Data writing and reading of area namespace 310_1.

In the above embodiments of Figures 5 to 13, it is assumed that the amount of data corresponding to each area is larger than the size of each block in the flash memory module 124. However, the main device 110 can also store the data in each area. The corresponding amount of data is less than the size of each block in the flash memory module 124, and its related access methods are as follows.

Figure 14 is a flow chart for writing data from the main device 110 to the region namespace 310_1 according to another embodiment of the present invention. This embodiment assumes that the amount of data corresponding to each region is smaller than the flash memory. The size of each block in module 124. In step 1400, the process begins. The main device 110 and the storage device 120_1 are powered on and complete the initialization operation. The main device 110 sets basic settings such as the size of each area, the number of areas, and the logical block address size on the storage device 120_1, for example Set using the Zoned Namespaces Command Set. In step 1402, the host device 110 sends a write command and corresponding data to the flash memory controller 122, where the data is data corresponding to one or more areas, such as area Z3 in Figure 4 corresponding to the logic Data at addresses LBA_k~LBA_(k+x-1). In step 1404, the flash memory controller 122 selects at least one block (blank block, or spare block) from the area name space 310_1, and sequentially writes data from the master device 110 in logical address order. into the at least one block. In this embodiment, one block is only used to write data in a single area. Taking Figure 15 as an example, the flash memory controller 122 writes data in area Z0 to block B20 and area Z1. The data of area Z2 is written to block B30, the data of area Z2 is written to block B35,... and so on. In step 1406, after the data in each area is completely written, the flash memory controller 122 will write the remaining data pages in each block that are not used for system control into invalid data, or directly write the remaining data pages into invalid data. Maintain a blank state. Taking Figure 15 as an example, after the flash memory controller 122 writes all the data in area Z0 to block B20, the block will keep the remaining data pages of B20 blank or fill in invalid data. After writing all the data in area Z1 to block B30, the bank controller 122 will keep the remaining data pages of block B30 blank or fill in invalid data, and the flash memory controller 122 will write all the data in area Z2. After writing to block B35, the remaining data pages of block B35 will remain blank or filled with invalid data.

Please note that in one embodiment, the master device 110 sends write instructions to the consecutive logical addresses of areas Z0, Z1, and Z2, and the flash memory controller 122 selects blocks B20, B30, and B35 for Store data belonging to areas Z0, Z1, and Z2. Since the area size set by the device 110 is not consistent with the size of the physical block, the data to be written by the main device 110 still cannot fill the storage space of the physical block. For example, the physical block B20 cannot be filled for storage. The storage space of the host data, so the flash memory controller 122 still needs to leave these storage spaces in the physical block B20 blank or fill them with invalid data, so although the main device 110 targets the continuous logical bits in the areas Z0 and Z1 The flash memory controller 122 still does not store the data corresponding to the starting logical address of the area Z1 in the physical block B20 when the physical block B20 still has space to store data. In other words, even if the master device 110 sends write commands with consecutive logical addresses (for example, a write command including the last logical address of area Z0 and the first logical address of area Z1), and a certain A specific physical block (such as physical block B20) has enough space to store the data of the continuous logical addresses, and the flash memory controller 122 still does not continuously store the data corresponding to the continuous logical addresses in the In this specific physical block, the data corresponding to the first logical address of area Z1 is jumped to be written into another physical block, such as block B30. Correspondingly, if the master device 110 sends a read command for consecutive logical addresses in areas Z0 and Z1 (for example, a read command including the last logical address of area Z0 and the first logical address of area Z1), After reading the data stored in the last logical address of the corresponding area Z1 in the physical block B20, the flash memory controller 122 will also jump to read the first storage location of the block B30 to obtain Data of the first logical address of area Z1.

In step 1408, the flash memory controller 122 creates or updates an L2P mapping table to record the mapping relationship between logical addresses and physical addresses for subsequent use in reading data from the region namespace 310_1. Figure 16 is a schematic diagram of an L2P mapping table 1600 according to an embodiment of the present invention. The L2P mapping table 1600 includes two fields, one of which records the area number or related identifiable content, and the other field records the physical block address of the block. Referring to Figure 6 at the same time, since the data of areas Z0, Z1, and Z2 are written to blocks B20, B30, and B35 respectively, the L2P mapping table 1600 records the physical block addresses PBA20 and areas of area Z0 and block B20. The physical block address PBA30 of Z1 and block B30, and the physical block address PBA35 of area Z2 and block B35. In another embodiment, the above-mentioned area number is represented by the starting logical address of the area, or the block number can be linked to the starting logical address of the block through another lookup table. For example, suppose Area Z0 is used to store data with logical addresses LBA_1~LBA_2000, area Z1 is used to store data with logical addresses LBA_2001~LBA_4000, area Z2 is used to store data with logical addresses LBA_4001~LBA_6000, then the area The starting logical addresses of Z0, Z1, and Z2 are LBA_1, LBA_2001, and LBA_4001 respectively. Please note that in this embodiment, each physical block only corresponds to one area. For example, blocks B20, B30, and B35 only correspond to areas Z0, Z1, and Z2 respectively. In other words, a single block only stores data in a single area. For example, block B20 only stores data corresponding to area Z0, block B30 only stores data corresponding to area Z1, and block B35 only stores data corresponding to area Z2. .

In the above embodiment, the data stored in any physical block in the area namespace 310_1 must belong to the same area. That is, the logical addresses of all the data stored in any physical block will belong to same area. Therefore, the L2P mapping table 1600 in this embodiment may only include the physical block address of the area namespace 310_1, and will not include any data page addresses. That is, the L2P mapping table 1600 will not record any data in the block. Data page serial number or related data page information. In addition, the L2P mapping table 1600 only records the area number or starting logical address of each area. Therefore, the L2P mapping table 1600 itself only has a small amount of data, so the 2P mapping table 1600 can be resident in the buffer memory. 216 or DRAM 240 without causing too much burden on the storage space of the buffer memory 216 or DRAM 240. In one embodiment, the physical block address recorded in the above-mentioned L2P mapping table 1600 can be additionally matched with the physical data page address of the first data page, and adding an additional physical data page address will not be practical. Storage space creates too big a burden. Please note that after the main device 110 sets the area size and the number of areas, the starting logical address of each area is fixed. Therefore, similarly, the L2P mapping table 1600 can be further simplified into one field. That is, there is only the physical block address field. The logical address field can be represented by an entry in the table without actually storing the starting logical addresses of multiple areas.

In addition, if the host device 110 wants to reset an area, such as the area Z1, the flash memory controller 122 usually modifies the L2P mapping table 1600 to the physical block address corresponding to the area Z1. Delete the fields, for example, delete the physical block address PBA30 in the L2P mapping table 1600, which means that the host no longer needs the data stored in these physical blocks. The flash memory controller 122 can erase these physical blocks later. Please note that the physical block B30 stores the data that the main device 110 wants to store and the invalid data. Although the main device 110 wants to The reset area Z1 does not contain the invalid data. For management convenience, after receiving the reset command for area Z1 from the master device 110, the flash memory controller 122 will still delete the physical block address PBA30 in the L2P mapping table 1600 as a whole, even if the master device 110 The area Z1 to be reset does not contain the invalid data stored in the physical block B30. Moreover, before erasing the physical block B30, the flash memory controller 122 will not move the invalid data not included in the reset command issued by the master device 110 to other physical blocks, but will The entire entity block is deleted directly.

Figure 17 is a flow chart of reading data from the area namespace 310_1 according to another embodiment of the present invention. This embodiment assumes that the area namespace 310_1 has stored the areas Z0, Z1 and Z2 shown in Figure 15. material. In step 1700, the process starts. The main device 110 and the storage device 120_1 are powered on and complete the initialization operation (for example, the boot process). In step 1702, the master device 110 sends a read command to request reading of data with a specific logical address. In step 1704, the microprocessor 212 in the flash memory controller 122 determines which area the specific logical address belongs to, and calculates the specific logical address according to the logical address recorded in the L2P mapping table 1600. The corresponding address of an entity data page. Take the L2P mapping table 1600 in Figure 16 as an illustration. Since the L2P mapping table 1600 records the area number or starting logical address of each area, and the number of logical addresses in each area is known, Therefore, the microprocessor 212 can know which area the specific logical address belongs to based on the above information. For example, an area contains 2000 logical addresses. The microprocessor 212 determines the logical address that the host wants to access. (specific logical address) divided by 2000, the obtained quotient is the area where the specific logical address is located. The embodiments in Figures 15 and 16 are used for illustration. It is assumed that the microprocessor 212 converts the specific logical address After dividing by 2000, it is found that the quotient is 1, and it can be judged that the specific logical address belongs to area Z1. Then the microprocessor 212 determines the specific logical address according to the difference between the specific logical address and the starting logical address of area Z1 (the difference is also The microprocessor 212 divides the specific logical address by 2000), and then determines the data corresponding to the specific logical address based on how much data of the logical address can be stored in each data page of the block. The address of the entity data page. For the convenience of explanation, assume that each data page in the block can only store data at one logical address, and the difference between this specific logical address and the starting logical address of area Z1 is two hundred logical addresses, then The microprocessor 212 can calculate that the specific logical address corresponds to the physical data page address of the two hundredth data page of block B20.

In step 1706, the microprocessor 212 reads the corresponding data from the area namespace 310_1 according to the physical block address and the physical data page address determined in step 1704, and returns the read data. to the main device 110.

As mentioned above, through the contents described in the above embodiments, the flash memory controller 122 can still effectively complete the data of the area namespace 310_1 while only establishing a very small size of the L2P mapping table 700/720. writing and reading. However, in this embodiment, a large amount of physical block storage space is still wasted, such as blank or invalid data pages as shown in Figure 15.

Figure 18 is a flow chart for writing data from the master device 110 to the region namespace 310_1 according to another embodiment of the present invention. This embodiment assumes that the amount of data corresponding to each region is smaller than the flash memory. The size of each block in module 124. In step 1800, the process begins. The main device 110 and the storage device 120_1 are powered on and complete the initialization operation. The main device 110 sets basic settings such as the size of each area, the number of areas, and the size of the logical block address for the storage device 120_1, such as Set using the Zoned Namespaces Command Set. In step 1802, the host device 110 sends a write command and corresponding data to the flash memory controller 122, where the data is data corresponding to one or more areas, such as area Z3 in Figure 4 corresponding to the logic Data at addresses LBA_k~LBA_(k+x-1). In step 1804, the flash memory controller 122 selects at least one block (blank block, or spare block) from the area name space 310_1, or selects multiple blank blocks and a common block, and The data of the master device 110 is sequentially written into these blocks according to the logical address sequence within a region. For example, referring to FIG. 19, the flash memory controller 122 can sequentially write the data of areas Z0, Z2, and Z1 into blocks B20 and B30 in logical address order. Taking Figure 19 as an example, the first data in area Z0 is written starting from the first data page of block B20. After all the data in area Z0 is written, please refer to the L2P mapping table in Figure 20. In 2000, the table will be described in detail below. The flash memory controller 122 changes the available index corresponding to the area number Z0 from 0 to 1, which means that the data in the area number Z0 is completely written, and the data stored in the area number Z0 is completed. The remaining space in the physical block PBA20 can be used to store other data. Because the remaining space in the physical block PBA20 can be used to store other data, the data in area Z2 can also be written to the remaining data pages in block B20. If the flash memory controller 122 is processing the data in area Z2. When writing instructions, if no physical block is found and its corresponding available index is 1, the flash memory controller 122 should extract a blank block or a spare block to write data in area Z2.

In this example, since the available index corresponding to the physical block PBA20 is 1, the flash memory controller 122 can directly use the physical block PBA20 to store the data in the area Z2 without extracting another blank block or spare area. block. Since the number of remaining data pages in block B20 is not enough to store all the data in area Z2, the data in area Z2 is divided into the first part Z2_1 and the second part Z2_2, where the first part Z2_1 is stored in block B20, and In the second part Z2_2, the flash memory controller 122 extracts another blank block, block B30, and starts writing from the first data page of block B30. Since the physical block PBA20 is full after the first part Z2_1 of Z2 is filled with the remaining data pages of the block B20, and no more data can be written, the flash memory controller 122 will change the available index corresponding to the area Z0 to 0, and let the available indicators corresponding to area Z2_1 remain at 0. After the writing of the second part Z2_2 of area Z2 is completed, the flash memory controller 122 changes the available index corresponding to the area number Z2_2 from 0 to 1. Similarly, the data of area Z1 also starts to be written to the area. The remaining data pages of block B30.

In step 1806, the flash memory controller 122 creates or updates an L2P mapping table to record the mapping relationship between logical addresses and physical addresses for subsequent use in reading data from the region namespace 310_1. Figure 20 is a schematic diagram of an L2P mapping table 2000 according to an embodiment of the present invention. The L2P mapping table 2000 contains two fields, one of which records the block number or logical address range, and the other field records the entity corresponding to the first logical address of the logical address range. Block address and entity data page address. In Figure 20, the L2P mapping table 2000 records area Z0 or the first logical address of the logical address range of area Z0, as well as the corresponding physical block address PBA20 and the physical data page address P1 and area Z2. The logical address range of the first part Z2_1 and the physical block address PBA20 and physical data page address Pa corresponding to the first logical address of the range, the logical address range of the second part Z2_2 of the area Z2 and The physical block address PBA30 and the physical data page address P1 corresponding to the first logical address of the interval, and the area Z1 or the logical address interval of area Z1 and the physical area corresponding to the first logical address of the interval The block address PBA30 and the physical data page address Pb. Please note that in this example, a physical block filled with data stores multiple areas of data.

In addition, it should be noted that during the writing process of the data in areas Z0, Z2, and area Z1, the writing process may not start writing the data in area Z1 after all the data in area Z0 is written. Region namespace 310_1, in other words, it is possible that the flash memory controller 122 needs to start writing the data of region Z1 into the region namespace 310_1 before the data of region Z0 has been written. Therefore, as mentioned above, in another embodiment of the present invention, the L2P mapping table 2000 may additionally include an available indicator field, which is used to indicate whether the data of the area has been completely written in the shared block.

In the above embodiments, since the L2P mapping table 2000 stores the address relationship within the block corresponding to the data in different areas, it can be considered that data with logical addresses belonging to different areas can be stored in the same physical block. , so the space of the physical block can be effectively utilized.

It should be noted that the L2P mapping table 2000 in this embodiment will only record a small number of logical addresses (a small number of physical data page addresses). Therefore, the L2P mapping table 2000 itself only has a small amount of data. Therefore, the L2P mapping table 2000 It can reside in the buffer memory 216 or the DRAM 240 without causing too much burden on the storage space of the buffer memory 216 or the DRAM 240 .

Figure 21 is a flow chart of reading data from the area namespace 310_1 according to an embodiment of the present invention. This embodiment assumes that the area namespace 310_1 has stored the data of the areas Z1, Z1 and Z2 shown in Figure 19 . In step 2100, the process starts. The main device 110 and the storage device 120_1 are powered on and complete the initialization operation (for example, the boot process). In step 2102, the master device 110 sends a read command to request reading data with a specific logical address. In step 2104, the microprocessor 212 in the flash memory controller 122 determines which area the specific logical address belongs to, and calculates the specific area number or logical address according to the area number or logical address recorded in the L2P mapping table 2000. A physical data page address corresponding to the logical address. Take the L2P mapping table 2000 in Figure 20 as an illustration. Since the L2P mapping table 2000 records the block number or logical address range of an area, plus the number of logical addresses that each block can store is Therefore, the microprocessor 212 can know which area and which block the specific logical address belongs to based on the above information. Next, assuming that the specific logical address belongs to the area Z0, the microprocessor 212 determines the difference between the specific logical address and the starting logical address of the area Z0, and then determines the data that each data page of the block can store. How many logical addresses of data are needed to determine the physical data page address corresponding to the specific logical address.

In step 2106, the microprocessor 212 reads the corresponding data from the area namespace 310_1 according to the physical block address and the physical data page address determined in step 2104, and returns the read data. to the main device 110.

As mentioned above, through the contents described in the above embodiments, the flash memory controller 122 can still effectively complete the data writing of the area namespace 310_1 while only establishing a very small size of the L2P mapping table 2000. and read.

Referring to the embodiments shown in Figures 5 to 21 above, Figures 5 to 7 describe that the amount of data corresponding to each area is greater than the size of each block in the flash memory module 124, and the flash memory Each block in the module 124 will only store data corresponding to a single area, that is, data in different areas will not be written to the same physical block. Figures 8 to 12 describe that the amount of data corresponding to each area is larger than the size of each block in the flash memory module 124, and some blocks in the flash memory module 124 will store the corresponding Data in multiple areas, that is, data in different areas, can be written to the same physical block. Figures 13 to 17 illustrate that the amount of data corresponding to each area is less than the size of each block in the flash memory module 124, and each block in the flash memory module 124 only stores the corresponding Data to a single area, that is, data in different areas will not be written to the same physical block. Figures 18 to 21 illustrate that the amount of data corresponding to each area is less than the size of each block in the flash memory module 124, and the blocks in the flash memory module 124 will store multiple Regional data, that is, data in different regions can be written to the same physical block.

In one embodiment, the above four access modes can be selectively applied in the region namespace of the flash memory module 124, and if the flash memory module 124 has multiple region namespaces, these regions Namespaces can also use different access modes. Specifically, referring to FIG. 3 , the microprocessor 212 in the flash memory controller 122 can select the access mode to be used according to the size of each area in the area name space 310_1. For example, if The amount of data corresponding to each area of the area namespace 310_1 is larger than the size of each block in the flash memory module 124. The microprocessor 212 can adopt the access mode mentioned in Figures 5 to 7 or The access mode mentioned in Figures 8 to 12 is used to access the area namespace 310_1; if the amount of data corresponding to each area of the area namespace 310_2 is less than each block in the flash memory module 124 The microprocessor 212 can use the access modes mentioned in Figures 13 to 17 or the access modes mentioned in Figures 18 to 21 to access the area name space 310_2. Similarly, the microprocessor 212 in the flash memory controller 122 can select the access mode to be used according to the size of each area of the area namespace 310_2, and the access mode used by the area namespace 310_2 is not certain. It should be the same as the area namespace 310_1. For example, the area namespace 310_1 can adopt the access mode mentioned in Figures 5 to 7, and the area namespace 310_2 can adopt the access mode mentioned in Figures 8 to 12.

Please note that since the flash memory controller 122 cannot know in advance the area size to be set by the host device 110, in order to allow the flash memory controller 122 to cooperate with all host devices that meet the specifications, the flash memory controller 122 must The bank controller 122 must be capable of executing all access methods of the embodiments shown in Figures 5 to 21. For example, the flash memory controller 122 learns the single physical block size (or super block size, the concept of super block will be discussed in detail below) of the flash memory module 124 and the main device 110 After setting the area size, you can plan the actual memory space that can be used by the main device according to the physical block size and area size, and select which of the above four access modes should be used for access.

If the area size is smaller than the physical block size, the flash memory controller 122 has to select the methods shown in Figures 13 to 21 for access. Since the access modes mentioned in Figures 13 to 17 may waste more memory space, it may even cause the flash memory controller 122 to be unable to plan enough memory space for the host to use. For example, as follows In access mode, the flash memory controller 122 can only plan a flash memory module with a total capacity of 2TB to have a capacity of 1.2TB for the main device 110 to use, and the main device may expect at least 1.5TB of capacity to be used. Then the flash memory controller 122 needs to change its access mode. For example, the flash memory controller 122 can be changed to the method shown in Figures 18 to 21 for access. Since this access mode will greatly reduce the waste of flash memory space, the flash memory controller 122 More capacity can be planned for the main device 110 to use. For example, the flash memory controller 122 can plan a flash memory module with a total capacity of 2TB to have a capacity of 1.8TB for the main device 110 to use. In this way, The memory storage space usage requirement of the main device 110 is met. In other words, the capacity that the main device 110 may expect can be regarded as a standard. When the planned capacity of the regional namespace is higher than the standard of the main device 110 when using the access methods in Figures 13 to 17, the speed will be reduced. The flash memory controller 122 can select the access methods in Figures 13 to 17; in addition, if the planned capacity of the regional namespace is lower than the standard of the main device 110 when using the access methods in Figures 13 to 17, then The flash memory controller 122 can select the access modes shown in Figures 18 to 21.

If the area size is larger than the physical block size, the flash memory controller 122 has to select the methods shown in Figures 5 to 12 for access. Since the access modes mentioned in Figures 5 to 7 may waste more memory space, it may even cause the flash memory controller 122 to be unable to plan enough memory space for the host to use. For example, as follows In access mode, the flash memory controller 122 can only plan a flash memory module with a total capacity of 2TB to have a capacity of 1.2TB for the main device 110 to use, and the main device may expect at least 1.5TB of capacity to be used. Then the flash memory controller 122 needs to change its access mode. For example, the flash memory controller 122 can be changed to the method shown in Figures 8 to 12 for access. Since this access mode will greatly reduce the waste of flash memory space, the flash memory controller 122 More capacity can be planned for the main device 110 to use. For example, the flash memory controller 122 can plan a flash memory module with a total capacity of 2TB to have a capacity of 1.8TB for the main device 110 to use. In this way, The memory storage space usage requirement of the main device 110 is met. In other words, the capacity that the main device 110 may expect can be regarded as a standard, and when the planned capacity of the regional namespace is higher than the standard of the main device 110 when using the access methods in Figures 5 to 7, the fast The flash memory controller 122 can select the access methods in Figures 5 to 7; in addition, if the planned capacity of the regional namespace is lower than the standard of the main device 110 when using the access methods in Figures 5 to 7, then The flash memory controller 122 can select the access modes shown in Figures 8 to 12.

Figure 25 is a flow chart of a control method applied to a flash memory controller according to an embodiment of the present invention. With reference to the contents described in the above embodiments, the flow of the control method is as follows:

Step 2500: The process starts.

Step 2502: Receive a setting command from a host device, wherein the setting command sets at least a portion of the flash memory module as a region namespace, wherein the region namespace logically includes multiple regions, The master device must write and access data in the area namespace in units of areas. The size of each area is the same. The logical addresses corresponding to each area must be continuous, and There will be no overlapping logical addresses between regions.

Step 2504: Use one of a first access mode, a second access mode, a third access mode, and a fourth access mode to write data from the host device to the flash In the memory module, the data is all the data in a specific area.

Step 2506: If the first access mode is used, write the data into multiple specific blocks of the flash memory module sequentially according to the order of the logical addresses of the data.

Step 2508: After the data is completely written, invalid data is written into the remaining data page of the last specific block of the plurality of specific blocks, or the remaining data page is kept blank without writing any data.

Step 2510: If the second access mode is used, write the data into the specific blocks of the flash memory module sequentially according to the order of the logical addresses of the data.

Step 2512: After the data is completely written, use a completion indicator to mark the last specific block of the plurality of specific blocks as writing completion.

Step 2514: If the third access mode is used, write the data to a single specific block of the flash memory module sequentially according to the sequence of the logical addresses of the data.

Step 2516: After the data is completely written, invalid data is written into the remaining data pages of the specific block, or the remaining data pages are kept blank without writing any data.

Step 2518: If the fourth access mode is used, write the data into individual specific blocks of the flash memory module in sequence according to the sequence of the logical addresses of the data.

Step 2520: After the data is completely written, use a completion indicator to mark the specific block as being written complete.

Please note that in another embodiment, in order to make the design of the controller 122 simpler, the controller 122 may only support a single access mode among the above four access modes, or the controller 122 may only support Two of the above four access modes, or the controller 122 can only support three of the above four access modes, must be designed according to the specific flash memory module and host device.

In addition, in one embodiment of the present invention, the storage device 120_1 may be a Secure Digital Memory Card, which supports data transmission in the traditional secure digital mode, that is, using the UHS-I input/output communication interface standard. Communicates with the host device 110, and also supports PCIe mode that supports both the PCIe channel and the NVMe protocol.

In the implementation of the flash memory module 124, the flash memory controller 122 configures the blocks belonging to different data planes (planes) inside the flash memory module 124 as a super block, so as to Facilitates management of data access. Specifically, refer to the schematic diagram of the general storage space 320_1 of the flash memory module 124 shown in FIG. 22 . As shown in Figure 22, the general storage space 320_1 includes two channels, channel 1 and channel 2, which are connected to multiple flash memory chips (chips) 2210, 2220, 2230, and 2240 respectively. The bulk chip 2210 includes two data planes 2212 and 2214, the flash memory chip 2220 includes two data planes 2222 and 2224, and the flash memory chip 2230 includes two data planes 2232 and 2234. The memory chip 2240 includes two data planes 2242 and 2244, and each data plane includes a plurality of blocks B0~BN. During the process of configuring or initializing the general storage space 320_1, the flash memory controller 122 will configure the first block B0 of each data plane as a super block 2261, and the second block B0 of each data plane. Block B1 is configured as a super block 2262,..., and so on. As shown in Figure 22, the super block 2261 includes eight physical blocks, and the flash memory controller 122 is similar to a normal block when accessing the super block 2261. For example, the super block 2261 It is itself an erasure unit, that is, although the eight blocks B0 of the super block 2261 can be erased separately, the flash memory controller 122 will definitely erase the eight blocks B0 together. ; In addition, when writing data to the super block 2261, the first data page of the data plane 2212, the first data page of the data plane 2214, the first data page of the data plane 2222, and the first data page of the data plane 2224 can be sequentially written. Write data to the first data page of data page 2244, and then write data to the second data page of data page 2212, and then write data to the second data page of data page 2214 in sequence. Two data pages, ..., and so on. In other words, the flash memory controller 122 will write the first data page of each block B0 in the super block 2261 until it is full, and then continue to write the data in the super block 2261. The second data page of each block B0. The super block is a logical set block set by the flash memory controller 122 in order to facilitate the management of the storage space 320_1, and is not a physical set block. In addition, when performing garbage collection, calculating block valid pages, and calculating the length of block writing time, calculations can also be performed in units of super blocks. Under the teachings of the present invention, those who are familiar with this art can use the embodiments shown in Figures 5 to 21 to understand that one of the physical blocks mentioned in the embodiments shown in Figures 5 to 21 can also It can be a super block, and all relevant embodiments can be implemented using super blocks instead of being limited to a single physical block.

However, when the flash memory controller 122 configures the blocks in the flash memory module 124 as super blocks, it is very difficult to access data if the embodiments of Figures 5 to 8 are used. It is possible that each block has many remaining data pages (blank data pages), thus wasting the internal space of the flash memory module 124 . For example, assuming that the data size of the area planned by the main device 110 is about the size of six physical blocks, the data amount stored in the eight-block super block 2261 will only be six physical blocks. A large amount of data, that is, about two blocks of storage space in super block 2261, is wasted by keeping it blank or writing invalid data. Therefore, an embodiment of the present invention proposes a method of configuring the area namespace 310_1 according to the data amount of the area set by the host device 110, so as to efficiently use the area namespace 310_1.

FIG. 23 is a flowchart of a method of configuring the flash memory module 124 according to an embodiment of the present invention. In step 2300, the process starts, and the main device 110, the flash memory controller 122 and the flash memory module 124 have completed related initialization operations. In step 2302, the host device 110 sets at least a part of the flash memory module 124 as a region namespace by sending a setting command set. In the following description, the region namespace 310_1 is used as an explanation. For example, the host device 110 sets basic settings such as the size, number of regions, and logical block address size of each zone in the zone namespace 310_1 on the storage device 120_1, for example, using a Zoned Namespaces Command Set. In step 2304, the microprocessor 212 in the flash memory controller 122 determines the data size of the zone (Zone size) set by the host device 110, and each block (physical block) in the flash memory module 124. block) to determine the number of blocks contained in a super block. Specifically, it is assumed that the data size of the area set by the main device 110 is A, the data size used by the host in each physical block in the flash memory module 124 is B, and the microprocessor 212 uses If the remainder obtained after A is divided by B is not zero, then the quotient obtained after A is divided by B plus one is the number of blocks contained in a super block. And if the remainder obtained by the microprocessor 212 after dividing A by B is zero, then the quotient obtained after dividing A by B can be the number of blocks included in a super block. Taking the example in Figure 24 as an example, the flash memory module 124 includes a plurality of flash memory chips 2410, 2420, 2430, and 2440. The flash memory chip 2410 includes two data planes 2412 and 2414. The flash memory chip 2420 includes two data planes 2422 and 2424, the flash memory chip 2430 includes two data planes 2432 and 2434, and the flash memory chip 2440 includes two data planes 2442 and 2444, and each Each data plane contains multiple blocks B0~BN. If the quotient of A divided by B is '5' and the remainder is '3', the microprocessor 212 can determine that a super block contains six blocks. , therefore, in the process of configuring or initializing the area namespace 310_1, the flash memory controller 122 will configure the first block B0 of the data plane 2412, 2414, 2422, 2424, 2432, 2434 as a super Block 2461, the second block B1 of data planes 2412, 2414, 2422, 2424, 2432, 2434 are configured as a super block 2462,..., and so on. In addition, the blocks B0~BN of data plane 2442 and data plane 2444 do not need to be configured as super blocks, or they can form an additional super area independent of data planes 2412, 2414, 2422, 2424, 2432, and 2434. block. In another embodiment, during the process of configuring or initializing the region namespace 310_1, the flash memory controller 122 groups the first block B0 of the data planes 2412, 2414, 2422, 2424, 2432, and 2434. The second block B1 is configured as a super block 2461, and the data planes 2422, 2424, 2432, 2434, 2442, 2444 are configured as a super block 2462. As long as each block in the same super block can be accessed in parallel, the super block access speed can be improved. Therefore, the super block can be set arbitrarily while complying with this concept.

In another embodiment, assume that the data size of the area set by the host device 110 is C, and the data size used by the host in each physical block of the flash memory module 124 is D. If C The quotient after dividing by D is '3' and the remainder is '2', then the microprocessor 212 can determine that a super block contains 4 blocks, that is, the quotient is plus one. After receiving the command from the master device to set the area namespace 310_1, the flash memory controller 122 configures the first block B0 of the data planes 2412, 2414, 2422, and 2424 as a super block 2461, and 2432 , 2434, 2442, and the first block B0 of 2444 are configured as a super block 2462, and so on.

Please note that the storage device 120_1, the storage device 120_2... the storage device 120_N, etc. can perform preliminary super block settings on the flash memory module when performing initialization settings before leaving the factory. Taking the storage device 120_1 as an example, the super block setting at this time can configure the first block B0 of the data planes 2412, 2414, 2422, 2424, 2432, 2434, 2442, and 2444 that can be accessed simultaneously as a super block. Block 2461 configures the second block B1 of the data planes 2412, 2414, 2422, 2424, 2432, 2434, 2442, and 2444 as a super block 2462 to obtain the maximum access bandwidth. . After the storage device 120_1 is connected to the host device 110 and obtains the command for the region namespace from the host device 110 (for example, setting the region namespace 310_1), the size of the region namespace is allocated in the flash memory module 124. A specific storage area is defined as a dedicated space of the area name space 310_1, and based on the setting of the size of each area of the area name space 310_1 by the main device 110, the size and combination method of the super block of the specific storage space are reset. For example, the first block B0 of the data planes 2412, 2414, 2422, and 2424 is configured as a super block 2461, and the first block B0 of the data planes 2432, 2434, 2442, and 2444 is configured as a super area. Block 2462, and so on. At this time, there will be two super blocks of different sizes in the storage device 120_1. The super block setting of the specific storage area exclusive to the area namespace 310_1 will be different from the super block setting of the specific storage area not exclusive to the area namespace 310_1. The settings are different. Moreover, the super block setting of the specific storage area dedicated to the area namespace 310_1 is also different from the initialization setting of the storage device 120_1 before leaving the factory.

As mentioned above, the number of blocks included in the super block is determined according to the data amount of the area set by the main device 110, so that the super block can achieve optimal space utilization.

It should be noted that the number of flash memory chips and the number of data areas included in each flash memory chip in the embodiments of Figures 22 and 24 are only used as examples and are not part of the present invention. limits. In addition, in the embodiments of Figures 22 and 24, the flash memory chips 2410, 2420, 2430, 2440 included in the regional namespace 310_1 and the flash memory chips 2210, 2220, 2230 included in the general storage space 320_1 , 2240 can be integrated. Specifically, the flash memory module 124 may only include four flash memory chips 2210, 2220, 2230, and 2240, and the flash memory chips 2210, 2220, 2230, and 2240 as a whole include the components shown in Figure 3 The area namespace 310_1 and the general storage space 320_1 are shown. Therefore, the microprocessor 212 can configure the four flash memory chips 2210, 2220, 2230, 2240 to simultaneously contain a variety of super blocks with different block numbers. , for example, includes a super block containing eight blocks as shown in Figure 22 and a super block containing six blocks as shown in Figure 24.

On the other hand, the general storage space 320_1 shown in Figure 3 can also be configured as a regional namespace by the host device 110 at a subsequent point in time, and at this time, the size of the previously configured super block in the general storage space 320_1 Changes will be required. Specifically, at the first point in time, the microprocessor will set the general storage space 320_1 to plan the size of each super block. Taking Figure 22 as an example, since a super block can contain up to eight blocks , so the microprocessor 212 sets each super block to include eight blocks. Next, if the main device 110 resets the general storage space 320_1 as a region namespace, the microprocessor 212 needs to reset the number of blocks included in each super block, such as the six regions shown in Figure 22 block.

Please note that in order to increase the access speed, the flash memory controller 122 can usually temporarily store the data that the main device 110 wants to store in the storage device 120_1 in the single-layer storage memory cell of the flash memory module 124. , or in other words, it is temporarily stored in the flash memory module 124 in the SLC storage method, and finally the data will be stored in the multi-layer storage memory cells, or in other words, it is stored in the flash memory module in the MLC storage method. In group 124. In the embodiment of the present invention, the process of storing the data in the flash memory module 124 in the SLC storage mode is omitted, and the final state of storing the data in the flash memory module 124 in the MLC storage mode is directly explained. In this way, those familiar with this art can combine the technology of the present invention with the technology of temporarily storing data in the flash memory module 124 in the SLC storage manner under the teaching of the present invention.

To briefly summarize the present invention, in the control method of the present invention applied to a flash memory controller, through the mode of planning area data to be written to the flash memory, the size of the L2P mapping table can be effectively reduced to reduce the buffer memory. memory or DRAM; in addition, by determining the number of blocks contained in a super block based on the amount of data in the area and the size of the physical block, the space of the flash memory module can be used more efficiently. The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

100: Electronic devices 110: Main device 120_1, 120_2, 120_N: storage device 122:Flash memory controller 124:Flash memory module 212:Microprocessor 212C:Program code 212M: read-only memory 214:Control logic 216: Buffer memory 218:Interface logic 232:Encoder 234:Decoder 240:Dynamic Random Access Memory 200:block BL1, BL2, BL3: bit lines WL0~WL2, WL4~WL6: character lines 310_1, 310_2: Region namespace 320_1, 320_2: General storage space Z0, Z1, Z2, Z3: Area LBA_k~LBA_(k+x-1): logical address 500~508: steps B3, B7, B8, B12, B99, B6: block P1~PM:Information page 700, 710, 720, 730:L2P mapping table 800~806: steps 900~906: steps 1100A, 1100B:L2P mapping table 1130A, 1130B: Shared block table 1230: Shared block table 1300~1306: steps 1400~1408: steps B20, B30, B35: block 1600:L2P mapping table 1700~1706: steps 1800~1806: steps 2000:L2P mapping table 2100~2106: steps 2210, 2220, 2230, 2240: Flash memory chip 2212, 2214, 2222, 2224, 2232, 2234, 2242, 2244: Data surface 2261, 2262: super block 2300~2306: Steps 2412, 2414, 2422, 2424, 2432, 2434, 2442, 2444: Data surface 2461, 2462: super block

Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present invention. Figure 2A is a schematic diagram of a flash memory controller in a storage device according to an embodiment of the present invention. Figure 2B is a schematic diagram of a block in a flash memory module according to an embodiment of the present invention. Figure 3 is a schematic diagram of a flash memory module including a general storage space and a regional namespace. Figure 4 is a schematic diagram of the regional namespace being divided into multiple regions. Figure 5 is a flowchart of writing data from a master device into a regional namespace according to an embodiment of the present invention. Figure 6 is a schematic diagram of area data being written to a block in a flash memory module. Figure 7A is a schematic diagram of an L2P mapping table according to an embodiment of the present invention. Figure 7B is a schematic diagram of an L2P mapping table according to another embodiment of the present invention. Figure 7C is a schematic diagram of an L2P mapping table according to another embodiment of the present invention. Figure 7D is a schematic diagram of an L2P mapping table according to another embodiment of the present invention. Figure 8 is a flow chart of reading data from a regional namespace according to an embodiment of the present invention. Figure 9 is a flowchart of writing data from a master device to a regional namespace according to another embodiment of the present invention. Figure 10 is a schematic diagram of area data being written to a block in a flash memory module. Figure 11A is a schematic diagram of an L2P mapping table and a shared block table according to an embodiment of the present invention. Figure 11B is a schematic diagram of an L2P mapping table and a shared block table according to an embodiment of the present invention. Figure 12 is a schematic diagram of a shared block table according to another embodiment of the present invention. Figure 13 is a flow chart of reading data from a regional namespace according to an embodiment of the present invention. Figure 14 is a flowchart of writing data from a master device to a regional namespace according to another embodiment of the present invention. Figure 15 is a schematic diagram of area data being written to a block in a flash memory module. Figure 16 is a schematic diagram of an L2P mapping table according to an embodiment of the present invention. Figure 17 is a flow chart of reading data from a regional namespace according to another embodiment of the present invention. Figure 18 is a flowchart of writing data from the master device to the regional namespace according to another embodiment of the present invention. Figure 19 is a schematic diagram of area data being written to a block in a flash memory module. Figure 20 is a schematic diagram of an L2P mapping table according to an embodiment of the present invention. Figure 21 is a flow chart of reading data from a regional namespace according to an embodiment of the present invention. Figure 22 is a schematic diagram of a super block in a general storage space. Figure 23 is a flow chart of a method of configuring a flash memory module according to an embodiment of the present invention. Figure 24 is a schematic diagram of a super block within a zone namespace. Figure 25 is a flowchart of a control method applied to a flash memory controller according to an embodiment of the present invention.

100: Electronic devices 110: Main device 120_1, 120_2, 120_N: storage device 122:Flash memory controller 124:Flash memory module

Claims (9)

A control method applied to a flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes multiple data planes, each data The surface contains multiple blocks, and each block contains multiple data pages, and the control method includes: Receive a setting command from a host device, wherein the setting command sets at least a portion of the flash memory module as a zoned namespace, wherein the zoned namespace logically includes multiple zones (zone), the master device must write and access data in the zone namespace in units of zones. The size of each zone is the same, and the logical address corresponding to each zone must be Continuous, and there will be no overlapping logical addresses between areas; Configure the area namespace to plan a plurality of first super blocks, where each first super block includes a plurality of blocks located in at least two data planes, and each first super block The number of blocks contained in a block is determined by the size of each area and the size of each block; Receive data from the host device corresponding to a specific area, where the data is all data in the specific area; and sequentially writing the data into a specific first super block among the plurality of first super blocks of the flash memory module according to the order of the logical addresses of the data; From the perspective of storing data from the main device, a single first super block will only store data in a single area. The control method described in item 1 of the patent application also includes: Setting another part of the flash memory module as a general storage space; and The general storage space is configured to plan a plurality of second super blocks, where each second super block includes a plurality of blocks respectively of the plurality of data planes. For the control method described in Item 1 of the patent application, the number of blocks included in each first super block is different from the number of blocks included in each second super block. A flash memory controller, wherein the flash memory controller is used to access a flash memory module. The flash memory module includes multiple data planes, and each data plane includes multiple data planes. blocks, and each block contains multiple data pages, and the flash memory controller includes: A read-only memory used to store a program code; a microprocessor for executing the program code to control access to the flash memory module; and a buffer memory; The microprocessor receives a setting command from a host device, wherein the setting command sets at least a portion of the flash memory module to a zoned namespace, wherein the zoned namespace is logical The ground contains multiple zones (zones). The master device must write and access data in the zone namespace in units of zones. The size of each zone is the same, and the corresponding Logical addresses must be continuous, and there will be no overlapping logical addresses between regions; The microprocessor configures the area namespace to plan a plurality of first super blocks, where each first super block includes a plurality of blocks located in at least two data planes, and each first super block The number of blocks included in a first super block is determined based on the size of each area and the size of each block; the microprocessor receives data corresponding to a specific area from the main device, where The data is all the data in the specific area, and the microprocessor sequentially writes the data to the first super blocks of the flash memory module according to the order of the logical addresses of the data. In a specific first super block in; From the perspective of storing data from the main device, a single first super block will only store data in a single area. The flash memory controller as described in item 4 of the patent application, wherein the microprocessor sets another part of the flash memory module as a general storage space, and configures the general storage space to A plurality of second super blocks are planned, where each second super block includes a plurality of blocks respectively of the plurality of data planes. In the flash memory controller described in claim 5 of the patent application, the number of blocks included in each first super block is different from the number of blocks included in each second super block. A storage device including: A flash memory module, wherein the flash memory module includes multiple data planes, each data plane includes multiple blocks, and each block includes multiple data pages; and a flash memory controller for accessing the flash memory module; wherein the flash memory controller receives a setting command from a host device, wherein the setting command sets at least a portion of the flash memory module as a zoned namespace, wherein the zoned namespace The system logically contains multiple zones. The master device must write and access data in the zone namespace in units of zones. The size of each zone is the same, and all data in each zone must be written and accessed. The corresponding logical addresses must be continuous, and there will be no overlapping logical addresses between regions; The flash memory controller configures the area namespace to plan a plurality of first super blocks, where each first super block includes a plurality of blocks located in at least two data planes. , and the number of blocks included in each first super block is determined according to the size of each area and the size of each block; the flash memory controller receives a corresponding message from the main device to a Data in a specific area, where the data is all data in the specific area, and the flash memory controller writes the data to the flash memory module sequentially according to the order of the logical addresses of the data In a specific first super block among the plurality of first super blocks; From the perspective of storing data from the main device, a single first super block will only store data in a single area. The storage device as described in Item 7 of the patent application, wherein the flash memory controller sets another part of the flash memory module as a general storage space, and configures the general storage space for planning A plurality of second super blocks are generated, where each second super block includes a plurality of blocks respectively of the plurality of data planes. In the storage device described in claim 8 of the patent application, the number of blocks included in each first super block is different from the number of blocks included in each second super block.