TWI819598B - computing system - Google Patents

Abstract

A computing system includes a substrate and a first grid array connector. The substrate supports an integrated circuit, the substrate has a first side and a second side, and has a plurality of via holes and includes a first set of terminals located in some of the plurality of via holes, the The first set of terminals each have a flexible contact on the first side. A first grid array connector is located on the first side, the first grid array connector supports a first plurality of cables terminated in the first grid array connector, the first plurality of Cables are configured to each provide a differential signal path, and the first grid array connector is configured to electrically connect conductors in the first plurality of cables to flexible contacts of the first set of terminals. , so that conductors in the first plurality of cables are in electrical communication with the integrated circuit.

Description

computing system

The present invention relates to the field of connector systems, and more particularly to a connector system suitable for use in high data rate applications.

Historically, computing device boxes have featured some type of processor (disposed in a chip package) and multiple connectors on a front panel of the box. The plurality of connectors and the processor are mounted on a circuit substrate (often called a motherboard), and the circuit substrate includes a plurality of traces that connect the plurality of connectors to the processor, thereby Information can be provided between the plurality of connectors and the processor. Unfortunately, as data rates have increased, this well-known system design has become difficult to use due to losses in the circuit substrate.

Various bypass connector systems are known to provide between an input/output (IO) connector and an integrated circuit (such as, but not limited to, an application specific integrated circuit (ASIC) disposed in a chip package) connection. A common configuration would be to have a first connector (often an IO connector) at a panel of a box and a second connector that interfaces with a circuit substrate (or another connector) at the chip package nearby, wherein the first connector and the second connector are connected via a cable. As is known, cables are much lower in loss than standard circuit boards and using a cable significantly reduces losses between the first connector and the second connector. Although this situation is well suited for 56Gbps applications, especially those using fourth-order pulse amplitude modulation (PAM 4) encoding, as data rates move toward The addition of 112Gbps (using PAM 4 encoding) makes it more challenging to keep the available insertion loss low enough to support one channel length. Some options offer good electrical performance but are difficult to assemble and thus create process issues when trying to build a component such as a 1U server. Therefore, some would appreciate a connector system that allows a connection to a chip package to be low loss and still easy to assemble.

A computing system is provided, including a substrate and a first grid array connector. the substrate supports an integrated circuit, the substrate has a first side and a second side, and has a plurality of via holes and includes a first set of terminals located in some of the plurality of via holes, Each of the first set of terminals has a flexible contact on the first side. The first grid array connector is located on the first side, the first grid array connector supports a first plurality of cables terminated in the first grid array connector, the first A plurality of cables are configured to each provide a differential signal path, and the first grid array connector is configured to electrically connect conductors in the first plurality of cables to flexible terminals of the first set of terminals. Contacts enable conductors in the first plurality of cables to be in electrical communication with the integrated circuit.

In one embodiment, the substrate further includes a second set of terminals located in other vias of the plurality of vias, the second set of terminals having the flexible contacts on the second side. pieces.

In one embodiment, the computing system further includes a second grid array connector located on the second side, the second grid array connector supporting a third terminal connected to the first grid array connector. Two plurality of cables, the second plurality of cables are configured to each provide a differential signal path, and the second grid array connector is configured to electrically connect conductors in the second plurality of cables to the second plurality of cables. The flexible contacts of the second set of terminals enable conductors in the second plurality of cables to electrically communicate with the integrated circuit. letter.

In one embodiment, the computing system further includes: a first compressible element and a heat sink. The first compressible element is located on the first grid array connector. The heat sink compresses the first compressible element such that the first grid array connector is biased toward the flexible contacts, and the heat sink is further configured to transfer thermal energy to the integrated circuit.

In one embodiment, the computing system further includes a second compressible element located on the second grid array connector and a retaining frame configured to press against the second compressible element, wherein the A second compressible element urges the second grid array connector toward the flexible contacts on the second side of the substrate.

In one embodiment, the computing system further includes: a first compressible element and a heat sink. The first compressible element is located on the first grid array connector. The heat sink compresses the first compressible element such that the first grid array connector is biased toward the flexible contacts, and the heat sink is further configured to transfer thermal energy to the integrated circuit.

A computing system is provided, including a lower circuit board, a plurality of terminals and an upper circuit board. The lower circuit board has a plurality of guide holes. The plurality of terminals are located in the plurality of guide holes, and each terminal includes a press-fitting portion inserted into one of the corresponding guide holes and a flexible portion. The upper circuit board has a first surface and a second surface. The upper circuit board includes a plurality of conductors terminated to the upper circuit board through the first surface. Each of the conductors is electrically connected to the A pad on the second surface, wherein the pad is configured to electrically engage the flexible portion of the corresponding terminal.

In one embodiment, the computing system further includes an integrated circuit mounted on the lower circuit board. A circuit, the integrated circuit communicating with the plurality of vias.

In one embodiment, the computing system further includes a base to assist in supporting the plurality of conductors and a compressible member configured to bias the base and pads on the second surface toward the desired location. The flexible portion of the plurality of terminals.

In one embodiment, the computing system further includes a heat sink that compresses the compressible element, and the heat sink is further configured to transfer thermal energy to the integrated circuit.

20, 220, 420, 520, 920: Cable

21, 21’, 221: conductor

23, 23’: Insulation layer

24, 224: Welding Department

26:Outer covering

28, 228: Shielding layer

30, 30’: support

43, 243: Open your mouth

47, 247: Incline

47’:Tapered guide hole

50, 150’, 250, 450, 550, 650, 750, 850: base plate

51a, 251a, 1010a: mounting surface

51b, 251b, 1010b: connection surface

52, 252, 952: connecting path

53, 253, 1053: support guide holes

54, 54’, 259a, 259b: ground plane

55, 255: opening

55a: Taper

56, 258: Ground pad

57, 257, 1057: short trace

58, 256, 656, 1058: signal pad

59:Taper angle

61, 561, 1061: Solder loading parts

62:Connection pattern

70, 170, 170’, 170a, 170b, 270, 370, 470, 670, 770, 870: Grid Array Connector System

71, 271, 471, 798a, 799a, 871, 971: Base

72: Attachment features

185:Mezzanine connector

186: Clamping element

191:First connector

193: Cable set

194, 394, 494, 994: chip packaging

195, 305, 405, 605, 905: Radiator

210, 310, 410, 610, 710, 910, 950: circuit substrate

229a: first spacing

229b: Second spacing

240a, 540a: first support

240b, 540b: second support

241: Depression

273, 473: Alignment of the feet

275:Finger

277: Holding molded parts

280, 480, 580, 680, 880: insert

281, 481, 581, 681: Frame

282, 282a~c, 582, 682: Contacts

283a~c, 283c’: end

284a~c: middle part

301, 901, 1001: Computing system

305a, 905a: protrusion

306, 406, 906: Attachment elements

307, 407: Keep the frame

308, 908: Keep legs

398:Connection area

410a, 910a: top side

410b, 910b: bottom side

458: Alignment opening

464, 964.1: Compressible element

465, 965: base

466, 966: Compressible fingers

467, 967: Holding arm

470a: first end

470b:Second end

471a, 971a: Holding buckle

494a:First fate

494b:Second fate

670a: Subgrid Array Module

694a: Integrated circuits

594b, 694b: Wafer substrate

682a, 682b: docking end

798, 799: Connector

798b, 799b: terminal

799c: Solder connection

873:Feet

874: Locking element

875: Cover

876:Latching arm

877: Fastening openings

884: Fastening opening

907: Lower holding frame

911:Substrate

913: Reinforcement ring

958: Alignment opening

964.1: Upper compressible element

964.2: Lower compressible element

915, 968: Gap

970.1: Upper Grid Array Connector System

970.2: Lower Grid Array Connector System

978:Central channel

998:Connect area

1010: Second circuit substrate

1080:Terminal

1087: Press fitting department

1087a:Ontology

1087b:Open your mouth

1088: Flexible part

1088a:Part 1

1088b: Second curved part

1088c:Part 3

1088d: hook end part

This application is illustrated by way of example, but is not limited to, the drawings, in which like reference numerals represent similar parts, and in the drawings: FIG. 1 illustrates an embodiment of a cable terminated to a substrate. Stereo view.

FIG. 2 shows a partially exploded perspective view of the embodiment shown in FIG. 1 .

Figure 3 shows a simplified exploded perspective view of an embodiment of a cable and stand that can be connected together.

Figure 4 shows a perspective view of an embodiment of a support.

Figure 5 shows a bottom view of an embodiment of a substrate.

FIG. 6 shows a top view of the substrate shown in FIG. 5 .

Figure 7 shows a cross-sectional side view of an embodiment of a substrate.

Figure 8 shows a perspective view of an embodiment of a grid array connector system.

FIG. 9 shows another perspective view of the embodiment shown in FIG. 8 .

Figure 10 shows a partial bottom view of an embodiment of a substrate.

Figure 11 shows a partially cutaway perspective view of a grid array connector system.

12 shows a side view of a grid array connector system configured to interface with a chip package that is connected to a connector located underneath the chip package.

Figure 13 shows a side view of the embodiment shown in Figure 12, with the connectors in a mated state.

Figure 14 shows a schematic diagram of an embodiment of a grid array connector system positioned in a system.

Figure 15 shows a schematic diagram of two grid array connector systems connected by a cable set.

Figure 16 shows a schematic diagram of an embodiment of a grid array connector system configured to include a chip socket.

Figure 17 shows a perspective view of another embodiment of a grid array connector system mounted on a circuit substrate.

Figure 18 shows a simplified perspective view of the grid array connector shown in Figure 17.

FIG. 19 shows a perspective, partially exploded view of the embodiment shown in FIG. 18 .

FIG. 20 shows a perspective view of an embodiment of an internal design of a grid array connector system that can be used with the embodiment shown in FIG. 18 .

21 illustrates a perspective, partially cutaway, partial view of an embodiment of an internal design of a grid array connector system.

FIG. 22 shows a perspective view of an embodiment of an internal design of a grid array connector system that can be used with the embodiment shown in FIG. 18 .

Figure 23 shows a cutaway perspective view of Figure 22 taken along line 23-23.

FIG. 24 shows a simplified perspective view of the embodiment shown in FIG. 23 .

Figure 25 shows a perspective view of an embodiment of a substrate.

26 illustrates a side view of an embodiment of a grid array connector system including an interposer mounted on a circuit substrate.

Figure 27A shows an embodiment of a contact suitable for use with an insert.

Figure 27B shows another embodiment of a contact suitable for use with an insert.

Figure 27C shows yet another embodiment of a contact suitable for use with an insert.

Figure 28 shows a perspective view of another embodiment of a grid array connector system that can be used with a heat sink.

FIG. 29 shows a perspective, partially exploded view of the embodiment shown in FIG. 28 .

FIG. 30 shows another perspective view of the embodiment shown in FIG. 29 .

Figure 31 shows a side view of an embodiment of a grid array connector system that can be used with a heat sink.

Figure 32 shows a simplified plan view of an embodiment of a chip package and multiple grid array connector systems.

33 illustrates a perspective view of an embodiment of a chip package and multiple grid array connector systems.

Figure 34 shows a perspective view of a grid array connector system shown in Figure 33.

Figure 35 shows another perspective view of the embodiment shown in Figure 34.

Figure 36 shows a plan view of an embodiment of a chip package mounted on a circuit substrate that can be used with the embodiment shown in Figure 33.

Figure 37 illustrates a partial side view of an embodiment of a grid array connector system showing an alternative insert configuration.

Figure 37A shows an enlarged, simplified side view of the embodiment shown in Figure 37.

Figure 38 shows a schematic diagram of a grid array connector system mounted on a wafer substrate.

Figure 39 shows a schematic diagram of an embodiment of connecting a substrate to an interposer.

40 illustrates a perspective, partially exploded view of an embodiment of a grid array connector system capable of mating with a circuit substrate via a mating connector.

Figure 41 shows a perspective view of the grid array connector system shown in Figure 40.

FIG. 42 shows a perspective view of the docking connector shown in FIG. 40 .

Figure 43 shows a perspective view of an embodiment of a grid array connector system.

FIG. 44 shows another perspective view of the embodiment shown in FIG. 43 .

Figure 45 shows a top perspective view of an embodiment of a computing system.

Figure 46 shows a bottom perspective view of the embodiment of the computing system shown in Figure 45.

Figure 47 shows an exploded top perspective view of components of the computing system shown in Figure 45.

Figure 48 shows a partial cutaway view from a top perspective view of the computing system shown in Figure 45.

Figure 49 is an exploded top perspective view of components of an embodiment of a computing system.

Figure 50 is an exploded bottom perspective view of components of the computing system shown in Figure 49.

FIG. 51 is a top perspective view of a terminal of the computing system shown in FIG. 49 .

Figure 52 is an assembled top perspective view of the components of the computing system shown in Figure 49.

Figure 53 shows a partial cutaway view from a top perspective view of the computing system shown in Figure 49.

Figure 54 is a top perspective view of components of the computing system shown in Figure 49.

The following detailed description illustrates exemplary embodiments, and the disclosed features are not intended to be limited to the expressly disclosed combinations. Thus, unless otherwise stated, features disclosed herein may be combined together to form other combinations not shown for the sake of simplicity.

As can be appreciated from Figures 1 to 7, features of one embodiment are disclosed to allow a cable 20 to be terminated directly to a substrate 50, which can be a conventional circuit substrate or any other desired substrate. (Such as but not limited to a ceramic and/or plastic metal composite structure). The substrate 50 includes a mounting surface 51a and a connecting surface 51b, wherein one or more connecting passages 52 extend between the mounting surface 51a and the connecting surface 51b. Although terminating one or two conductors from one cable 20 to a substrate can be accomplished in a wide range of methods, when attempting to terminate larger numbers of cables 20 in a compact array, especially if This becomes more complex when good electrical performance is required while providing the required manufacturing processing flexibility. The illustrated embodiment includes a cable 20 having a pair of conductors 21 capable of functioning as a differential pair. The pair of conductors 21 is surrounded by an insulating layer 23 , and the insulating layer 23 is then covered by a shielding layer 28 , and then the shielding layer 28 is covered by an outer cladding 26 . It is contemplated that a drain wire is not required in most applications, but can be included if required and can be connected to the stand if included.

In order to connect the conductors 21 to signal pads 58 provided in a signal layer within the substrate 50, each conductor 21 may be attached to a support via 53 provided by the substrate 50 via a solder 24. or via a solder or other known attachment means if required). Figure 7 A cross-section of an embodiment of a support guide hole 53 structure is shown. The conductor 21 can be inserted into an opening 43 in the substrate 50, and the opening 43 is aligned with an opening 55. The opening 55 optionally includes a taper 55a to facilitate the easy insertion of the conductor 21. Preferably, the opening 43 will also include a bevel 47 for assisting in guiding the conductor 21 to the position required to support the guide hole 53 and then positioning it so that one end of the conductor 21 is adjacent to a front side of the support guide hole 53 Be positioned. A laser can then be used to weld the conductor 21 to the support via 53 or to solder the conductor 21 to the support via 53 . In order to connect the shielding layer 28 of the cable 20 to the ground pad 56 on the connection surface 51b, a support 30 is provided to connect the shielding layer 28 to a grounding surface 54 on the substrate 50.

If conductor 21 is soldered to support via 53, solder 24 will resist dislodgement when exposed to the high temperatures associated with soldering, and after soldering conductor 21 to support via 53, standoff 30 will be at a higher Temperature (eg, using a higher temperature solder) enables attachment to substrate 50 and shield 28 without fear of losing the connection between conductor 21 and support via 53 . This in turn will allow later use of lower temperature solder to solder the substrate 50 to other structures once all required cables 20 are attached, thereby making the process of assembling a complete system easier to manufacture. Note that the use of solder to attach standoff 30 to ground plane 54 is not required, however, for some applications, standoff 30 may be attached via a conductive adhesive or may even be spot-on via a laser. Welding (potentially in multiple locations).

As mentioned above, in order to facilitate the installation of the conductor 21 into the substrate 50, the substrate 50 may be drilled with a tapered hole to obtain a structure as shown in FIG. 7 . If a taper is provided, the taper angle 59 can be a wide range of angles, but will typically be from 15 degrees to about 40 degrees, with the actual angle depending at least in part on the spacing of the apertures and the thickness of the substrate . Preferably, the taper angle 59 is sufficient to allow a pair of conductors 21 to be naturally spaced apart to fit into the two enlarged openings 43 and subsequently automatically align the two conductors 21 in In two independent and adjacent openings 55 , when further inserted into the openings 55 , the two conductors 21 will be automatically guided to positions corresponding to the two supporting guide holes 53 .

To allow for improved attachment and proper ball grid array spacing, support via 53 may be connected to a signal pad 58 via a short trace 57 as shown in FIG. 5 . As can be appreciated, short trace 57 is only partially visible due to the solder mask. A solder charge 61, which may be a solder ball (eg, as shown in FIG. 9), may be positioned on both ground pad 56 and signal pad 58 to allow attachment of the grid array. Note that the design shown shows a uniform solder ball layout but layouts with uneven spacing are also considered. An additional benefit of this configuration is that attaching a solder load 61 to a solder 24 is less repeatable from a manufacturing perspective, and supports via 53 connection to signal pad 58 with short trace 57 This allows a solder loader 61 to be positioned on a conventional pad in a more reliable manner.

Although the weld 24 shown is relatively strong, it is generally desirable to provide some sort of stress relief for the cable 20 . In one embodiment, a portion of the plurality of conductors 21 and the substrate 50 may be encapsulated in an insulating material (potentially using a low pressure molding process) to provide a base 71 . Base 71 may include attachment features 72 (such as shown in FIG. 8 ) to form a grid array connector system 70 . The grid array connector system 70 may include a substrate 50 having a connection surface 51 b including a plurality of solder loading members 61 forming a connection pattern 62 . As can be appreciated, the internal design of grid array connector system 70 may be arranged in accordance with FIGS. 1-7.

As can be appreciated from Figure 9, in a compact and low-profile configuration, a relatively large connection pattern 62 can be formed to allow a greater number of connections, thereby allowing a grid array connector System 70 is more closely aligned with a corresponding application specific integrated circuit (ASIC). Although such a construction is beneficial for connecting large numbers of differential pairs together, the resulting size can cause problems when trying to solder attach the connection pattern 62 to another surface because the size prevents sufficient thermal energy from reaching the solder inside. Loading piece 61. In order to prevent uneven thermal energy distribution (and resulting connection problems) from occurring, one or more thermal paths (which may be slots or openings) may be provided in the substrate 50 and/or the base 71, to allow improved and more uniform heat transfer to all solder loads 61. The thermal path may come from the side or extend through the base 71 and substrate 50 within the connection pattern 62 (thereby creating a break in the connection pattern 62). The approach to introducing thermal paths to improve the thermal performance of solder attachments is based on the size of the pattern connections and many other parameters, such as cycle times and materials, and is therefore left to those of ordinary skill in the art to determine as needed.

As mentioned above, as shown in FIG. 5 , in certain embodiments, solder loading 61 is attached to signal pad 58 spaced apart from support via 53 . Note that this has the advantage of avoiding soldering to a soldered surface prior to reflow that is inconsistent and may be difficult to reliably attach a solder ball to. As can be appreciated, such a configuration allows isolation to be advantageously used by surrounding signal pads 58 with ground pads 56, such as shown in FIG. 10 . The disadvantage of such a construction is that a short trace 57 is required to connect the support via 53 to the signal pad 58 and the short trace 57 can affect signal integrity. Figure 11 shows another embodiment with a configuration that allows direct via-solder ball attachment. As shown, conductor 21' is supported by an insulating layer 23' which is located in a support 30' which is attached to ground plane 54'. The conductor 21' extends through a tapered guide hole 47' and the end portion is positioned and soldered to the corresponding pad. A plurality of solder loads 61 are then positioned on all pads in a conventional manner. For larger gauge conductors 21', such a construction may be easier This is done because the spacing between conductors 21' will be more consistent with the spacing required for the ball grid array. However, as is known, getting solder balls to solder consistently to a surface to be soldered can be challenging, especially if the surface to be soldered is not completely uniform. One possible approach to this is to extend the support vias 53 less into the substrate 50 and solder the conductor 21 to the support vias 53 below the top surface so that the solder loader 61 is placed in a location other than the solder portion 24 itself. part. Such a configuration may allow for good electrical performance while providing a more consistent surface for placement of solder balls, since the resulting contact area supporting via 53 may provide a rounded rim-shaped surface or may even be slightly concave.

As can be appreciated from FIGS. 12-13, one potential application of the embodiment shown in FIGS. 1-11 is the inclusion of a mezzanine connector 185 in a grid array connector system 170. As is known, the mezzanine connector 185 can be made to function in a compact space, can be hermaphroditic, and can have excellent electrical performance due to the ability to provide a relatively linear configuration. Accordingly, the illustrated embodiment includes a mezzanine connector 185 that allows the grid array connector system 170 to be mounted on a substrate 150' (which may be any desired type of substrate, as described above , a reversible connection between a chip package 194 on which the substrate 150' is mounted on another mezzanine connector 185). Such a configuration may provide excellent electrical performance while also providing low insertion force for docking chip package 194 to grid array connector system 170 . As can be appreciated, one advantage of this design is that it allows chip package 194 to be attached to a connector (such as mezzanine connector 185) that is separate from substrate 150' and that connector can be mated to a different docking connection. connector (such as grid array connector system 170). This allows the two parts to be machined independently and can help reduce scrap and/or rework. Naturally, the design shown also allows for existing chip packages 194 (which can be replaced by a desired An integrated circuit designed to be quickly replaced with a higher performance chip package 194.

Figure 14 shows a simplified schematic diagram of another potential configuration. A first connector 191 is located adjacent to a box mounting surface and connected to a grid array connector system 170 via a cable set 193 (which includes a plurality of cables). A chip package 194 is mounted directly to the grid array connector system 170 and a heat sink 195 is disposed on the chip package 194 . As can be appreciated, such a system allows for additional flexibility in the system, particularly if the first connector 191 is removably mounted (thereby allowing complete retrofitting if required).

Note that in some embodiments, the substrate connected grid array connector system may also be configured with a socket design having a plurality of contacts configured to attach directly to multiple contacts on the ASIC package. A pad. For example, such a grid array connector system could include an interposer (with multiple flexible contacts) and the base would be formed into a receptacle type shape (which is slightly more complex) but could allow for the elimination of A second connector is therefore satisfactory. As schematically shown in FIG. 16 , the grid array connector system 170 ′ is configured to include a socket assembly that directly receives a chip package 194 and includes a clamping component 186 (which may be integrally or independently configured. ) to hold the chip package 194 in place. Although a rotating clamping element 186 is shown and is quite common in known chip packages 194, the clamping element 186 is not so limited and a wide range of clamping configurations are possible. In some embodiments, for example, the clamping element 186 may be integrated into a heat sink and attached by separate fasteners. Although conventional socket designs are less suitable for high signal transmission frequencies and corresponding high data rates due in part to terminal design and uniform spacing, they are improved by a more customized and less The illustrated embodiment overcomes these problems with a uniform grid array coupled with the ability to provide extremely clean (electrically speaking) connections of conductors to multiple contacts of the bonded chip package 194 in the grid array connector system 170'. limitation.

As can be appreciated from Figure 15, the use of the grid array connector system disclosed herein is not limited to a particular application, such as a bypass application. This technology works well as a jumper between two chip packages and allows significantly greater flexibility in the location of the chip packages. For example, one or more of the grid array connector systems 170a, 170b can be located adjacent to a liquid cooling block located at the rear of the adjacent device (which reduces air flow across the server's main chassis). need). Additionally, although two grid array connector systems 170a, 170b are shown connected together by a cable set 193, in one embodiment, three or more grid array connector systems (and corresponding Chip packages) can be connected together through a cable set to help provide improved high-performance computing (HPC) performance.

Turning to Figures 17-27C, another embodiment of a grid array connector system 270 is shown. The grid array connector system 270 includes a base 271 located on a substrate 250, and a plurality of cables 220 terminated on the substrate 250. In one embodiment, the plurality of cables 220 are arranged in columns of four, which provides the required compactness and density, but other configurations may be suitable depending on the application. Similar to the aforementioned substrate 50, the substrate 250 includes a mounting surface 251a and a connecting surface 251b, and a plurality of connecting passages 252 extend between the mounting surface 251a and the connecting surface 251b. The substrate 250 may further include ground planes 259a, 259b internally to provide improved electrical performance. The plurality of connection passages 252 include two openings 243 , each of the two openings 243 is aligned with an opening 255 in a supporting guide hole 253 . Substrate 250 provides a connection surface at There is a grid arrangement of signal pads 256 and ground pads 258 on 251b. The signal pads 256 and the ground pads 258 may be connected to a chip substrate or interposer (such as interposer 280) or directly on the circuit substrate 210.

The plurality of cables 220 are terminated to the base plate 250 by using a first support 240a and a second support 240b, and once terminated, the base plate 250 and the first support 240a and the second support 240b can be held by a The molding 277 holds. The holding molding 277 may be a low pressure molding or a potting compound. As can be appreciated, the base 271 includes a plurality of fingers 275 that form passages through which a plurality of cables extend, and the base 271 includes a plurality of alignment feet 273 that form a plurality of alignment feet 273 . The feet 273 may be used to align the base 271 with a mating component.

The first stand 240a can be mounted on the base plate 250 in a manner similar to the way the stand 30 is attached to the base plate 50 and the cable 220 is first connected to the second stand 240b, and in one embodiment, the plurality of cables 220 A shielding layer 228 of each strip is electrically connected to the corresponding second support 240b (via solder or welding or conductive adhesive). The second support 240b is docked with the first support 240a, and is pressed against the second support 240b through an adhesive, a welding part or an interference fit (such as a recess 241 on the first support 240a). As shown in Figures 20-21), the first support 240a and the second support 240b can be held together. In other words, an interference fit may properly hold the first support 240a and the second support 240b together.

As described above for the substrate 50, the substrate 250 includes a plurality of openings 243. Each of the plurality of openings 243 may have a slope 247, and the slope 247 may be used to guide the conductor 221 in the cable 220 to a desired position. This can cause the two conductors 221 to change from a first pitch 229a to a second pitch 229b that is different from the first pitch. In one embodiment, the second pitch 229b is at least 50% greater than the first pitch 229a to provide an improved pad layout on the connection surface 251b. Spacing so modified is optional but determined It is beneficial to have a cable 220 with a small size of conductor 221. Conductors 221 are mounted to support vias 253 (preferably via welds 224, but other attachment methods may be used, as discussed above). Support vias 253 may be electrically connected to signal pads 256 on connection surface 251b via short traces 257 in substrate 250 (if such signal pads 256 are independent of support vias 253).

As mentioned before, the signal pads 256 and the ground pads 258 on the substrate 250 can be directly connected to pads on another surface (such as the circuit substrate 210) through solder. However, as shown in Figure 26, a different option is possible. Instead of substrate 250 being soldered to circuit substrate 210 , an interposer 280 may be used to connect pads on substrate 250 to pads on circuit substrate 210 . The insert 280 includes a frame 281 that holds a plurality of contacts 282 that engage pads on both sides of the insert 280 . Contacts 282a, 282b, 282c are shown in FIGS. 27A-27C and may be retained by frame 281. The contact member 282a includes two end portions 283a and a middle portion 284a. The middle portion 284a is not configured to flex in a significant manner. The contact piece 282b includes two end portions 283b and a middle portion 284b, the middle portion 284b is configured to flex. Contact 282c includes end portion 283c and end portion 283c', with an intermediate portion 284c not intended to flex in a significant manner. As can be appreciated, these contacts 282a-c may have multiple contact points at one or both ends and be compressible or incompressible as desired, depending on the application. Additionally, because multiple ground connections may be present, it may be desirable for the ground contacts to be configured differently than the signal contacts (eg, have different impedances) to help properly adjust the common-mode and differential-mode impedances. Therefore, the signal contacts may be configured differently than the ground contacts.

28 to 30 illustrate an embodiment of a computing system 301. The computing system 301 includes a heat sink 305. As shown, a grid array connector system 370 is mounted on a plurality of chip packages 394 side. As shown, grid array connector system 370 is located on four sides of chip package 394 (both positioned on a circuit substrate 310 ), but grid array connector system 370 may also be mounted on fewer sides. . A retaining frame 307 having a plurality of retaining legs 308 may be provided in conjunction with attachment elements 306 to help secure the heat spreader 305 in a desired position, and the heat spreader 305 includes a protrusion 305a designed to press against the chip package. 394 to ensure a good thermal connection between the heat sink 305 and the chip package 394. In order to ensure that there is a sufficiently effective thermal connection between the heat sink 305 and the chip package 394, one may include some type of thermal interface material (TIM), which may be a paste or other suitable material. If their thermal efficiency is required to be better, the chip package 394 can be directly soldered to the heat sink 305. As can be appreciated, circuit substrate 310 may include a connection area 398 aligned with chip package 394 to provide additional signal paths to other components (or to mounting components directly beneath chip package 394). As can be appreciated, the heat spreader 305 presses against both the chip package 394 and the grid array connector system 370 and thereby ensures that both are firmly pressed into place and maintain a reliable connection.

Figures 31 to 36 show another embodiment similar to the embodiment shown in Figures 28 to 30. A heat sink 405 with an attachment element 406 is connected to a holding frame 407 located on a bottom side 410b of a circuit substrate 410. Positioned between the circuit substrate 410 and the heat sink 405 (on a top side 410a of the circuit substrate 410) is a chip package 494 and a plurality of grid array connector systems 470. As can be appreciated from Figure 32, each of the plurality of grid array connector systems 470 is positioned with a first end 470a aligned with a first edge 494a of the chip package 494 and a second end 470b extending beyond the chip. A second edge 494b of the package 494 is provided to improve connection density. Naturally, if this density is not required, other configurations would be suitable.

Similar to the above embodiment, the grid array connector system 470 includes a plurality of cables 420 held by a base 471 and connected to a base plate 450 and the base plate 450 is connected to an insert 480 , the insert 480 It has a frame 481 holding a plurality of contact pieces. The circuit substrate 410 includes a plurality of alignment openings 458 , and the plurality of alignment openings 458 are configured to interface with the plurality of alignment feet 473 . Naturally, on each side of the chip package 494, the plurality of alignment openings 458 may be provided in the same pattern to allow for interoperability, or may be provided in a different pattern to ensure that only certain grid array connector systems 470 Can be positioned on certain sides. As can be appreciated, it is desirable that the interface between chip package 494 and heat sink 405 defines the vertical position of heat sink 405 because the thermal connection between chip package 494 and heat sink 405 affects the amount of heat removed from chip package 494 . The system shown includes a compressible element 464 that ensures that the heat sink 405 is pressed against the grid array connector system 470 with the required force (and thereby allows the heat sink 405 to be vertically positioned relative to the circuit board 410 fluctuate in position). The illustrated compressible element 464 includes a base 465 having a plurality of compressible fingers 466 and includes a latching arm 467 that engages a latching buckle 471a to secure the compressible element 464 to the base 471 . As can be appreciated, mounting a grid array connector on all four sides of a chip package 494 provides a tighter connection to the chip package 494 and reduces any traces between the chip package 494 and the cable 420 length (thus reducing insertion loss to a predetermined level), but it is also contemplated to mount the grid array connector system 470 on fewer sides of the chip package 494 (in order to have the same number of connections, the grid array connector system 470 will naturally have to be larger). Additionally, as can be appreciated from Figure 34, although the grid array connector system 470 is shown with four cables 420 in each column of cables 420, some other number of cables 420 may be provided.

Turning to Figures 37-37A, another embodiment of a grid array connector configuration is shown. The simplified partial view of Figure 37 shows a cable 520 connected to a second support 540b, which is connected to a first support 540a, which in turn is connected to the base plate 550. As such, parts of the design are similar to the previously described embodiments. However, what is slightly different is that the insert 580 includes a frame 581 that holds a plurality of contacts 582 in the form of cylinders. The plurality of contacts 582 will be soldered directly to the substrate 550 and may each include a second side that will be soldered to a pad on the chip substrate 594b. The chip substrate 594b will directly support the integrated circuit, which is disposed in the chip package and typically connected to a circuit substrate (not shown) through a plurality of solder mounts 561. The embodiment shown in Figures 37-37A thus illustrates a situation in which a grid array connector system can be more tightly integrated with a chip package. Naturally, such a configuration would require the wafer substrate 594b to be slightly larger than typically required, but the potential for improved electrical performance may make such a configuration desirable. One benefit of such a configuration is that the die substrate 594b can be constrained to the grid array connector system before the integrated circuit is soldered to the die substrate 594b, thereby ensuring that the integrated circuit can be installed into the intended system. Naturally, the insert 580 design shown in this embodiment can also be used in a more traditional configuration and allows the grid array connector system to be soldered directly to the circuit substrate.

Note that although the insert 580 is not required, the use of an insert 580 can help with coplanarity of the mating surfaces. An insert 580 tends to be between 0.3 and 2.0 mm in thickness, it will be understood that a thinner design will reduce compliance and thus make coplanarity more difficult to deal with, while a thicker design will take up more space. space and ultimately becomes less desirable for a connector.

38 and 39 illustrate a schematic diagram of an embodiment in which the grid array connector system 670 is more tightly integrated into the chip package. As shown, a circuit substrate 610 supports a wafer substrate 694b, which in turn supports an integrated circuit 694a. An insert 680 is mounted on the wafer substrate 694b and connected to a sub-grid array module 670a. The sub-grid array module 670a includes a base, a substrate and a plurality of terminated cables. A heat sink 605 is configured to be thermally connected to the integrated circuit 694a to assist in dissipating heat. As can be appreciated, the illustrated designs provide a significant variation. The interposer 680 may be soldered directly to both the substrate (which is not shown separately) and the wafer substrate 594b or may be soldered to only one of the two and use a contact tip that presses against a pad on the non-soldered side. An embodiment of the weld side/press side is schematically shown in Figure 39, where a base plate 650 engages an insert 680. The insert 680 includes a frame 681 that holds a plurality of contacts 682. The plurality of contacts 682 have a pair of connecting terminals 682a that are flexed when joined to the signal pad 656 and are configured to be soldered to another circuit substrate or A mating end 682b of the wafer substrate. Depending on the configuration, the heat sink 605 may be pressed against the grid array connector system 670 to ensure an electrical connection (often using a compressible element), or if the grid array connector system 670 is soldered in place, the heat sink 605 may be provided with gaps relative to the grid array connector system 670 .

As can be appreciated from Figures 40-42, another embodiment of a grid array connector system 770 is shown, the grid array connector system 770 including a connector 798 mounted to a substrate 750, and the connector 798 is configured to interface with a connector 799 on a circuit substrate 710 . Connector 798 includes a base 798a that holds a plurality of terminals 798b that are connected to substrate 750 in a desired manner, often by a solder attachment. Connector 799 includes a base 799a that holds a plurality of terminals 799b connected to circuit substrate 710 via solder connections 799c.

Another embodiment is shown in Figures 43-44. Although the internal construction may be any of the internal designs described above, a grid array connector system 870 includes a cover 875 having a fastening opening 877 . Cover 875 includes a latching arm 876 that engages a locking element on base 871 874. Fastening opening 877 aligns with a fastening opening 884 that extends through grid array connector system 870 (including through base plate 850 and an interposer 880). The grid array connector system 870 still has optional feet 873 to aid in alignment with a mating circuit substrate, but the grid array connector system 870 can be retained by a separate fastener. The illustrated embodiment thus provides an alternative method of attaching the grid array connector system 870 in place.

Figures 45-48 illustrate an embodiment of a computing system 901 that includes the components of Figures 28-30 and further includes an upper compressible element 964.1 similar to the compressible element 464 provided in Figures 31-36. For ease of explanation, computing system 901 is described with respect to the postures shown in Figures 45-48, whereby the terms "up," "down," etc. are used. It is understood that other gestures are within the scope of this disclosure.

A heat sink 905 and an attachment element 906 are connected to a lower holding frame 907 by holding legs 908. The lower holding frame 907 is located on a bottom side 910b of a circuit substrate 910. The holding legs 908 hold the frame 907 from below. extend. A chip package 994 and a plurality of upper grid array connector systems 970.1 connected to a circuit substrate 950 are located between a top side 910a of the circuit substrate 910 and the lower surface of the heat sink 905. In this way, the circuit substrate 950 is an upper circuit substrate and the circuit substrate 910 is a lower circuit substrate.

The circuit substrate 950 can be a conventional circuit substrate like the previous embodiments or any other suitable substrate, such as but not limited to a ceramic and/or plastic metal composite structure. The circuit substrate 950 includes a mounting surface and a connection surface, wherein more than one connection path 952 extends between the mounting surface and the connection surface. The circuit substrate 950 may also include a ground plane internally to improve electrical performance.

Each upper grid array connector system 970.1 is similar to the embodiment discussed above and includes a plurality of cables 920 held by a base 971 and connected to connection vias on the circuit substrate 950 as described above. Road 952. Similar to that shown in Figure 33, circuit substrate 950 may be connected to an interposer (such as interposer 480) having a frame (such as frame 481) that holds a plurality of contacts. Upper grid array connector systems 970.1 are positioned to form a central channel 978 between upper grid array connector systems 970.1. Chip package 994 is disposed within a central channel 978 formed by a plurality of upper grid array connector systems 970.1.

The circuit substrate 910 includes a base material 911 having a connection area 998 aligned with the chip package 994 to provide additional signal paths to other components (or to mounting components below the chip package 994). Connection area 998 is at a central portion of substrate 911. As shown in FIG. 47 , the circuit substrate 950 is mounted at the center of the base material 911 above the connection area 998 and over the portion of the circuit substrate 910 outside the connection area 998 , but the circuit substrate 950 is not connected to the entire base of the circuit substrate 910 . Material 911 overlaps. In this way, a portion of the base material 911 extends outward from each edge of the circuit substrate 950 by a predetermined distance, thereby providing a reinforcing ring 913 . The reinforcement ring 913 provides reinforcement, planarization and reinforcement for the connection paths 952 on the circuit substrate 950 to which the upper grid array connector system 970.1 is connected and on which the chip package 994 is mounted. Because the connection vias 952 on the circuit substrate 950 surround the chip package 994, the stiffener ring 913 provides planarity to the connection vias 952 on the circuit substrate 950. The base material 911 also has alignment openings 958 through which the retention legs 908 extend. The alignment opening 958 is configured to penetrate the reinforcement ring 913 so that the alignment opening 958 is outside the circuit substrate 950 , but the alignment opening 958 does not interfere with the performance provided by the reinforcement ring 913 .

The heat sink 905 includes a protrusion 905a, which is designed to press against the chip package 994 to ensure a good thermal connection between the heat sink 905 and the chip package 994. In order to ensure that there is a sufficiently effective thermal connection between the heat sink 905 and the chip package 994, one may include certain types of Thermal interface material (TIM), the thermal interface material can be a paste or other suitable materials. If better thermal efficiency is required, the chip package 994 can be directly soldered to the heat sink 905 . As can be appreciated, heat spreader 905 presses against both chip package 994 and upper grid array connector system 970.1 and thereby ensures that both are firmly pressed into place and maintain a reliable connection.

As can be appreciated, it is desirable that the interface between chip package 994 and heat sink 905 defines the vertical position of heat sink 905 because the thermal connection between chip package 994 and heat sink 905 affects the amount of heat removed from chip package 994 . The illustrated computing system 901 includes an upper compressible element 964.1 that ensures that the heat sink 905 is pressed against the upper grid array connector system 970.1 with the required force (and thereby allows the heat sink 905 to contact the circuit). The substrate 910 fluctuates in the vertical position). Upper compressible element 964.1 includes a base 965 having a plurality of compressible fingers 966 extending from an upper surface of base 965 and a plurality of latching arms 967 extending from a lower surface of base 965. The latching arm 967 engages the latching buckle 971a on the base 971 to secure the upper compressible element 964.1 to the base 971. Base 965 abuts base 971 while compressible fingers 966 engage the lower surface of heat sink 905 . Upper compressible element 964.1 differs from compressible element 464 shown in Figure 33 in that a single upper compressible element 964.1 is secured to all upper grid array connector systems 970.1, rather than multiple independent ones as shown in Figure 33. compressible element 464. The single upper compressible element 964.1 of this embodiment has a continuous base 965 with a centrally located notch 968 that is larger than the periphery of the chip package 994. A plurality of compressible fingers 966 are disposed around the base 965 such that the compressible fingers 966 are disposed above each base 971 . In one embodiment, notch 968 conforms to the shape of the periphery of chip package 994 . In one embodiment, notch 968 is square. Upper compressible element 964.1 preferably includes a plurality of latching arms 967 that engage respective latching buckles 971a.

As can be appreciated, although mounting the grid array connector system 970.1 on all four sides of a chip package 994 provides a tighter connection to the chip package 994 and reduces the risk of any traces between the chip package 994 and the cable 920 length (thus reducing insertion loss to a predetermined level), but it is also contemplated to mount upper grid array connector system 970.1 on fewer sides of chip package 994 (in order to have the same number of connections, upper grid array connector system 970.1 will naturally have to be larger).

The embodiment of the computing system 901 shown in FIGS. 45-48 also includes a plurality of lower grid array connector systems 970.2 and a lower compressible element 964.2 between the bottom side 910b of the circuit substrate 910 and the lower retention frame 907.

The lower holding frame 907 includes a gap 915 passing through a central portion of the lower holding frame 907 .

Each lower grid array connector system 970.2 may be connected to the circuit substrate 910 in a manner similar to the previous embodiments, or may be connected directly to the circuit substrate 910. Each lower grid array connector system 970.2 is similar to the embodiment discussed above and includes a plurality of cables 920 held by a base 971 and connected to the circuit substrate 910. The location of the lower grid array connector system 970.2 may mirror the location of the upper grid array connector system 970.1.

Lower compressible element 964.2 may be formed identically to upper compressible element 964.1 and such specific details will not be described. In use, the lower compressible element 964.2 is flipped relative to the upper compressible element 964.1. Lower compressible element 964.2 forces lower grid array connector system 970.2 into engagement with circuit substrate 910.

To form computing system 901, chip package 994, upper grid array connector system 970.1 and circuit substrate 950 are electrically connected to circuit substrate 910. Upper compressible element 964.1 is attached to a plurality of bases 971 of a plurality of upper grid array connector systems 970.1. The heat sink 905 is positioned over the upper compressible element 964.1 and the protrusions 905a on the heat sink 905 pass through the notches 968 on the upper compressible element 964.1 and through the central channel 978 formed by the plurality of upper grid array connector systems 970.1, to bond the upper surface of chip package 994. The plurality of lower grid array connector systems 970.2 are electrically connected to the circuit substrate 910, and the lower compressible elements 964.2 are attached to the plurality of bases 971 of the plurality of lower grid array connector systems 970.2. The lower holding frame 907 is then attached to the heat sink 905 by passing the holding legs 908 of the lower holding frame 907 through the alignment openings 958 on the circuit substrate 910 . The retaining legs 908 are joined by attachment elements 906 of the heat sink 905 to form a sandwich construction. The connection area 998 of the circuit substrate 910 is accessible from below the computing system 901 through the aperture 915 in the lower retaining frame 907 and through the aperture 968 in the lower compressible element 964.2.

Figures 49-54 illustrate another embodiment of a computing system 1001 like the embodiments shown in Figures 29 and 45 (the chip package is not shown in Figures 49-54). Computing system 1001 includes grid array connector system 270 except that interposer 280 is not provided. As such, the plurality of cables 220 are directly terminated to the substrate 250 in the manner described with respect to FIGS. 1-7 and 17-27C and the specific details are not repeated herein. The computing system 1001 also includes a second circuit substrate 1010, and each cable 220 is connected to the second circuit substrate 1010 through a terminal 1080. In this embodiment, terminals 1080 are used in place of insert 280.

The second circuit substrate 1010 like the circuit substrates 210, 310, 410, 610, 710 may be a conventional circuit substrate or any other desired substrate, such as but not limited to a ceramic and/or plastic metal composite structure. The second circuit substrate 1010 includes a mounting surface 1010a and a connection surface 1010b, wherein more than one connection path having a conductive supporting via hole 1053 therein is on the second circuit substrate 1010 and extends between the mounting surface 1010a and the connecting surface 1010b. In one embodiment, the support guide hole 1053 is cylindrical. In one embodiment, each support via 1053 can be connected to a signal pad 1058 on the connection surface 1010b of the second circuit substrate 1010 through a short trace 1057, as shown in FIG. 52, and can be a solder ball. Solder loader 1061 can be located on signal pad 1058. Alternatively, solder loader 1061 may be located on the end of support via 1053 at connection surface 1010b and short trace 1057 eliminated.

Each terminal 1080 includes a press-fitting portion 1087 and a flexible portion 1088 . The press-fit portion 1087 is sized to coincide with the inner dimensions of the support guide hole 1053 when inserted into the support guide hole 1053 . When inserted, the press-fit portion 1087 contacts the support via 1053, thereby achieving an electrical connection.

In the embodiment shown, the press fit portion 1087 is formed from an elongated circular or oval body 1087a with an opening 1087b therethrough. The body 1087a may be larger than the inner size of the support guide hole 1053, so that when the press-fitting portion 1087 is inserted into the support guide hole 1053, the body 1087a itself will deform and be flattened to reduce the diameter of the opening 1087b. In one embodiment, the flexible portion 1088 is formed from a return arm with a hooked end. As shown, the foldback arm consists of a first portion 1088a extending perpendicularly to the body 1087a from one end of the body 1087a, a second curved portion 1088b extending from an end opposite the first portion 1088a, and an end opposite the second curved portion 1088b. A third portion 1088c is formed that extends overlapping the first portion 1088a so that the third portion 1088c is "bent back" on the first portion 1088a by the second curved portion 1088b. The hooked end is formed by a hooked end portion 1088d extending from an opposite end of the third portion 1088c and extending a predetermined distance beyond the press fit portion 1087. The free end of the hook-shaped end portion 1088d faces the body 1087a and the support guide hole 1053 and the mounting surface 1010a. The flexible portion 1088 extends outward from the support guide hole 1053 as shown in FIG. 52 (FIG. 52 only shows the support guide hole 1053 and does not show the second circuit substrate. 1010).

When the substrate 250 is docked with the second circuit substrate 1010, the signal pad 256 on the connection surface 251b of the substrate 250 is connected to the third portion 1088c of the flexible portion 1088 of the terminal 1080. The folded back third portion 1088c and hooked end portion 1088d flex toward the first portion 1088a. Preferably, when the flexible portion 1088 flexes, the hooked end portion 1088d engages the support guide hole 1053. The engagement of the hooked end portion 1088d with the support guide hole 1053 provides several advantages. Engaging the support guide hole 1053 produces a wiping action. Additionally, when hook end portion 1088d directly engages support via 1053, an alternative path is provided for the electrical path through terminal 1080, as signals can travel from cable 220 along third portion 1088c to the hook end. section 1088d and then to support via 1053. With hook end portion 1088d not engaged with support via 1053, an electrical path through terminal 1080 is maintained.

Other shapes for flexible portion 1088 that allow for flexure are also contemplated. For example, the flexible portion 1088 may be formed by a V-shaped first portion having a pair of arms extending from one end of the body 1087a, an inverted V-shaped second portion having a pair of arms extending from the first portion, and an opening. When the flexure 1088 is engaged by the base plate 250, the first and second pairs of arms flatten to at least partially close the opening such that the first pair of arms engages the support guide hole 1053 and the second pair of arms engages the signal MAT 256.

Compared with soldering the terminal 1080 to the second circuit substrate 1010, using the press-fit portion 1087 provides an easier assembly. In addition, since the terminal 1080 is not soldered to the second circuit substrate 1010, the solder loading member 1061 can be directly soldered to the supporting via hole 1053. The flexible portion 1088 is also configured to accommodate irregularities in the circuit substrate 210 and the second circuit substrate 1010 while still providing a reliable electrical path between the circuit substrate 210 and the second circuit substrate 1010 .

As can be appreciated from the various embodiments illustrated herein, different features of the different embodiments described herein may be combined together to form additional combinations. For example, the internal design of the grid array connector system shown in FIGS. 1-7 can be used as an alternative to the internal design shown in FIGS. 20-25. Likewise, various insert configurations can be employed (or omitted) depending on the application and system requirements. As a result, the embodiments illustrated herein are particularly suited to providing a wide range of configurations, not all of which are shown individually to avoid duplication and unnecessary duplication.

The disclosure provided herein illustrates features by means of preferred and exemplary embodiments thereof. Numerous other embodiments, modifications, and variations within the scope and spirit of the appended claims will occur to those of ordinary skill in the art upon reading this disclosure.

901:Computing system

905: Radiator

906: Attachment elements

907: Lower holding frame

908:Keep the legs

910:Circuit substrate

958: Alignment opening

970.1: Upper Grid Array Connector System

970.2: Lower Grid Array Connector System

Claims (10)

A computing system includes: a substrate supporting an integrated circuit, the substrate having a first side and a second side, and having a plurality of vias and including a via located in some of the plurality of vias. a first set of terminals, each of the first set of terminals having a flexible contact on the first side; and a first grid array connector located on the first side, the first grid The grid array connector supports a first plurality of cables terminated in the first grid array connector, the first plurality of cables are configured to each provide a differential signal path, the first grid array connection The device is configured to electrically connect conductors in the first plurality of cables to the flexible contacts of the first set of terminals such that the conductors in the first plurality of cables are in contact with the integrated circuit Telecommunications. The computing system of claim 1, wherein the substrate further includes a second group of terminals located in other via holes of the plurality of via holes, the second group of terminals having The flexible contact piece. The computing system of claim 2, further comprising a second grid array connector located on the second side, the second grid array connector supporting one end connected to the first grid array connector a second plurality of cables, the second plurality of cables are configured to each provide a differential signal path, and the second grid array connector is configured to electrically connect conductors in the second plurality of cables Flexible contacts on the second set of terminals enable conductors in the second plurality of cables to be in electrical communication with the integrated circuit. The computing system of claim 3, further comprising: a first compressible element located on the first grid array connector; and a heat sink compressing the first compressible element such that the third a grid array The connector is biased toward the flexible contacts, and the heat sink is further configured to transfer thermal energy to the integrated circuit. The computing system of claim 4, further comprising a second compressible element located on the second grid array connector and a retaining frame configured to press against the second compressible element, wherein, The second compressible element urges the second grid array connector toward the flexible contacts on the second side of the substrate. The computing system of claim 1, further comprising: a first compressible element located on the first grid array connector; and a heat sink compressing the first compressible element such that the third A grid array connector is biased toward the flexible contacts, and the heat sink is configured to transfer thermal energy to the integrated circuit. A computing system includes: a circuit board with a plurality of guide holes; a plurality of terminals located in the plurality of guide holes; each terminal includes a press-fitting part inserted into one of the corresponding guide holes and a flexible a curved portion; and an upper circuit board having a first surface and a second surface, the upper circuit board including a plurality of conductors terminated to the upper circuit board via the first surface, each of the conductors electrically A pad is connected to the second surface, wherein the pad is configured to electrically engage the flexible portion of the corresponding terminal. The computing system of claim 7, further comprising an integrated circuit mounted on the lower circuit board, the integrated circuit communicating with the plurality of vias. The computing system of claim 8, further comprising a base to assist in supporting the plurality of conductors and a compressible member configured to connect the base to a pad on the second surface. Flexible portions biased toward the plurality of terminals. The computing system of claim 9, further comprising a heat sink compressing the compressible element, the heat sink further configured to transfer thermal energy to the integrated circuit.

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