TWI817340B - Semiconductor structure having polygonal bonding pad - Google Patents

Abstract

The present disclosure provides a semiconductor structure including a substrate; a redistribution layer (RDL) disposed over the substrate, and including a dielectric layer over the substrate, a conductive plug extending within the dielectric layer, and a bonding pad adjacent to the conductive plug and surrounded by the dielectric layer; and a conductive bump disposed over the conductive plug, wherein the bonding pad is at least partially in contact with the conductive plug and the conductive bump. Further, a method of manufacturing the semiconductor structure is also provided.

Description

Semiconductor structure with polygonal bonding pads

This application claims the priority of U.S. Patent Application Nos. 17/541,792 and 17/543,194 (i.e., the priority dates are "December 3, 2021" and "December 6, 2021"), and the contents are as follows The full text is incorporated into this article by reference.

The present disclosure relates to a semiconductor structure. More particularly, it relates to a semiconductor structure having a bonding pad at least partially exposed through a redistribution layer to accommodate an external interconnect structure.

Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The fabrication of semiconductor devices includes sequentially depositing different material layers on a semiconductor substrate and patterning the material layers using lithography and etching processes to form a plurality of microelectronic devices on or in the semiconductor substrate, Such microelectronic components include transistors, diodes, resistors and/or capacitors.

The semiconductor industry continues to increase the integration density of microelectronic devices by continuously shrinking the minimum feature size, which allows more devices to be integrated into a given area. For example, in order to further increase the density of the semiconductor elements, stacking of two or more elements has been investigated. Therefore, it is desirable to develop improvements that address related manufacturing challenges.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a base; a redistribution layer disposed on the base, and includes a dielectric layer, a conductive plug and a bonding pad; the dielectric layer is disposed on the base; the conductive plug extends on the dielectric In the layer, the bonding pad is adjacent to the conductive plug and surrounded by the dielectric layer; and a conductive bump is disposed on the conductive plug; wherein the bonding pad at least partially contacts the conductive plug and the conductive bump.

In some embodiments, a first surface of the conductive plug and a second surface of the bonding pad are exposed through the dielectric layer.

In some embodiments, the first surface of the conductive plug and the second surface of the bonding pad are substantially coplanar.

In some embodiments, the first surface of the conductive plug and the second surface of the bonding pad contact a seed layer of the conductive bump.

In some embodiments, the first surface of the conductive plug, the second surface of the bonding pad, and a third surface of the dielectric layer are substantially coplanar.

In some embodiments, the first surface of the conductive plug is completely covered by the conductive bump.

In some embodiments, a first portion of the second surface of the bonding pad is covered by the conductive bump, and a second portion of the second surface is exposed through the dielectric layer and by the conductive bump. exposed, and the first portion is substantially smaller than the second portion.

In some embodiments, an upper cross-section of the bonding pad has an annular shape, A fan shape or a polygonal shape.

In some embodiments, a height of the conductive plug is substantially greater than a thickness of the bonding pad.

In some embodiments, the redistribution layer has a conductive component that electrically connects the conductive plug to the substrate.

In some embodiments, the conductive component is electrically connected to the conductive plug via the conductive plug.

In some embodiments, the conductive component is electrically connected to the bonding pad via the conductive plug.

In some embodiments, the conductive bump is electrically connected to a component disposed on the substrate via the conductive component and the conductive plug.

In some embodiments, the conductive component includes a bonding pad portion and a through-hole portion, the bonding pad portion extends horizontally within the dielectric layer, and the through-hole portion is coupled to the bonding pad portion and extends vertically from the bonding pad portion .

In some embodiments, the conductive plug contacts the bonding pad and the soldering pad portion.

Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first substrate; and a redistribution layer disposed on the first substrate and including a dielectric layer, a conductive plug and a bonding pad, the dielectric layer is disposed on the first substrate, the conductive The plug extends within the dielectric layer, the bonding pad is surrounded by the dielectric layer and contacts the conductive plug; wherein the conductive plug is at least partially surrounded by the bonding pad.

In some embodiments, the semiconductor structure further includes a conductive bump covering the conductive plug and partially covering the bonding pad.

In some embodiments, the conductive plug has a width that is substantially smaller than the conductive plug. The width of the bump.

In some embodiments, an interface between the conductive plug and the bonding pad is disposed under the conductive bump.

In some embodiments, the conductive bump is disposed on and coupled to an interconnect structure of a second substrate.

In some embodiments, the bonding pad includes a first bonding pad and a second bonding pad, the second bonding pad is spaced apart from the first bonding pad, and the conductive plug is disposed between the first bonding pad and the first bonding pad. between the second bonding pads.

In some embodiments, the conductive plug contacts the first joint part and the second joint part.

In some embodiments, the semiconductor structure further includes a bonding wire disposed on and bonded to the bonding pad.

In some embodiments, the first substrate includes a plurality of components disposed thereon and a plurality of insulators that separate the plurality of components.

Yet another embodiment of the present disclosure provides a method of manufacturing a semiconductor structure. The preparation method includes providing a substrate and a redistribution layer. The redistribution layer is provided on the substrate. The redistribution layer has a dielectric layer and a conductive plug. The dielectric layer is provided on the substrate. The conductive plug extending within the dielectric layer; disposing an etch stop layer on the redistribution layer; disposing a first patterned photoresist on the etch stop layer; removing a portion of the dielectric layer and passing through the first patterning A portion of the etch stop layer exposed by photoresist; removing the first patterned photoresist; disposing a first seed layer on the etch stop layer and the dielectric exposed through the first patterned photoresist on a portion of the first seed layer; disposing a second patterned photoresist on the first seed layer; disposing a conductive material on a portion of the first seed layer exposed through the second patterned photoresist on; remove the second patterned photoresist; remove the etch stop layer; and remove a portion of the conductive material protruding from the dielectric layer to form a bonding pad adjacent to the conductive plug and surrounded by a dielectric layer.

In some embodiments, the first seed layer disposed on the etch stop layer contacts the conductive plug.

In some embodiments, the bonding pad includes the first seed layer and the conductive material.

In some embodiments, the portion of the conductive material protrudes from the etch stop layer after the second patterned photoresist is removed.

In some embodiments, removal of the portion of the dielectric layer exposed through the first patterned photoresist includes forming an opening extending into the dielectric layer and disposed adjacent the conductive plug.

In some embodiments, the conductive plug is at least partially exposed after the opening is formed.

In some embodiments, the opening surrounds the conductive plug.

In some embodiments, the second patterned photoresist fills a portion of the opening.

In some embodiments, the second patterned photoresist is at least partially surrounded by the first seed layer.

In some embodiments, the preparation method further includes: disposing a dielectric material in the opening and on the etching stop layer; and removing a portion of the dielectric material disposed on the etching stop layer.

In some embodiments, the semiconductor structure further includes: setting a second seed crystal layer on the bonding pad, the conductive plug and the dielectric layer; disposing a third patterned photoresist on the second seed layer; and forming a conductive bump on the second seed layer via the third The exposed portion of the photoresist is patterned.

In summary, because the bond pad is disposed adjacent the conductive plug in the redistribution layer, the bond pad can accommodate an external interconnect structure, such as a wire bond. Furthermore, the bond pad can be formed into different shapes so that the bond pad can accommodate the external interconnect structure from the same direction surrounding the conductive plug. Therefore, a flexible interconnection and wiring of the semiconductor structure can be achieved.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

100:Semiconductor Structure

101: Base

101a: Semiconductor layer

101b:Insulator

101c:Components

101d: Rear side

101e: Front side

102:Redistribution layer

102a: Solder pad part

102b:Through hole part

102c: Conductive plug

102d:Joint pad

102e: Seed layer

102f: soldering pad

102g: dielectric layer

102h: first surface

102i: Second surface

102j:Third surface

102k: First bonding pad

102m: Second bonding pad

102n:Part 1

102p:Part 2

102r:Interface

102s: Open your mouth

103: Conductive bumps

103a: Lower bump metal layer

103b: Metal layer

103c: Barrier layer

103d: Solder components

104: Etch stop layer

105: First patterned photoresist

106: First seed layer

107: Second patterned photoresist

108: Conductive materials

109:Dielectric materials

110: Second seed layer

111: The third patterned photoresist

112:Joining wire

H1: height

H2: height

S200: Preparation method

S201: Steps

S202: Step

S203: Step

S204: Step

S205: Step

S206: Step

S207: Step

S208: Step

S209: Step

S210: Steps

S211: Step

W1: Width

W2: Width

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.

FIG. 2 is a schematic top cross-sectional view illustrating a semiconductor device along a cross-section line A-A' in FIG. 1 according to an embodiment.

3 is a schematic top cross-sectional view illustrating a semiconductor device along a cross-section line A-A' in FIG. 1 according to an embodiment.

4 is a schematic top cross-sectional view illustrating a semiconductor device along a cross-section line A-A' in FIG. 1 according to an embodiment.

FIG. 5 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.

6 is a schematic top cross-sectional view illustrating a semiconductor device along a cross-section line B-B' in FIG. 5 according to an embodiment.

7 is a schematic top cross-sectional view illustrating a semiconductor device along a cross-section line B-B' in FIG. 5 according to an embodiment.

FIG. 8 is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

9 to 36 are schematic cross-sectional views illustrating various intermediate stages of preparing a semiconductor structure according to some embodiments of the present disclosure.

Specific language will now be used to describe the embodiments or examples of the present disclosure illustrated in the drawings. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modifications or improvements to the described embodiments, as well as any further applications of the principles described in this document, are within the realm of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment even if they share the same element number.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the “first device” discussed below "element", "component", "region", "layer" or "section" may be referred to as a second device, component, region, layer or section without departing from This article teaches.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor structure 100 according to some embodiments of the present disclosure. In some embodiments, semiconductor structure 100 is part of a die, a package, or a component. In some embodiments, the semiconductor structure 100 is a flip-chip package. In some embodiments, the semiconductor structure 100 includes a substrate 101, a redistribution layer 102, and a conductive bump 103. The redistribution layer 102 is disposed on the substrate 101, and the conductive bump 103 is disposed on the redistribution layer 102.

In some embodiments, substrate 101 is part of a wafer. In some embodiments, substrate 101 is sawn from a wafer by dicing, cutting, or other suitable operations. In some embodiments, substrate 101 includes a semiconductor material, such as silicon. In some embodiments, substrate 101 is a silicon substrate. In some embodiments, the substrate 101 includes a semiconductor layer 101a, a plurality of insulators 101b, and a plurality of components 101c disposed on the semiconductor layer 101a and separated by the insulators 101b.

In some embodiments, the semiconductor layer 101a includes a back side 101d and a front side Side 101e, front side 101e is provided opposite to rear side 101d. During fabrication of semiconductor structure 100, back side 101d is disposed on a support substrate. The components 101c are formed on the front side 101e and are configured to be electrically connected to an external circuit. In some embodiments, the devices 101c are metal oxide semiconductor (MOS) devices. In some embodiments, the insulators 101b are shallow trench isolation (STI).

In some embodiments, redistribution layer 102 is disposed on front side 101e of substrate 101 . The redistribution layer 102 rewires a path of a circuit from the components 101 c on the substrate 101 to the conductive bumps 103 . In some embodiments, the redistribution layer 102 includes a conductive component (102a and 102b), a conductive plug 102c, a bonding pad 102d, and a dielectric layer 102g surrounding the conductive component (102a and 102b), Conductive plug 102c and bonding pad 102d.

In some embodiments, dielectric layer 102g is disposed on front side 101e of substrate 101 and covers components 101c. Dielectric layer 102g includes a dielectric material such as an oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer, or the like. In some embodiments, dielectric layer 102g includes a number of dielectric layers stacked on top of each other. In some embodiments, each dielectric layer includes a material that is the same as or different from the material of the other dielectric layers.

In some embodiments, the conductive components (102a and 102b) are an interconnection electrically connected to the substrate 101. Conductive components (102a and 102b) are disposed within dielectric layer 102g. In some embodiments, conductive components (102a and 102b) include conductive materials such as gold, silver, copper, nickel, aluminum, or the like. In some embodiments, the conductive components (102a and 102b) include a bonding pad portion 102a and a through hole portion 102b. The bonding pad portion 102a extends horizontally within the dielectric layer 102g. The through hole portion 102b is coupled to the bonding pad portion 102a and Extend vertically within the dielectric layer 102g and away from the bonding pad portion 102a.

In some embodiments, conductive plug 102c extends vertically within dielectric layer 102g and toward conductive components (102a and 102b). In some embodiments, conductive plug 102c is disposed on pad portion 102a. The conductive plug 102c is electrically connected to the substrate 101 via the conductive components (102a and 102b). In some embodiments, conductive plug 102c is surrounded by dielectric layer 102g. In some embodiments, a first surface 102h of conductive plug 102c is exposed through dielectric layer 102g. In some embodiments, conductive plug 102c includes a conductive material such as gold, silver, copper, nickel, aluminum, or the like.

In some embodiments, bond pad 102d is disposed adjacent conductive plug 102c and is surrounded by dielectric layer 102g. In some embodiments, bond pad 102d at least partially contacts conductive plug 102c. Bonding pad 102d is electrically connected to conductive plug 102c. In some embodiments, a side wall of bond pad 102d contacts a side wall of conductive plug 102c. In some embodiments, bond pad 102d is electrically connected to conductive components (102a and 102b) via conductive plug 102c. In some embodiments, bond pad 102d includes a conductive material such as gold, silver, copper, nickel, aluminum, or the like.

In some embodiments, the bonding pad 102d includes a seed layer 102e and a bonding pad 102f, and the bonding pad 102f is surrounded by the seed layer 102e. In some embodiments, seed layer 102e contacts conductive plug 102c. In some embodiments, seed layer 102e is surrounded by dielectric layer 102g and conductive plug 102c. In some embodiments, seed layer 102e is a single layer or a composite stack and includes a material such as copper, aluminum, tungsten, or combinations thereof. In some embodiments, bonding pad 102f contacts and is completely surrounded by seed layer 102e. In some embodiments, bonding pad 102f includes a conductive material such as copper, silver, gold, or the like.

In some embodiments, conductive plug 102c is at least partially surrounded by bond pad 102d. In some embodiments, an upper cross-section of the bonding pad 102d along the line A-A' in FIG. 1 can be for any different shapes. In some embodiments, the upper cross-section of the bonding pad 102d has a polygonal shape. For example, as shown in FIG. 2 , the upper cross section of the bonding pad 102d is in a fan-shaped shape. For example, as shown in FIGS. 3 and 4 , the upper cross-section of the bonding pad 102d is a quarter-ring shape or a half-ring shape.

In some embodiments, the upper cross-section of the bonding pad 102d along the cross-section line B-B' of FIG. 5 has an annular shape as shown in FIG. 6 . In some embodiments, as shown in FIGS. 5 and 7 , the bonding pad 102d includes a first bonding pad 102k and a second bonding pad 102m, and the second bonding pad 102m is spaced apart from the first bonding pad 102k. The conductive plug 102c is disposed between the first bonding pad 102k and the second bonding pad 102m. In some embodiments, conductive plug 102c contacts first bonding pad 102k and second bonding pad 102m. In some embodiments, an upper cross-section of the first bonding pad 102k and an upper cross-section of the second bonding pad 102m are both fan-shaped.

Referring back to FIG. 1 , in some embodiments, bonding pad 102d includes a second surface 102i exposed through dielectric layer 102g. In some embodiments, the second surface 102i of the bond pad 102d is generally coplanar with the first surface 102h of the conductive plug 102c. In some embodiments, the second surface 102i includes an upper surface of the seed layer 102e and an upper surface of the bonding pad 102f.

In some embodiments, the conductive plug 102c has a height H1 that is substantially greater than a height H2 of the bonding pad 102d. The height H1 of the conductive plug 102c extends from the first surface 102h to the pad portion 102a. The height H2 of the bond pad 102d extends from the second surface 102i to the front side 101e of the substrate 101.

In some embodiments, the dielectric layer 102g includes a third surface 102j disposed opposite the front side 101e of the substrate 101. In some embodiments, the first surface 102h of the conductive plug 102c, the second surface 102i of the bonding pad 102d, and the third surface 102j of the dielectric layer 102g Roughly coplanar.

In some embodiments, conductive bumps 103 are disposed on conductive plugs 102c. In some embodiments, the conductive bump 103 is disposed on a portion of the bonding pad 102d and the dielectric layer 102g of the redistribution layer 102. In some embodiments, bonding pad 102d at least partially contacts conductive plug 102c and conductive bump 103. In some embodiments, conductive components (102a and 102b) are electrically connected to conductive bumps 103 via conductive plugs 102c. In some embodiments, the conductive bumps 103 are electrically connected to the components 101 c disposed on the substrate 101 . In some embodiments, the first surface 102h of the conductive plug 102c and the second surface 102i of the bonding pad 102d contact the conductive bump 103.

In some embodiments, an interface 102r between the conductive plug 102c and the bonding pad 102d is disposed under the conductive bump 103. In some embodiments, the conductive bumps 103 are disposed on and bonded to an interconnect structure of other substrates (not shown). For example, because the semiconductor structure 100 is a flip-chip package, the semiconductor structure 100 as shown in FIG. 1 is flipped upside down, and the conductive bumps 103 are disposed on an interconnection structure and bonded to the interconnection structure, and the interconnection structure For example, a bonding pad is provided on another substrate under the semiconductor structure 100 .

In some embodiments, first surface 102h is completely covered by and contacts conductive bumps 103 . In some embodiments, a first portion 102n of the second surface 102i covered by the conductive bumps 103 is substantially smaller than a second portion of the second surface 102i exposed through the dielectric layer 102g and exposed by the conductive bumps 103 102p. In some embodiments, the second portion 102p of the second surface 102i of the bonding pad 102d is configured to receive a bonding wire to electrically connect the semiconductor structure 100 to other semiconductor structures or other substrates. Because bond pad 102d can be formed into different shapes and sizes as desired, bond pad 102d can accommodate external interconnect structures, such as bond wires with different orientations around conductive plugs. Therefore, a flexible interconnection and wiring of the semiconductor structure 100 can be achieved.

In some embodiments, conductive bumps 103 include conductive materials such as lead, tin, copper, gold, nickel, or the like. In some embodiments, the conductive bump 103 is a ball grid array (BGA) solder ball, a controlled collapse chip connection (C4) bump, a microbump, a pillar, or the like. . In some embodiments, the conductive plug 102c has a width W1 that is substantially smaller than a width W2 of the conductive bump 103.

In some embodiments, conductive bump 103 includes under bump metal (UBM) layer 103a, a metal layer 103b, a barrier layer 103c, and a solder component 103d. In some embodiments, lower bump metal layer 103a is disposed on conductive plug 102c and dielectric layer 102g. The lower bump metal layer 103a contacts the first surface 102h and the third surface 102j. In some embodiments, lower bump metal layer 103a covers first surface 102h and partially covers second surface 102i. In some embodiments, the lower bump metal layer 103a is a seed layer or an adhesive layer for accommodating the conductive bumps 103 of the metal layer 103b. In some embodiments, lower bump metal layer 103a contacts the first surface of conductive plug 102c and the second surface 102i of bond pad 102d. In some embodiments, lower bump metal layer 103a includes titanium, copper, gold, or the like. In some embodiments, lower bump metal layer 103a includes at least two conductive materials.

In some embodiments, metal layer 103b is disposed on lower bump metal layer 103a and conductive plug 102c. In some embodiments, metal layer 103b includes a conductive material such as copper, silver, gold, or the like. In some embodiments, the barrier layer 103c is disposed on the metal layer 103b, the lower bump metal layer 103a, and the conductive plug 102c. In some embodiments, barrier layer 103c is configured to prevent metal layer 103b from diffusing into solder component 103d. In some embodiments, barrier layer 103c includes titanium, titanium nitride, tantalum, tantalum nitride, nickel, or the like.

In some embodiments, solder component 103d is disposed on barrier layer 103c, metal layer 103b, and lower bump metal layer 103a. In some embodiments, solder component 103d includes Reflowable material. In some embodiments, solder component 103d includes tin, lead, silver, copper, nickel, or the like. In some embodiments, solder component 103d is configured to bond an interconnect structure of another substrate to semiconductor structure 100, such as a bonding pad.

FIG. 8 is a schematic flowchart illustrating a method S200 for manufacturing a semiconductor structure according to some embodiments of the present disclosure. 9 to 36 are schematic cross-sectional views illustrating various intermediate stages of preparing the semiconductor structure 100 according to some embodiments of the present disclosure.

Each stage shown in FIGS. 9 to 36 is also illustrated in the flowchart in FIG. 8 . In the following discussion, the various manufacturing stages shown in FIGS. 9 through 36 are discussed with reference to the various processing steps shown in FIG. 8 . The preparation method S200 includes many steps and the description and explanation shall not be regarded as limiting the order of such steps. The preparation method S200 includes many steps (S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, S211).

Referring to FIG. 9 , according to step S201 in FIG. 8 , a substrate 101 and a redistribution layer 102 disposed on the substrate 101 are provided. In some embodiments, the redistribution layer 102 includes a dielectric layer 102g and a conductive plug 102c. The dielectric layer 102g is disposed on the substrate 101, and the conductive plug 102c extends within the dielectric layer 102g. In some embodiments, the fabrication technique of redistribution layer 102 includes disposing dielectric material on substrate 101; removing portions of the dielectric material and disposing conductive material to form conductive plug 102c and a conductive component (102a and 102b) .

Referring to FIG. 10 , according to step S202 in FIG. 10 , an etch stop layer 104 is disposed on the redistribution layer 102 . The etch stop layer 104 is disposed on the dielectric layer 102g and the conductive plug 102c. In some embodiments, etch stop layer 104 includes a dielectric material that has an etch selectivity that is different from the etch selectivity of adjacent materials. In some embodiments, etch stop layer 104 includes nitride, silicon nitride, or the like. In some embodiments, the etching final The stop layer 104 is deposited by chemical vapor deposition (CVD) or any other suitable process.

Please refer to FIG. 11. According to a step S203 in FIG. 8, a first patterned photoresist 105 is disposed on the etching stop layer 104. In some embodiments, the fabrication technique of the first patterned photoresist 105 includes disposing a photoresist material on the etch stop layer 104; covering some portions of the photoresist material; and then removing the exposed portions of the photoresist material to pattern The photoresist material is oxidized to form a first patterned photoresist 105 . In some embodiments, a portion of the etch stop layer 104 is exposed through the first patterned photoresist 105 . In some embodiments, portions of etch stop layer 104 are exposed via first patterned photoresist 105 as shown in FIG. 12 . In some embodiments, the exposed portions of the photoresist material are configured to form a ring field having a donut shape. In some embodiments, the photoresist material is applied by spin coating or any other suitable process.

Referring to FIG. 13, according to a step S204 in FIG. 8, some portions of the dielectric layer 102g and the etching stop layer 104 exposed through the first patterned photoresist 105 are removed. In some embodiments, portions of the dielectric layer 102g and the etch stop layer 104 exposed through the first patterned photoresist 105 are removed simultaneously or sequentially. Some portions of the dielectric layer 102g and the etch stop layer 104 exposed through the first patterned photoresist 105 are removed through an etching process, such as dry etching or other suitable etching processes. In some embodiments, an opening 102s is formed. In some embodiments, removal of the portions of dielectric layer 102g exposed through first patterned photoresist 105 includes forming openings 102s that extend into dielectric layer 102g and are disposed adjacent conductive plugs 102c. In some embodiments, conductive plug 102c is at least partially exposed after opening 102s is formed. In some embodiments, a plurality of openings 102s are formed as shown in Figure 14. In some embodiments, opening 102s surrounds conductive plug 102c. In some embodiments, at least a portion of conductive plug 102c is exposed via opening 102s.

Please refer to Figure 15 or Figure 16. According to a step S205 in Figure 8, remove the first Patterned photoresist 105. In some embodiments, the first patterned photoresist 105 is removed by etching, stripping, or any suitable process.

Referring to FIG. 17 , according to a step S206 in FIG. 8 , a first seed layer 106 is disposed on the etch stop layer 104 and on a portion of the dielectric layer 102g exposed through the etch stop layer 104 . In some embodiments, the first seed layer 106 is disposed conformally to the etch stop layer 104 and the opening 102s. In some embodiments, the first seed layer 106 is disposed conformally with the plurality of openings 102s as shown in FIG. 18 . In some embodiments, at least a portion of first seed layer 106 contacts the portion of conductive plug 102c that is exposed via opening 102s. In some embodiments, the first seed layer 106 is a single layer or a composite stack and includes materials such as copper, titanium, tungsten, or combinations thereof. In some embodiments, the first seed layer 106 is provided by deposition, physical vapor deposition (PVD), or any other suitable process.

Please refer to FIG. 19. According to a step S207 in FIG. 8, a second patterned photoresist 107 is disposed on the first seed layer 106. In some embodiments, the fabrication technique of the second patterned photoresist 107 includes disposing a photoresist material on the first seed layer 106; covering some portions of the photoresist material; and then removing the exposed portions of the photoresist material. The photoresist material is patterned to form a second patterned photoresist 107 . In some embodiments, a portion of the first seed layer 106 is exposed through the second patterned photoresist 107 . In some embodiments, the photoresist material is provided by spin coating or other suitable processes. In some embodiments, a portion of the first seed layer 106 is covered by the second patterned photoresist 107 as shown in FIG. 20 . The second patterned photoresist 107 fills the opening 102s. In some embodiments, the second patterned photoresist 107 is at least partially surrounded by the first seed layer 106 .

Referring to FIG. 21 or FIG. 22 , according to a step S208 in FIG. 8 , a conductive material is disposed on the portion of the first seed layer 106 exposed through the second patterned photoresist 107 . exist In some embodiments, conductive material 108 contacts first seed layer 106 and fills opening 102s. In some embodiments, conductive material 108 includes copper, silver, gold, or the like. In some embodiments, conductive material 108 is provided by electroplating or any other suitable process.

Referring to FIG. 23 , according to step S209 in FIG. 8 , the second patterned photoresist 107 is removed. In some embodiments, the second patterned photoresist 107 is removed by etching, stripping, or any other suitable process. In some embodiments, after the second patterned photoresist is removed as shown in FIG. 24, the opening 102s is exposed.

In some embodiments, after the second patterned photoresist 107 is removed as shown in FIG. 23, as shown in FIG. 25, a portion of the conductive material 108 protruding from the etch stop layer 104 is removed. In some embodiments, the portion of conductive material 108 protruding from etch stop layer 104 is removed by etching, planarization, chemical mechanical polishing (CMP), or any other suitable process.

In some embodiments, after the second patterned photoresist 107 is removed as shown in FIG. 24, as shown in FIG. 26, an additional dielectric material 109 is disposed on the etch stop layer 104. In some embodiments, additional dielectric material 109 fills opening 102s. In some embodiments, additional dielectric material 109 surrounds a portion of conductive material 108 . In some embodiments, as shown in FIG. 27 , the additional dielectric material 109 and the portion of the conductive material 108 protruding from the etch stop layer 104 are removed. In some embodiments, the additional dielectric material 109 and the portion of the conductive material 108 protruding from the etch stop layer 104 are removed by etching, chemical mechanical polishing (CMP), or any other suitable process.

Referring to FIG. 28 or FIG. 29 , according to step S210 in FIG. 8 , the etching stop layer 104 is removed. In some embodiments, etch stop layer 104 is removed by etching or any other suitable process. In some embodiments, as shown in Figure 28, after the etch stop layer 104 is removed, a portion of the first seed layer 106 and a portion of the conductive material 108 protrude from the dielectric layer 102g. stretch. In some embodiments, as shown in Figure 29, after the etch stop layer 104 is removed, a portion of the first seed layer 106, a portion of the conductive material 108, and a portion of the additional dielectric material 109 are removed.

Referring to Figure 30 or Figure 31, according to a step S211 in Figure 8, the portion of the conductive material 108 protruding from the dielectric layer 102g is removed to form a bonding pad 102d adjacent to the conductive plug 102c and covered by the dielectric layer 102g. surrounded by. In some embodiments, conductive material 108 and portions of first seed layer 106 protruding from dielectric layer 102g are removed by etching, planarization, CMP, or any other suitable process. In some embodiments, forming includes bonding pad 102d including a seed layer 102e and a bonding pad 102f. Bond pad 102d contacts conductive plug 102c. In some embodiments, as shown in FIG. 31 , the portion of additional dielectric material 109 protruding from dielectric layer 102g is removed; as a result, a remaining portion of additional dielectric material 109 is bonded to dielectric layer 102g together.

In some embodiments, after the bonding pad 102d is formed, as shown in FIG. 32, a second seed layer 110 is disposed on the bonding pad 102d, the conductive plug 102c and the dielectric layer 102g. In some embodiments, the second seed layer 110 is a single layer or a composite stack including materials such as copper, titanium, tungsten, or combinations thereof. In some embodiments, the second seed layer 110 is provided by deposition, PVD, or any other suitable process.

In some embodiments, after the second seed layer 110 is deposited, as shown in FIG. 33 , a third patterned photoresist 111 is disposed on the second seed layer 110 . In some embodiments, the manufacturing technique of the third patterned photoresist 111 includes disposing a photoresist material on the second seed layer 110; covering some portions of the photoresist material; and then removing the portions of the photoresist material. Expose the portion to pattern the photoresist material, thereby forming a third patterned photoresist 111 . In some embodiments, a portion of the second seed layer 110 is exposed through the third patterned photoresist 111 . In some embodiments , the photoresist material is disposed by spin coating or any other suitable process.

In some embodiments, as shown in FIGS. 34 and 35 , a conductive bump 103 is formed on the portion of the second seed layer 110 exposed through the third patterned photoresist 111 . In some embodiments, as shown in FIG. 34 , a metal layer 103b, a barrier layer 103c and a solder component 103d are sequentially disposed on the portion of the second seed layer 110 exposed through the third patterned photoresist 111 superior. In some embodiments, the metal layer 103b and the barrier layer 103c are formed by electroplating, sputtering, deposition, or any other suitable process.

In some embodiments, metal layer 103b includes a conductive material such as copper, silver, gold, or the like. In some embodiments, barrier layer 103c includes titanium, titanium nitride, tantalum, tantalum nitride, nickel, or the like. In some embodiments, the manufacturing technique of solder component 103d includes pasting, deposition, or any suitable process. In some embodiments, solder component 103d includes tin, lead, silver, copper, nickel, or the like. In some embodiments, the solder component 103d undergoes a reflow process to become dome-shaped.

In some embodiments, after the metal layer 103b, the barrier layer 103c and the solder component 103d are provided, as shown in FIG. 35, the third patterned photoresist 111 is removed. In some embodiments, the third patterned photoresist 111 is removed by etching, stripping, or any suitable process.

In some embodiments, a portion of the second seed layer 110 exposed by the metal layer 103b, the barrier layer 103c, and the solder component 103d is removed to form the lower bump metal layer 103a. In some embodiments, the portion of the second seed layer 110 exposed by the metal layer 103b, the barrier layer 103c, and the solder component 103d is removed by etching or any suitable process. In some embodiments, conductive bump 103 is formed including lower bump metal layer 103a, metal layer 103b, barrier layer 103c, and solder component 103d. In some embodiments, as shown in Figure 36, a bonding wire 112 is disposed and bonded to bonding pad 102d. The bonding wire 112 connects the half through the bonding pad 102d The conductive structure 100 is electrically connected to an external circuit.

An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a base; a redistribution layer disposed on the base, and includes a dielectric layer, a conductive plug and a bonding pad; the dielectric layer is disposed on the base; the conductive plug extends on the dielectric In the layer, the bonding pad is adjacent to the conductive plug and surrounded by the dielectric layer; and a conductive bump is disposed on the conductive plug; wherein the bonding pad at least partially contacts the conductive plug and the conductive bump.

Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first substrate; and a redistribution layer disposed on the first substrate and including a dielectric layer, a conductive plug and a bonding pad, the dielectric layer is disposed on the first substrate, the conductive The plug extends within the dielectric layer, the bonding pad is surrounded by the dielectric layer and contacts the conductive plug; wherein the conductive plug is at least partially surrounded by the bonding pad.

Yet another embodiment of the present disclosure provides a method of manufacturing a semiconductor structure. The preparation method includes providing a substrate and a redistribution layer. The redistribution layer is provided on the substrate. The redistribution layer has a dielectric layer and a conductive plug. The dielectric layer is provided on the substrate. The conductive plug extending within the dielectric layer; disposing an etch stop layer on the redistribution layer; disposing a first patterned photoresist on the etch stop layer; removing a portion of the dielectric layer and passing through the first patterning A portion of the etch stop layer exposed by photoresist; removing the first patterned photoresist; disposing a first seed layer on the etch stop layer and the dielectric exposed through the first patterned photoresist on a portion of the first seed layer; disposing a second patterned photoresist on the first seed layer; disposing a conductive material on a portion of the first seed layer exposed through the second patterned photoresist; removing the second patterned photoresist; remove the etch stop layer; and remove a portion of the conductive material protruding from the dielectric layer to form a bonding pad adjacent the conductive plug and by the dielectric layer surrounded by.

In summary, because the bond pad is disposed adjacent the conductive plug in the redistribution layer, the bond pad can accommodate an external interconnect structure, such as a wire bond. Furthermore, the bond pad can be formed into different shapes so that the bond pad can accommodate the external interconnect structure from the same direction surrounding the conductive plug. Therefore, a flexible interconnection and wiring of the semiconductor structure can be achieved.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

100:Semiconductor Structure 101: Base 101a: Semiconductor layer 101b:Insulator 101c:Components 101d: Rear side 101e: Front side 102:Redistribution layer 102a: Solder pad part 102b:Through hole part 102c: Conductive plug 102d:Joint pad 102e: Solder pad 102f: seed layer 102g: dielectric layer 102h: first surface 102i: Second surface 102j:Third surface 102n:Part 1 102p:Part 2 102r:Interface 103: Conductive bumps 103a: Lower bump metal layer 103b: Metal layer 103c: Barrier layer 103d: Solder components H1: height H2: height W1: Width W2: Width

Claims (29)

A semiconductor structure includes: a substrate; a redistribution layer disposed on the substrate and including a dielectric layer, a conductive plug and a bonding pad, the dielectric layer is disposed on the substrate, and the conductive plug extends on the In the dielectric layer, the bonding pad is adjacent to the conductive plug and surrounded by the dielectric layer; and a conductive bump is disposed on the conductive plug; wherein the bonding pad at least partially contacts the conductive plug and the conductive bump; wherein A first surface of the conductive plug and a second surface of the bonding pad are exposed through the dielectric layer. The semiconductor structure of claim 1, wherein the first surface of the conductive plug and the second surface of the bonding pad are substantially coplanar. The semiconductor structure of claim 1, wherein the first surface of the conductive plug and the second surface of the bonding pad contact a seed layer of the conductive bump. The semiconductor structure of claim 1, wherein the first surface of the conductive plug, the second surface of the bonding pad, and a third surface of the dielectric layer are substantially coplanar. The semiconductor structure of claim 1, wherein the first surface of the conductive plug is completely covered by the conductive bump. The semiconductor structure of claim 1, wherein a first portion of the second surface of the bonding pad is covered by the conductive bump, a second portion of the second surface is exposed through the dielectric layer and is The conductive bump is exposed, and the first portion is substantially smaller than the second portion. The semiconductor structure of claim 1, wherein an upper cross-section of the bonding pad has an annular shape, a fan shape or a polygonal shape. The semiconductor structure of claim 1, wherein a height of the conductive plug is substantially greater than a thickness of the bonding pad. The semiconductor structure of claim 1, wherein the redistribution layer has a conductive component, and the conductive plug is electrically connected to the substrate. The semiconductor structure of claim 9, wherein the conductive component is electrically connected to the conductive plug via the conductive plug. The semiconductor structure of claim 9, wherein the conductive component is electrically connected to the bonding pad via the conductive plug. A semiconductor structure includes: a first substrate; and a redistribution layer, which is provided on the first substrate and includes a dielectric layer and a conductive plug. plug and a bonding pad, the dielectric layer is disposed on the first substrate, the conductive plug extends in the dielectric layer, the bonding pad is surrounded by the dielectric layer and contacts the conductive plug; a conductive bump covering The conductive plug partially covers the bonding pad; wherein the conductive plug is at least partially surrounded by the bonding pad. The semiconductor structure of claim 12, wherein a width of the conductive plug is substantially smaller than a width of the conductive bump. The semiconductor structure of claim 12, wherein an interface between the conductive plug and the bonding pad is disposed under the conductive bump. The semiconductor structure of claim 12, wherein the conductive bump is disposed on an interconnection structure of a second substrate and bonded to the interconnection structure of the second substrate. The semiconductor structure of claim 12, wherein the bonding pad includes a first bonding pad and a second bonding pad, the second bonding pad is spaced apart from the first bonding pad, and the conductive plug is disposed on the third bonding pad. between a bonding pad and the second bonding pad. The semiconductor structure of claim 12, further comprising a bonding wire disposed on the bonding pad and bonded to the bonding pad. The semiconductor structure of claim 12, wherein the first substrate includes a plurality of components and a plurality of insulators disposed thereon, and the plurality of insulators separate the plurality of components. A method for preparing a semiconductor structure, including: providing a substrate and a redistribution layer, the redistribution layer being disposed on the substrate, wherein the redistribution layer has a dielectric layer and a conductive plug, the dielectric layer being disposed on the base on, the conductive plug extends within the dielectric layer; an etch stop layer is disposed on the redistribution layer; a first patterned photoresist is disposed on the etch stop layer; a portion of the dielectric layer is removed and via A portion of the etch stop layer exposed by the first patterned photoresist; removing the first patterned photoresist; disposing a first seed layer on the etch stop layer and through the first patterned photoresist on a portion of the dielectric layer exposed; disposing a second patterned photoresist on the first seed layer; disposing a conductive material on a portion of the first seed layer exposed through the second patterned photoresist on a portion; remove the second patterned photoresist; remove the etch stop layer; and remove a portion of the conductive material protruding from the dielectric layer to form a bonding pad adjacent to the conductive plug and surrounded by this dielectric layer. The preparation method of claim 19, wherein the first seed layer disposed on the etching stop layer contacts the conductive plug. The preparation method of claim 19, wherein the bonding pad includes the first seed layer and the conductive material. The preparation method of claim 19, wherein after the second patterned photoresist is removed, the portion of the conductive material protrudes from the etching stop layer. The preparation method of claim 19, wherein removing the portion of the dielectric layer exposed through the first patterned photoresist includes forming an opening extending into the dielectric layer and disposed adjacent to the conductive plug at. The preparation method of claim 23, wherein after the opening is formed, the conductive plug is at least partially exposed. The preparation method as claimed in claim 23, wherein the opening surrounds the conductive plug. The preparation method of claim 25, wherein the second patterned photoresist fills a part of the opening. The preparation method of claim 25, wherein the second patterned photoresist is at least partially surrounded by the first seed layer. The preparation method of claim 25, further comprising: disposing a dielectric material in the opening and on the etching stop layer; and A portion of the dielectric material disposed on the etch stop layer is removed. The preparation method of claim 19, further comprising: arranging a second seed layer on the bonding pad, the conductive plug and the dielectric layer; arranging a third patterned photoresist on the second seed layer on; and forming a conductive bump on a portion of the second seed layer exposed through the third patterned photoresist.