TWI812094B - Filament forming method for resistive memory unit - Google Patents

Abstract

A filament forming method for resistive memory unit is provided, applying a first bias voltages including a gate voltage and drain voltage, in a first forming stage, to the resistive memory unit for multiple times. When the reading current in the forming process of the first forming stage reaches a first saturation state, latching the read current of the first saturation state as a saturation read current, and determining whether an increasing rate of the saturation read current is less than a first threshold value. If the saturation read current is not less than the first threshold value, a second forming stage is performed by applying a second bias voltages by increasing the gate voltage and reducing the drain voltage, to the resistive memory unit for multiple times until the read current reaches a second saturation state, latching the read current of the second saturation state as the saturation read current, and determining whether the increasing rate of the saturated read current is less than the first threshold value. When the increasing rate of the saturation read current is not less than the first threshold value and the saturation read current reaches a target value, the method is finished.

Description

Resistive wire forming method for resistive memory unit

The invention relates to a resistance wire forming method of a resistive memory unit.

Resistive memory is very suitable as the next generation of non-volatile memory devices due to its potential advantages of low power consumption, high-speed operation, high density and compatibility with complementary metal oxide semiconductor process technology.

Figure 1 shows a schematic structural diagram of a general 1T1R resistive memory. As shown in Figure 1, a resistive memory usually includes a resistive element R and a switching element T. The resistive element R includes an upper electrode 14b and a lower electrode 14a arranged oppositely and a dielectric layer (for example, transition metal oxide (TMO)) 12 located between the upper electrode 14b and the lower electrode 14a. In a resistive memory Before being able to repeatedly switch between high and low resistance states to memorize data, the filament forming process must first be performed. The filament forming process involves applying a bias voltage to the resistive memory. For example, on the gate of the switching element T The gate voltage Vg is applied, and the drain voltage Vd is applied to the electrode 14b above the resistive element R. The bias voltage, such as a forward bias voltage, generates oxygen vacancies and oxygen ions in the dielectric layer, and causes the oxygen ions to escape from the dielectric layer (TMO ) to form a current path (resistance wire structure) in the dielectric layer, thereby changing the resistive memory from a high resistance state to a low resistance state. After that, the resistive memory can be reset (RESET) or set (SET) ) program to switch the resistive memory to a high-resistance state and a low-resistance state respectively to complete the memory of data.

Figure 2 shows the relationship between the voltage acting on the dielectric layer (such as TMO) and the forming current (i.e., the read current after the forming process is completed) during the resistor wire forming process, as well as the correlation with the gate voltage. It can be seen from Figure 2 that when the gate voltage Vg is above 1.5V, the voltage acting on the TMO will be too small (below 0.3V as shown in the figure), so there is not enough electric field to push oxygen ions out of the TMO. When the gate voltage Vg is too low (such as Vg=0.65V), although the voltage acting on the TMO increases, the forming current is almost 0, which means that there are not enough oxygen vacancies in the TMO to form a current path. Therefore, it is difficult to select an appropriate gate voltage Vg for resistor wire molding, resulting in poor molding efficiency.

Figure 3 shows the current change diagram before and after the initial (first) reset after the resistor wire is formed in the conventional art. The x-axis in the figure is the current before the initial reset, and the y-axis is the current after the initial reset. After the resistor is formed, when the current flows too early and the initial reset is performed, many bits will increase the current after the reset instead of decreasing the current. That is, the formed resistance wire structure may not be stable enough, resulting in degradation of the reliability of the resistive memory. This will also affect molding efficiency.

In summary, a more reliable molding method is needed to enable enough oxygen ions to escape from the TMO, form a stable resistor wire structure, and reduce the generation of current tails.

According to an embodiment of the present invention, a resistance wire forming method for a resistive memory is provided, including: applying a first bias voltage to the resistive memory unit multiple times until the read current of the resistive memory unit reaches a first saturation state, wherein the first bias voltage each time includes a gate voltage and a drain voltage; latch the read current in the first saturation state as a saturated read current, and determine the saturated read Whether the increase rate of the current is lower than a first threshold; when it is determined that the increase rate of the saturated read current is not lower than a first threshold, the gate voltage is increased and the gate voltage is decreased for the first bias voltage. The drain voltage is used as a second bias voltage; the second bias voltage is applied to the resistive memory cell until the read current of the resistive memory cell reaches a second saturation state; latch lock the read current in the second saturated state as the saturated read current, and determine again whether the increase rate of the saturated read current is lower than the first threshold; and determine the saturated read current Whether the target current value is reached, and if the target current value is reached, the forming method is ended.

According to another embodiment of the present invention, a resistance wire forming method of a resistive memory unit is provided, including: performing a first-stage forming process to apply a first bias voltage including a gate voltage and a drain voltage to the said resistive wire multiple times. The resistive memory unit, until the read current of the resistive memory unit reaches a first saturated state, the read current that latches the first saturated state is a saturated read current, and determines that the saturated read current Check whether the increase rate of the current is lower than the first threshold; when the increase rate of the saturated read current is not lower than the first threshold, execute the second stage molding process and apply a second bias voltage to the The resistive memory unit waits until the read current of the resistive memory unit reaches a second saturation state, and determines whether the increase rate of the saturated read current is lower than the first threshold, wherein the third The second bias voltage is to increase the gate voltage and reduce the drain voltage; and when the increase rate of the saturated read current is lower than the first threshold, and when the saturated read current reaches the target current value When, the blocking wire forming method ends.

The most basic resistive memory unit is composed of a switching element (transistor) and a resistive element (1T1R). The resistive element is composed of upper and lower layers of metal electrodes and a middle layer such as a transition metal oxide (hereinafter referred to as TMO). composed of dielectric layers (refer to the example in Figure 1). The following embodiments will be described with a resistive memory cell of 1T1R structure, but it is not limited to this structure. The method disclosed in this embodiment can also be applied to other resistive memory cell structures such as 2T1R or 2T2R.

FIG. 4 is a schematic flowchart of the resistance wire forming method of the resistive memory in this embodiment. FIG. 5A shows a waveform diagram of the applied voltage in the process of the resistance wire forming method of the resistive memory in this embodiment.

Please refer to Figures 4 and 5. First, the resistive memory in the initial high-resistance state is subjected to the first stage of resistive wire molding. In step S100, gate voltage Vg and drain voltage Vd (first bias voltage) are applied to the resistive memory cell. The gate voltage Vg and the drain voltage Vd are, for example, pulse voltages with a certain width. In this embodiment, the gate voltage Vg of the first bias is, for example, 1V, and its pulse width PW is, for example, 50 ns; the drain voltage Vd of the first bias is, for example, 4V, and its pulse width PW is, for example, 50 ns.

Next, in step S102, the read current Icell is sensed to the resistive memory cell and the read current Icell is latched. For example, a register (such as a shift register) or a storage unit with similar functions can be set up in the memory system to latch the latest read current Icell.

Next, in step S104, it is determined whether the increase rate of the read current Icell is lower than the first threshold. When the increase rate of the read current Icell is not lower than the first threshold, it means that the read current Icell has not reached the saturation state. At this time, the cycle of steps S100, S102, and S104 will continue to apply the gate to the resistive memory cell. voltage Vg and drain voltage Vd (first bias voltage) until the increase rate of the read current Icell is lower than the first threshold.

In one embodiment, when the read current Icell is stored through the N-bit shift register, for example, 1/2 ^N can be used as the first threshold. For example, when the read current Icell is stored through a 3-bit shift register, 1/2 ³ =0.125 can be used as the first threshold.

In step S104, when it is determined that the increase rate of the read current Icell is lower than the first threshold, it means that the read current Icell has reached a saturated state, and the first stage of resistor wire forming is completed. Then in step S106, the read current Icell is latched as the saturated read current. As shown in Figure 5A, the read current Icell in the first stage reaches saturation after applying the first bias voltage (pulse voltage F1~F8) 8 times. At this time, the read current Icell corresponding to the pulse voltage F8 is latched to the saturated read state. Take current.

Next, in step S110, it is determined whether the increase rate of the saturated read current is lower than a second threshold. When the increase rate of the saturated read current is not lower than the second threshold, it means that further oxygen vacancies and oxygen ions can still be generated in the dielectric layer (TMO), and the formed resistance wire structure has not yet reached a stable state. At this time, Continue to perform the second stage of resistive wire molding on the resistive memory unit. At this time, the resistive memory unit is in an initial low-resistance state.

In one embodiment, when latching the saturation read current through the N-bit shift register, for example, 1/2 ^N may be used as the second threshold. Similarly, when latching the saturation read current through a 3-bit shift register, for example, 1/2 ³ =0.125 can be used as the second threshold.

In step S110, when the increase rate of the saturated read current is not less than the second critical value, step S112 is performed to increase the gate voltage Vg and decrease the drain voltage Vd as the second bias voltage. After that, return to step S100, apply gate voltage Vg and drain voltage Vd (second bias) to the resistive memory cell, and repeat the cycle of steps S100 to S104 until the read current Icell reaches the saturated state again ( After the increase rate of the read current Icell is lower than the first threshold), the saturated read current Icell is latched again (step S106). As shown in the second stage of Figure 5A, in this embodiment, when it is determined that the increase rate of the saturated read current has not been lower than the second threshold, the gate voltage Vg is increased to 1.5V and the drain voltage is reduced to 3V is used as the second bias voltage, and after applying the second bias voltage P1 to P3 to the resistive memory unit three times, the read current Icell of the resistive memory unit reaches a saturated state again. At this time, the read current Icell corresponding to the pulse voltage P3 is latched to the saturated read current. Similarly, when it is determined again that the increase rate of the saturated read current has not been lower than the second threshold, the gate voltage Vg is first increased to 2V, the drain voltage is reduced to 2.5V as the third bias voltage, and then the After the third bias voltage 2P1~2P2 is applied to the resistive memory unit twice, the read current Icell of the resistive memory unit reaches a saturated state again. At this time, the read current Icell corresponding to the pulse voltage 2P2 is latched to the saturated read current.

As shown in FIG. 4 and FIG. 5A , before it is determined that the increase rate of the saturated read current is lower than the second threshold, this embodiment will continue to adjust the bias voltage applied to the resistive memory cell until the increase rate of the saturated read current is low. at the second threshold. Here, the amount of increase in the gate voltage Vg and the amount of decrease in the drain voltage Vd in the bias voltage are not particularly limited.

Returning to step S110, when it is determined that the increase rate of the saturated reading current is lower than the second threshold, it means that the resistor wire structure has reached a stable state, and the second stage of resistor wire forming is completed. Then a final verification stage is carried out to verify whether the saturated read current of the resistive memory cell has reached the target current value. Specifically, step S120 is performed to determine whether the saturated read current has reached the target current value. When it is determined that the saturated reading current reaches the target current value, the resistor wire forming method of the present invention ends. On the contrary, when it is determined that the saturated read current has not reached the target current value, step S122 is executed to increase both the gate voltage Vg and the drain voltage Vd, and in step S124, the increased gate voltage Vg is applied to the resistive memory cell. and drain voltage Vd. Next, in step S126, the read current Icell is sensed again and it is determined whether the read current Icell reaches the target current value. If the target current value has been reached, the resistor wire forming method of this embodiment is ended. Otherwise, the loop of steps S122, S124 and S126 is executed again until the reading current Icell reaches the target current value.

FIG. 6A shows the distribution diagram of the current before initial reset and the current after initial reset using the resistor wire forming method of this embodiment. 6B shows the distribution diagram of the current before initial reset and the current after initial reset using the conventional resistance wire forming method of FIG. 5B. As shown in Figure 6A, after using the process of Figure 4 to perform resistance wire molding in this embodiment, the resistive memory unit has an obvious low resistance state (high current before initial reset), and has almost no resistance after the initial reset. The current tail appears above the dashed line in Figure 6A. Therefore, it can be seen that the resistor wire structure formed in the present invention has a stable state and can avoid the generation of large current tails.

On the contrary, as a comparison, through the voltage application method of the conventional resistance wire forming method as shown in Figure 5B, it can be seen from Figure 6B that it cannot form an obvious low resistance state (the current before the initial reset is low), and during the After the initial reset, there is still a lot of current tail above the dotted line. The formed resistance wire structure is not stable and has poor reliability.

As mentioned above, the resistance wire forming method of this embodiment will first repeatedly verify whether the formed resistance wire structure has reached a stable state through two stages of resistance wire forming, and only after it is determined that the formed resistance wire structure has been stabilized, further steps will be taken. Verify that the read current of the resistive memory cell has reached the target current value. Compared with the conventional method, when it is not judged whether the resistance wire structure is stable, it is directly verified whether the read current reaches the target current value. The resistance wire forming method of this embodiment can effectively reduce the generation of current tails and improve the reliability of the resistive memory unit.

12: Dielectric layer (TMO) 14a: Lower electrode 14b:Electrode T: switching element R: Resistor element Vg: gate voltage Vd: drain voltage S100~S236: Each step

Figure 1 shows a schematic structural diagram of a general 1T1R resistive memory. Figure 2 shows the relationship between the voltage acting on the dielectric layer and the forming current during the resistor wire forming process, as well as the correlation with the gate voltage. FIG. 3 illustrates the correlation distribution diagram of the conventional current before initial reset and the current after initial reset. FIG. 4 is a schematic flowchart of the resistance wire forming method of the resistive memory in this embodiment. FIG. 5A illustrates an example of bias voltage application in the resistance wire forming method of the resistive memory in this embodiment. FIG. 5B illustrates a bias voltage application method in a conventional resistor wire forming method. FIG. 6A shows the distribution diagram of the initial current and the current after reset using the molding process of this embodiment. FIG. 6B shows the distribution diagram of the initial current and the current after reset using the conventional molding process of FIG. 5B.

S100~S126: Each step

Claims (14)

A resistance wire forming method for a resistive memory unit, including: Applying a first bias voltage to the resistive memory unit multiple times until the read current of the resistive memory unit reaches a first saturation state, wherein each The first bias voltage includes a gate voltage and a drain voltage; Latch the read current in the first saturated state as a saturated read current, and determine whether the increase rate of the saturated read current is lower than a first threshold; When it is determined that the increase rate of the saturated read current is not lower than the first threshold, for the first bias voltage, the gate voltage is increased and the drain voltage is decreased as the second bias voltage ; Applying the second bias voltage to the resistive memory cell until the read current of the resistive memory cell reaches a second saturation state, latching the read in the second saturation state current as the saturated read current, and determine again whether the increase rate of the saturated read current is lower than the first threshold; and When it is determined that the increase rate of the saturated read current is lower than the first threshold, it is determined whether the saturated read current reaches the target current value, and when the target current value is reached, the resistance is terminated. Silk forming method. According to the resistance wire forming method of the resistive memory unit of claim 1, when the increase rate of the read current is lower than a second threshold, it is determined that the read current has reached the first saturation state. The resistance wire forming method of a resistive memory unit as claimed in claim 1, wherein the read current in the latch second saturation state is used as the saturated read current, and the saturated read is determined Under the condition that the current increase rate is not lower than the first threshold, it further includes: Continue to apply the second bias voltage, increase the gate voltage and decrease the drain voltage as the third bias voltage; Applying the third bias voltage to the resistive memory cell until the read current of the resistive memory cell reaches a third saturation state; and The read current in the third saturated state is latched as the saturated read current, and it is determined again whether the increase rate of the saturated read current is lower than the first threshold. The resistance wire forming method of the resistive memory unit as described in claim 1 further includes: When it is determined that the saturated read current has not reached the target current value, increase the gate voltage and the drain voltage; and Apply the increased gate voltage and the increased drain voltage to the resistive memory unit, and determine whether the read current of the resistive memory unit reaches the target current value. The resistance wire forming method of a resistive memory cell as claimed in claim 2, wherein the second threshold is determined by the number of bits of the storage cell that latch the read current. The resistance wire forming method of a resistive memory cell as claimed in claim 5, wherein when the number of bits is N (N is a positive integer), the second threshold is 1/2 ^N . The resistance wire forming method of a resistive memory cell as claimed in claim 1, wherein the drain voltage is greater than the gate voltage. A resistance wire forming method for a resistive memory unit, including: Execute a first-stage molding process to apply a first bias voltage including a gate voltage and a drain voltage to the resistive memory unit multiple times until the read current of the resistive memory unit reaches a first saturation state. , the read current that latches the first saturated state is a saturated read current, and determines whether the increase rate of the saturated read current is lower than a first threshold; When the increase rate of the saturated read current is not lower than the first threshold, a second stage shaping process is performed, and a second bias voltage is applied to the resistive memory unit multiple times until the resistive memory unit The read current of the body unit reaches a second saturated state, the read current latching the second saturated state is the saturated read current, and it is determined whether the increase rate of the saturated read current is lower than the first threshold, wherein the second bias is to increase the gate voltage and decrease the drain voltage; and When the increase rate of the saturated read current is not lower than the first threshold, and when the saturated read current reaches the target current value, the resistor wire forming method is ended. According to the resistance wire forming method of the resistive memory unit described in claim 8, when the increase rate of the read current is lower than the second threshold, it is determined that the read current has reached the first saturation state. The resistance wire forming method of a resistive memory unit as claimed in claim 8, wherein the read current in the second saturated state is the saturated read current, and the saturated read current is determined If the increase rate is not lower than the first threshold, the method further includes: applying a third bias voltage to the resistive memory unit multiple times, and executing the second-stage molding process again until the resistive memory unit The read current of the memory cell reaches a third saturated state, the read current latching the third saturated state is the saturated read current, and it is determined whether the increase rate of the saturated read current is low. At the first threshold, wherein the third bias voltage is relative to the second bias voltage, the gate voltage is increased and the drain voltage is decreased. The resistance wire forming method of the resistive memory unit as described in claim 8 further includes: When the saturated read current does not reach the target current value, increase the gate voltage and the drain voltage; Apply the increased gate voltage and the increased drain voltage to the resistive memory unit, and determine whether the read current of the resistive memory unit reaches the target current value. The resistance wire forming method of a resistive memory cell as claimed in claim 9, wherein the second threshold is determined by the number of bits of the storage cell that latch the read current. The resistance wire forming method of a resistive memory cell as claimed in claim 12, wherein when the number of bits is N (N is a positive integer), the second threshold is 1/2 ^N . The resistance wire forming method of a resistive memory cell as claimed in claim 8, wherein the drain voltage is greater than the gate voltage.