TWI810768B - Printed circuit board and manufacturing method thereof - Google Patents
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- TWI810768B TWI810768B TW110148995A TW110148995A TWI810768B TW I810768 B TWI810768 B TW I810768B TW 110148995 A TW110148995 A TW 110148995A TW 110148995 A TW110148995 A TW 110148995A TW I810768 B TWI810768 B TW I810768B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 281
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 157
- 229910052802 copper Inorganic materials 0.000 claims abstract description 155
- 239000010949 copper Substances 0.000 claims abstract description 155
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims description 78
- 229910052751 metal Inorganic materials 0.000 claims description 78
- 239000000463 material Substances 0.000 claims description 54
- 230000004308 accommodation Effects 0.000 claims description 18
- 210000004209 hair Anatomy 0.000 claims description 16
- 238000009713 electroplating Methods 0.000 claims description 15
- 239000004642 Polyimide Substances 0.000 claims description 8
- 229920001721 polyimide Polymers 0.000 claims description 8
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 6
- 229910052731 fluorine Inorganic materials 0.000 claims description 6
- 239000011737 fluorine Substances 0.000 claims description 6
- 229920000642 polymer Polymers 0.000 claims description 5
- 238000006479 redox reaction Methods 0.000 claims description 5
- 229920000106 Liquid crystal polymer Polymers 0.000 claims description 4
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 claims description 4
- 229910010293 ceramic material Inorganic materials 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 268
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000003032 molecular docking Methods 0.000 description 2
- 102200048773 rs2224391 Human genes 0.000 description 2
- 229920006026 co-polymeric resin Polymers 0.000 description 1
- 230000003699 hair surface Effects 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- -1 polytetrafluoroethylene, tetrachloroethylene Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
本申請涉及一種電路板及電路板的製作方法,特別是具有高密度對接效果的電路板。The present application relates to a circuit board and a method for making the circuit board, in particular to a circuit board with a high-density docking effect.
傳統之軟性電路板(Flexible Printed Circuit, FPC)要製作成多層的形式,例如十至二十層,在作業上一般會較為複雜且困難。The traditional flexible printed circuit (FPC) has to be made into multi-layers, such as ten to twenty layers, which is generally more complicated and difficult to operate.
此外,傳統之FPC係以膠層進行多層堆疊,然而在一層一層堆疊的狀況下,容易耗時又耗能。並且採用膠層黏合堆疊時,為使層與層之間電性連接,需另外生成導電柱等,而使製程更加複雜,且良率等亦會受到影響。再者,FPC往往需要在高溫下進行焊接或壓合,導致FPC受到高溫而影響特性。In addition, the traditional FPC is multi-layer stacked with adhesive layers. However, in the case of layer-by-layer stacking, it is easy to consume time and energy. In addition, when adhesive layers are used for bonding and stacking, in order to electrically connect the layers, it is necessary to generate additional conductive pillars, which makes the manufacturing process more complicated, and the yield rate will also be affected. Furthermore, FPC often needs to be welded or pressed at a high temperature, causing the FPC to be subjected to high temperature to affect its characteristics.
鑒於上述,根據一實施例提供一種電路板的製作方法,包括提供第一基板及第二基板。第一基板包括第一基材層及第一銅層,第一基材層具有相對之第一表面及第二表面,第一銅層位於第一表面。第二基板包括第二基材層及第二銅層,第二基材層具有相對之第三表面及第四表面,第二銅層位於第三表面。進行預處理,在第一基板的第一銅層之表面形成第一絨毛層,在第二基板的第二銅層之表面上形成第二絨毛層。第一絨毛層具有複數個第一絨毛及複數個第一容納部,各第一絨毛之間形成第一容納部。第二絨毛層具有複數個第二絨毛及複數個第二容納部,各第二絨毛之間形成第二容納部。將第一基板與第二基板對接,使第一基板的該些第一絨毛與第二基板的該些第二容納部,第二基板的該些第二絨毛與第一基板的該些第一容納部相互嵌合。In view of the above, according to an embodiment, a method for manufacturing a circuit board is provided, including providing a first substrate and a second substrate. The first substrate includes a first base material layer and a first copper layer, the first base material layer has a first surface and a second surface opposite to each other, and the first copper layer is located on the first surface. The second substrate includes a second base material layer and a second copper layer, the second base material layer has a third surface and a fourth surface opposite to each other, and the second copper layer is located on the third surface. Pretreatment is performed to form a first fluff layer on the surface of the first copper layer of the first substrate, and to form a second fluff layer on the surface of the second copper layer of the second substrate. The first fluff layer has a plurality of first fluffs and a plurality of first accommodation parts, and the first accommodation parts are formed between the first fluffs. The second fluff layer has a plurality of second fluffs and a plurality of second accommodation parts, and the second accommodation parts are formed between the second fluffs. The first substrate is docked with the second substrate, so that the first hairs of the first substrate are connected to the second receiving parts of the second substrate, and the second hairs of the second substrate are connected to the first hairs of the first substrate. The accommodating parts are fitted with each other.
在一些實施例中,於提供第一基板及第二基板的步驟前,進行電鍍沉積,於第一基材層的第一表面形成第一金屬層,於第二基材層的第三表面形成第二金屬層。進行電鍍,在第一金屬層上形成第一銅層,在第二金屬層上形成第二銅層。In some embodiments, before the step of providing the first substrate and the second substrate, electroplating deposition is performed to form the first metal layer on the first surface of the first base material layer, and form a metal layer on the third surface of the second base material layer. second metal layer. Electroplating is performed to form a first copper layer on the first metal layer and a second copper layer on the second metal layer.
在一些實施例中,於提供第一基板及第二基板的步驟前,進行金屬塗佈,於第一基材層的第一表面形成第一金屬層。於第二基材層的第三表面形成第二金屬層。進行氧化還原反應,在第一金屬層上形成第一銅層,在第二金屬層上形成第二銅層。In some embodiments, before the step of providing the first substrate and the second substrate, metal coating is performed to form a first metal layer on the first surface of the first base material layer. A second metal layer is formed on the third surface of the second base material layer. A redox reaction is performed to form a first copper layer on the first metal layer and a second copper layer on the second metal layer.
在一些實施例中,於提供第一基板及第二基板的步驟前,進行金屬化,於第一基材層的第一表面形成第一金屬層。於第二基材層的第三表面形成第二金屬層。進行電鍍,在第一金屬層上形成第一銅層,在第二金屬層上形成第二銅層。In some embodiments, before the steps of providing the first substrate and the second substrate, metallization is performed to form a first metal layer on the first surface of the first base material layer. A second metal layer is formed on the third surface of the second base material layer. Electroplating is performed to form a first copper layer on the first metal layer and a second copper layer on the second metal layer.
在一些實施例中,第一基材層及第二基材層係為聚醯亞胺、改質聚醯亞胺、液晶高分子、氟素高分子或陶瓷材料所製成。In some embodiments, the first substrate layer and the second substrate layer are made of polyimide, modified polyimide, liquid crystal polymer, fluorine polymer or ceramic material.
在一些實施例中,其中,第一基板包括第三銅層,第三銅層位於第二表面。第二基板包括第四銅層,第四銅層位於第四表面。進行預處理,在第一基板的第三銅層之表面上形成第三絨毛層,在第二基板的第四銅層之表面上形成第四絨毛層。第三絨毛層具有複數個第三絨毛及複數個第三容納部,各第三絨毛之間形成第三容納部。第四絨毛層具有複數個第四絨毛及複數個第四容納部,各第四絨毛之間形成第四容納部。In some embodiments, wherein the first substrate includes a third copper layer, and the third copper layer is located on the second surface. The second substrate includes a fourth copper layer, and the fourth copper layer is located on the fourth surface. Pretreatment is performed to form a third fluff layer on the surface of the third copper layer of the first substrate, and form a fourth fluff layer on the surface of the fourth copper layer of the second substrate. The third fluff layer has a plurality of third fluffs and a plurality of third receiving parts, and the third receiving parts are formed between the third fluffs. The fourth fluff layer has a plurality of fourth fluffs and a plurality of fourth receiving parts, and the fourth receiving parts are formed between the fourth fluffs.
在一些實施例中,第一銅層、第二銅層、第三銅層及第四銅層的厚度為2至150µm。In some embodiments, the thickness of the first copper layer, the second copper layer, the third copper layer and the fourth copper layer is 2 to 150 μm.
根據一實施例提供一種電路板,包括第一基板及第二基板。第一基板包括第一基材層及第一銅層,第一基材層具有相對之第一表面及第二表面,第一銅層位於第一表面。第一基板的第一銅層之表面上具有第一絨毛層,第一絨毛層具有複數個第一絨毛及複數個第一容納部,各第一絨毛之間形成第一容納部。第二基板具有第二基材層及第二銅層,第二基材層具有相對之第三表面及第四表面,第二銅層位於第三表面。第二基板的第二銅層之表面上具有第二絨毛層,第二絨毛層具有複數個第二絨毛及複數個第二容納部,各第二絨毛之間形成第二容納部。第一基板與第二基板對接,使第一基板的該些第一絨毛與第二基板的該些第二容納部相互嵌合,第二基板的該些第二絨毛與第一基板的該些第一容納部相互嵌合。According to an embodiment, a circuit board is provided, including a first substrate and a second substrate. The first substrate includes a first base material layer and a first copper layer, the first base material layer has a first surface and a second surface opposite to each other, and the first copper layer is located on the first surface. The surface of the first copper layer of the first substrate has a first fluff layer, and the first fluff layer has a plurality of first fluffs and a plurality of first accommodation parts, and the first accommodation parts are formed between the first fluffs. The second substrate has a second base material layer and a second copper layer, the second base material layer has a third surface and a fourth surface opposite to each other, and the second copper layer is located on the third surface. There is a second fluff layer on the surface of the second copper layer of the second substrate, and the second fluff layer has a plurality of second fluffs and a plurality of second accommodation parts, and the second accommodation parts are formed between the second fluffs. The first substrate is docked with the second substrate, so that the first hairs of the first substrate and the second receiving parts of the second substrate are mutually fitted, and the second hairs of the second substrate are connected with the first hairs of the first substrate. The first receiving parts fit into each other.
在一些實施例中,更包括第三基板,第三基板包括第三基材層及第五銅層,第三基材層具有相對之第五表面及第六表面,第五銅層位於第五表面。第三基板的第五銅層之表面上具有第五絨毛層,第五絨毛層具有複數個第五絨毛及複數個第五容納部,各第五絨毛之間形成第五容納部。第一基板與第三基板對接,使第一基板的該些第一絨毛與第三基板的該些第五容納部相互嵌合,第三基板的該些第五絨毛與第一基板的該些第一容納部相互嵌合,且第三基板與第二基板相互平行。In some embodiments, it further includes a third substrate, the third substrate includes a third substrate layer and a fifth copper layer, the third substrate layer has a fifth surface and a sixth surface opposite to each other, and the fifth copper layer is located on the fifth surface. The surface of the fifth copper layer of the third substrate has a fifth fluff layer, and the fifth fluff layer has a plurality of fifth fluffs and a plurality of fifth receiving parts, and the fifth receiving parts are formed between the fifth fluffs. The first substrate is docked with the third substrate, so that the first hairs of the first substrate are fitted with the fifth receiving parts of the third substrate, and the fifth hairs of the third substrate are connected with the fifth receiving parts of the first substrate. The first accommodating parts are fitted with each other, and the third substrate and the second substrate are parallel to each other.
在一些實施例中,第一基材層包括至少一基材、至少二金屬線路及至少一導通孔。至少二金屬線路係形成於至少一基材之相對二側面,至少一導通孔係貫穿至少一基材並電性連接至少二金屬線路。In some embodiments, the first substrate layer includes at least one substrate, at least two metal lines, and at least one via hole. At least two metal circuits are formed on two opposite sides of at least one substrate, and at least one via hole penetrates through at least one substrate and electrically connects at least two metal circuits.
綜上所述,透過電路板的製作方法,製作具有絨毛銅面結構的基板。藉由將具有絨毛銅面結構的基板模組化,使基板能夠透過絨毛層與其他基板的絨毛層相互嵌合,以達到快速壓合嵌接的效果。此外,由於基板與其他基板的嵌合能夠在較低溫下進行,因此可以避免因較高溫的作業環境而影響電路板之特性。To sum up, through the manufacturing method of the circuit board, the substrate with the copper hair surface structure is manufactured. By modularizing the substrate with the fuzzy copper surface structure, the substrate can be interfitted with the fuzz layers of other substrates through the fuzz layer, so as to achieve the effect of fast pressing and fitting. In addition, since the bonding between the substrate and other substrates can be carried out at a relatively low temperature, it is possible to avoid affecting the characteristics of the circuit board due to a relatively high temperature operating environment.
請參閱圖11並同時參閱圖1至圖6B。圖1為根據一第一實施例電路板的製作方法之具有銅層之基板立體示意圖。圖2為根據一第一實施例電路板的製作方法之具有絨毛銅層之基板立體示意圖。圖3A為圖2中標號3A的局部放大圖。圖3B為圖2中標號3B的局部放大圖。圖4為根據一第一實施例電路板之立體示意圖。圖5為圖4中標號5的局部放大圖。圖6A為根據一第一實施例電路板的製作方法之基板側視圖。圖6B為根據一第一實施例電路板的基板結構示意圖。圖11為根據一第一實施例電路板的製作方法之流程圖。電路板100係為軟性電路板,可以應用於例如手機、筆記型電腦或平板電腦。Please refer to FIG. 11 and also refer to FIGS. 1 to 6B. FIG. 1 is a schematic perspective view of a substrate with a copper layer according to a manufacturing method of a circuit board according to a first embodiment. FIG. 2 is a schematic perspective view of a substrate with a fuzzy copper layer according to a manufacturing method of a circuit board according to a first embodiment. FIG. 3A is a partially enlarged view of the
一種電路板100的製作方法,包括提供第一基板110及第二基板130(步驟S10)。如圖1所示,第一基板110包括第一基材層111及第一銅層112,第一基材層111具有相對之第一表面111a及第二表面111b,第一銅層112位於第一表面111a。第二基板130具有第二基材層131及第二銅層132,第二基材層131具有相對之第三表面131a及第四表面131b,第二銅層132位於第三表面131a。A method for manufacturing a
進行預處理(步驟S11A),如圖2、圖3A及圖3B所示,在第一基板110的第一銅層112之表面形成第一絨毛層113,在第二基板130的第二銅層132之表面上形成第二絨毛層133。第一絨毛層113具有複數個第一絨毛1131及複數個第一容納部1132,各第一絨毛1131之間形成第一容納部1132。第二絨毛層133具有複數個第二絨毛1331及複數個第二容納部1332,各第二絨毛1331之間形成第二容納部1332。Carry out pretreatment (step S11A), as shown in Fig. 2, Fig. 3A and Fig. 3B, form the
在第一實施例中,第一基板110與第二基板130具有相同對應之結構。在第一實施例中,如圖1所示,第一基板110及第二基板130係為軟質銅箔基板(Flexible Copper Clad Laminate, FCCL)。圖6A示出了帶有雙面銅箔之基板,但不限於此,亦可以僅具有單面之銅箔。在其他實施態樣中,第一基板110及第二基板130可以例如為低溫共燒陶瓷(Low Temperature Co-fired Ceramic, LTCC)或積層陶瓷電容器(Multi-layer Ceramic Capacitor, MLCC)等帶有銅之基板。此外,第一基板110及第二基板130的銅層亦可以藉由電鍍或氧化還原反應所形成。關於第一基板110的第一銅層112及第二基板130的第二銅層132之形成具有多種實施態樣(容後詳述)。In the first embodiment, the
接著,將第一基板110與第二基板130對接(步驟S12),如圖4及圖5所示,使第一基板110的該些第一絨毛1131與第二基板130的該些第二容納部1332相互嵌合,第二基板130的該些第二絨毛1331與第一基板110的該些第一容納部1132相互嵌合。Next, the
具體來說,第一基板110的第一銅層112具有多個第一絨毛1131,各個第一絨毛1131之間的間隙形成第一容納部1132,第二基板130的第二銅層132具有多個第二絨毛1331,各個第二絨毛1331之間的間隙形成第二容納部1332。當第一基板110與第二基板130相互對接時,第一基板110的第一絨毛1131容納至第二基板130的第二容納部1332,第二基板130的第二絨毛1331容納至第一基板110的第一容納部1132,以使第一絨毛層113與第二絨毛層133形成類似拉鍊的形式,相互嵌合。在第一實施例中,第一基板110與第二基板130在溫度250℃以下,透過焊接或壓合的方式相互嵌合。Specifically, the
也就是說,透過電路板100的製作方法,製作具有絨毛銅面結構的第一基板110及第二基板130。將具有絨毛銅面結構的第一基板110模組化,使得第一基板110能夠透過絨毛層與第二基板130的絨毛層相互嵌合,以達到快速壓合嵌接的效果。此外,由於第一基板110與第二基板130的嵌合能夠在較低溫下進行,因此可以避免較高溫的作業環境而影響電路板之特性。在第一實施例中,第一基材層111及第二基材層131係為聚醯亞胺、改質聚醯亞胺、液晶高分子、氟素高分子或陶瓷材料所製成,並且第一基材層111及第二基材層131可以為相同材料,也可以是不同材料。在此,氟素高分子係為聚四氟乙烯、四氯乙烯共聚和樹脂或氟素樹脂。That is to say, through the manufacturing method of the
在第一實施例中,第一基材層111及第二基材層131可以例如為一層或多層基材所組成之基材層,以將一層或多層基材所組成之基材層模組化為第一基材層111或第二基材層131,再將該些模組化的第一基材層111或第二基材層131相互壓合嵌接,以使整體製程速度可以大幅提升。請參閱圖6B,圖6B為根據一第一實施例電路板的基板結構示意圖。舉例來說,第一基板110具有由多層基材1112及金屬線路1113所堆疊形成的第一基材層111。如圖6B所示,不同層之金屬線路1113間透過貫穿基材1112所形成的導通孔1111相互電性連接。導通孔1111之形成方式係使用習知例如可透過形成貫孔再於其中填充金屬膏體或電鍍層的方式,在此便不再詳加贅述。如此,將基材層模組化,並透過銅層對接至其他模組化之基材層,以達到多層板及多層板對接的效果。In the first embodiment, the
在圖6B中係以四層板為例示說明,但本發明不以此為限。在其他實施態樣中也可以是單面板、雙面板、五層板等各種態樣,皆可適用。In FIG. 6B , a four-layer board is used as an example for illustration, but the present invention is not limited thereto. In other implementation forms, various forms such as single-sided boards, double-sided boards, and five-layer boards are also applicable.
在其他實施態樣中,電路板100可以由多塊基板組成,不限於第一基板110及第二基板130之二個基板的堆疊(容後詳述)。In other implementations, the
關於第一基板110的第一銅層112及第二基板130的第二銅層132之形成具有多種實施態樣。Regarding the formation of the
接下來,請參閱圖12並同時參閱圖7及圖8。圖7為根據一第二實施例電路板的製作方法之基板立體示意圖。圖8為根據一第二實施例電路板的製作方法之具有金屬層之基板示意圖。圖12為根據一第二實施例電路板的製作方法之銅層形成流程圖。在第二實施例中,於提供第一基板110及第二基板130的步驟前,進行電鍍沉積(步驟S8A),於第一基材層111的第一表面111a形成第一金屬層114a,於第二基材層131的第三表面131a形成第二金屬層134a。進行電鍍(步驟S9A),在第一金屬層114a上形成第一銅層112,在第二金屬層134a上形成第二銅層132。具體來說,如圖7所示,第一基板110及第二基板130原先並不具有銅層,而是,如圖8所示,先透過電鍍沉積在第一基材層111與第二基材層131上分別形成第一金屬層114a及第二金屬層134a,再透過漸鍍以分別形成第一銅層112與第二銅層132,得到圖1之第一基板110與第二基板130。在第二實施例中,第一基板110及第二基板130電鍍沉積之金屬例如為鎳或惰性金屬。Next, please refer to FIG. 12 and also refer to FIG. 7 and FIG. 8 . FIG. 7 is a schematic perspective view of a substrate according to a manufacturing method of a circuit board according to a second embodiment. FIG. 8 is a schematic diagram of a substrate with a metal layer according to a manufacturing method of a circuit board according to a second embodiment. FIG. 12 is a flow chart of forming a copper layer in a manufacturing method of a circuit board according to a second embodiment. In the second embodiment, before the step of providing the
請參閱圖13並同時參閱圖7及圖9。圖9為根據一第三實施例電路板及一第四實施例的製作方法之具有金屬層之基板立體示意圖。圖13為根據一第三實施例電路板的製作方法之銅層形成流程圖。在第三實施例中,於提供第一基板110及第二基板130的步驟前,進行金屬塗佈(步驟S8B),於第一基材層111的第一表面111a形成第一金屬層114b,於第二基材層131的第三表面131a形成第二金屬層134b。進行氧化還原反應(步驟S9B),在第一金屬層114b上形成第一銅層112,在第二金屬層134b上形成第二銅層132,得到圖4之第一基板110與第二基板130。Please refer to FIG. 13 and also refer to FIG. 7 and FIG. 9 . FIG. 9 is a schematic perspective view of a substrate with a metal layer according to a third embodiment of a circuit board and a manufacturing method of a fourth embodiment. FIG. 13 is a flow chart of forming a copper layer in a manufacturing method of a circuit board according to a third embodiment. In the third embodiment, before the step of providing the
請參閱圖14並同時參閱圖7及圖9。圖14為根據一第四實施例電路板的製作方法之銅層形成流程圖。在第四實施例中,於提供第一基板110及第二基板130的步驟前,進行金屬化(步驟S8C),於第一基材層111的第一表面111a形成第一金屬層114b,於第二基材層131的第三表面131a形成第二金屬層134b。進行電鍍(步驟S9C),在第一金屬層114b上形成第一銅層112,在第二金屬層134b上形成第二銅層132,得到圖4之第一基板110與第二基板130。Please refer to FIG. 14 and also refer to FIG. 7 and FIG. 9 . FIG. 14 is a flow chart of forming a copper layer in a method for manufacturing a circuit board according to a fourth embodiment. In the fourth embodiment, before the step of providing the
在其他實施態樣中,電路板100可以由多塊基板組成,不限於第一基板110及第二基板130之二個基板的堆疊。In other embodiments, the
請參閱圖15並同時參閱圖10A。圖10A為根據一第五實施例電路板之立體示意圖。圖15為根據一第五實施例電路板的製作方法之流程圖。在第五實施例中,第一基板110更包括第三銅層115,第三銅層115位於第二表面111b。第二基板130更包括第四銅層135,第四銅層135位於第四表面131b。預處理時,除了形成第一絨毛層113及第二絨毛層133,亦進行預處理(步驟S11B),在第一基板110的第三銅層115之表面上形成第三絨毛層116,在第二基板130的第四銅層135之表面上形成第四絨毛層136。第三絨毛層116具有複數個第三絨毛1161及複數個第三容納部1162,各第三絨毛1161之間形成第三容納部1162。第四絨毛層136具有複數個第四絨毛1361及複數個第四容納部1362,各第四絨毛1361之間形成第四容納部1362。Please refer to Figure 15 in conjunction with Figure 10A. FIG. 10A is a schematic perspective view of a circuit board according to a fifth embodiment. FIG. 15 is a flowchart of a method for manufacturing a circuit board according to a fifth embodiment. In the fifth embodiment, the
具體來說,電路板100可以由多個基板堆疊而成,如圖10A所示,第一基材層111的第二表面111b可以形成第三銅層115,並以第三銅層115對接其他基板的絨毛層,而第二基板130亦可以透過第二基材層131的第四表面131b的第四銅層135來進行對接。由於透過絨毛銅層可以快速進行堆疊,能夠有效減少製作時間及人力消耗,此外由於以絨毛銅層堆疊的製作較為方便且容易,能夠更輕易地製作厚度較厚之多層板。在第五實施例中,第一銅層112、第二銅層132、第三銅層115及第四銅層135的厚度為2至150µm。Specifically, the
在第六實施例中,電路板100的基板能以多方向堆疊,達到多方撓曲的效果。請參閱圖10B及圖10C。圖10B為根據一第六實施例電路板之立體示意圖。圖10C為圖10B中標號10C的局部放大圖。電路板100更包括第三基板150,第三基板150包括第三基材層151及第五銅層152,第三基材層151具有相對之第五表面151a及第六表面151b,第五銅層152位於第五表面151a。第三基板150的第五銅層152之表面上具有第五絨毛層153,第五絨毛層153具有複數個第五絨毛1531及複數個第五容納部1532,各第五絨毛1531之間形成第五容納部1532。第一基板110與第三基板150對接,使第一基板110的該些第一絨毛1131與第三基板150的該些第五容納部1532相互嵌合,第三基板150的該些第五絨毛1531與第一基板110的該些第一容納部1132相互嵌合,且第三基板150與第二基板130相互平行。具體來說,第一基板110延伸出兩端部,第二基板130及第三基板150分別對接至第一基板110的兩端部,第二基板130及第三基板150之間具有間隙,且相互平行。於第二基板130及第三基板150之間預留間隙,以保留第一基板110撓曲的空間。如此,電路板100可以由不同方向上的基板堆疊而成,且具有多方撓曲的效果。In the sixth embodiment, the substrates of the
綜上所述,透過電路板100的製作方法,製作具有絨毛銅面結構的第一基板110及第二基板130。將具有絨毛銅面結構的第一基板110模組化,使得第一基板110能夠透過絨毛層與第二基板130的絨毛層相互嵌合。由於透過絨毛銅層可以快速進行堆疊,能夠有效減少製作時間及人力消耗,此外由於以絨毛銅層堆疊的製作較為方便且容易,能夠更輕易地製作厚度較厚之多層板。此外,由於第一基板110與第二基板130的嵌合能夠在較低溫下進行,因此可以避免較高溫的作業環境而影響電路板之特性。To sum up, through the manufacturing method of the
100:電路板 110:第一基板 111:第一基材層111a:第一表面 111b:第二表面 1111:導通孔 1112:基材 1113:金屬線路 112:第一銅層 113:第一絨毛層 1131:第一絨毛 1132:第一容納部 114a、114b:第一金屬層 115:第三銅層 116:第三絨毛層 1161:第三絨毛 1162:第三容納部 130:第二基板 131:第二基材層 131a:第三表面 131b:第四表面 132:第二銅層 133:第二絨毛層 1331:第二絨毛 1332:第二容納部 134a、134b:第二金屬層 135:第四銅層 136:第四絨毛層 1361:第四絨毛 1362:第四容納部 150:第三基板 151:第三基材層 151a:第五表面 151b:第六表面 152:第五銅層 153:第五絨毛層 1531:第五絨毛 1532:第五容納部 步驟S8A:進行電鍍沉積,於第一基材層的第一表面形成第一金屬層,於第二基材層的第三表面形成第二金屬層 步驟S8B:進行金屬塗佈,於第一基材層的第一表面形成第一金屬層,於第二基材層的第三表面形成第二金屬層 步驟S8C:進行金屬化,於第一基材層的第一表面形成第一金屬層,於第二基材層的第三表面形成第二金屬層 步驟S9A:進行電鍍,在第一金屬層上形成第一銅層,在第二金屬層上形成第二銅層 步驟S9B:進行氧化還原反應,在第一金屬層上形成第一銅層,在第二金屬層上形成第二銅層 步驟S9C: 進行電鍍,在第一金屬層上形成第一銅層,在第二金屬層上形成第二銅層 步驟S10:提供第一基板及第二基板 步驟S11A:進行預處理,在第一基板的第一銅層之表面形成第一絨毛層,在第二基板的第二銅層之表面上形成第二絨毛層 步驟S11B:進行預處理,在第一基板的第一銅層之表面及第三銅層之表面分別形成第一絨毛層及第三絨毛層,在第二基板的第二銅層之表面及第四銅層之表面分別形成第二絨毛層及第四絨毛層 步驟S12:將第一基板與第二基板對接 100: circuit board 110: the first substrate 111: the first substrate layer 111a: the first surface 111b: second surface 1111: via hole 1112: Substrate 1113: metal circuit 112: The first copper layer 113: the first fluff layer 1131: the first fluff 1132: The first containment department 114a, 114b: first metal layer 115: the third copper layer 116: The third fluff layer 1161: The third fluff 1162: The third containment department 130: second substrate 131: second substrate layer 131a: third surface 131b: fourth surface 132: second copper layer 133: Second fluff layer 1331: second fluff 1332: The second storage unit 134a, 134b: second metal layer 135: The fourth copper layer 136: The fourth fluff layer 1361: The fourth fluff 1362: The fourth containment department 150: The third substrate 151: the third substrate layer 151a: fifth surface 151b: sixth surface 152: fifth copper layer 153: The fifth fluff layer 1531: The fifth fluff 1532: Fifth Containment Department Step S8A: performing electroplating deposition, forming a first metal layer on the first surface of the first substrate layer, and forming a second metal layer on the third surface of the second substrate layer Step S8B: Carrying out metal coating, forming a first metal layer on the first surface of the first substrate layer, and forming a second metal layer on the third surface of the second substrate layer Step S8C: performing metallization, forming a first metal layer on the first surface of the first substrate layer, and forming a second metal layer on the third surface of the second substrate layer Step S9A: performing electroplating, forming a first copper layer on the first metal layer, and forming a second copper layer on the second metal layer Step S9B: performing redox reaction, forming a first copper layer on the first metal layer, and forming a second copper layer on the second metal layer Step S9C: performing electroplating, forming a first copper layer on the first metal layer, and forming a second copper layer on the second metal layer Step S10: providing a first substrate and a second substrate Step S11A: performing pretreatment, forming a first fluff layer on the surface of the first copper layer of the first substrate, and forming a second fluff layer on the surface of the second copper layer of the second substrate Step S11B: perform pretreatment, form the first fluff layer and the third fluff layer on the surface of the first copper layer of the first substrate and the surface of the third copper layer respectively, and form the first fluff layer and the third fluff layer on the surface of the second copper layer and the third copper layer of the second substrate The surface of the four copper layers forms the second fluff layer and the fourth fluff layer respectively Step S12: docking the first substrate with the second substrate
[圖1] 為根據一第一實施例電路板的製作方法之具有銅層之基板立體示意圖。
[圖2] 為根據一第一實施例電路板的製作方法之具有絨毛銅層之基板立體示意圖。
[圖3A] 為圖2中標號3A的局部放大圖。
[圖3B] 為圖2中標號3B的局部放大圖。
[圖4] 為根據一第一實施例電路板之立體示意圖。
[圖5] 為圖4中標號5的局部放大圖。
[圖6A] 為根據一第一實施例電路板的製作方法之基板側視圖。
[圖6B] 為根據一第一實施例電路板的基板結構示意圖。
[圖7] 為根據一第二實施例電路板的製作方法之基板立體示意圖。
[圖8] 為根據一第二實施例電路板的製作方法之具有金屬層之基板示意圖。
[圖9] 為根據一第三實施例電路板及一第四實施例的製作方法之具有金屬層之基板立體示意圖。
[圖10A] 為根據一第五實施例電路板之立體示意圖。
[圖10B] 為根據一第六實施例電路板之立體示意圖。
[圖10C] 為圖10B中標號10C的局部放大圖。
[圖11] 為根據一第一實施例電路板的製作方法之流程圖。
[圖12] 為根據一第二實施例電路板的製作方法之銅層形成流程圖。
[圖13] 為根據一第三實施例電路板的製作方法之銅層形成流程圖。
[圖14] 為根據一第四實施例電路板的製作方法之銅層形成流程圖。
[圖15] 為根據一第五實施例電路板的製作方法之流程圖。
[FIG. 1] is a three-dimensional schematic diagram of a substrate with a copper layer according to a manufacturing method of a circuit board according to a first embodiment.
[FIG. 2] It is a three-dimensional schematic diagram of a substrate with a copper layer with fluff according to a manufacturing method of a circuit board according to a first embodiment.
[FIG. 3A] is a partially enlarged view of
100:電路板
110:第一基板
111:第一基材層
111a:第一表面
111b:第二表面
112:第一銅層
130:第二基板
131:第二基材層
131a:第三表面
131b:第四表面
132:第二銅層
100: circuit board
110: the first substrate
111: the
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TW501386B (en) * | 1997-09-25 | 2002-09-01 | Nitto Denko Corp | Multilayer wiring substrate and method for producing the same |
TW200617549A (en) * | 2004-11-22 | 2006-06-01 | Au Optronics Corp | IC chip, IC assembly and flat display |
CN106658988A (en) * | 2017-02-07 | 2017-05-10 | 武汉华星光电技术有限公司 | Display, circuit board, and pin structure of circuit board |
CN109496077A (en) * | 2018-11-22 | 2019-03-19 | 深圳恒宝士线路板有限公司 | With the anti-etching method for manufacturing circuit board of oxide layer |
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TW501386B (en) * | 1997-09-25 | 2002-09-01 | Nitto Denko Corp | Multilayer wiring substrate and method for producing the same |
TW200617549A (en) * | 2004-11-22 | 2006-06-01 | Au Optronics Corp | IC chip, IC assembly and flat display |
CN106658988A (en) * | 2017-02-07 | 2017-05-10 | 武汉华星光电技术有限公司 | Display, circuit board, and pin structure of circuit board |
CN109496077A (en) * | 2018-11-22 | 2019-03-19 | 深圳恒宝士线路板有限公司 | With the anti-etching method for manufacturing circuit board of oxide layer |
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