TWI804248B - Low propagation delay level shifter - Google Patents

Abstract

A level shifter includes a low-level adjustment circuit, a comparator circuit, and a high-level adjustment circuit. The low-level adjustment circuit pulls down a level of one of a first input node and a second input node to a first low supply voltage. The comparator outputs a one having higher level in the level of the first input level and a second low supply voltage to a first output node, in which the second low supply voltage is higher than the first low supply voltage. The high-level adjustment circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate the output signal.

Description

Level Converter with Low Propagation Delay

This case is about level converters, especially level converters that can quickly switch signal levels.

Electronic devices usually contain several different circuitry. In some applications, the circuitry may operate at different voltage levels. In order to enable these circuit systems to transmit data or signals to each other, a level shifter (level shifter) can be provided between these circuit systems to ensure that the signal level conforms to the voltage level of the corresponding circuit system. In some related technologies, the level converter uses a plurality of cross-coupled inverters to perform level conversion. However, due to the influence of other clamping circuits and the operation delay of the inverters, a large transmission delay will be generated during the level switching of the signal. In this way, the switching process that will affect the signal will be delayed, so that the transition edge of the signal will have higher uncertainty.

In some implementation aspects, one of the purposes of the present invention is to provide a level converter with low transmission delay, so as to improve the deficiencies of the prior art.

In some implementation aspects, the level converter includes a low level adjustment circuit, a first comparison circuit and a high level adjustment circuit. The low level adjustment circuit selectively pulls down the level of one of a first input node and a second input node to a first low power supply voltage according to an input signal. The first comparison circuit outputs the level of the first input node and a second low power supply voltage which has a higher level to a first output node, wherein the second low power supply voltage is higher than the first low power supply voltage Voltage. The high level adjusting circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate an output signal.

In some implementation aspects, the level converter can provide an additional path to quickly adjust the level of the output node, thereby reducing the delay generated during the level switching process of the signal. In this way, the output signal generated by the level converter can have a fast-switching transition edge, thereby reducing the uncertainty of the transition edge of the output signal.

About the feature, implementation and effect of this case, hereby cooperate with drawing as preferred embodiment and describe in detail as follows.

100: level converter

110: Low level adjustment circuit

112,114: Inverter

120,130: comparison circuit

140: High level adjustment circuit

142,144: Inverter

400: level converter

410: select circuit

411,412: Inverter

413,414: logic gate

415: multiplexer

500: Input and output drivers

501: Input and output pads

510: level converter

520: delay matching circuit

530: Non-overlapping circuits

540: protection circuit

A, B: control nodes

D1, D2: Diodes

I1, I2: input nodes

MN1, MN2, MP1, MP2, N1~N4, P1~P8: Transistor

O1, O2: output nodes

S1~S5: signal

SC1, SC2: Control signal

SEL: select signal

SIN: input signal

VDDH, VDDL: high power supply voltage

VN, VP: clamp signal

VO, VO’: output signal

VSS,VSSH,VSSL: Low supply voltage

[Figure 1] is a schematic diagram of a level converter drawn according to some embodiments of this case; [Figure 2] is a schematic circuit diagram of a level converter drawn in Figure 1 according to some embodiments of this case; [Figure 3A] is a schematic diagram of a level converter according to some embodiments of this case For example, draw a schematic diagram of the operation of the level converter when the input signal in Fig. 2 has a low logic value; [Fig. 3B] is a schematic diagram of the operation of the level converter when the input signal in Fig. 2 has a high logic value according to some embodiments of the present case; [Fig. 4A] is a schematic diagram of a level converter drawn according to some embodiments of the present case; [FIG. 4B] is a waveform diagram of related signals drawn in FIG. 4A according to some embodiments of the present application; and [FIG. 5] is a schematic diagram of an input-output driver drawn according to some embodiments of the present application.

All terms used herein have their ordinary meanings. The definitions of the above-mentioned terms in commonly used dictionaries, and the use examples of any terms discussed here in the content of this case are only examples and should not limit the scope and meaning of this case. Likewise, this case is not limited to the various embodiments shown in this specification.

As used herein, "coupling" or "connection" can refer to two or more elements in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, and can also refer to two or more components. Components operate or act on each other. As used herein, the term "circuit" can be a device that is connected in a certain way to process signals by at least one transistor and/or at least one active and passive element.

FIG. 1 is a schematic diagram of a level converter 100 according to some embodiments of the present invention. The level converter 100 can be used to convert the signal level to be suitable for voltage ranges of different power domains. For example, the level converter 100 can receive the input signal SIN from other digital circuits (not shown), wherein the level range of the input signal SIN can be from the low power supply voltage VSSL to the high power supply voltage VDDL. The level converter 100 can generate an output signal VO according to the input signal SIN, wherein the level of the output signal VO ranges from a low power supply voltage VSSH to a high power supply voltage VDDH, wherein the high power supply voltage VDDH is higher than the low power supply voltage The power supply voltage VSSH, the low power supply voltage VSSH may be higher than or the same as the high power supply voltage VDDL, and the high power supply voltage VDDL is higher than the low power supply voltage VSSL.

The level converter 100 includes a low level adjustment circuit 110 , a comparison circuit 120 , a comparison circuit 130 and a high level adjustment circuit 140 . The low level adjusting circuit 110 selectively pulls down the level of one of the input node I1 and the input node I2 to the high power supply voltage VDDL according to the input signal SIN. The comparison circuit 120 outputs the higher level of the level of the input node I1 and the low power supply voltage VSSH to the output node O1 . The comparison circuit 130 outputs the higher level of the level of the input node I2 and the low power supply voltage VSSH to the output node O2 . The high level adjusting circuit 140 selectively adjusts the level of the output node O1 and the level of the output node O2 according to the level of the input node I1 and the level of the input node I2, and generates the output signal VO according to the level of the output node O2.

In this example, the low level adjustment circuit 110 operates in the first power domain defined by the low power supply voltage VSSL and the high power supply voltage VDDL. The low level adjustment circuit 110 can pull up the amplitude of the input signal SIN to the high power supply voltage VDDL or pull it down to the low power supply voltage VSSL, and adjust the level of the input node I1 and the level of the input node I2 accordingly. The high level adjustment circuit 140 operates in the second power domain defined by the low power supply voltage VSSH and the high power supply voltage VDDH. The high level adjustment circuit 140 can further pull up the level of the output node O1 (and the output node O2) to the high power supply voltage VDDH or the low power supply voltage VSSH according to the level of the input node I1 and the level of the input node I2, and accordingly generate Output signal VO.

As will be explained later, the comparison circuit 120 can help to pull down the level of the output node O1 to the low power supply voltage VSSH quickly, and the comparison circuit 130 can help to pull down the level of the output node O2 to the low power supply voltage VSSH quickly. In this way, the output signal VO can be quickly switched to low during the level conversion process. The level of the power supply voltage VSSH, thereby reducing the transient delay and uncertainty of the falling edge of the output signal VO.

FIG. 2 is a schematic circuit diagram of the level converter 100 of FIG. 1 according to some embodiments of the present invention. In this example, the low level adjustment circuit 110 includes an inverter 112 , an inverter 114 , a transistor N1 and a transistor N2 . The inverter 112 generates the signal S1 according to the input signal SIN. The inverter 114 generates a signal S2 according to the signal S1. The first end of transistor N1 (for example, the drain) is coupled to the input node I2, the second end of transistor N1 (for example, the source) receives the signal S1, and the control end of transistor N1 (for example, the gate) Receive high supply voltage VDDL. The first terminal of the transistor N2 is coupled to the input node I1, the second terminal of the transistor N2 receives the signal S2, and the control terminal of the transistor N2 receives the high power supply voltage VDDL.

Through the above arrangement, the transistor N1 and the transistor N2 can be biased by the high power supply voltage VDDL, the transistor N1 can selectively pull down the level of the input node I2 to the low power supply voltage VSSL according to the signal S1, and the transistor N2 can selectively pull down the level of the input node I1 to the low power supply voltage VSSL according to the signal S2. For example, when the input signal SIN is logic value 0, the level of the signal S1 is the high power supply voltage VDDL, and the level of the signal S2 is the low power supply voltage VSSL. Under this condition, the transistor N1 is turned off and the transistor N2 is turned on to pull down the level of the input node I1 to the low supply voltage VSSL. Alternatively, when the input signal SIN is logic value 1, the level of the signal S1 is the low power supply voltage VSSL, and the level of the signal S2 is the high power supply voltage VDDL. Under this condition, the transistor N2 is turned off and the transistor N1 is turned on to pull down the level of the input node I2 to the low supply voltage VSSL.

The high level adjustment circuit 140 includes a plurality of transistors P1 - P4 , a plurality of transistors N3 - N4 and a plurality of inverters 142 and 144 . The first end (for example, the source) of the transistor P1 receives the high power supply voltage VDDH, the second end (for example, the drain) of the transistor P1 is coupled to the control node A, and the transistor P1 A control terminal (for example, a gate) of is coupled to the output node O2. The transistor P1 can selectively pull up the level of the control node A to the high power supply voltage VDDH according to the level of the output node O2. The first end of the transistor P2 receives the high power voltage VDDH, the second end of the transistor P1 is coupled to the control node B, and the control end of the transistor P2 is coupled to the output node O1. The transistor P2 can selectively pull up the level of the control node B to the high power supply voltage VDDH according to the level of the output node O1. A first terminal of the transistor N3 is coupled to the control node A, a second terminal of the transistor N3 receives the low power voltage VSSH, and a control terminal of the transistor N3 is coupled to the control node B. The transistor N3 can selectively pull down the level of the control node A to the low power supply voltage VSSH according to the level of the control node B. The first terminal of the transistor N4 is coupled to the control node B, the second terminal of the transistor N4 receives the low power supply voltage VSSH, and the control terminal of the transistor N4 is coupled to the control node A. The transistor N4 can selectively pull down the level of the control node B to the low power supply voltage VSSH according to the level of the control node A. A first terminal of the transistor P3 is coupled to the control node A, a second terminal of the transistor P3 is coupled to the input node I1, and the control terminal of the transistor P3 receives the low power voltage VSSH. The transistor P3 can be biased by the low power supply voltage VSSH and selectively turned on according to the level of the control node A to adjust the level of the input node I1. A first terminal of the transistor P4 is coupled to the control node B, a second terminal of the transistor P4 is coupled to the input node I2, and the control terminal of the transistor P4 receives the low power voltage VSSH. The transistor P4 can be biased by the low power supply voltage VSSH and selectively turned on according to the level of the control node B to adjust the level of the input node I2.

The plurality of inverters 142 and 144 are powered by the high power supply voltage VDDH and the low power supply voltage VSSL, and are coupled in series to operate as a buffer, which can generate the output signal VO according to the level of the output node O1.

The comparison circuit 120 includes a plurality of transistors P5 and P6. The first end of the transistor P5 is coupled to the output node O1, the second end of the transistor P5 receives the low power supply voltage VSSH, and the control of the transistor P5 The terminal is coupled to the input node I1. A first terminal of the transistor P6 is coupled to the output node O1, a second terminal of the transistor P6 is coupled to the input node I1, and a control terminal of the transistor P6 receives the low power voltage VSSH. With the above arrangement, the transistor P5 can be selectively turned on according to the level of the input node I1 to transmit the low power supply voltage VSSH to the output node O1, and the transistor P6 can be selectively turned on according to the level of the input node I1 to connect Input node I1 to output node O1. For example, when the low supply voltage VSSH is higher than the level of the input node I1, the transistor P5 is turned on and the transistor P6 is turned off to transmit the low supply voltage VSSH to the output node O1. Alternatively, when the level of the input node I1 is higher than the low power supply voltage VSSH, the transistor P6 is turned on and the transistor P5 is turned off to connect the input node I1 to the output node O1.

The comparison circuit 130 includes a plurality of transistors P7 and P8. A first terminal of the transistor P7 is coupled to the output node O2, a second terminal of the transistor P7 receives the low power supply voltage VSSH, and a control terminal of the transistor P7 is coupled to the input node I2. A first terminal of the transistor P8 is coupled to the output node O2, a second terminal of the transistor P8 is coupled to the input node I2, and a control terminal of the transistor P8 receives the low power voltage VSSH. With the above arrangement, the transistor P7 can be selectively turned on according to the level of the input node I2 to transmit the low power supply voltage VSSH to the output node O2, and the transistor P8 can be selectively turned on according to the level of the input node I2 to connect Input node I2 to output node O2. For example, when the low supply voltage VSSH is higher than the level of the input node I2, the transistor P7 is turned on and the transistor P8 is turned off to transmit the low supply voltage VSSH to the output node O2. Alternatively, when the level of the input node I2 is higher than the low power supply voltage VSSH, the transistor P8 is turned on and the transistor P7 is turned off to connect the input node I2 to the output node O2.

It should be understood that the comparison circuit 120 and the comparison circuit 130 are equivalent to high voltage selection circuits, and the present application is not limited to the above arrangement. Various comparator circuits capable of outputting higher voltages are covered by this case.

FIG. 3A is a schematic diagram illustrating the operation of the level converter 100 when the input signal SIN in FIG. 2 has a low logic value according to some embodiments of the present invention. In the example of FIG. 3A , when the input signal SIN switches from a high level to a low level (ie, the input signal SIN has a low logic value), the signal S1 has a high level and the signal S2 has a low level. Under this condition, the transistor N1 is turned off and the transistor N2 is turned on to pull down the level of the input node I1 to the low supply voltage VSSL. Since the low supply voltage VSSH is higher than the level of the input node I1 (equivalent to the low supply voltage VSSL), the transistor P6 is turned off and the transistor P5 is turned on to transmit the low supply voltage VSSH to the output node O1. In this way, the level of the output node O1 can be quickly pulled down to the low power supply voltage VSSH to generate the output signal VO with a corresponding low level.

In addition, since the output node O1 is at a low level, the transistor P2 is turned on to pull up the level of the control node B to the high power supply voltage VDDH. Under this condition, transistor N4 is turned off, transistor N3 is turned on to pull down the level of control node A to the low supply voltage VSSH which turns off transistor P3, and transistor P4 is turned on to connect control node B to the input node I2. In this way, the level of the input node I2 can be pulled up to the high power supply voltage VDDH through the transistor P4 and the transistor P2. Since the level of the input node I2 is higher than the low supply voltage VSSH, the transistor P7 is turned off and the transistor P8 is turned on to connect the input node I2 to the output node O2, thereby turning off the transistor P1.

FIG. 3B is a schematic diagram illustrating the operation of the level converter 100 when the input signal SIN in FIG. 2 has a high logic value according to some embodiments of the present invention. In the example of FIG. 3B , when the input signal SIN switches from a low level to a high level (ie, the input signal SIN has a high logic value), the signal S2 has a high level and the signal S1 has a low level. Under this condition, the transistor N2 is turned off and the transistor N1 is turned on to pull down the level of the input node I2 to the low supply voltage VSSL. Since the low supply voltage VSSH is higher than the level of the input node I2 (equivalent to the low supply voltage VSSL), the transistor P8 is turned off and the transistor P7 is turned on to transmit the low supply voltage VSSH to output node O2. In this way, the level of the output node O2 can be quickly pulled down to the low power supply voltage VSSH.

In addition, since the output node O2 is at a low level, the transistor P1 is turned on to pull the level of the control node A to the high power supply voltage VDDH. Under this condition, transistor N3 is turned off, transistor N4 is turned on to pull down the level of control node B to the low supply voltage VSSH which turns off transistor P4, and transistor P3 is turned on to connect control node A to the input node I1. In this way, the level of the input node I1 can be pulled up to the high power supply voltage VDDH through the transistor P3 and the transistor P1. Since the level of the input node I1 is higher than the low supply voltage VSSH, the transistor P5 is turned off and the transistor P6 is turned on to connect the input node I1 to the output node O1, thereby turning off the transistor P2. In this way, the level of the input node I1 can be pulled up to the high power supply voltage VDDH to generate the output signal VO with a corresponding high level.

Based on the description of FIG. 3A and FIG. 3B , it should be understood that when the input signal SIN switches to a low level, the comparator circuit 120 can rapidly pull down the level of the output node O1 to the low power supply voltage VSSH. In this way, when the input signal SIN switches from a high level to a low level, the output signal VO can have a low-latency level switching to have a fast falling transition edge (ie, a falling edge). In contrast, when the input signal SIN switches to a high level, the level of the input node I1 is pulled up through the cooperative operation of the comparison circuit 130 and the high level adjustment circuit 140 , and then the level of the output signal VO is pulled up to the high power supply voltage VDDH. In some embodiments, in practical applications, the transient time of the output signal VO switching from the low level to the high level may be longer than the transient time of the output signal VO switching from the high level to the low level.

FIG. 4A is a schematic diagram of a level converter 400 according to some embodiments of the present invention. Compared with FIG. 2 , in this example, the level converter 400 further includes a selection circuit 410 , and the high level adjustment circuit 140 does not include a plurality of inverters 142 and 144 , and the output signal VO is generated through the selection circuit 410 . like As mentioned above, in the aforementioned example, the transient time of the output signal VO switching from low level to high level may be longer than the transient time of output signal VO switching from high level to low level. In order to further ensure that the output signal VO can have a fast-rising transition edge (ie, a rising edge), the selection circuit 410 can be used to further generate the output signal VO according to the level of the output node O2.

In detail, the selection circuit 410 selects a corresponding node from the output node O1 and the output node O2 according to the level of the output node O1 and the output node O2, and generates the output signal VO according to the level of the corresponding node. For example, the selection circuit 410 includes an inverter 411 , an inverter 412 , a logic gate 413 , a logic gate 414 and a multiplexer 415 . The inverter 411 generates a signal S3 according to the level of the output node O1. The inverter 412 generates a signal S4 according to the level of the output node O2. The logic gate 413 generates the signal S5 according to the signal S3 and the selection signal SEL. The logic gate 414 generates the selection signal SEL according to the signal S4 and the signal S5. In this example, the logic gate 413 and the logic gate 414 can be (but not limited to) NAND gates, and can be operated as SR flip-flops. The multiplexer 415 outputs the signal S4 as the output signal VO according to the selection signal SEL, or generates the output signal VO according to the level of the output node O1.

FIG. 4B is a waveform diagram plotting the related signals in FIG. 4A according to some embodiments of the present invention. When the input signal SIN has a high level, the output node O1 has a high level, and the output node O2 has a low level. Under this condition, the selection signal SEL has a low level, so the multiplexer 415 generates the output signal VO according to the level of the output node O1. When the input signal SIN switches from a high level to a low level, the level of the output node O1 is quickly pulled down to the low power supply voltage VSSL by the comparison circuit 120, so the multiplexer 415 can generate a corresponding output signal VO according to the level of the output node O1 . Then, when the level of the output node O2 is pulled up to the high power supply voltage VDDH (refer to FIG. 3A ) through the cooperative operation of the high level adjustment circuit 140 and the comparison circuit 130 , the selection signal SEL has a high level. Under this condition, the output signal S4 of the multiplexer 415 is output Signal VO. When the input signal SIN switches from a low level to a high level, the level of the output node O2 can be quickly pulled down to the low power supply voltage VSSL through the comparison circuit 130 (refer to FIG. 3B ), so that the signal S4 can have a fast rising transition edge. In this way, the multiplexer 415 can output the signal S4 as the output signal VO.

Equivalently speaking, the selection circuit 410 can select a corresponding node from the output node O1 and the output node O2 according to the level of the output node O1 and the level of the output node O2, wherein when the level of the corresponding node is from a high level (for example, When the high power supply voltage VDDH) is switched to a low level (for example, the low power supply voltage VSSL), the selection circuit 410 generates the output signal VO according to the level of the corresponding node. In this way, it can be ensured that the selection circuit 410 generates the output signal VO according to the level with a fast drop, thereby reducing the delay time of switching the level of the output signal VO.

Generally speaking, as the circuit is used for a longer period of time, the operating speed of the circuit will gradually slow down. Since the selection circuit 410 can choose to generate the output signal VO through the output node O1 of the comparison circuit 120 or through the output node O2 of the comparison circuit 130, and the number of transistors used in the pull-down path of the output node O1 or the output node O2 is small. , so it is relatively less affected by the use time. In other words, the durability of the level converter 400 can be further improved by the selection circuit 410 .

In the above embodiments, the plurality of transistors N1 - N4 are N-type transistors, and the plurality of transistors P1 - P8 are P-type transistors. The above-mentioned transistors can be implemented by metal oxide field effect transistors (MOSFETs), but the present application is not limited thereto. Transistors of various types or conduction types that can implement similar operations are all within the scope of this application.

FIG. 5 is a schematic diagram of an input-output driver 500 drawn according to some embodiments of the present invention. The I/O driver 500 includes a level converter 510 , a delay matching circuit 520 , a non-overlapping circuit 530 and a protection circuit 540 . Level converter 510 can be converted from the level shown in Figure 1 or Figure 2 The converter 100 or the level converter 400 of FIG. 4 is implemented. The level converter 510 can generate an output signal VO according to the input signal SIN. The delay matching circuit 520 generates the output signal VO' according to the input signal SIN, wherein the delay time introduced by the delay matching circuit 520 to the input signal SIN is the same (or close to) the delay time introduced by the level converter 510 to the input signal SIN. In other words, the non-overlapping circuit 530 receives the output signal VO and the output signal VO' at the same (or close) time. In some embodiments, the delay matching circuit 520 may (but is not limited to) have a circuit structure similar to that of the level converter 510 (but operate in a different power domain) to achieve similar delay times. The non-overlapping circuit 530 generates the control signal SC1 according to the output signal VO, and generates the control signal SC2 according to the output signal VO'. The non-overlapping circuit 530 can delay the output signal VO to generate the control signal SC1, and delay the output signal VO' to generate the control signal SC2, wherein there is a non-overlap period between the control signal SC1 and the control signal SC2 (for example, the transition of the control signal SC1 The interval between the state edge and the transition edge of the control signal SC1).

The protection circuit 540 includes a plurality of transistors MP1 , MP2 , MN1 and MN2 and a plurality of diodes D1 and D2 . A plurality of transistors MP1 , MP2 , MN1 and MN2 and a plurality of diodes D1 and D2 can operate the voltage protection circuit to provide basic voltage protection for the input and output pad 501 . The transistor MP1 receives the high power supply voltage VDDH, and is selectively turned on according to the control signal SC1. The transistor MP2 is controlled by the clamp signal VP and coupled to the input and output pad 501 . The transistor MN2 is controlled by the clamp signal VN and coupled to the input and output pad 501 . The transistor MN1 receives the low power supply voltage VSS, and is selectively turned on according to the control signal SC2.

By setting the non-overlap period between the control signal SC1 and the control signal SC2 , it can be ensured that the transistor MP1 and the transistor MN1 will not be turned on at the same time, thereby preventing the protection circuit 540 from generating short-circuit current. As mentioned above, in some related technologies, there is an operation delay in the level converter, so that the conversion of the signal The edge of the state produces high uncertainty. If the level converter of these technologies is used to generate the output signal VO, the transition edge of the control signal SC1 generated by the non-overlapping circuit 530 will also have uncertainty (that is, the transition time point of the control signal SC1 cannot be precisely controlled. ). As a result, the non-overlapping period between the control signal SC1 and the control signal SC2 may be too long to reduce the performance of the I/O driver 500 . Or, in some extreme cases, the transistor MP1 and the transistor MN1 may be turned on at the same time according to the control signal SC1 and the control signal SC2 , thereby generating a short-circuit current by mistake. Compared with the above techniques, using the level converter 100 or the level converter 400 provided by some embodiments of the present application, the non-overlapping circuit 530 can precisely control the transition time point of the control signal SC1 to ensure that the control signal SC1 and the control signal SC2 There is a certain non-overlapping period between them, and the non-overlapping period can be precisely controlled to have a shorter time length, so as to improve the performance of the input and output driver 500 .

To sum up, the level converter in some embodiments of the present application can provide an additional path to quickly adjust the level of the output node, thereby reducing the delay generated during the switching process of the signal level. In this way, the output signal generated by the level converter can have a fast-switching transition edge, thereby reducing the uncertainty of the transition edge of the output signal.

Although the embodiments of this case are as described above, these embodiments are not intended to limit this case. Those with ordinary knowledge in the technical field can make changes to the technical characteristics of this case according to the explicit or implied content of this case. All these changes All may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be subject to the definition of the scope of patent application in this specification.

100: level converter

110: Low level adjustment circuit

120,130: comparison circuit

140: High level adjustment circuit

I1, I2: input nodes

O1, O2: output nodes

SIN: input signal

VDDH, VDDL: high power supply voltage

VO: output signal

VSSH, VSSL: low supply voltage

Claims (10)

A level converter comprising: A low level adjustment circuit selectively pulls down the level of one of a first input node and a second input node to a first low power supply voltage according to an input signal; a first comparison circuit, outputting the level of the first input node and a second low power supply voltage which has a higher level to a first output node, wherein the second low power supply voltage is higher than the first low supply voltage; and A high level adjustment circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate an output signal. The level converter of claim 1, wherein the low level adjustment circuit operates in a first power domain, the high level adjustment circuit operates in a second power domain, and the first power domain is composed of the first low power supply voltage and A first high power supply voltage is defined, the second power domain is defined by the second low power supply voltage and a second high power supply voltage, and the second high power supply voltage is higher than the first high power supply voltage. The level converter of claim 1, wherein the low level adjustment circuit includes: a first inverter generating a first signal according to the input signal; a second inverter for generating a second signal according to the first signal; a first transistor, biased by a high power supply voltage, selectively pulls down the level of the second input node to the first low power supply voltage according to the first signal; and A second transistor is biased by the high power supply voltage and selectively pulls down the level of the first input node to the first low power supply voltage according to the second signal. The level converter of claim 1, wherein the high level adjustment circuit includes: a first transistor selectively pulls up a level of a first control node to a high power supply voltage according to a level of a second output node; a second transistor selectively pulls up the level of a second control node to the high power supply voltage according to the level of the first output node; a third transistor selectively pulls down the level of the first control node to the second low power supply voltage according to the level of the second control node; a fourth transistor selectively pulls down the level of the second control node to the second low power supply voltage according to the level of the first control node; a fifth transistor biased by the second low power supply voltage and selectively turned on according to the level of the first control node to adjust the level of the first input node; and A sixth transistor, biased by the second low power supply voltage, is selectively turned on according to the level of the second control node to adjust the level of the second input node. The level converter of claim 1, wherein the first comparison circuit includes: a first transistor selectively turned on according to the level of the first input node to transmit the second low power supply voltage to the first output node; and A second transistor is selectively turned on according to the level of the first input node to connect the first input node to the first output node. For example, the level converter of claim 1 further includes: a second comparator circuit, outputting the level of the second input node and the second low power supply voltage which has a higher level to a second output node, The high level adjustment circuit further selectively adjusts the level of the second output node according to the level of the first input node and the level of the second input node. For example, the level converter of claim 6 further includes: A selection circuit selects a corresponding node from the first output node and the second output node according to the level of the first output node and the level of the second output node, and generates the corresponding node according to the level of the corresponding node output signal. The level converter of claim 7, wherein when the level of the corresponding node is switched from a first level to a second level, the selection circuit generates the output signal according to the level of the corresponding node, and the second A level is higher than the second level. As the level converter of claim 7, wherein the selection circuit includes: a first inverter, generating a first signal according to the level of the first output node; a second inverter, generating a second signal according to the level of the second output node; a first logic gate, generating a third signal according to the first signal and a selection signal; a second logic gate generating the selection signal according to the second signal and the third signal; and A multiplexer outputs a second signal as the output signal according to the selection signal or generates the output signal according to the level of the first output node. The level converter of claim 1, wherein when the input signal is switched from a first level to a second level, the first comparison circuit is used to assist in pulling down the level of the first output node to be accelerated to The second low power supply voltage, and the first level is higher than the second level.

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