TWI804140B - Timing control circuit and operation method of timing control circuit - Google Patents

Abstract

A timing control circuit configured to perform a polarity reversal on a data voltage outputted to a pixel array of a display panel during a frame period every N scan lines is provided, where N is a positive integer. The timing control circuit includes a receiver and an adjustment circuit. The receiver is configurated to sequentially receive a first display data and a second display data for one data line of the display panel. The adjustment circuit is coupled to the receiver for adjusting at least one of the gray information of the second display data and the charging time of the second display data according to the voltage polarity of the first display data and the voltage polarity of the second display data. A corresponding operation method of the timing control circuit is also provided.

Description

Timing control circuit and operation method of timing control circuit

The invention is a timing control circuit, in particular, it relates to a technical means for adjusting the output signal according to the voltage polarity of the display data.

When the panel displays a static image for a long time, the liquid crystal will maintain a certain twisted state. When the picture is changed, problems such as crosstalk, burn-in and color cast often appear. The reasons include varying degrees of aging of liquid crystals, and the stiffness of liquid crystals caused by maintaining a specific twisted state for a long time. In order to solve this problem, the existing method is to periodically change the polarity of the liquid crystal voltage, which is called polarity reversal. The polarity inversion can be divided into frame inversion, column inversion, line inversion (or column inversion) and dot inversion. Considering the degree of power consumption and the display effect, polarity column inversion is the most commonly used. However, when the polarity column inversion is performed, due to the difference in the charging rate and charging saturation of the two pixel columns with different data voltage polarities, the twisting speed and twisting angle of the liquid crystal are different, resulting in a difference in brightness. At this time, dark lines will appear on the display screen.

FIG. 1 is a schematic diagram of waveforms for column inversion of the polarity of data voltages. FIG. 2 is a schematic diagram showing dark lines appearing on the display screen. Please refer to FIG. 1 , the vertical axis is the data voltage V and the horizontal axis is the time t. The data voltage V at different time points in FIG. 1 can be regarded as the data voltage received by a plurality of pixels in the same row of the display panel (as shown in FIG. 2 ) through the same data channel at the corresponding scanning timing. In FIG. 1 , curves C1 and C2 respectively represent the data voltage changing with time under the ideal state and the actual state. Assume a polarity row inversion every four pixel columns. In the actual state, when the polarity of the current data voltage is opposite to that of the previous data voltage, the pixel will be undercharged (please refer to the arrows 101-104 pointing, the curve C2 and the curve C1 have a drop). Therefore, a plurality of dark lines will be generated as shown in FIG. 2 (such as the positions corresponding to the pixel columns SL5 , SL9 , and SL13 ). This problem is exacerbated when the LCD rotation speed is not fast enough and the required frames per second is high. In addition, the dark lines of the engineering drawing (displayed with the same gray scale in large areas) will be more obvious than the natural drawing.

Therefore, a solution is needed to avoid the problem of dark lines appearing on the display screen when polarity inversion is performed.

The invention provides a timing control circuit, which can adjust its output signal according to the voltage polarity of the display data, thereby avoiding the problem of dark lines on the display screen under polarity inversion.

The timing control circuit of the present invention is used to control the polarity inversion of the data voltage output to the pixel array of the display panel during a frame period by N scanning lines, wherein N is a positive integer. The timing control circuit includes a receiver and an adjustment circuit. receiver It is used for sequentially receiving the first display data and the second display data for one data line of the display panel. The adjustment circuit is coupled to the receiver, and is used for adjusting at least one of the grayscale information of the second display data and the charging time of the second display data according to the voltage polarity of the first display data and the voltage polarity of the second display data.

The operation method of the timing control circuit of the present invention includes: the receiver of the timing control circuit sequentially receives the first display data and the second display data for one data line of the display panel; and the adjustment circuit of the timing control circuit according to the first The voltage polarity of the display data and the voltage polarity of the second display data are used to adjust at least one of the grayscale information of the second display data and the charging time of the second display data. Wherein, the timing control circuit is used to control the polarity inversion of the data voltage output to the pixel array of the display panel during a frame period by N scanning lines, and N is a positive integer.

In an embodiment of the present invention, the above adjustment circuit includes an acceleration driving circuit. The acceleration drive circuit is used to adjust the value according to the voltage polarity of the first display data, the voltage polarity of the second display data, and the gray scale difference between the gray scale information of the first display data and the gray scale information of the second display data. The gray information of the second display data is adjusted, thereby increasing the data voltage corresponding to the second display data.

In an embodiment of the present invention, the above timing control circuit includes a storage circuit. The storage circuit stores a plurality of candidate adjustment values. The acceleration drive circuit is also used to obtain an adjustment value from a plurality of candidate adjustment values.

In an embodiment of the present invention, compared with the case where the voltage polarity of the first display data and the second display data are the same, the above-mentioned speed-up driving circuit When the voltage polarities of the display data and the second display data are different, the adjustment range of the grayscale information of the second display data is larger.

In an embodiment of the present invention, the above timing control circuit includes a storage circuit. The storage circuit stores a plurality of candidate adjustment values. The adjustment circuit includes an acceleration drive circuit. The speed-up driving circuit is used to automatically adjust the voltage according to the grayscale difference between the grayscale information of the first display data and the grayscale information of the second display data when the voltage polarity of the second display data is different from that of the first display data. Multiple Alternative Adjustment Values Gets the adjustment value. The speed-up driving circuit is used to adjust the grayscale information of the second display data according to the adjustment value, thereby increasing the data voltage corresponding to the second display data.

In an embodiment of the present invention, the above-mentioned adjusting circuit includes a charging signal generating circuit. The charging signal generating circuit is used for generating a pulse signal to instruct the driving device to charge the data line with the second display data. The charging signal generating circuit is also used for adjusting the conversion pulse signal to advance the charging time point when the voltage polarity of the second display data is different from that of the first display data.

In an embodiment of the present invention, the above-mentioned adjusting circuit includes a polarity signal generating circuit. The polarity signal generating circuit is used for generating a polarity inversion control signal to indicate the voltage polarity of the first display data and the voltage polarity of the second display data.

Based on the above, the timing control circuit of the present invention can adjust at least one of the gray scale information and the charging time of the second display data for the situation that the data voltage polarities of the first display data and the second display data are different. In this way, the problem of undercharging of multiple pixel columns with polarity reversal can be solved, and further reduce or avoid the appearance of dark lines on the display panel at the positions corresponding to the above multiple pixel columns. condition.

100: Electronic device

101~104: Arrow

300: display device

310: timing control circuit

311: Adjustment circuit

701~103: Arrow

C1, C2, C2': Curves

D, D': display data

DL1~DL4: data line

G1: charging signal generation circuit

G2: polarity signal generating circuit

OD: speed up drive circuit

p1~p13: pixels

PQ: picture quality adjustment circuit

Rx: Receiver

SG: control signal generation circuit

SL1~SL13: Pixel columns

S_TP, S_TP': signal

S_POL: control signal

SD: source driver

S810, S820: steps

t: time

Tx: Transmitter

Tx_D: signal

V: data voltage

FIG. 1 is a schematic diagram of waveforms for column inversion of the polarity of data voltages.

FIG. 2 is a schematic diagram showing dark lines appearing on the display screen.

FIG. 3 is a schematic block diagram of a display device according to an embodiment of the present invention.

FIG. 4 is a schematic block diagram of a control signal generating circuit and an acceleration driving circuit according to an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating that the data voltage received by the pixel array exhibits polarity column inversion.

FIG. 6A is a schematic waveform diagram of the column inversion of the polarity of the data voltage without using the present invention.

FIG. 6B is a schematic waveform diagram of the column inversion of the polarity of the data voltage in the first embodiment of the present invention.

FIG. 7A is a schematic waveform diagram of the column inversion of the polarity of the data voltage without using the present invention.

FIG. 7B is a schematic waveform diagram of the column inversion of the polarity of the data voltage in the second embodiment of the present invention.

FIG. 8 is a flow chart showing the steps of the operation method of the timing control circuit according to an embodiment of the present invention.

In the present invention, the display operation of the display device is to turn on the charging path of one pixel row at a time according to the vertical scanning signal, and charge all the pixels in the pixel row according to the data voltage by the source driver. Afterwards, the charging path of the pixel row is turned off, and the charging path of another pixel row is turned on for charging, and so on.

FIG. 3 is a schematic block diagram of a display device according to an embodiment of the present invention. Please refer to FIG. 3 , the display device 300 includes a timing control circuit 310 , a source driver SD and a pixel array (not shown). The pixel array includes multiple pixel columns, and each pixel column includes multiple pixels. The timing control circuit 310 is used to provide display data and various control signals to the source driver SD. The source driver SD is used to generate data voltages according to the received display data and various control signals to charge the corresponding pixel columns (on state).

The timing control circuit 310 includes a receiver Rx, an image quality adjustment circuit PQ, an adjustment circuit 311 and a transmitter Tx. The receiver Rx is used for receiving the display data D. The image quality adjustment circuit PQ is used for adjusting the image quality according to the display data D. The adjustment circuit 311 includes a control signal generation circuit SG and an acceleration drive circuit OD. The control signal generating circuit SG is used to generate various control signals according to the display data D, and provide the aforementioned various control signals to the source driver SD through the transmitter Tx. The aforementioned various control signals include the signal S_TP (or S_TP') and the signal S_POL. The speed-up driving circuit OD is used to receive the display data D, and provide the display data D (or D') to the source driver SD through the transmitter Tx. The source driver SD includes a plurality of source driving units for driving corresponding pixel columns on the panel.

It should be noted that functions of the receiver Rx, the image quality adjustment circuit PQ, and the transmitter Tx are well known to those skilled in the art of the present invention, so details are not repeated here. And, the focus of the present invention is also not here. The purpose of the present invention is to improve the control signal generating circuit SG and the acceleration drive circuit OD so that their functions are different from those of the past. In the present invention, the acceleration driving circuit OD can determine the compensation amount for the current display data D according to the current display data D, the previous display data D and the signal S_POL (compensation is referred to as display data D′). Wherein, the compensation amount determined under the condition that there is a difference between the current display data D and the previous display data D and the voltage polarity is different will be greater than that between the current display data D and the previous display data D but the voltage polarity is the same The amount of compensation determined under the circumstances. That is to say, the acceleration driving circuit OD will determine a compensation amount for the current display data D and its corresponding source driving unit, so as to avoid insufficient driving force of the source driving unit, resulting in brightness differences between adjacent pixel rows. situation.

In addition, the control signal generating circuit SG can further determine whether to adjust the generation time point of at least one pulse of the signal S_TP according to the signal S_POL (referred to as signal S_TP' after adjustment). The timing control circuit 310 of the present invention can adjust at least one of the grayscale information of the current display data and the charging time of the current display data in response to the voltage polarity of the current display data being different from that of the previous display data.

FIG. 4 is a schematic block diagram of a control signal generating circuit and an acceleration driving circuit according to an embodiment of the present invention. Please refer to FIG. 3 and FIG. 4 at the same time, the control signal generating circuit SG includes a charging signal generating circuit G1 and a polarity signal generating circuit G2. Charge The electrical signal generating circuit G1 is coupled to the polarity signal generating circuit G2 for generating the signal S_TP (or S_TP') according to the signal S_POL. The signal S_TP (or S_TP') is provided by the transmitter Tx to the source driver SD. The source driver SD determines the starting time point of charging the multiple data lines according to the signal S_TP (or S_TP'). The polarity signal generating circuit G2 is used for generating the signal S_POL. The signal S_TP is provided to the source driver SD by the transmitter Tx. The source driver SD determines the polarity of the output data voltage according to the signal S_POL. The signal S_POL is also provided to the acceleration driving circuit OD at the same time. The acceleration driving circuit OD receives the display data D and the signal S_POL. The speed-up driving circuit OD provides the display data D (or D') to the source driver SD through the transmitter Tx according to the display data D and the signal S_POL. The functions of the control signal generating circuit SG and the acceleration driving circuit OD will be described below with multiple embodiments when polarity inversion is performed.

FIG. 5 is a schematic diagram illustrating that the data voltage received by the pixel array exhibits polarity column inversion. Figure 5 shows only a portion of the pixel array. All the pixels in FIG. 5 are to display the same gray scale (appeared with the same background color), and the only difference lies in whether the provided data voltage is positive or negative. In this embodiment, polarity inversion is performed every 4 pixel columns. Please refer to FIG. 5 , the pixel rows SL1 - SL13 are turned on sequentially in such a way that only one pixel row is turned on at a time. The source driver charges the plurality of pixels in the turned-on pixel row through the data lines DL1 - DL4 according to the data voltage. The data voltage provided by the source driver to the pixel rows SL1-SL4 and SL9-SL12 is positive, and the data voltage provided to the pixel rows SL5-SL8 and SL13 is negative. It can be seen that the polarities of the data voltages supplied to the pixel row SL4 and the pixel row SL5 are different (from positive polarity to for negative polarity). The polarities of the data voltages provided to the pixel row SL8 and the pixel row SL9 are different (from negative polarity to positive polarity). Due to the polarity switching of the data voltage, the source driver SD does not charge the pixel rows SL5 and SL9 enough, resulting in dark lines in the display screen corresponding to the pixel rows SL5 and SL9 as shown in FIG. 2 .

Please refer to FIG. 4 and FIG. 5 at the same time. In the first embodiment, only the acceleration driving circuit OD determines whether to compensate the data voltage V according to the signal S_POL, and the charging signal generating circuit G1 outputs the signal S_TP to the source driver as usual. The timing control circuit sequentially receives a plurality of display data for each data line of the display panel, and instructs the source driver to drive the pixel array. Taking the data line DL1 as an example, the timing control circuit sequentially receives a plurality of display data corresponding to the data line DL1 (assuming that the gray levels are the same). The source driver charges the pixel p1 with the positive polarity data voltage corresponding to the first display data according to the signal S_TP (the pixel row SL1 is turned on). Next, the source driver charges the pixel p2 with the positive polarity data voltage corresponding to the second display data according to the signal S_TP (the pixel row SL2 is turned on). Next, the source driver sequentially charges the pixel p3 with the positive polarity data voltage corresponding to the third display data according to the signal S_TP (the pixel row SL3 is turned on). Next, the source driver charges the pixel p4 with the positive polarity data voltage corresponding to the fourth display data according to the signal S_TP, and so on.

However, the data voltage polarity of the fourth display data is different from that of the fifth display data, so the speed-up driving circuit OD of the timing control circuit can perform the following operations. The speed-up driving circuit OD can compare the gray scale information and the data voltage polarity (according to the signal S_TP) of the fourth display data and the fifth display data. Acceleration drive circuit OD can be based on the grayscale information of the 4th display data and the 5th display data The gray level difference between them, and at the same time, decide whether to adjust the output display data according to the comparison result of the data voltage polarity of the fourth display data and the fifth display data. In the first embodiment, since the grayscale information of the fourth display data and the fifth display data are the same, the acceleration drive circuit OD is only adjusted with an adjustment value according to the comparison result of the data voltage polarity (the polarity is different). Display data D, and output the adjustment result (that is, display data D').

FIG. 6A is a schematic waveform diagram of the column inversion of the polarity of the data voltage without using the present invention. FIG. 6B is a schematic waveform diagram of the column inversion of the polarity of the data voltage in the first embodiment of the present invention. In FIG. 6A and FIG. 6B , the horizontal axis is the time t, and the vertical axis is the material voltage V (which can be regarded as the output data voltage of one data channel). Curve C1 represents the time-varying data voltage in an ideal state. Curves C2 and C2' both represent the data voltage changing with time under the actual state. Assume a polarity row inversion every four pixel columns. Vcom is a reference voltage, and can also be regarded as an intermediate voltage. T represents the time interval required to charge a pixel column.

Please refer to FIG. 5 and FIG. 6A at the same time. It can be seen that the pixel p5 is driven by the negative data voltage, but the pixel p4 is driven by the positive data voltage (all the pixels in the pixel column SL5 are the same). Before the pixel p5 is driven, the speed-up driving circuit OD can know in advance that the polarity of the data voltage corresponding to the pixel p5 will be reversed according to the signal S_TP. Therefore, the acceleration drive circuit OD can adjust the display data of the corresponding pixel p5 (for example, adjust the grayscale from 128 to 140), so that the source driver uses a larger (farther away from the reference voltage Vcom) than the original when driving the pixel p5. ) data voltage to drive the pixel p5. Please compare Figure 6A and Figure 6B, the pixel in Figure 6A p5 will darken the display screen at the position corresponding to the pixel p5 due to insufficient charging. In fact, this is true for the entire pixel row SL5 , so a dark line appears on the display screen at the position of the pixel row SL5 . In FIG. 6B , since the pixel p5 is driven by the adjusted display data (see display data D' in FIG. 4 ), the charging condition of the pixel p5 is closer to the ideal state. Similarly, the charging conditions of the pixel p9 and the pixel p13 in FIG. 6B are both more ideal than those in FIG. 6A . In other words, the problem of dark lines on the display screen at positions corresponding to the pixel columns SL5 , SL9 and SL13 can be alleviated or avoided.

In one embodiment, the speed-up driving circuit OD of the present invention can determine the adjustment range of the second display data through a look-up table method according to a look-up table. The comparison table may include a plurality of grayscale difference information, a plurality of polarity reversal information (positive to negative or negative to positive), and corresponding multiple optional adjustment values. The look-up table can be pre-stored in a storage circuit, such as a static random access memory (Static Random Access Memory, SRAM). The acceleration driving circuit OD can select a candidate adjustment value as the adjustment value through a look-up table method, thereby adjusting the second display data (for example, the gray scale information is adjusted from 128 to 140). Compared with the case where the voltage polarity of the first display data is the same as that of the second display data, the speed-up driving circuit OD can control the gray scale of the second display data when the voltage polarity of the first display data is different from that of the second display data. The adjustment of information is relatively large.

Please refer to FIG. 4 and FIG. 5 at the same time. In the second embodiment, only the charging signal generating circuit G1 decides whether to adjust the signal S_TP according to the signal S_POL, and the acceleration driving circuit OD outputs the display data D to the source driver as usual. Taking the data line DL1 as an example, before the pixels p5, p9 and p13 are actually driven, the charging signal generating circuit G1 can know that the polarity of the data voltage is about to reverse through the signal S_POL. Specifically, the charging signal generating circuit G1 can compare the data voltage polarities corresponding to the two display data before and after, and decide whether to adjust the signal S_TP according to the comparison result. When the comparison result indicates that the polarity of the data voltage will be reversed, the charging signal generating circuit G1 adjusts the signal S_TP to advance the charging time of the corresponding pixels p5 , p9 and p13 .

FIG. 7A is a schematic waveform diagram of the column inversion of the polarity of the data voltage without using the present invention. FIG. 7B is a schematic waveform diagram of the column inversion of the polarity of the data voltage in the second embodiment of the present invention. Similarly, in FIG. 7A and FIG. 7B , the horizontal axis is the time t, and the vertical axis is the data voltage V (which can be regarded as the data voltage output by one data channel). Curve C1 represents the time-varying data voltage in an ideal state. Curves C2 and C2' both represent the data voltage changing with time under the actual state. The transmitter Tx outputs display data D according to the signal Tx_D. Vcom is a reference voltage, and can also be regarded as an intermediate voltage. T represents the time interval required to charge a pixel column.

Please refer to FIG. 5 and FIG. 7A at the same time. It can be seen that the pixel p5 is driven by the negative data voltage, but the pixel p4 is driven by the positive data voltage (all the pixels in the pixel row SL5 are the same). Before the pixel p5 is driven, the charging signal generating circuit G1 can know in advance that the polarity of the data voltage corresponding to the pixel p5 will be reversed according to the signal S_TP. Therefore, the charging signal generating circuit G1 can adjust the signal S_TP so as to advance the timing of charging the pixel p5 by the source driver. Please compare FIG. 7A and FIG. 7B . In FIG. 7A , the pixel p5 in FIG. 7A will be darkened at the position corresponding to the pixel p5 due to insufficient charging. In fact, this is the case for the entire pixel row SL5 , so a dark line appears on the display screen at the position of the pixel row SL5 . In Figure 7B, because The pixel p5 is driven earlier, so that the charging start time point of the pixel p5 is advanced (see arrow 701 ), so the charging condition is more ideal (closer to the curve C1 than in FIG. 7A ). Wherein, the frequency of the signal Tx_D and the position of the rising edge of the signal will not be changed due to the adoption of the technical solution of the present invention. Similarly, the charging start time points of the pixel p9 and the pixel p13 are advanced (see arrows 702 and 703 ), so the charging conditions of the pixel p9 and the pixel p13 in FIG. 7B are more ideal than those in FIG. 7A . Thereby, the problem of dark lines on the display screen at positions corresponding to the pixel columns SL5 , SL9 and SL13 can be alleviated or avoided.

Please refer to FIG. 4 and FIG. 5 at the same time. In the third embodiment, the acceleration driving circuit OD determines whether to compensate the data voltage V according to the signal S_POL, and the charging signal generating circuit G1 also determines whether to adjust the signal S_TP according to the signal S_POL. Taking the pixel p5 of the pixel row SL5 as an example, the display data corresponding to the pixel p5 can be adjusted according to the comparison result of the data voltage polarity, and the charging start time point of the pixel p5 can also be advanced according to the comparison result of the data voltage polarity. Furthermore, the problem of dark lines on the display screen at positions corresponding to the pixel columns SL5 , SL9 and SL13 can be alleviated or avoided.

FIG. 8 is a flow chart showing the steps of the operation method of the timing control circuit according to an embodiment of the present invention. Please refer to FIG. 3 and FIG. 8 at the same time. In step S810 , the timing control circuit 310 sequentially receives the first display data and the second display data for one data line of the display panel. In step S820, the timing control circuit 310 adjusts at least one of the grayscale information of the second display data and the charging time of the second display data according to the voltage polarity of the first display data and the voltage polarity of the second display data.

It should be noted that although the above-mentioned embodiments are described based on the fact that the polarity is reversed every 4 columns, the present invention is not limited thereto. The present invention is also applicable to column polarity inversion for any number of columns, such as polarity inversion every 2 columns or every 8 columns. In addition, although the above-mentioned embodiments are described in the case of polarity column inversion, the present invention can also be applied to the case of dot inversion. In short, the present invention can be used as long as a single data channel experiences polarity inversion during a frame.

To sum up, the timing control circuit of the present invention can adjust at least one of the grayscale information of the current display data and the charging time for the situation that the data voltage polarities of the previous display data and the current display data are different. In this way, the problem of undercharging of multiple pixel columns with polarity inversion can be solved, and the situation of dark lines appearing on the display panel at the positions corresponding to the multiple pixel columns can be further alleviated or avoided.

300: display device

310: timing control circuit

311: Adjustment circuit

D, D': display data

OD: speed up drive circuit

PQ: picture quality adjustment circuit

Rx: Receiver

SG: control signal generation circuit

S_TP, S_TP': signal

S_POL: signal

SD: source driver

Tx: Transmitter

Claims (14)

A timing control circuit, used to control the polarity inversion of a data voltage output to a pixel array of a display panel during a frame period, separated by N scanning lines, where N is a positive integer, and the timing control circuit includes: a receiving a device for sequentially receiving a first display data and a second display data for a data line of the display panel; and an adjustment circuit coupled to the receiver for use in accordance with the voltage polarity of the first display data and The voltage polarity of the second display data is used to adjust at least one of grayscale information of the second display data and charging time of the second display data. The timing control circuit as described in Claim 1, wherein the adjustment circuit includes: an acceleration driving circuit, which is used to control the voltage polarity of the first display data, the voltage polarity of the second display data, and the gray of the first display data A grayscale difference between the grayscale information and the grayscale information of the second display data is used to adjust the grayscale information of the second display data with an adjustment value, thereby increasing a data voltage corresponding to the second display data. The timing control circuit as described in claim 2, wherein the timing control circuit includes a storage circuit, the storage circuit stores a plurality of candidate adjustment values, and the acceleration drive circuit is also used to obtain the adjustment from the candidate adjustment values value. The timing control circuit according to claim 2, wherein compared with the case where the voltage polarity of the first display data and the second display data are the same, the accelerated drive When the voltage polarity of the first display data is different from that of the second display data, the circuit can adjust the grayscale information of the second display data to a greater extent. The timing control circuit as described in claim 1, wherein the timing control circuit includes a storage circuit, the storage circuit stores a plurality of candidate adjustment values, and the adjustment circuit further includes: an acceleration drive circuit for the second When the voltage polarity of the display data is different from that of the first display data, according to a grayscale difference between the grayscale information of the first display data and the grayscale information of the second display data, the selected The adjustment value obtains an adjustment value, wherein the acceleration driving circuit is used to adjust the grayscale information of the second display data according to the adjustment value, thereby increasing a data voltage corresponding to the second display data. The timing control circuit according to claim 1, wherein the adjustment circuit further includes: a charging signal generating circuit for generating a pulse signal to instruct a driving device to charge the data line with the second display data A time point, wherein the charging signal generating circuit is also used to adjust the pulse signal to advance the time point when the voltage polarity of the second display data is different from that of the first display data. The timing control circuit according to claim 1, wherein the adjustment circuit further includes: a polarity signal generating circuit for generating a polarity inversion control signal to indicate the voltage polarity of the first display data and the voltage polarity of the second display data the voltage polarity. An operation method of a timing control circuit, wherein the timing control circuit is used to control the polarity inversion of a data voltage output to a pixel array of a display panel during a frame period, N scanning lines are separated, and N is a positive integer, the The operation method includes: a receiver of the timing control circuit sequentially receives a first display data and a second display data for a data line of the display panel; and an adjustment circuit of the timing control circuit according to the first display data The voltage polarity of the first display data and the voltage polarity of the second display data are used to adjust at least one of the gray scale information of the second display data and the charging time of the second display data. The operation method of the timing control circuit as described in claim 8, wherein the adjustment circuit includes an acceleration drive circuit, and the operation method further includes: the acceleration drive circuit according to the voltage polarity of the first display data, the second display data the voltage polarity of the first display data and a gray scale difference between the gray scale information of the first display data and the gray scale information of the second display data, adjust the gray scale information of the second display data with an adjustment value, thereby improving A data voltage corresponding to the second display data. The operation method of the timing control circuit as described in claim 9, wherein the timing control circuit includes a storage circuit, and the storage circuit stores a plurality of alternative adjustment values, and the operation method further includes: the acceleration driving circuit from the Some alternative adjustment values to get the adjustment value. The operation method of the timing control circuit as described in Claim 9, wherein compared with the case where the voltage polarity of the first display data and the second display data are the same, the voltage of the first display data and the second display data different polarities Under the circumstances, the gray level information of the second display data is adjusted by the accelerated driving circuit with a relatively large adjustment range. The operation method of the timing control circuit as described in Claim 8, wherein the timing control circuit includes a storage circuit, the storage circuit stores a plurality of candidate adjustment values, and the adjustment circuit includes an acceleration drive circuit, the operation method also Including: when the voltage polarity of the second display data is different from the voltage polarity of the first display data, the acceleration drive circuit according to the difference between the grayscale information of the first display data and the grayscale information of the second display data A grayscale difference, an adjustment value is obtained from the candidate adjustment values; and the acceleration driving circuit adjusts the grayscale information of the second display data according to the adjustment value, thereby improving a corresponding to the second display data data voltage. The operation method of the timing control circuit as described in Claim 8, wherein the adjustment circuit includes a charging signal generating circuit, and the operating method further includes: generating a pulse signal by the charging signal generating circuit to instruct a driving device to use the first 2. A time point when the data line is charged by the second display data, wherein: when the voltage polarity of the second display data is different from the voltage polarity of the first display data, the charging signal generating circuit adjusts the pulse signal to The time point is advanced. The operation method of the timing control circuit as described in claim 8, wherein the adjustment circuit includes a polarity signal generation circuit, and the operation method further includes: generating a polarity inversion control signal by the polarity signal generation circuit to indicate the The voltage polarity of the first display data and the voltage polarity of the second display data.

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