TWI847651B - Electronic packaging structure and manufacturing method thereof - Google Patents
Electronic packaging structure and manufacturing method thereof Download PDFInfo
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- TWI847651B TWI847651B TW112114187A TW112114187A TWI847651B TW I847651 B TWI847651 B TW I847651B TW 112114187 A TW112114187 A TW 112114187A TW 112114187 A TW112114187 A TW 112114187A TW I847651 B TWI847651 B TW I847651B
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- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000004100 electronic packaging Methods 0.000 title abstract description 15
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electrostatic, Electromagnetic, Magneto- Strictive, And Variable-Resistance Transducers (AREA)
Abstract
Description
本發明是有關於一種電子封裝結構及其製造方法,且特別是有關於一種具有電子元件嵌於多個電路結構之間的電子封裝結構及其製造方法。 The present invention relates to an electronic packaging structure and a manufacturing method thereof, and in particular to an electronic packaging structure having electronic components embedded between multiple circuit structures and a manufacturing method thereof.
隨著科技進步,電子產品的功能越來越豐富,且對於電子行動裝置也日趨依賴。因應電子產品微型化與輕量化的需求,將天線(antenna)結構與晶片封裝結構的整合有助於電子產品的微型化及輕量化。一般來說,對於現行的具有天線結構的晶片封裝結構來說,通常是將晶片設置於電路基板上,並覆蓋膜封材料於晶片上,以形成晶片封裝結構。而天線結構則設置於晶片封裝結構上,並透過晶片封裝結構中貫穿膜封材料的導電柱或導電球使天線結構與電路基板電性連接。然而,於上述封裝結構中,電子元件可能較難受到良好的保護;且/或,上述封裝結構可能無法有效防止射頻(radio frequency)訊號於傳輸過程中發散,且具有較大的體積。 With the advancement of technology, the functions of electronic products are becoming more and more abundant, and electronic mobile devices are becoming more and more dependent. In response to the demand for miniaturization and lightweighting of electronic products, the integration of antenna structure and chip packaging structure is conducive to the miniaturization and lightweighting of electronic products. Generally speaking, for the existing chip packaging structure with antenna structure, the chip is usually set on the circuit substrate and the film sealing material is covered on the chip to form a chip packaging structure. The antenna structure is set on the chip packaging structure, and the antenna structure is electrically connected to the circuit substrate through the conductive column or conductive ball that penetrates the film sealing material in the chip packaging structure. However, in the above-mentioned packaging structure, the electronic components may be difficult to be well protected; and/or, the above-mentioned packaging structure may not be able to effectively prevent the radio frequency signal from being dispersed during the transmission process and has a larger volume.
本發明提供一種電子封裝結構,其所包括的電子元件可能可以受到良好的保護。 The present invention provides an electronic packaging structure, the electronic components included therein may be well protected.
本發明的電子封裝結構包括第一電路結構、第二電路結構以及至少一電子元件。第一電路結構底側具有至少一空腔。第一電路結構位於第二電路結構上。第一電路結構和第二電路結構彼此電性連接。電子元件配置於第二電路結構上。電子元件對應於第一電路結構的空腔。 The electronic package structure of the present invention includes a first circuit structure, a second circuit structure and at least one electronic component. The bottom side of the first circuit structure has at least one cavity. The first circuit structure is located on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic component is arranged on the second circuit structure. The electronic component corresponds to the cavity of the first circuit structure.
在本發明的一實施例中,第一電路結構的空腔的內表面覆蓋有導電材料。 In one embodiment of the present invention, the inner surface of the cavity of the first circuit structure is covered with a conductive material.
在本發明的一實施例中,第一電路結構包括至少一同軸導電通孔。同軸導電通孔包括內導電層、外導電層以及介電層。介電層位於內導電層與外導電層之間。 In one embodiment of the present invention, the first circuit structure includes at least one coaxial conductive via. The coaxial conductive via includes an inner conductive layer, an outer conductive layer, and a dielectric layer. The dielectric layer is located between the inner conductive layer and the outer conductive layer.
在本發明的一實施例中,同軸導電通孔的外導電層的材質包括銅。 In one embodiment of the present invention, the material of the outer conductive layer of the coaxial conductive via includes copper.
在本發明的一實施例中,同軸導電通孔的介電層的材質包括樹脂。 In one embodiment of the present invention, the material of the dielectric layer of the coaxial conductive via includes resin.
在本發明的一實施例中,第一電路結構更包括上導電層以及下導電層。同軸導電通孔的外導電層的兩端分別連接部分的上導電層和部分的下導電層。 In one embodiment of the present invention, the first circuit structure further includes an upper conductive layer and a lower conductive layer. The two ends of the outer conductive layer of the coaxial conductive via are respectively connected to a portion of the upper conductive layer and a portion of the lower conductive layer.
在本發明的一實施例中,同軸導電通孔的內導電層電性 連接至第一電路結構的兩側的最外層電路。 In one embodiment of the present invention, the inner conductive layer of the coaxial conductive via is electrically connected to the outermost circuits on both sides of the first circuit structure.
在本發明的一實施例中,第一電路結構或第二電路結構中的至少其中之一包括位於最外部的阻焊層。 In one embodiment of the present invention, at least one of the first circuit structure or the second circuit structure includes a solder resist layer located at the outermost portion.
在本發明的一實施例中,電子封裝結構更包括填充材料。填充材料位於第一電路結構和第二電路結構之間。 In one embodiment of the present invention, the electronic packaging structure further includes a filling material. The filling material is located between the first circuit structure and the second circuit structure.
在本發明的一實施例中,電子封裝結構更包括導電連接件。導電連接件位於第一電路結構和第二電路結構之間以使第一電路結構與第二電路結構彼此電性連接。 In one embodiment of the present invention, the electronic package structure further includes a conductive connector. The conductive connector is located between the first circuit structure and the second circuit structure to electrically connect the first circuit structure and the second circuit structure to each other.
在本發明的一實施例中,電子封裝結構更包括導電連接件。導電連接件位於電子元件和第二電路結構之間以使電子元件與第二電路結構彼此電性連接。 In one embodiment of the present invention, the electronic package structure further includes a conductive connector. The conductive connector is located between the electronic component and the second circuit structure to electrically connect the electronic component and the second circuit structure to each other.
本發明的電子封裝結構的製造方法包括以下步驟:提供第一電路結構,其底側具有至少一空腔;提供第二電路結構;配置至少一電子元件於第二電路結構上;以及將具有電子元件配置於其上的第二電路結構和第一電路結構彼此電性連接,且使第一電路結構位於第二電路結構上,以使配置於第二電路結構上的電子元件對應於第一電路結構的空腔。 The manufacturing method of the electronic package structure of the present invention includes the following steps: providing a first circuit structure having at least one cavity on its bottom side; providing a second circuit structure; configuring at least one electronic component on the second circuit structure; and electrically connecting the second circuit structure having the electronic component configured thereon and the first circuit structure to each other, and positioning the first circuit structure on the second circuit structure so that the electronic component configured on the second circuit structure corresponds to the cavity of the first circuit structure.
基於上述,在電子封裝結構中,由於電子元件位於第一電路結構和第二電路結構之間,且至少部分的電子元件可以位於第一電路結構的空腔內。如此一來,可以使電子元件具有較佳的保護,而可以降低電子元件損傷或損壞的可能,而可以提升電子封裝結構的品質。 Based on the above, in the electronic packaging structure, since the electronic component is located between the first circuit structure and the second circuit structure, and at least part of the electronic component can be located in the cavity of the first circuit structure. In this way, the electronic component can be better protected, and the possibility of damage or destruction of the electronic component can be reduced, thereby improving the quality of the electronic packaging structure.
901、902:電子封裝結構 901, 902: Electronic packaging structure
100、100’:第一電路結構 100, 100': first circuit structure
101:核心結構 101: Core structure
155:第五上絕緣層 155: Fifth upper insulating layer
151:第五上線路層 151: Fifth upper line layer
151c:第五上導電層 151c: fifth upper conductive layer
135:第三上絕緣層 135: The third upper insulating layer
131:第三上線路層 131: The third upper line layer
131c:第三上導電層 131c: third upper conductive layer
115:第一上絕緣層 115: First upper insulating layer
111:第一上線路層 111: First upper line layer
105:第一核心層 105: First core layer
112:第一下線路層 112: First lower circuit layer
116:第一下絕緣層 116: The first lower insulating layer
132:第三下線路層 132: The third lower circuit layer
132c:第三下導電層 132c: The third lower conductive layer
136:第三下絕緣層 136: The third lower insulating layer
152:第五下線路層 152: The fifth lower circuit layer
152c:第五下導電層 152c: Fifth lower conductive layer
156:第五下絕緣層 156: The fifth lower insulating layer
108:貫通孔 108:Through hole
109:貫通孔 109:Through hole
190、190’:同軸導電通孔 190, 190’: coaxial conductive vias
196:第二介電層 196: Second dielectric layer
192:導電層 192: Conductive layer
195:第一介電層 195: First dielectric layer
191、191’:導電層 191, 191’: Conductive layer
170:空腔 170: Cavity
172:底線路層 172: Bottom line layer
172a:第一線路部分 172a: First line section
172b:第二線路部分 172b: Second line section
300:電子元件 300: Electronic components
200:第二電路結構 200: Second circuit structure
265:第六上絕緣層 265: Sixth upper insulating layer
241:第四上線路層 241: Fourth upper line layer
245:第四上絕緣層 245: The fourth upper insulating layer
221:第二上線路層 221: Second upper line layer
205:第二核心層 205: Second core layer
222:第二下線路層 222: Second lower circuit layer
246:第四下絕緣層 246: The fourth lower insulation layer
242:第四下線路層 242: Fourth lower circuit layer
266:第六下絕緣層 266: The sixth lower insulation layer
401、402:導電連接件 401, 402: Conductive connectors
408:填充材料 408: Filling material
圖1A至圖1P是依照本發明第一實施例的一種電子封裝結構的部分製造方法的部分示意圖。 Figures 1A to 1P are partial schematic diagrams of a partial manufacturing method of an electronic packaging structure according to the first embodiment of the present invention.
圖2是依照本發明第二實施例的一種電子封裝結構的部分示意圖。 Figure 2 is a partial schematic diagram of an electronic packaging structure according to the second embodiment of the present invention.
下文列舉實施例並配合所附圖式來進行詳細地說明,但所提供的實施例並非用以限制本發明所涵蓋的範圍。此外,圖式僅以說明為目的,並未依照原尺寸作圖。 The following is a detailed description of the embodiments and the accompanying drawings, but the embodiments provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn according to the original size.
此外,關於文中所使用「包括」、「具有」等等用語,均為開放性的用語,也就是指「包括但不限於」。 In addition, the terms "including", "having", etc. used in this article are open terms, which means "including but not limited to".
應當理解,儘管術語「第一」、「第二」、「第三」等在本文中可以用於描述各種元件、部件、區域、層及/或部分,但是這些元件、部件、區域、及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開。因此,下面討論的「第一元件」、「部件」、「區域」、「層」、或「部分」可以被稱為第二元件、部件、區域、層或部分而不脫離本文的教導。 It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer", or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.
本文中所提到的方向用語,例如:「上」、「下」、「頂」、 底」等,僅是參考附圖的方向。因此,使用的方向用語是用來說明,而並非用來限制本發明。 The directional terms mentioned in this article, such as "up", "down", "top", "bottom", etc., are only for reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and are not used to limit the present invention.
在附圖中,各圖式繪示的是特定實施例中所使用的方法、結構及/或材料的通常性特徵。然而,這些圖式不應被解釋為界定或限制由這些實施例所涵蓋的範圍或性質。舉例來說,為了清楚起見,各膜層、區域及/或結構的相對尺寸、厚度及位置可能縮小或放大。 In the accompanying drawings, each diagram depicts the general characteristics of the methods, structures and/or materials used in a particular embodiment. However, these diagrams should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, the relative size, thickness and position of each film layer, region and/or structure may be reduced or exaggerated for clarity.
在下述實施例中,相同或相似的元件將採用相同或相似的標號,且將省略其贅述。此外,不同實施例中的特徵在沒有衝突的情況下可相互組合,且依本說明書或申請專利範圍所作之簡單的等效變化與修飾,皆仍屬本專利涵蓋的範圍內。 In the following embodiments, the same or similar components will be labeled with the same or similar reference numerals, and their redundant description will be omitted. In addition, the features in different embodiments can be combined with each other without conflict, and simple equivalent changes and modifications made according to this specification or the scope of the patent application are still within the scope of this patent.
<第一電路結構><First Circuit Structure>
第一電路結構100(標示於圖1L)的形成方式可以如圖1A至圖1M所示。圖1A至圖1L可以是第一電路結構100的部分形成方式的部分剖視示意圖。圖1M可以是第一電路結構100的部分形成方式的部分底視示意圖。圖1M可以是對應於圖1K的底視示意圖。
The formation method of the first circuit structure 100 (indicated in FIG. 1L) can be as shown in FIG. 1A to FIG. 1M. FIG. 1A to FIG. 1L can be partial cross-sectional schematic diagrams of the partial formation method of the
請參照圖1A,提供核心結構(core strueture)101。
Please refer to Figure 1A to provide a
在一實施例中,核心結構101可以包括第一核心層105。第一核心層105可包括高分子玻璃纖維複合材料基板、玻璃基板、陶瓷基板、絕緣矽基板或聚醯亞胺(polyimide;PI)玻璃纖維複合基板等,但本發明不限於此。
In one embodiment, the
在一實施例中,第一核心層105的厚度可以約為200微米(micrometer;μm)。
In one embodiment, the thickness of the
在一實施例中,核心結構101可以更包括位於第一核心層105表面上的線路層。舉例而言,核心結構可以更包括第一上線路層111和第一下線路層112。第一上線路層111和第一下線路層112分別位於第一核心層105的上表面和下表面。線路層(包括,但不限於第一上線路層111或第一下線路層112)的線路設計(layout design)可以依據設計上的需求而加以調整,於本發明並不加以限定。
In one embodiment, the
在一實施例中,核心結構101可以包括圖案化後的銅箔基板(Copper Clad Laminate,CCL),但本發明不限於此。
In one embodiment, the
在一未繪示的實施例中或一未繪示的剖面上,第一上線路層111中對應的線路和第一下線路層112中對應的線路可能可以藉由貫穿第一核心層105的導電通孔(conductive via)(未繪示)而彼此電性連接。
In an unillustrated embodiment or an unillustrated cross section, the corresponding lines in the first
請參照圖1B,於第一核心層105的上下兩側分別形成對應的絕緣層。舉例而言,第一上絕緣層115和第一下絕緣層116可以分別位於第一核心層105的上表面和下表面。
Referring to FIG. 1B , corresponding insulating layers are formed on the upper and lower sides of the
絕緣層(如:第一上絕緣層115和/或第一下絕緣層116)可以藉由適當的方式所形成。在一實施例中,絕緣層可以藉由塗佈及固化(如:光固化、熱固化或靜置固化)的方式所形成;舉例而言,絕緣層可以包括聚醯亞胺塗層(polyimide coating layer)。
在一實施例中,絕緣層可以藉由貼覆的方式形成;舉例而言,絕緣層可以包括聚醯亞胺乾膜(polyimide dry film)。
The insulating layer (e.g., the first upper insulating
在一實施例中,絕緣層可以覆蓋對應的線路層。舉例而言,第一上絕緣層115可以覆蓋第一上線路層111;且/或,第一下絕緣層116可以覆蓋第一下線路層112。
In one embodiment, the insulating layer may cover the corresponding circuit layer. For example, the first upper insulating
在一實施例中,第一上絕緣層115或第一下絕緣層116可以直接接觸部分的第一核心層105。
In one embodiment, the first upper insulating
在一實施例中,第一上絕緣層115和第一下絕緣層116的厚度可以相同或相似。舉例而言,第一上絕緣層115的厚度和第一下絕緣層116的厚度的比值可以介於90%~110%。在一實施例中,第一上絕緣層115的厚度或第一下絕緣層116的厚度可以約為250微米。
In one embodiment, the thickness of the first upper insulating
請繼續參照圖1B,在一實施例中,絕緣層上可以具有導電層。舉例而言,第三上導電層131c可以覆蓋第一上絕緣層115,且/或第三下導電層132c可以覆蓋第一下絕緣層116。
Please continue to refer to FIG. 1B . In one embodiment, a conductive layer may be provided on the insulating layer. For example, the third upper
在一實施例中,絕緣層上的導電層可以藉由濺鍍的方式所形成。在一實施例中,絕緣層上的導電層(如:第三上導電層131c和/或第三下導電層132c)可以被稱為鍍覆種子層(plating seed layer)。
In one embodiment, the conductive layer on the insulating layer can be formed by sputtering. In one embodiment, the conductive layer on the insulating layer (such as the third upper
在一實施例中,絕緣層上的導電層可以藉由貼覆的方式所形成。在一實施例中,絕緣層及位於其上的導電層(如:第一上絕緣層115和第三上導電層131c;和/或,第一下絕緣層116和
第三下導電層132c)可以是銅箔基板(Copper Clad Laminate,CCL)。
In one embodiment, the conductive layer on the insulating layer can be formed by lamination. In one embodiment, the insulating layer and the conductive layer thereon (such as: the first upper insulating
在一實施例中,第三上導電層131c和第三下導電層132c的厚度可以相同或相似。舉例而言,第三上導電層131c的厚度和第三下導電層132c的厚度的比值可以介於90%~110%。
In one embodiment, the thickness of the third upper
請參照圖1C,形成至少一貫通孔(through hole)108。貫通孔108可以貫穿第一核心層105及位於其表面上的部分膜層。舉例而言,貫通孔108可以貫穿部分的第一上線路層111。在一實施例中,貫通孔108可以藉由雷射鑽孔、機械鑽孔及/或其他適宜的方式所形成。
Referring to FIG. 1C , at least one through
值得注意的是,於圖1C中僅示例性地繪示了一個貫通孔108,但本發明不限於此。在其他未繪示的實施例或其他未繪示的剖面上,可以具有其他相同或相似於貫通孔108的貫通孔。
It is worth noting that only one through
請參照圖1D,於貫通孔108的內壁上形成導電層(可被稱為:外導電層)191。在一實施例中,可以藉由電鍍的方式以於第三上導電層131c上及/或第三下導電層132c上形成對應的電鍍層。前述的電鍍層可以進一步地延伸至貫通孔108內壁上,而形成對應的導電層191。在一實施例中,內壁上的導電層191可以包括銅層。
Referring to FIG. 1D , a conductive layer (which may be referred to as an outer conductive layer) 191 is formed on the inner wall of the through
在一實施例中,導電層191覆蓋內壁的形式(如:範圍及/或厚鍍)可以藉由適當的電鍍方式或參數而進行調整。
In one embodiment, the form of the
在一實施例中,導電層191可以完全覆蓋貫通孔108的
內壁。
In one embodiment, the
在另一實施例中,相似於導電層191的導電層可以部分覆蓋貫通孔108的內壁。舉例而言,用於進行電鍍的電流源可以僅施加於第三下導電層132c,而不施加於第三上導電層131c。如此一來,可以使貫通孔108的內壁較接近第三上導電層131c的部分未被導電層所覆蓋。
In another embodiment, a conductive layer similar to the
在一實施例中,導電層191不會完全填滿貫通孔108。在一實施例中,於垂直於貫通孔108的延伸方向的一方向上,導電層191的內緣的最大距離可以約為400微米至500微米。也就是說,覆蓋有導電層191的貫通孔108的內徑可以約為400微米至500微米。
In one embodiment, the
請參照圖1E,於覆蓋有導電層191的貫通孔108內形成第一介電層195。第一介電層195的材質可以包括塞孔樹脂材料、高分子玻璃陶瓷混合材料或其他適宜的介電材料。
Referring to FIG. 1E , a first
在一實施例中,可以藉由適當的平整化製程(如:研磨製程(polishing process)),以使第一介電層195具有較平整的外表面,但本發明不限於此。
In one embodiment, a suitable planarization process (such as a polishing process) can be used to make the
請繼續參照圖1E,可以藉由適當的圖案化製程(如:微影蝕刻製程)而將第三上導電層131c及位於其上的電鍍層圖案化,以對應地形成第三上線路層131;且/或,可以藉由適當的圖案化製程(如:微影蝕刻製程)而將第三下導電層132c及位於其上的電鍍層圖案化,以對應地形成第三下線路層132。也就是說,
第三上線路層131或第三下線路層132可以包括多個導電層的堆疊。
Please continue to refer to FIG. 1E , the third upper
請參照圖1F,於第一核心層105的上下兩側分別形成對應的絕緣層。舉例而言,第三上絕緣層135和第三下絕緣層136可以分別位於第一核心層105的上表面和下表面。
Referring to FIG. 1F , corresponding insulating layers are formed on the upper and lower sides of the
絕緣層可以藉由適當的方式所形成。舉例而言,絕緣層(如:第三上絕緣層135和/或第三下絕緣層136)可以包括聚醯亞胺塗層或聚醯亞胺乾膜。
The insulating layer can be formed by a suitable method. For example, the insulating layer (such as the third upper insulating
在一實施例中,絕緣層可以覆蓋對應的線路層。舉例而言,第三上絕緣層135可以覆蓋第三上線路層131,且/或第三下絕緣層136可以覆蓋第三下線路層132。
In one embodiment, the insulating layer may cover the corresponding circuit layer. For example, the third upper insulating
在一實施例中,第三上絕緣層135可以直接接觸部分的第一上絕緣層115;且/或,第三下絕緣層136可以直接接觸部分的第一下絕緣層116。
In one embodiment, the third upper insulating
在一實施例中,第三上絕緣層135和第三下絕緣層136的厚度可以相同或相似。舉例而言,第三上絕緣層135的厚度和第三下絕緣層136的厚度的比值可以介於90%~110%。在一實施例中,第三上絕緣層135的厚度及/或第三下絕緣層136的厚度可以小於第一上絕緣層115的厚度及/或第一下絕緣層116的厚度。在一實施例中,第三上絕緣層135的厚度或第三下絕緣層136的厚度可以約為50微米。
In one embodiment, the thickness of the third upper insulating
請繼續參照圖1F,在一實施例中,絕緣層上可以具有導
電層。舉例而言,第五上導電層151c可以覆蓋第三上絕緣層135;且/或,第五下導電層152c可以覆蓋第三下絕緣層136。
Please continue to refer to FIG. 1F. In one embodiment, the insulating layer may have a conductive layer. For example, the fifth upper
在一實施例中,絕緣層上的導電層可以藉由濺鍍的方式所形成。在一實施例中,絕緣層上的導電層(如:第五上導電層151c和/或第五下導電層152c)可以被稱為鍍覆種子層(plating seed layer)。
In one embodiment, the conductive layer on the insulating layer can be formed by sputtering. In one embodiment, the conductive layer on the insulating layer (such as the fifth upper
在一實施例中,絕緣層上的導電層可以藉由貼覆的方式所形成。在一實施例中,絕緣層及位於其上的導電層(如:第三上絕緣層135和第五上導電層151c;和/或,第三下絕緣層136和五下導電層152c)可以是銅箔基板(Copper Clad Laminate,CCL)。
In one embodiment, the conductive layer on the insulating layer can be formed by lamination. In one embodiment, the insulating layer and the conductive layer thereon (such as the third upper insulating
在一實施例中,第五上導電層151c和第五下導電層152c的厚度可以相同或相似。舉例而言,第五上導電層151c的厚度和第五下導電層152c的厚度的比值可以介於90%~110%。
In one embodiment, the thickness of the fifth upper
請參照圖1G,形成至少一貫通孔(through hole)109。貫通孔109可以貫穿第一介電層195及位於其表面上的膜層(如:第三上絕緣層135、第五上導電層151c、第三下絕緣層136和/或第五下導電層152c)。在一實施例中,貫通孔109可以藉由雷射鑽孔、機械鑽孔及/或其他適宜的方式所形成。
Please refer to FIG. 1G to form at least one through
請參照圖1H,於貫通孔109的內壁上形成導電層(可被稱為:內導電層)192。在一實施例中,可以藉由電鍍的方式以於第五上導電層151c上及/或第五下導電層152c上形成對應的電鍍層。前述的電鍍層可以進一步地延伸至貫通孔109內壁上,而形
成對應的導電層192。在一實施例中,內壁上的導電層192可以包括銅層。
Referring to FIG. 1H , a conductive layer (which may be referred to as an inner conductive layer) 192 is formed on the inner wall of the through
在一實施例中,導電層192可以完全覆蓋貫通孔109的內壁。
In one embodiment, the
在一實施例中,導電層192不會完全填滿貫通孔109。在一實施例中,於垂直於貫通孔109的延伸方向的一方向上,導電層192的內緣的最大距離可以約為50微米至150微米。也就是說,覆蓋有導電層192的貫通孔109的內徑可以約為50微米至150微米。
In one embodiment, the
在一未繪示的實施例中,導電層192可以完全填滿貫通孔109。在一未繪示的實施例中,於貫通孔109內的導電層192可以為導電柱。
In an embodiment not shown, the
請參照圖1I,在一實施例中,於覆蓋有導電層192的貫通孔109內形成第二介電層196。第二介電層196的材質可以包括塞孔樹脂材料、高分子玻璃陶瓷混合材料或其他適宜的介電材料。
Referring to FIG. 1I , in one embodiment, a
在一實施例中,可以藉由適當的平整化製程(如:研磨製程(polishing process)),以使第二介電層196具有較平整的外表面,但本發明不限於此。
In one embodiment, a suitable planarization process (such as a polishing process) can be used to make the
在一實施例中,外導電層191、第一介電層195、內導電層192及第二介電層196可以構成同軸導電通孔(coaxial conductive via)190。
In one embodiment, the outer
請繼續參照圖1I,可以藉由適當的圖案化製程(如:微
影蝕刻製程)而將第五上導電層151c及位於其上的電鍍層圖案化,以對應地形成第五上線路層151;且/或,可以藉由適當的圖案化製程(如:微影蝕刻製程)而將第五下導電層152c及位於其上的電鍍層圖案化,以對應地形成第五下線路層152。也就是說,第五上線路層151或第五下線路層152可以包括多個導電層的堆疊。
Please continue to refer to FIG. 1I. The fifth upper
請參照圖1J,於第一核心層105的一側形成空腔170。在一實施例中,可以藉由蝕刻、燒蝕、鑽磨或其他適宜的方式,移除部分的絕緣層(如:部分的第三下絕緣層136及部分的第一下絕緣層116),以形成對應的空腔170。
Referring to FIG. 1J , a
在一實施例中,空腔170的深度可以約為200微米。
In one embodiment, the depth of
在一實施例中,於形成空腔170的過程中,可以移除部分的第三下絕緣層136,而可以暴露出部分的第三下線路層132。
In one embodiment, during the process of forming the
請參照圖1K及圖1M,在一實施例中,可以於第一核心層105對應於空腔170的一側形成底線路層172。底線路層172可以藉由濺鍍、電鍍、微影蝕刻及/或其他適宜的方式所形成。
Referring to FIG. 1K and FIG. 1M, in one embodiment, a
在一實施例中,底線路層172至少完全地覆蓋空腔170。
In one embodiment, the
請繼續參照圖1K,在一實施例中,可以於第五上線路層151上鍍覆對應的導電層。在一實施例中,鍍覆於第五上線路層151上的導電層可以進一步地覆蓋第二介電層196的一側。
Please continue to refer to FIG. 1K. In one embodiment, a corresponding conductive layer may be coated on the fifth
就結構上而言,鍍覆於第五上線路層151上的導電層可以與第五上線路層151直接接觸而構成多層導電結構,且前述多
層導電結構之間不具有絕緣材質或介電材質。為求簡潔,第五上線路層151及位於其上的導電層仍可被稱為第五上線路層並沿用相同的標號。
Structurally, the conductive layer coated on the fifth
請參照圖1L,在一實施例中,可以於第一核心層105的上下兩側分別形成對應的絕緣層。舉例而言,第五上絕緣層155和第五下絕緣層156可以分別位於第一核心層105的上表面和下表面。
Referring to FIG. 1L , in one embodiment, corresponding insulating layers may be formed on the upper and lower sides of the
在一實施例中,第五上絕緣層155的厚度或第五下絕緣層156的厚度可以約為20微米。
In one embodiment, the thickness of the fifth upper insulating
在一實施例中,第五上絕緣層155和/或第五下絕緣層156可以被稱為阻焊層。在一實施例中,第一電路結構100的阻焊層可以為其最外部的絕緣層。舉例而言,第五上絕緣層155可以為第一電路結構100中最頂端的絕緣層,且/或第五下絕緣層156可以為第一電路結構100中最底端的絕緣層。
In one embodiment, the fifth upper insulating
在一實施例中,第一電路結構100的底線路層172可以為其最底端的導電層。
In one embodiment, the
經過上述製程後即可大致上完成一實施例之第一電路結構100的製作。
After the above process, the manufacturing of the
請參照圖1L,第一電路結構100底側具有至少一空腔170,且第一電路結構100可以更包括至少一同軸導電通孔190。
Referring to FIG. 1L , the bottom side of the
在一實施例中,同軸導電通孔190可以包括外導電層191、第一介電層195和內導電層192。第一介電層195位於外導
電層191和內導電層192之間。外導電層191至少圍繞部分的內導電層192。外導電層191和內導電層192彼此電性分離。
In one embodiment, the coaxial conductive via 190 may include an outer
在一實施例中,同軸導電通孔190可以更包括第二介電層196。內導電層192可以位於第一介電層195和第二介電層196之間。
In one embodiment, the coaxial conductive via 190 may further include a
在一實施例中,第一電路結構100可以包括第一核心層105、位於第一核心層105上側及/或下側的對應線路層及/或對應線路層絕緣層。空腔170位於第一核心層105的下側。同軸導電通孔190貫穿第一核心層105及部分的絕緣層,以電性連接於線路層中對應的線路。
In one embodiment, the
舉例而言,第一電路結構100可以包括第五上絕緣層155、第五上線路層151、第三上絕緣層135、第三上線路層131、第一上絕緣層115、第一上線路層111、第一核心層105、第一下線路層112、第一下絕緣層116、第三下線路層132、第三下絕緣層136、第五下線路層152以及第五下絕緣層156。空腔170貫穿部分的第三下絕緣層136且內凹於部分的第一下絕緣層116。同軸導電通孔190貫穿第一上絕緣層115、第一核心層105及第一下絕緣層116。同軸導電通孔190的內導電層192電性連接於第五上線路層151中對應的一線路及第五下線路層152中對應的一線路。同軸導電通孔190的外導電層191電性連接於第三上線路層131中對應的一線路及/或第一上線路層111中對應的一線路;且同軸導電通孔190的外導電層191電性連接於第三下線路層132中對
應的一線路及/或第五下線路層152中對應的另一線路。
For example, the
在一實施例中,第一電路結構100可以更包括底線路層172。底線路層172可以包括第一線路部分172a及第二線路部分172b。第一線路部分172a及第二線路部分172b彼此電性分離。
In one embodiment, the
第一線路部分172a可以電性連接於外導電層191。舉例而言,第一線路部分172a可以嵌入第三下絕緣層136,而可以藉由第三下絕緣層136所暴露出的部分第三下線路層132中對應的線路而電性連接於外導電層191。
The
第二線路部分172b可以電性連接於內導電層192。舉例而言,第二線路部分172b可以藉由第五下線路層152中對應的線路而電性連接於內導電層192。
The
在一實施例中,第一線路部分172a至少完全覆蓋空腔170。舉例而言,第一線路部分172a至少完全覆蓋空腔170的側壁及底部。
In one embodiment, the
在一實施例中,部分的線路層可以位於第五下絕緣層156和第三下絕緣層136之間。舉例而言,部分的第一線路部分172a及/或部分的第二線路部分172b可以位於第五下絕緣層156和第三下絕緣層136之間。
In one embodiment, part of the circuit layer may be located between the fifth lower insulating
在一實施例中,第一核心層105兩側的部分膜層(如:絕緣層)可以對稱性地配置。如此一來,在第一電路結構100的製作及/或後續的應用上,可以降低翹曲(warpage)的程度及/或可能,而可以提升良率及/或品質。
In one embodiment, some film layers (such as insulating layers) on both sides of the
舉例而言,第一上絕緣層115及第一下絕緣層116可以位於第一核心層105的兩側,且第一上絕緣層115和第一下絕緣層116的厚度可以相同或相似。又舉例而言,第一上絕緣層115及第一下絕緣層116可以分別接觸第一核心層105的兩側。
For example, the first upper insulating
舉例而言,第三上絕緣層135及第三下絕緣層136可以位於第一核心層105的兩側,且第三上絕緣層135和第三下絕緣層136的厚度可以相同或相似。又舉例而言,第三上絕緣層135及第三下絕緣層136可以分別接觸第一上絕緣層115及第一下絕緣層116。
For example, the third upper insulating
舉例而言,第五上絕緣層155及第五下絕緣層156可以位於第一核心層105的兩側,且第五上絕緣層155和第五下絕緣層156的厚度可以相同或相似。又舉例而言,第五上絕緣層155及第五下絕緣層156可以分別接觸第三上絕緣層135及第三下絕緣層136。
For example, the fifth upper insulating
<第二電路結構><Second Circuit Structure>
第二電路結構200的形成方式可以相似於第一電路結構100的形成方式。
The
請參照圖1N,第二電路結構200可以包括第二核心層205、位於第二核心層205上側及/或下側的對應線路層及/或對應線路層絕緣層。舉例而言,第二電路結構200可以包括第六上絕緣層265、第四上線路層241、第四上絕緣層245、第二上線路層221、第二核心層205、第二下線路層222、第四下絕緣層246、第
四下線路層242以及第六下絕緣層266。
Referring to FIG. 1N , the
在一實施例中,第二核心層205可包括高分子玻璃纖維複合材料基板、玻璃基板、陶瓷基板、絕緣矽基板或聚醯亞胺(polyimide;PI)玻璃纖維複合基板等,但本發明不限於此。在一實施例中,第二電路結構200可以被稱為硬板。
In one embodiment, the
在一實施例中,第二核心層205可包括聚醯亞胺(polyimide;PI)基板、聚對苯二甲酸乙二酯(polyethylene terephthalate;PET)基板等,但本發明不限於此。在一實施例中,第二電路結構200可以被稱為軟板。
In one embodiment, the
在一實施例中,第二電路結構200可以為軟硬接合板。
In one embodiment, the
在一實施例中,第二核心層205的厚度可以約為60微米。
In one embodiment, the thickness of the
在一實施例中,第四上線路層241、第四下線路層242、第二上線路層221及/或第二下線路層222的材質及/或形成方式可以相同或相似於前述的線路層(如:第五上線路層151、第五下線路層152、第三上線路層131、第三下線路層132、第一上線路層111及/或第一下線路層112)的材質及/或形成方式。
In one embodiment, the material and/or formation method of the fourth
在一實施例中,第四上絕緣層245及/或第四下絕緣層246的材質及/或形成方式可以相同或相似於前述的第一上絕緣層115、第一下絕緣層116、第三上絕緣層135和/或第三下絕緣層136的材質及/或形成方式。
In one embodiment, the material and/or formation method of the fourth upper insulating
在一實施例中,第四上絕緣層245的厚度或第四下絕緣層246的厚度可以約為25微米。
In one embodiment, the thickness of the fourth upper insulating
在一實施例中,第六上絕緣層265及/或第六下絕緣層266的材質及/或形成方式可以相同或相似於前述的第五上絕緣層155和/或第五下絕緣層156的材質及/或形成方式。
In one embodiment, the material and/or formation method of the sixth upper insulating
在一實施例中,第六上絕緣層265的厚度或第六下絕緣層266的厚度可以約為20微米。
In one embodiment, the thickness of the sixth upper insulating
在一實施例中,第六上絕緣層265和/或第六下絕緣層266可以被稱為阻焊層。在一實施例中,第二電路結構200的阻焊層可以為其最外部的絕緣層。
In one embodiment, the sixth upper insulating
在一實施例中,第六上絕緣層265可以具有對應的開口而可以暴露出第四上線路層241中對應的線路。在一實施例中,第六上絕緣層265的開口所暴露出的部分第四上線路層241可以被稱為連接墊。
In one embodiment, the sixth upper insulating
在一實施例中,第六下絕緣層266可以具有對應的開口而可以暴露出第四下線路層242中對應的線路。在一實施例中,第六下絕緣層266的開口所暴露出的部分第四下線路層242可以被稱為連接墊。
In one embodiment, the sixth lower insulating
<第二電路結構與電子元件之整合><Integration of the Second Circuit Structure and Electronic Components>
請參照圖1O,可以將電子元件300配置於第二電路結構200上,且使電子元件300電性連接於第四上線路層241中對應的線路。
Please refer to FIG. 1O , the
在一實施例中,電子元件300可以藉由對應的導電連接件402電性連接於第四上線路層241中對應的線路。導電連接件
402可以包括導電柱(如:銅柱)、焊料(如:焊球)、導電膠(如:銀漿或錫膏)或其他適宜的導電件。
In one embodiment, the
在一實施例中,電子元件300可以藉由覆晶接合(flip-chip bonding)的方式電性連接於第四上線路層241中對應的線路。
In one embodiment, the
在一實施例中,電子元件300中可以包括對應的通訊模組(communication module)。舉例而言,電子元件300可以適於藉由對應的天線接收及/或傳送訊號。在一實施例中,電子元件300中可以包括通訊晶片。
In one embodiment, the
<電子封裝結構><Electronic packaging structure>
請參照圖1P,將整合有電子元件300之第二電路結構200中對應的線路和第一電路結構100中對應的線路彼此電性連接。並且,使電子元件300對應於第一電路結構100的空腔170配置。電子元件300位於第一電路結構100和第二電路結構200之間。電子元件300至少部分地位於第一電路結構100的空腔170內。
Referring to FIG. 1P , the corresponding circuit in the
第二電路結構200中對應的線路和第一電路結構100中對應的線路可以藉由對應的導電連接件401電性連接。導電連接件401可以包括導電柱(如:銅柱)、焊料(如:焊球)、導電膠(如:銀漿或錫膏)或其他適宜的導電件。
The corresponding circuits in the
經過上述製程後即可大致上完成一實施例之電子封裝結構901的製作。值得注意的是,本發明並未限定第一電路結構100和第二電路結構200的先後製作順序。
After the above process, the manufacturing of the electronic package structure 901 of an embodiment can be substantially completed. It is worth noting that the present invention does not limit the order of manufacturing the
電子封裝結構901包括第一電路結構100、第二電路結構
200以及至少一電子元件300。第一電路結構100底側具有至少一空腔170。第一電路結構100包括至少一同軸導電通孔190。第一電路結構100位於第二電路結構200上。第一電路結構100和第二電路結構200且彼此電性連接。電子元件300配置於第二電路結構200上。電子元件300對應於第一電路結構100的空腔170。
The electronic package structure 901 includes a
在一實施例中,電子封裝結構901可以更包括絕緣的填充材料408。填充材料408可以位於第一電路結構100與第二電路結構200之間,且/或填充於第一電路結構100的空腔170內。
In one embodiment, the electronic package structure 901 may further include an insulating
在一實施例中,填充材料408可以包括絕緣的導熱材料。舉例而言,導熱材料可以填充於第一電路結構100的空腔170內,且導熱材料可以熱耦接於電子元件300及位於空腔170內的第一線路部分172a。如此一來,在電子元件300運作時,產生的熱可以較容易或較快速的被傳遞至外界。導熱材料例如是熱界面材料(Thermal interface material,TIM),但本發明不限於此。
In one embodiment, the filling
在一實施例中,沿著平行於第一電路結構100的厚度的一方向上,電子元件300完全重疊於空腔170內的第一線路部分172a。並且,第一線路部分172a可以接地。前述的接地可以包括浮動接地(floating ground)或物理性接地(physical ground)。因此,第一線路部分172a可以視為電磁干擾屏蔽(Electromagnetic Interference shielding,EMI Shielding)層。如此一來,在電子元件300運作時,可以降低電子元件300干擾其他元件或被其他元件干擾的可能,而可以提升訊號品質。
In one embodiment, the
在一實施例中,第五上線路層151中至少部分的線路可以為天線。電子元件300可以藉由第二電路結構200中對應的線路及第一電路結構100的同軸導電通孔190的內導電層192電性連接於前述的天線。在一實施例中,電子元件300電性連接的天線可以被稱為被勵天線(driven antenna)。在一實施例中,作為天線的部分第五上線路層151可以為第一電路結構100中最頂端的導電層。
In one embodiment, at least part of the circuit in the fifth
在一實施例中,在與電子元件300電性連接的天線和電子元件300之間的至少部分電流路徑(current path)的外圍,由於可以受到接地的導體所圍繞、隔離或屏蔽。如此一來,可以降低訊號的被干擾且/或可以提升訊號的品質。
In one embodiment, at least part of the current path between the antenna electrically connected to the
在一實施例中,與電子元件300電性連接的天線和接地的第一線路部分172a之間的部分線路層(如:部分的第一下線路層112)可以被稱為寄生天線(parasitic antenna),但本發明不限於此。
In one embodiment, a portion of the circuit layer between the antenna electrically connected to the
圖2是依照本發明的第二實施例的一種電子封裝結構的部分剖視示意圖。請參照圖2和圖1P,本實施例的電子封裝結構902及其製造方法和前述實施例的電子封裝結構901及其製造方法相似,其類似的構件以相同的標號表示,且具有類似的功能,並省略描述。
FIG2 is a partial cross-sectional schematic diagram of an electronic package structure according to the second embodiment of the present invention. Referring to FIG2 and FIG1P, the
電子封裝結構902包括第一電路結構100’、第二電路結構200以及至少一電子元件300。第一電路結構100’包括至少一
同軸導電通孔190’。
The
在一實施例中,同軸導電通孔190’可以包括外導電層191’、第一介電層195和內導電層192。第一介電層195位於外導電層191’和內導電層192之間。外導電層191’圍繞部分的內導電層192。外導電層191’和內導電層192彼此電性分離。
In one embodiment, the coaxial conductive via 190' may include an outer conductive layer 191', a first
在一實施例中,於垂直於第一電路結構100’的厚度的一方向上,外導電層191’未位於內導電層192和第五上線路層151之間。並且,第五上線路層151僅作為天線(如:被勵天線);或是,第五上線路層151僅作為天線及無訊號傳輸用途的虛設線路(dummy pattern)。
In one embodiment, in a direction perpendicular to the thickness of the first circuit structure 100', the outer conductive layer 191' is not located between the inner
在一實施例中,於垂直於第一電路結構100’的厚度的一方向上,外導電層191’未位於內導電層192和第三上線路層131之間。並且,第三上線路層131僅作為天線(如:寄生天線);或是,第三上線路層131僅作為天線及無訊號傳輸用途的虛設線路;或是,第三上線路層131僅作為無訊號傳輸用途的虛設線路。
In one embodiment, in a direction perpendicular to the thickness of the first circuit structure 100', the outer conductive layer 191' is not located between the inner
在一實施例中,於垂直於第一電路結構100’的厚度的一方向上,外導電層191’未位於內導電層192和第一上線路層111之間。並且,第一上線路層111僅作為天線(如:寄生天線);或是,第一上線路層111僅作為天線及無訊號傳輸用途的虛設線路;或是,第一上線路層111僅作為無訊號傳輸用途的虛設線路。
In one embodiment, in a direction perpendicular to the thickness of the first circuit structure 100', the outer conductive layer 191' is not located between the inner
在一實施例中,於垂直於第一電路結構100’的厚度的一方向上,外導電層191’未位於內導電層192和第一下線路層112
之間。並且,第一下線路層112僅作為天線(如:寄生天線);或是,第一下線路層112僅作為天線及無訊號傳輸用途的虛設線路;或是,第一下線路層112僅作為無訊號傳輸用途的虛設線路。
In one embodiment, in a direction perpendicular to the thickness of the first circuit structure 100', the outer conductive layer 191' is not located between the inner
前述實施例中,導電層或線路層可為單層或多層結構。而若為多層結構的導電層或線路層,則前述的多層結構之間可以不具有絕緣材質或介電材質。另外,就結構上而言,若為多層結構的導電層或線路層,則縱使前述多層結構是由不同的製程所形成,但仍可以(但,不限)用相同的用語和/或符號表示。 In the above embodiments, the conductive layer or circuit layer may be a single layer or a multi-layer structure. If it is a multi-layer structure of the conductive layer or circuit layer, the multi-layer structure may not have insulating materials or dielectric materials. In addition, in terms of structure, if it is a multi-layer structure of the conductive layer or circuit layer, even if the multi-layer structure is formed by different processes, it can still be represented by the same terms and/or symbols (but not limited to).
前述實施例中,絕緣層或介電層可為單層或多層結構。而若為多層結構的絕緣層或介電層,則前述的多層結構之間可以不具有導電材質。另外,就結構上而言,若為多層結構的絕緣層或介電層,則縱使前述多層結構是由不同的製程所形成,但仍可以(但,不限)用相同的用語和/或符號表示。 In the above embodiments, the insulating layer or dielectric layer may be a single layer or a multi-layer structure. If the insulating layer or dielectric layer is a multi-layer structure, there may be no conductive material between the multi-layer structure. In addition, in terms of structure, if the insulating layer or dielectric layer is a multi-layer structure, even if the multi-layer structure is formed by different processes, it can still be represented by the same terms and/or symbols (but not limited to).
前述實施例中,一線路層中對應的線路與另一線路層中對應的線路可以藉由對應的導電通孔而彼此電性連接。也就是說,除非有特別說明或引含,縱使於圖式中未繪示出一線路層中對應的線路與另一線路層中對應的線路彼此電性連接,但前述一線路層中對應的線路與前述另一線路層中對應的線路仍可以藉由圖式中未繪示出或未繪示的剖面上的導電通孔而彼此電性連接。 In the aforementioned embodiments, the corresponding circuits in one circuit layer and the corresponding circuits in another circuit layer can be electrically connected to each other through corresponding conductive vias. That is to say, unless otherwise specified or implied, even if the corresponding circuits in one circuit layer and the corresponding circuits in another circuit layer are not shown in the drawings to be electrically connected to each other, the corresponding circuits in the aforementioned circuit layer and the corresponding circuits in the aforementioned other circuit layer can still be electrically connected to each other through conductive vias not shown in the drawings or on the cross-sections not shown.
綜上所述,在電子封裝結構中,由於電子元件位於第一電路結構和第二電路結構之間,且至少部分的電子元件可以位於第一電路結構的空腔內。如此一來,可以使電子元件具有較佳的 保護,而可以降低電子元件損傷或損壞的可能,而可以提升電子封裝結構的品質。 In summary, in the electronic packaging structure, since the electronic component is located between the first circuit structure and the second circuit structure, and at least part of the electronic component can be located in the cavity of the first circuit structure. In this way, the electronic component can be better protected, and the possibility of damage or destruction of the electronic component can be reduced, thereby improving the quality of the electronic packaging structure.
另一方面,電子封裝結構的第一電路結構可以更包括同軸導電通孔。電子元件可以藉由同軸導電通孔電性連接至對應的線路(如:天線)。如此一來,可以提升訊號的被干擾且/或可以提升訊號的品質。 On the other hand, the first circuit structure of the electronic package structure may further include a coaxial conductive via. The electronic component may be electrically connected to a corresponding circuit (such as an antenna) via the coaxial conductive via. In this way, the interference of the signal may be improved and/or the quality of the signal may be improved.
901:電子封裝結構
100:第一電路結構
155:第五上絕緣層
151:第五上線路層
135:第三上絕緣層
131:第三上線路層
115:第一上絕緣層
111:第一上線路層
105:第一核心層
112:第一下線路層
116:第一下絕緣層
132:第三下線路層
136:第三下絕緣層
152:第五下線路層
156:第五下絕緣層
190:同軸導電通孔
196:第二介電層
192:導電層
195:第一介電層
191:導電層
170:空腔
172:底線路層
172a:第一線路部分
172b:第二線路部分
300:電子元件
200:第二電路結構
265:第六上絕緣層
241:第四上線路層
245:第四上絕緣層
221:第二上線路層
205:第二核心層
222:第二下線路層
246:第四下絕緣層
242:第四下線路層
266:第六下絕緣層
401、402:導電連接件
408:填充材料
901: electronic packaging structure
100: first circuit structure
155: fifth upper insulating layer
151: fifth upper wiring layer
135: third upper insulating layer
131: third upper wiring layer
115: first upper insulating layer
111: first upper wiring layer
105: first core layer
112: first lower wiring layer
116: first lower insulating layer
132: third lower wiring layer
136: third lower insulating layer
152: fifth lower wiring layer
156: fifth lower insulating layer
190: coaxial conductive via
196: second dielectric layer
192: conductive layer
195: first dielectric layer
191: conductive layer
170: cavity
172:
Claims (11)
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TW200950043A (en) * | 2008-03-24 | 2009-12-01 | Ngk Spark Plug Co | Parts built-in wiring substrate |
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TW202201706A (en) * | 2020-06-16 | 2022-01-01 | 大陸商珠海越亞半導體股份有限公司 | Heat dissipation and electromagnetic shielding embedded packaging structure, manufacturing method thereof and substrate |
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TW200746974A (en) * | 2006-04-25 | 2007-12-16 | Ngk Spark Plug Co | Method for manufacturing wiring board |
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TW202125754A (en) * | 2019-12-17 | 2021-07-01 | 南韓商三星電子股份有限公司 | Semiconductor package |
TW202201706A (en) * | 2020-06-16 | 2022-01-01 | 大陸商珠海越亞半導體股份有限公司 | Heat dissipation and electromagnetic shielding embedded packaging structure, manufacturing method thereof and substrate |
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