TWI845278B - Semiconductor structure and semiconductor device - Google Patents

Abstract

The present disclosure provides a semiconductor structure including: a substrate; an epitaxial layer disposed on the substrate; multiple field plate structures including a first field plate structure and a second field plate structure disposed in a first cell and a second cell of the semiconductor structure, respectively; an upper electrode layer covering the field plate structures, wherein the upper electrode layer is separated from the epitaxial layer in the first cell and in direct contact with the epitaxial layer in the second cell; and a lower electrode layer disposed under the substrate and opposite to the epitaxial layer.

Description

Semiconductor structure and semiconductor device

The present invention relates to semiconductor structures, and more particularly to semiconductor structures including field plate structures.

In recent years, the semiconductor industry has made significant progress in the development of power devices. Currently, a variety of power devices have been developed, such as high voltage metal-oxide-semiconductor (HVMOS) transistors, insulated gate bipolar transistors (IGBT), junction field effect transistors (JFET), and Schottky barrier diodes (SBD). These devices are usually used in power amplification, power control and other applications in power systems of household appliances, communication equipment and automotive generators.

In existing metal oxide semiconductor transistor designs, the on-resistance of the transistor can be reduced by using a trench transistor structure. In addition, by forming a transistor including a split-gate, the parasitic capacitance of the semiconductor element can be reduced to reduce switching loss. Furthermore, a chip including a fast recovery diode (FRD) or a Schottky barrier diode can be connected in parallel to a chip with a transistor. In this way, the reverse recovery charge can be reduced to further reduce switching loss.

However, in order to package the two chips together, bonding wires are needed for electrical connection, which will generate additional parasitic inductance and unnecessary signals. In addition, since diodes and transistors located on different chips need to be packaged, such traditional processes are lengthy and the resulting semiconductor structure takes up a larger space. Therefore, the research and development of power components requires continuous updates and adjustments to solve the various problems faced by power components during manufacturing and operation.

A semiconductor structure includes: a substrate; an epitaxial layer disposed on the substrate; a plurality of field plate structures, including a first field plate structure and a second field plate structure disposed in a first unit and a second unit of the semiconductor structure respectively; a plurality of shielding layers disposed between a plurality of bottoms of the field plate structures and the epitaxial layer; an upper electrode layer covering the field plate structure, wherein the upper electrode layer is separated from the epitaxial layer in the first unit and directly contacts the epitaxial layer in the second unit; and a lower electrode layer disposed under the substrate and opposite to the epitaxial layer.

A semiconductor device comprises: the semiconductor structure as described above; a transition layer laterally surrounding the semiconductor structure; and a channel blocking layer laterally surrounding the transition layer, wherein the semiconductor structure has a plurality of first units and second units.

The following disclosure provides many different embodiments or examples to show different components of the embodiments of the present invention. The following will disclose specific examples of the components of this specification and their arrangement to simplify the disclosure. Of course, these specific examples are not used to limit the disclosure. For example, if the following invention content of this specification describes forming a first component on or above a second component, it means that it includes an embodiment in which the first and second components formed are in direct contact, and also includes an embodiment in which an additional component can be formed between the above-mentioned first and second components, and the first and second components are not in direct contact. In addition, the various examples in the disclosure may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is to simplify and clarify, and is not used to limit the relationship between the various embodiments and/or the configurations.

Furthermore, to facilitate description of the relationship between one element or component and another element or component in the drawings, spatially relative terms may be used, such as "under," "below," "lower," "above," "upper," and the like. In addition to the orientation depicted in the drawings, spatially relative terms also cover different orientations of the device in use or operation. When the device is turned to a different orientation (for example, rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

Here, the terms "about", "approximately", and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meaning of "about", "approximately", and "generally" can still be implied.

Some embodiments of the present invention are described below, and additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the stages may be replaced or deleted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components may be replaced or deleted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

As used herein, the term "substantially" means that a given amount of value may vary based on a particular technology node associated with the target semiconductor device. In some embodiments, based on a particular technology node, the term "substantially" may mean that a given amount of value is within a range of, for example, ±5% of a target (or desired) value.

The present disclosure provides a semiconductor structure and a semiconductor device including the semiconductor structure, and the semiconductor structure may include a first unit and a second unit as a control element and a diode element, respectively. The multiple field plate structures disclosed in the present disclosure are arranged in both the first unit and the second unit, and the first unit and the second unit can be formed to have a common substrate and epitaxial layer. Therefore, the manufacturing of the control unit and the diode unit disclosed in the present disclosure can be well integrated, thereby reducing the use of masks in the manufacturing process and avoiding the generation of additional parasitic inductance between the two units. In addition, the second unit as a single carrier element can reduce the reverse recovery time of the semiconductor structure. The shielding layer disposed between the bottom of the field plate structure and the epitaxial layer can reduce the electric field in the oxide of the field plate structure and reduce the parasitic capacitance between the gate and the drain of the semiconductor structure. Furthermore, by reducing the surface electric field of the Schottky diode through the provision of the field plate structure and the shielding layer, the leakage current from the image force barrier lowering effect can be reduced. Therefore, the semiconductor structure and semiconductor device disclosed in the present invention can reduce the power loss during operation while having better reverse recovery properties.

FIG. 1 is a cross-sectional view of a semiconductor structure 10 according to some embodiments of the present disclosure. The semiconductor structure 10 may include a substrate 100 and an epitaxial layer 102 disposed on the substrate 100. The semiconductor structure 10 may further include a plurality of field plate structures 110, which include a first field plate structure 110A and a second field plate structure 110B disposed in a first unit 10A and a second unit 10B of the semiconductor structure 10, respectively. As shown in FIG. 1 , a plurality of shielding layers 120 may be disposed between the bottom of each field plate structure 110 and the epitaxial layer 102. The semiconductor structure 10 may further include an upper electrode layer 130 covering the field plate structure 110 and a lower electrode layer 140 disposed under the substrate 100 and opposite to the epitaxial layer 102. As shown in FIG. 1 , the upper electrode layer 130 may be separated from the epitaxial layer 102 in the first unit 10A and directly contact the epitaxial layer 102 in the second unit 10B.

In some embodiments, the substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. In some embodiments, the substrate 100 is formed of silicon, germanium, other suitable semiconductor materials, or a combination thereof. For example, in a specific embodiment, the substrate 100 includes silicon. In some embodiments, the substrate 100 may include a compound semiconductor, such as silicon carbide, gallium nitride, gallium oxide, gallium arsenide, other suitable semiconductor materials, or a combination thereof. In some embodiments, the substrate 100 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, other suitable materials, or a combination thereof. In some embodiments, the substrate 100 may be composed of multiple layers of materials, such as multiple layers of silicon/silicon germanium, silicon/silicon carbide.

In some embodiments of the present disclosure, for example, the substrate 100 is a doped wafer doped with a first conductivity type, and the first conductivity type is n-type. In some other embodiments, the first conductivity type may also be p-type. In the case where the first conductivity type is n-type, the dopant having the first conductivity type may be, for example, nitrogen, phosphorus, arsenic, antimony, bismuth, or silicon. In some embodiments, the doping concentration of the substrate 100 may be between about 1e19 atoms/cm ³ and about 1E21 atoms/cm ³ .

The epitaxial layer 102 may include the same or similar material as the substrate 100, such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, gallium arsenide, silicon germanium, silicon germanium carbide, other suitable materials, or combinations thereof. In some embodiments, the substrate 100 and the epitaxial layer 102 have the same conductivity type (e.g., n-type), and the substrate 100 and the epitaxial layer 102 may include the same dopant. In some embodiments, the dopant concentration of the epitaxial layer 102 is less than the dopant concentration of the substrate 100. In some embodiments, the dopant concentration of the epitaxial layer 102 may be between about 1e13 atoms/cm ³ and about 1e18 atoms/cm ³ . In some embodiments of the present disclosure, for example, the epitaxial layer 102 includes silicon carbide. By forming the epitaxial layer 102 with silicon carbide, the epitaxial layer 102 can be doped with a dopant that is suitable for the energy band range of silicon carbide and has a lower activation energy. In addition, the epitaxial layer 102 formed of silicon carbide can provide a higher breakdown voltage, a lower leakage current, and a lower on-resistance.

In some embodiments, each field plate structure 110 includes a conductive filling layer 112 and a dielectric spacer layer 114. At least a portion of the conductive filling layer 112 may be embedded in the epitaxial layer 102, and the dielectric spacer layer 114 may extend between the conductive filling layer 112 and the epitaxial layer 102. In some embodiments, as shown in FIG. 1 , the conductive filling layer 112 may be completely embedded in the epitaxial layer 102 in the second cell 10B, such that the upper surface of the conductive filling layer 112 is lower than or coplanar with the upper surface of the epitaxial layer 102. In some embodiments, the dielectric spacer layer 114 has a top portion extending between the conductive filling layer 112 and the upper electrode layer 130.

The material of the conductive fill layer 112 may include polysilicon, metal, metal nitride, other suitable conductive materials, or a combination thereof. The material of the dielectric spacer 114 may include silicon oxide, tantalum oxide, zirconia, aluminum oxide, aluminum dioxide tantalum alloy, silicon dioxide tantalum, silicon tantalum oxynitride, tantalum oxide, titanium oxide, tantalum oxide, other suitable high-k dielectric materials, or a combination thereof. In some embodiments, the dielectric spacer 114 includes an oxide having an element in common with the epitaxial layer 102. For example, in a specific embodiment, the epitaxial layer 102 includes silicon or silicon carbide, and the dielectric spacer 114 includes silicon oxide.

In some embodiments, the field plate structure 110 includes a conductive filling layer 112 configured as a separated gate structure. As shown in FIG. 1 , the conductive filling layer 112 may include an upper conductive layer 112U and a lower conductive layer 112L separated by a dielectric spacer layer 114. The upper conductive layer 112U in the first cell 10A may be electrically connected to a gate (not shown). In some embodiments, the lower conductive layer 112L is electrically connected to a source (not shown). Depending on the design requirements of the semiconductor structure 10, the upper conductive layer 112U in the second cell 10B may be electrically connected to a gate or a source. If the upper conductive layer 112U in the second cell 10B is electrically connected to the gate, when a forward bias is applied to the upper conductive layer 112U in the second cell 10B, an accumulation layer of carriers can be generated in the epitaxial layer 102 adjacent to the upper conductive layer 112U, which is beneficial to the generation of a forward current. If the upper conductive layer 112U in the second cell 10B is electrically connected to the source, the parasitic capacitance of the dielectric spacer 114 generated between the upper conductive layer 112U and the epitaxial layer 102 can be reduced, which is beneficial to reducing the switching loss of the semiconductor structure 10.

It should be understood that, although the conductive filling layer 112 of the field plate structure 110 in the first cell 10A and the second cell 10B shown in FIG. 1 are configured as a separate gate structure, the present disclosure does not limit the conductive filling layer 112 in all cells to be a separate gate structure. For example, the conductive filling layer 112 in one of the first cell 10A and the second cell 10B can be configured as a separate gate structure, and the conductive filling layer 112 in the other can be a single block.

The dielectric spacer layer 114 may include an opening O in, for example, the first cell 10A and/or the second cell 10B, and the conductive filling layer 112 may be in direct contact with the shielding layer 120 through the opening O. However, the dielectric spacer layer 114 may also extend between the conductive filling layer 112 and the shielding layer 120 to separate the two. In some embodiments, the area of the lower surface of the lower conductive layer 112L is smaller than the area of the upper surface of the lower conductive layer 112L. In some embodiments, the substrate 100 and the epitaxial layer 102 have a first conductivity type (e.g., n-type), and the shielding layer 120 has a second conductivity type (e.g., p-type) opposite to the first conductivity type. The shielding layer 120 can be used to separate the conductive filling layer 112 and the epitaxial layer 102 to avoid generating an excessively high electric field in the dielectric spacer layer 114. In addition, by providing the shielding layer 120, the electric field in the oxide (e.g., the dielectric spacer layer 114) in the field plate structure 110 can be reduced and the parasitic capacitance between the gate and the drain of the semiconductor structure 10 can be reduced. Furthermore, by providing the field plate structure 110 and the shielding layer 120, the surface electric field of the Schottky diode element in the second unit 10B can be reduced, and the leakage current from the image force barrier lowering effect can be reduced.

The material of the shielding layer 120 may include, for example, a semiconductor material formed by implantation, other suitable materials, or a combination thereof. In some embodiments of the present disclosure, for example, the shielding layer 120 has a second conductivity type of p-type, and is doped with dopants such as boron and aluminum in the shielding layer 120. In some embodiments, the doping concentration of the shielding layer 120 may be between about 1e14 atoms/cm ³ and about 1e19 atoms/cm ³ .

In some embodiments, as shown in FIG. 1 , the epitaxial layer 102 includes a doping structure 150 in the first cell 10A that laterally surrounds the first field plate structure 110A and at an interface with the upper electrode layer 130. The doping structure 150 may include a doping well 152, a first heavily doped region 154, and a second heavily doped region 156. In some embodiments, a portion of the doping well 152 adjacent to the first field plate structure 110A can be used as a channel region when the semiconductor structure 10 is in operation. For example, when a forward bias is applied to the conductive fill layer 112, an inversion layer can be formed near the sidewall of the first field plate structure 110A adjacent to the doped well 152 to generate current. The second heavily doped region 156 can be used to electrically connect the doped well 152 to the upper electrode layer 130. The first heavily doped region 154 can be electrically connected to the source.

The first heavily doped region 154 may have the same first conductivity type (e.g., n-type) as the epitaxial layer 102, and the doped well 152 and the second heavily doped region 156 may have the same second conductivity type (e.g., p-type) as the shielding layer 120. The doping concentration of the doped well 152 may be between about 1e15 atoms/cm ³ and about 1e18 atoms/cm ^3. The doping concentration of the first heavily doped region 154 may be between about 1e18 atoms/cm ³ and about 1e21 atoms/cm ^3. The doping concentration of the second heavily doped region 156 may be between about 1e18 atoms/cm ³ and about 1e21 atoms/cm ³ .

The doped structure 150 may include a material that is the same as or similar to the portion of the epitaxial layer 102 below the doped structure 150, such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, gallium arsenide, silicon germanium, silicon germanium carbide, other suitable materials, or a combination thereof. The doped structure 150 may be formed by performing a doping process in the epitaxial material used to form the epitaxial layer 102 in a portion of the semiconductor structure 10 in a region used to form the first cell 10A. In some embodiments, the upper surface of the doped structure 150 is lower than the upper surface of the first field plate structure 110A. In some embodiments, the upper surface of the doped structure 150 is substantially coplanar with the upper surface of the epitaxial layer 102 in the second cell 10B. Depending on the configuration of the doped structure 150, in some embodiments, as shown in FIG. 1 , the upper surface of the epitaxial layer 102 in the first cell 10A is at the same height as the upper surface in the second cell 10B.

The upper electrode layer 130 and the lower electrode layer 140 can be electrically connected to the source and drain (not shown) of the semiconductor structure 10, respectively. However, depending on the structural design of the semiconductor structure 10, in some embodiments of the present disclosure, the upper electrode layer 130 and the lower electrode layer 140 themselves can also be regarded as the source and drain of the semiconductor structure 10, respectively. In addition, in the second unit 10B, a Schottky contact can be provided on the interface between the upper electrode layer 130 and the epitaxial layer 102. In this way, the second unit 10B can operate as a single carrier element (e.g., a Schottky diode element), thereby improving the reverse recovery properties of the semiconductor structure 10 and reducing the reverse recovery time.

In some embodiments, multiple top portions of the field plate structure 110 protrude into the upper electrode layer 130. As shown in FIG. 1 , the top portions of the first field plate structure 110A and the second field plate structure 110B may protrude into the upper electrode layer 130. Further as shown in FIG. 1 , the top portions of the first field plate structure 110A and the second field plate structure 110B may have a top surface higher than the surrounding doping structure 150 and the epitaxial layer 102 in the first cell 10A and the second cell 10B, respectively.

The upper electrode layer 130 may be or include, for example, platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), gold (Au), iron (Fe), nickel (Ni), benium (Be), chromium (Cr), cobalt (Co), antimony (Sb), iridium (Ir), molybdenum (Mo), nimum (Os), thorium (Th), vanadium (V), some other metal or metal nitride, or a combination thereof.

The lower electrode layer 140 may be or include the same or similar material as the upper electrode layer 130. For example, the lower electrode layer 140 may be or include, for example, platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), gold (Au), iron (Fe), nickel (Ni), benium (Be), chromium (Cr), cobalt (Co), antimony (Sb), iridium (Ir), molybdenum (Mo), nimum (Os), thorium (Th), vanadium (V), some other metal or metal nitride, or a combination thereof.

It should be understood that the first unit 10A and the second unit 10B may also be referred to as the control element and the diode element of the semiconductor structure 10, respectively. The substrate 100 and the epitaxial layer 102 may extend continuously between the first unit 10A and the second unit 10B. In some embodiments, the first unit 10A and the second unit 10B are electrically connected in parallel via the upper electrode layer 130 and the lower electrode layer 140. In some embodiments of the present disclosure, a plurality of field plate structures 110 are disposed in both the first unit 10A and the second unit 10B, and the first unit 10A and the second unit 10B may have a common substrate 100 and epitaxial layer 102. Therefore, the control unit and the diode unit of the semiconductor structure 10 can be well integrated. Compared with a conventional semiconductor structure including a control unit and a diode unit, the use of a mask in a manufacturing process can be reduced, and additional parasitic inductance between the two units can be avoided.

2A and 3A are referred to for explaining the configuration of the semiconductor devices 1 and 2, and FIG. 2B and 3B are referred to for explaining the layout of the first unit 10A and the second unit 10B in the semiconductor structure 10.

FIG. 2A is a top view of a semiconductor device 1 according to some embodiments of the present disclosure. In addition to the semiconductor structure 10 as described above, a transition layer 12 and a channel blocking layer 14 may be provided which laterally surround the semiconductor structure 10. The semiconductor structure 10 may have a plurality of first cells and second cells, and the first cells and the second cells may be used as a control cell and a diode cell of the semiconductor device 1, respectively. The structure and configuration of the first cells and the second cells are similar to the first cells 10A and the second cells 10B in FIG. 1, and their detailed description is omitted for simplicity.

The transition layer 12 can be used to protect the internal components of the semiconductor structure 10. The material of the transition layer 12 can include the same or similar material as the above-mentioned epitaxial layer 102, other suitable materials, or a combination of the foregoing. In some embodiments, the transition layer is doped to have a second conductivity type. The channel blocking layer 14 can be used to isolate adjacent chips. The material of the channel blocking layer 14 can include the same or similar material as the above-mentioned epitaxial layer 102, other suitable materials, or a combination of the foregoing. In some embodiments, the channel blocking layer 14 is doped to have a first conductivity type.

FIG. 2B is a cross-sectional schematic diagram showing the layout of the first unit 10A and the second unit 10B according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 2B, the first units 10A and the second units 10B are arranged alternately with each other in a transverse direction. Since the first unit 10A is the part through which the current flows when the semiconductor structure 10 is turned on, the first unit 10A will become a heat source. By disposing the second unit 10B between the two first units 10A, the two heat sources can be isolated and the temperature rise rate of the chip can be slowed down.

FIG. 3A is a top view of a semiconductor device 2 according to some other embodiments of the present disclosure. The difference from the semiconductor device 1 shown in FIG. 2A is that the semiconductor structure 10 in the semiconductor device 2 has a first area A1 and a second area A2, and the first unit and the second unit used as the control unit and the diode unit of the semiconductor device 1 are respectively located in the first area A1 and the second area A2. In some embodiments, one of the first area A1 and the second area A2 laterally surrounds the other. For example, as shown in FIG. 3A, in some embodiments, the second area A2 laterally surrounds the first area A1. In other embodiments, the first area A1 may also be configured to laterally surround the second area A2. The functions and materials of the transition layer 12 and the channel blocking layer 14 are similar to those of the transition layer 12 and the channel blocking layer 14 in FIG. 2A , and their descriptions are omitted here for simplicity.

FIG. 3B is a cross-sectional schematic diagram showing the layout of the first unit 10A and the second unit 10B according to some other embodiments of the present disclosure. As shown in FIG. 3B, in an embodiment where a plurality of first units 10A and a plurality of second units 10B are respectively arranged in respective regions, a plurality of first units 10A are adjacent to each other, and a plurality of second units 10B are adjacent to each other. In this way, since the complexity of the routing of the source, drain, and gate to the first unit 10A and the second unit 10B can be reduced, the manufacturing process of the semiconductor structure 10 can be made easier.

It should be noted that, although the first unit 10A and the second unit 10B are shown as being adjacent to each other in Figures 2B and 3B, the present disclosure is not limited thereto. In some other embodiments, for example, an additional structure may be disposed between the first unit 10A and the second unit 10B.

FIG. 4 shows the effect of the area of a region having an embedded Schottky barrier diode (E-SBD) in a semiconductor device (hereinafter referred to as a diode region) on the current change of the semiconductor device during reverse recovery according to some embodiments of the present disclosure. FIG. 5 shows the effect of the area of the diode region in a semiconductor device on the reverse recovery time (T _rr ) and reverse recovery charge (Q _rr ) of the semiconductor device. FIG. 6 shows the effect of the area of the diode region in a semiconductor device on the switching energy (E _sw ) and reverse recovery softness factor (RRSF) of the semiconductor device. FIG. 7 shows the effect of the diode area in a semiconductor device on the power loss of the semiconductor device at different switching frequencies.

The measurement of the current change during reverse recovery as shown in FIG. 4 can be performed by digital simulation software, and a person skilled in the art can arbitrarily select the voltage and current to be measured. In addition, a person skilled in the art can select the area of a specific region having a control element (e.g., the first region A1 in FIG. 3A or the region occupied by the first unit in the semiconductor structure, hereinafter referred to as the control region) to observe the effect of the area of the diode region on the current change during reverse recovery of the semiconductor device. In a specific example, a dynamic test measurement is performed with a voltage of 800V and a current of 20A, thereby obtaining the change of the diode current over time as shown in FIG. 4.

In the current waveform of each measurement result, the time from the beginning of the diode current decrease to the reverse peak is called ta, and the time from the peak value to the current zero point is called tb, and the sum of the time ta and tb can be called the reverse recovery time (T _rr ). It can be seen from Figures 4 and 5 that as the area of the diode region increases relative to the area of the control region, the reverse recovery time of the semiconductor device gradually decreases, that is, the semiconductor device has a faster response speed.

In addition, in each current waveform of Figure 4, the value of the current integral over time from the beginning of the current decrease to the return to the current zero point is the reverse recovery charge ( _Qrr ) during the reverse recovery period. It can be seen from Figures 4 and 5 that as the area of the diode region increases relative to the area of the control region, the reverse recovery charge of the semiconductor device gradually decreases. Referring to Figure 6, as the area of the diode region increases, the switching energy ( _Esw ) also gradually decreases. Therefore, by connecting the second unit as a diode element in parallel to the first unit as a control element, the power loss of the semiconductor device during operation can be reduced.

The ratio of time tb to time ta, tb/ta, can be called the reverse recovery softness factor (RRSF). As shown in Figures 4 and 6, as the area of the diode region increases relative to the area of the control region, the reverse recovery softness factor (RRSF) of the semiconductor device gradually increases, and the slope of the current value to time in the process from the reverse peak to the current zero point becomes smaller. Therefore, by connecting more second units with diode elements in parallel to the first unit as the control element, the possibility of the semiconductor device generating a spike voltage after reverse recovery can be reduced, avoiding additional power loss.

Referring to Figure 7, as the area of the diode region increases relative to the area of the control region, the power loss of the semiconductor device at each switching frequency also decreases. This is because the power loss of the semiconductor device comes from the power loss during current conduction and switching, and the increase in the area of the diode region reduces the switching energy, which reduces the power loss during switching.

In summary, the present disclosure provides a semiconductor structure and a semiconductor device including the semiconductor structure, and the semiconductor structure may include a first unit and a second unit as a control element and a diode element, respectively. The multiple field plate structures disclosed in the present disclosure are arranged in both the first unit and the second unit, and the first unit and the second unit can be formed to have a common substrate and epitaxial layer. Therefore, the manufacturing of the control unit and the diode unit disclosed in the present disclosure can be well integrated, thereby reducing the use of masks in the manufacturing process and avoiding the generation of additional parasitic inductance between the two units. In addition, the second unit as a single carrier element can reduce the reverse recovery time of the semiconductor structure. The shielding layer disposed between the bottom of the field plate structure and the epitaxial layer can reduce the electric field in the oxide of the field plate structure and reduce the parasitic capacitance between the gate and the drain of the semiconductor structure. Furthermore, by reducing the surface electric field of the Schottky diode through the provision of the field plate structure and the shielding layer, the leakage current from the mirror force barrier reduction effect can be reduced. Therefore, the semiconductor structure and semiconductor device disclosed in the present invention can reduce the power loss during operation while having better reverse recovery properties.

The features of several embodiments are summarized above so that those with ordinary knowledge in the art to which the present invention belongs can more easily understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the art to which the present invention belongs should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art to which the present invention belongs should also understand that such equivalent processes and structures do not violate the spirit and scope of the present invention, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present invention.

1,2:Semiconductor devices

10: Semiconductor structure

10A: Unit 1

10B: Unit 2

12: Transition layer

14: Channel blocking layer

100: Base

102: Epitaxial layer

110: Field plate structure

110A: First Field Plate Structure

110B: Second field plate structure

112: Conductive filling layer

112L: Lower conductive layer

112U: Upper conductive layer

114: Dielectric spacer layer

120: Shielding layer

130: Upper electrode layer

140: Lower electrode layer

150: mixed structure

152: Mixed Well

154: First heavy doping area

156: Second mixed area

A1: Area 1

A2: Second Area

O: Open

The following will be described in detail with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. Figure 1 is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure. Figure 2A is a top view of a semiconductor device according to some embodiments of the present disclosure. Figure 2B is a cross-sectional schematic diagram showing the layout of the first unit and the second unit according to some embodiments of the present disclosure. Figure 3A is a top view of a semiconductor device according to some other embodiments of the present disclosure. Figure 3B is a cross-sectional schematic diagram showing the layout of the first unit and the second unit according to some other embodiments of the present disclosure. FIG. 4 illustrates the effect of the area of an embedded Schottky barrier diode (E-SBD) in a semiconductor device on the current change of the semiconductor device during reverse recovery according to some embodiments of the present disclosure. FIG. 5 illustrates the effect of the area of an embedded Schottky barrier diode in a semiconductor device on the reverse recovery time (T _rr ) and reverse recovery charge (Q _rr ) of the semiconductor device according to some embodiments of the present disclosure. FIG. 6 illustrates the effect of the area of an embedded Schottky barrier diode in a semiconductor device on the switching energy (E _sw ) and reverse recovery softness factor (RRSF) of the semiconductor device according to some embodiments of the present disclosure. FIG. 7 illustrates the effect of the area of a semiconductor device having an embedded Schottky barrier diode on the power loss of the semiconductor device at different switching frequencies according to some embodiments of the present disclosure.

10:Semiconductor structure

10A: Unit 1

10B: Unit 2

100: Base

102: Epitaxial layer

110: Field plate structure

110A: First stage plate structure

110B: Second field plate structure

112: Conductive filling layer

112L: Lower conductive layer

112U: Upper conductive layer

114: Dielectric spacer layer

120: Shielding layer

130: Upper electrode layer

140: Lower electrode layer

150:Doped structure

152: Mixed Well

154: The first heavily doped area

156: Second mixed area

O: Open

Claims (18)

A semiconductor structure includes: a substrate; an epitaxial layer disposed on the substrate; a plurality of field plate structures, each of the field plate structures includes: a conductive filling layer, at least a portion of which is embedded in the epitaxial layer; and a dielectric spacer layer extending between the conductive filling layer and the epitaxial layer, and the dielectric spacer layer includes an opening, wherein the field plate structures include a first field plate structure and a second field plate structure respectively disposed in a first unit and a second unit of the semiconductor structure; A plurality of shielding layers are disposed between the plurality of bottoms of the field plate structures and the epitaxial layer, and the conductive filling layer is in direct contact with the shielding layers through the opening; an upper electrode layer covers the field plate structures, wherein the upper electrode layer is separated from the epitaxial layer in the first unit and directly contacts the epitaxial layer in the second unit; and a lower electrode layer is disposed under the substrate and opposite to the epitaxial layer. A semiconductor structure as claimed in claim 1, wherein the dielectric spacer layer has a top portion extending between the conductive fill layer and the upper electrode layer. A semiconductor structure as claimed in claim 1, wherein the conductive filling layer includes an upper conductive layer and a lower conductive layer separated by the dielectric spacer layer, and the upper conductive layer in the first unit is electrically connected to a gate. A semiconductor structure as claimed in claim 3, wherein the lower conductive layer is electrically connected to a source, and the upper conductive layer in the second unit is electrically connected to the gate or the source. A semiconductor structure as claimed in claim 3, wherein the area of a lower surface of the lower conductive layer is smaller than the area of an upper surface of the lower conductive layer. A semiconductor structure as claimed in claim 1, wherein in the second unit, there is a Schottky contact at the interface between the upper electrode layer and the epitaxial layer. A semiconductor structure as claimed in claim 1, wherein the epitaxial layer in the first unit includes a doped structure laterally surrounding the first field plate structure and at the interface with the upper electrode layer. A semiconductor structure as claimed in claim 7, wherein the upper surface of the doped structure is lower than the upper surface of the first field plate structure. A semiconductor structure as claimed in claim 7, wherein the upper surface of the doped structure is coplanar with the upper surface of the epitaxial layer in the second unit. A semiconductor structure as claimed in claim 1, wherein the top portions of the field plate structures protrude into the upper electrode layer. A semiconductor structure as claimed in claim 1, wherein the substrate and the epitaxial layer extend continuously between the first unit and the second unit. A semiconductor structure as claimed in claim 1, wherein the upper surface of the epitaxial layer in the first unit is at the same height as the upper surface in the second unit. A semiconductor structure as claimed in claim 1, wherein the substrate and the epitaxial layer have a first conductivity type, and the shielding layers have a second conductivity type opposite to the first conductivity type. A semiconductor structure as claimed in claim 1, wherein the first unit and the second unit are electrically connected in parallel via the upper electrode layer and the lower electrode layer. A semiconductor structure as claimed in claim 1, wherein the epitaxial layer comprises silicon carbide. A semiconductor device, comprising: a semiconductor structure as claimed in any one of claims 1 to 15; a transition layer laterally surrounding the semiconductor structure; and a channel blocking layer laterally surrounding the transition layer; wherein the semiconductor structure has a plurality of the first units and the second units. A semiconductor device as claimed in claim 16, wherein each of the first units and the second units are arranged alternately with each other horizontally. A semiconductor device as claimed in claim 16, wherein the first units and the second units are respectively located in a first region and a second region of the semiconductor structure, and one of the first region and the second region laterally surrounds the other.

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